From 86328f9881c2dd46dbf7ccf9ddc425cd27ecde1c Mon Sep 17 00:00:00 2001 From: Gerardo Marx Date: Thu, 16 Jul 2026 14:00:03 -0600 Subject: [PATCH] initial commit --- gpio_bitfield_cpu2/.ccsproject | 12 + gpio_bitfield_cpu2/.clangd | 8 + gpio_bitfield_cpu2/.cproject | 185 + gpio_bitfield_cpu2/.project | 33 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.core.resources.prefs | 2 + gpio_bitfield_cpu2/2837xD_FLASH_lnk_cpu2.cmd | 148 + gpio_bitfield_cpu2/2837xD_RAM_lnk_cpu2.cmd | 104 + ...D_CodeStartBranch.asm.4EE093348ADEE433.idx | Bin 0 -> 1028 bytes .../index/device.c.0B89A1F1F3993A3F.idx | Bin 0 -> 11806 bytes .../index/device.h.FC78F7DABF8D1C4D.idx | Bin 0 -> 3236 bytes .../index/driverlib.h.BEE08E1C139315B9.idx | Bin 0 -> 862 bytes .../gpio_bitfield_cpu2.c.3F85F893C12398EA.idx | Bin 0 -> 578 bytes .../CPU2_RAM/.clangd/compile_commands.json | 17 + .../device/F2837xD_CodeStartBranch.asm | 112 + gpio_bitfield_cpu2/device/device.c | 706 ++ gpio_bitfield_cpu2/device/device.h | 394 + gpio_bitfield_cpu2/device/driverlib.h | 87 + gpio_bitfield_cpu2/device/driverlib/adc.c | 342 + gpio_bitfield_cpu2/device/driverlib/adc.h | 2098 +++++ gpio_bitfield_cpu2/device/driverlib/asysctl.c | 43 + gpio_bitfield_cpu2/device/driverlib/asysctl.h | 160 + gpio_bitfield_cpu2/device/driverlib/can.c | 1122 +++ gpio_bitfield_cpu2/device/driverlib/can.h | 1924 +++++ .../device/driverlib/ccs/Debug/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Debug/driverlib_coff.lib | Bin 0 -> 575952 bytes .../driverlib/ccs/Debug/driverlib_eabi.lib | Bin 0 -> 1003104 bytes .../driverlib/ccs/Release/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Release/driverlib_coff.lib | Bin 0 -> 375766 bytes .../driverlib/ccs/Release/driverlib_eabi.lib | Bin 0 -> 654036 bytes .../driverlib/ccs/driverlib.projectspec | 46 + gpio_bitfield_cpu2/device/driverlib/cla.c | 89 + gpio_bitfield_cpu2/device/driverlib/cla.h | 984 +++ gpio_bitfield_cpu2/device/driverlib/clb.c | 145 + gpio_bitfield_cpu2/device/driverlib/clb.h | 1290 +++ gpio_bitfield_cpu2/device/driverlib/cmpss.c | 223 + gpio_bitfield_cpu2/device/driverlib/cmpss.h | 1325 +++ gpio_bitfield_cpu2/device/driverlib/cpu.h | 172 + .../device/driverlib/cputimer.c | 61 + .../device/driverlib/cputimer.h | 509 ++ gpio_bitfield_cpu2/device/driverlib/dac.c | 93 + gpio_bitfield_cpu2/device/driverlib/dac.h | 604 ++ gpio_bitfield_cpu2/device/driverlib/dcsm.c | 377 + gpio_bitfield_cpu2/device/driverlib/dcsm.h | 669 ++ gpio_bitfield_cpu2/device/driverlib/debug.h | 91 + gpio_bitfield_cpu2/device/driverlib/dma.c | 370 + gpio_bitfield_cpu2/device/driverlib/dma.h | 1171 +++ .../driver_inclusive_terminology_mapping.h | 109 + gpio_bitfield_cpu2/device/driverlib/ecap.c | 61 + gpio_bitfield_cpu2/device/driverlib/ecap.h | 1164 +++ gpio_bitfield_cpu2/device/driverlib/emif.c | 46 + gpio_bitfield_cpu2/device/driverlib/emif.h | 1369 +++ gpio_bitfield_cpu2/device/driverlib/epwm.c | 363 + gpio_bitfield_cpu2/device/driverlib/epwm.h | 7496 +++++++++++++++++ gpio_bitfield_cpu2/device/driverlib/eqep.c | 149 + gpio_bitfield_cpu2/device/driverlib/eqep.h | 1691 ++++ gpio_bitfield_cpu2/device/driverlib/flash.c | 175 + gpio_bitfield_cpu2/device/driverlib/flash.h | 1671 ++++ gpio_bitfield_cpu2/device/driverlib/gpio.c | 489 ++ gpio_bitfield_cpu2/device/driverlib/gpio.h | 1047 +++ gpio_bitfield_cpu2/device/driverlib/hrpwm.c | 47 + gpio_bitfield_cpu2/device/driverlib/hrpwm.h | 1657 ++++ .../driverlib/hw_reg_inclusive_terminology.h | 29 + gpio_bitfield_cpu2/device/driverlib/i2c.c | 351 + gpio_bitfield_cpu2/device/driverlib/i2c.h | 1386 +++ .../device/driverlib/inc/hw_adc.h | 911 ++ .../device/driverlib/inc/hw_asysctl.h | 145 + .../device/driverlib/inc/hw_can.h | 514 ++ .../device/driverlib/inc/hw_cla.h | 241 + .../device/driverlib/inc/hw_clb.h | 661 ++ .../device/driverlib/inc/hw_clbxbar.h | 1272 +++ .../device/driverlib/inc/hw_cmpss.h | 235 + .../device/driverlib/inc/hw_cputimer.h | 112 + .../device/driverlib/inc/hw_dac.h | 122 + .../device/driverlib/inc/hw_dcsm.h | 442 + .../device/driverlib/inc/hw_dma.h | 165 + .../device/driverlib/inc/hw_ecap.h | 157 + .../device/driverlib/inc/hw_emif.h | 259 + .../device/driverlib/inc/hw_epwm.h | 1050 +++ .../device/driverlib/inc/hw_epwmxbar.h | 1192 +++ .../device/driverlib/inc/hw_eqep.h | 225 + .../device/driverlib/inc/hw_flash.h | 286 + .../device/driverlib/inc/hw_gpio.h | 4018 +++++++++ .../device/driverlib/inc/hw_hic.h | 344 + .../device/driverlib/inc/hw_hrpwm.h | 1058 +++ .../device/driverlib/inc/hw_i2c.h | 208 + .../device/driverlib/inc/hw_inputxbar.h | 92 + .../device/driverlib/inc/hw_ints.h | 212 + .../device/driverlib/inc/hw_ipc.h | 323 + .../device/driverlib/inc/hw_mcbsp.h | 286 + .../device/driverlib/inc/hw_memcfg.h | 870 ++ .../device/driverlib/inc/hw_memmap.h | 208 + .../device/driverlib/inc/hw_nmi.h | 134 + .../device/driverlib/inc/hw_otp.h | 63 + .../device/driverlib/inc/hw_outputxbar.h | 1340 +++ .../device/driverlib/inc/hw_pie.h | 636 ++ .../device/driverlib/inc/hw_sci.h | 209 + .../device/driverlib/inc/hw_sdfm.h | 431 + .../device/driverlib/inc/hw_spi.h | 157 + .../device/driverlib/inc/hw_sysctl.h | 1428 ++++ .../device/driverlib/inc/hw_types.h | 166 + .../device/driverlib/inc/hw_upp.h | 306 + .../device/driverlib/inc/hw_usb.h | 4614 ++++++++++ .../device/driverlib/inc/hw_xbar.h | 271 + .../device/driverlib/inc/hw_xint.h | 108 + .../device/driverlib/interrupt.c | 425 + .../device/driverlib/interrupt.h | 497 ++ gpio_bitfield_cpu2/device/driverlib/ipc.c | 445 + gpio_bitfield_cpu2/device/driverlib/ipc.h | 880 ++ gpio_bitfield_cpu2/device/driverlib/mcbsp.c | 1621 ++++ gpio_bitfield_cpu2/device/driverlib/mcbsp.h | 3340 ++++++++ gpio_bitfield_cpu2/device/driverlib/memcfg.c | 701 ++ gpio_bitfield_cpu2/device/driverlib/memcfg.h | 1266 +++ gpio_bitfield_cpu2/device/driverlib/pin_map.h | 894 ++ .../device/driverlib/pin_map_legacy.h | 95 + gpio_bitfield_cpu2/device/driverlib/sci.c | 421 + gpio_bitfield_cpu2/device/driverlib/sci.h | 1646 ++++ gpio_bitfield_cpu2/device/driverlib/sdfm.c | 188 + gpio_bitfield_cpu2/device/driverlib/sdfm.h | 1178 +++ gpio_bitfield_cpu2/device/driverlib/spi.c | 661 ++ gpio_bitfield_cpu2/device/driverlib/spi.h | 1743 ++++ gpio_bitfield_cpu2/device/driverlib/sysctl.c | 1469 ++++ gpio_bitfield_cpu2/device/driverlib/sysctl.h | 3531 ++++++++ gpio_bitfield_cpu2/device/driverlib/upp.c | 298 + gpio_bitfield_cpu2/device/driverlib/upp.h | 1574 ++++ gpio_bitfield_cpu2/device/driverlib/usb.c | 4018 +++++++++ gpio_bitfield_cpu2/device/driverlib/usb.h | 560 ++ gpio_bitfield_cpu2/device/driverlib/version.c | 54 + gpio_bitfield_cpu2/device/driverlib/version.h | 101 + gpio_bitfield_cpu2/device/driverlib/xbar.c | 255 + gpio_bitfield_cpu2/device/driverlib/xbar.h | 1294 +++ gpio_bitfield_cpu2/gpio_bitfield_cpu2.c | 0 .../targetConfigs/TMS320F28377D.ccxml | 22 + gpio_bitfield_cpu2/targetConfigs/readme.txt | 9 + gpio_driverlib_cpu1/.ccsproject | 12 + gpio_driverlib_cpu1/.clangd | 8 + gpio_driverlib_cpu1/.cproject | 185 + gpio_driverlib_cpu1/.project | 33 + .../org.eclipse.cdt.codan.core.prefs | 3 + .../org.eclipse.core.resources.prefs | 9 + gpio_driverlib_cpu1/2837xD_FLASH_lnk_cpu1.cmd | 176 + gpio_driverlib_cpu1/2837xD_RAM_lnk_cpu1.cmd | 141 + ...D_CodeStartBranch.asm.9982C06611A2C0D7.idx | Bin 0 -> 1024 bytes .../index/device.c.E7CB02094E34E1A6.idx | Bin 0 -> 11802 bytes .../index/device.h.E9CAB133E05C7633.idx | Bin 0 -> 3210 bytes .../index/driverlib.h.87B503574AD85612.idx | Bin 0 -> 860 bytes ...gpio_driverlib_cpu1.c.23D1B9BF748D0959.idx | Bin 0 -> 790 bytes .../CPU1_RAM/.clangd/compile_commands.json | 17 + gpio_driverlib_cpu1/CPU1_RAM/ccsObjs.opt | 6 + .../device/F2837xD_CodeStartBranch.obj | Bin 0 -> 3828 bytes gpio_driverlib_cpu1/CPU1_RAM/device/device.d | 267 + .../CPU1_RAM/device/device.obj | Bin 0 -> 28520 bytes .../CPU1_RAM/device/subdir_rules.mk | 18 + .../CPU1_RAM/device/subdir_vars.mk | 38 + .../CPU1_RAM/gpio_driverlib_cpu1.d | 267 + .../CPU1_RAM/gpio_driverlib_cpu1.map | 360 + .../CPU1_RAM/gpio_driverlib_cpu1.obj | Bin 0 -> 7992 bytes .../CPU1_RAM/gpio_driverlib_cpu1.out | Bin 0 -> 57756 bytes .../CPU1_RAM/gpio_driverlib_cpu1_linkInfo.xml | 4696 +++++++++++ gpio_driverlib_cpu1/CPU1_RAM/makefile | 149 + gpio_driverlib_cpu1/CPU1_RAM/objects.mk | 8 + gpio_driverlib_cpu1/CPU1_RAM/sources.mk | 110 + gpio_driverlib_cpu1/CPU1_RAM/subdir_rules.mk | 12 + gpio_driverlib_cpu1/CPU1_RAM/subdir_vars.mk | 30 + .../device/F2837xD_CodeStartBranch.asm | 112 + gpio_driverlib_cpu1/device/device.c | 706 ++ gpio_driverlib_cpu1/device/device.h | 394 + gpio_driverlib_cpu1/device/driverlib.h | 87 + gpio_driverlib_cpu1/device/driverlib/adc.c | 342 + gpio_driverlib_cpu1/device/driverlib/adc.h | 2098 +++++ .../device/driverlib/asysctl.c | 43 + .../device/driverlib/asysctl.h | 160 + gpio_driverlib_cpu1/device/driverlib/can.c | 1122 +++ gpio_driverlib_cpu1/device/driverlib/can.h | 1924 +++++ .../device/driverlib/ccs/Debug/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Debug/driverlib_coff.lib | Bin 0 -> 575952 bytes .../driverlib/ccs/Debug/driverlib_eabi.lib | Bin 0 -> 1003104 bytes .../driverlib/ccs/Release/driverlib.lib | Bin 0 -> 698 bytes .../driverlib/ccs/Release/driverlib_coff.lib | Bin 0 -> 375766 bytes .../driverlib/ccs/Release/driverlib_eabi.lib | Bin 0 -> 654036 bytes .../driverlib/ccs/driverlib.projectspec | 46 + gpio_driverlib_cpu1/device/driverlib/cla.c | 89 + gpio_driverlib_cpu1/device/driverlib/cla.h | 984 +++ gpio_driverlib_cpu1/device/driverlib/clb.c | 145 + gpio_driverlib_cpu1/device/driverlib/clb.h | 1290 +++ gpio_driverlib_cpu1/device/driverlib/cmpss.c | 223 + gpio_driverlib_cpu1/device/driverlib/cmpss.h | 1325 +++ gpio_driverlib_cpu1/device/driverlib/cpu.h | 172 + .../device/driverlib/cputimer.c | 61 + .../device/driverlib/cputimer.h | 509 ++ gpio_driverlib_cpu1/device/driverlib/dac.c | 93 + gpio_driverlib_cpu1/device/driverlib/dac.h | 604 ++ gpio_driverlib_cpu1/device/driverlib/dcsm.c | 377 + gpio_driverlib_cpu1/device/driverlib/dcsm.h | 669 ++ gpio_driverlib_cpu1/device/driverlib/debug.h | 91 + gpio_driverlib_cpu1/device/driverlib/dma.c | 370 + gpio_driverlib_cpu1/device/driverlib/dma.h | 1171 +++ .../driver_inclusive_terminology_mapping.h | 109 + gpio_driverlib_cpu1/device/driverlib/ecap.c | 61 + gpio_driverlib_cpu1/device/driverlib/ecap.h | 1164 +++ gpio_driverlib_cpu1/device/driverlib/emif.c | 46 + gpio_driverlib_cpu1/device/driverlib/emif.h | 1369 +++ gpio_driverlib_cpu1/device/driverlib/epwm.c | 363 + gpio_driverlib_cpu1/device/driverlib/epwm.h | 7496 +++++++++++++++++ gpio_driverlib_cpu1/device/driverlib/eqep.c | 149 + gpio_driverlib_cpu1/device/driverlib/eqep.h | 1691 ++++ gpio_driverlib_cpu1/device/driverlib/flash.c | 175 + gpio_driverlib_cpu1/device/driverlib/flash.h | 1671 ++++ gpio_driverlib_cpu1/device/driverlib/gpio.c | 489 ++ gpio_driverlib_cpu1/device/driverlib/gpio.h | 1047 +++ gpio_driverlib_cpu1/device/driverlib/hrpwm.c | 47 + gpio_driverlib_cpu1/device/driverlib/hrpwm.h | 1657 ++++ .../driverlib/hw_reg_inclusive_terminology.h | 29 + gpio_driverlib_cpu1/device/driverlib/i2c.c | 351 + gpio_driverlib_cpu1/device/driverlib/i2c.h | 1386 +++ .../device/driverlib/inc/hw_adc.h | 911 ++ .../device/driverlib/inc/hw_asysctl.h | 145 + .../device/driverlib/inc/hw_can.h | 514 ++ .../device/driverlib/inc/hw_cla.h | 241 + .../device/driverlib/inc/hw_clb.h | 661 ++ .../device/driverlib/inc/hw_clbxbar.h | 1272 +++ .../device/driverlib/inc/hw_cmpss.h | 235 + .../device/driverlib/inc/hw_cputimer.h | 112 + .../device/driverlib/inc/hw_dac.h | 122 + .../device/driverlib/inc/hw_dcsm.h | 442 + .../device/driverlib/inc/hw_dma.h | 165 + .../device/driverlib/inc/hw_ecap.h | 157 + .../device/driverlib/inc/hw_emif.h | 259 + .../device/driverlib/inc/hw_epwm.h | 1050 +++ .../device/driverlib/inc/hw_epwmxbar.h | 1192 +++ .../device/driverlib/inc/hw_eqep.h | 225 + .../device/driverlib/inc/hw_flash.h | 286 + .../device/driverlib/inc/hw_gpio.h | 4018 +++++++++ .../device/driverlib/inc/hw_hic.h | 344 + .../device/driverlib/inc/hw_hrpwm.h | 1058 +++ .../device/driverlib/inc/hw_i2c.h | 208 + .../device/driverlib/inc/hw_inputxbar.h | 92 + .../device/driverlib/inc/hw_ints.h | 212 + .../device/driverlib/inc/hw_ipc.h | 323 + .../device/driverlib/inc/hw_mcbsp.h | 286 + .../device/driverlib/inc/hw_memcfg.h | 870 ++ .../device/driverlib/inc/hw_memmap.h | 208 + .../device/driverlib/inc/hw_nmi.h | 134 + .../device/driverlib/inc/hw_otp.h | 63 + .../device/driverlib/inc/hw_outputxbar.h | 1340 +++ .../device/driverlib/inc/hw_pie.h | 636 ++ .../device/driverlib/inc/hw_sci.h | 209 + .../device/driverlib/inc/hw_sdfm.h | 431 + .../device/driverlib/inc/hw_spi.h | 157 + .../device/driverlib/inc/hw_sysctl.h | 1428 ++++ .../device/driverlib/inc/hw_types.h | 166 + .../device/driverlib/inc/hw_upp.h | 306 + .../device/driverlib/inc/hw_usb.h | 4614 ++++++++++ .../device/driverlib/inc/hw_xbar.h | 271 + .../device/driverlib/inc/hw_xint.h | 108 + .../device/driverlib/interrupt.c | 425 + .../device/driverlib/interrupt.h | 497 ++ gpio_driverlib_cpu1/device/driverlib/ipc.c | 445 + gpio_driverlib_cpu1/device/driverlib/ipc.h | 880 ++ gpio_driverlib_cpu1/device/driverlib/mcbsp.c | 1621 ++++ gpio_driverlib_cpu1/device/driverlib/mcbsp.h | 3340 ++++++++ gpio_driverlib_cpu1/device/driverlib/memcfg.c | 701 ++ gpio_driverlib_cpu1/device/driverlib/memcfg.h | 1266 +++ .../device/driverlib/pin_map.h | 894 ++ .../device/driverlib/pin_map_legacy.h | 95 + gpio_driverlib_cpu1/device/driverlib/sci.c | 421 + gpio_driverlib_cpu1/device/driverlib/sci.h | 1646 ++++ gpio_driverlib_cpu1/device/driverlib/sdfm.c | 188 + gpio_driverlib_cpu1/device/driverlib/sdfm.h | 1178 +++ gpio_driverlib_cpu1/device/driverlib/spi.c | 661 ++ gpio_driverlib_cpu1/device/driverlib/spi.h | 1743 ++++ gpio_driverlib_cpu1/device/driverlib/sysctl.c | 1469 ++++ gpio_driverlib_cpu1/device/driverlib/sysctl.h | 3531 ++++++++ gpio_driverlib_cpu1/device/driverlib/upp.c | 298 + gpio_driverlib_cpu1/device/driverlib/upp.h | 1574 ++++ gpio_driverlib_cpu1/device/driverlib/usb.c | 4018 +++++++++ gpio_driverlib_cpu1/device/driverlib/usb.h | 560 ++ .../device/driverlib/version.c | 54 + .../device/driverlib/version.h | 101 + gpio_driverlib_cpu1/device/driverlib/xbar.c | 255 + gpio_driverlib_cpu1/device/driverlib/xbar.h | 1294 +++ gpio_driverlib_cpu1/gpio_driverlib_cpu1.c | 0 .../targetConfigs/TMS320F28377D.ccxml | 22 + gpio_driverlib_cpu1/targetConfigs/readme.txt | 9 + 284 files changed, 185385 insertions(+) create mode 100644 gpio_bitfield_cpu2/.ccsproject create mode 100644 gpio_bitfield_cpu2/.clangd create mode 100644 gpio_bitfield_cpu2/.cproject create mode 100644 gpio_bitfield_cpu2/.project create mode 100644 gpio_bitfield_cpu2/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 gpio_bitfield_cpu2/.settings/org.eclipse.core.resources.prefs create mode 100644 gpio_bitfield_cpu2/2837xD_FLASH_lnk_cpu2.cmd create mode 100644 gpio_bitfield_cpu2/2837xD_RAM_lnk_cpu2.cmd create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.4EE093348ADEE433.idx create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.c.0B89A1F1F3993A3F.idx create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/device.h.FC78F7DABF8D1C4D.idx create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/driverlib.h.BEE08E1C139315B9.idx create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/.cache/clangd/index/gpio_bitfield_cpu2.c.3F85F893C12398EA.idx create mode 100644 gpio_bitfield_cpu2/CPU2_RAM/.clangd/compile_commands.json create mode 100644 gpio_bitfield_cpu2/device/F2837xD_CodeStartBranch.asm create mode 100644 gpio_bitfield_cpu2/device/device.c create mode 100644 gpio_bitfield_cpu2/device/device.h create mode 100644 gpio_bitfield_cpu2/device/driverlib.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/adc.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/adc.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/asysctl.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/asysctl.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/can.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/can.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Debug/driverlib.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Debug/driverlib_coff.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Debug/driverlib_eabi.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Release/driverlib.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Release/driverlib_coff.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/Release/driverlib_eabi.lib create mode 100644 gpio_bitfield_cpu2/device/driverlib/ccs/driverlib.projectspec create mode 100644 gpio_bitfield_cpu2/device/driverlib/cla.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/cla.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/clb.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/clb.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/cmpss.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/cmpss.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/cpu.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/cputimer.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/cputimer.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/dac.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/dac.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/dcsm.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/dcsm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/debug.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/dma.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/dma.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/ecap.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/ecap.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/emif.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/emif.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/epwm.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/epwm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/eqep.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/eqep.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/flash.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/flash.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/gpio.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/gpio.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/hrpwm.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/hrpwm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/hw_reg_inclusive_terminology.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/i2c.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/i2c.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_adc.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_asysctl.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_can.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_cla.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_clb.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_clbxbar.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_cmpss.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_cputimer.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_dac.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_dcsm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_dma.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_ecap.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_emif.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_epwm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_epwmxbar.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_eqep.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_flash.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_gpio.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_hic.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_hrpwm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_i2c.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_inputxbar.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_ints.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_ipc.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_mcbsp.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_memcfg.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_memmap.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_nmi.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_otp.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_outputxbar.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_pie.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_sci.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_sdfm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_spi.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_sysctl.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_types.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_upp.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_usb.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_xbar.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/inc/hw_xint.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/interrupt.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/interrupt.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/ipc.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/ipc.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/mcbsp.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/mcbsp.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/memcfg.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/memcfg.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/pin_map.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/pin_map_legacy.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/sci.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/sci.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/sdfm.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/sdfm.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/spi.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/spi.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/sysctl.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/sysctl.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/upp.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/upp.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/usb.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/usb.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/version.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/version.h create mode 100644 gpio_bitfield_cpu2/device/driverlib/xbar.c create mode 100644 gpio_bitfield_cpu2/device/driverlib/xbar.h create mode 100644 gpio_bitfield_cpu2/gpio_bitfield_cpu2.c create mode 100644 gpio_bitfield_cpu2/targetConfigs/TMS320F28377D.ccxml create mode 100644 gpio_bitfield_cpu2/targetConfigs/readme.txt create mode 100644 gpio_driverlib_cpu1/.ccsproject create mode 100644 gpio_driverlib_cpu1/.clangd create mode 100644 gpio_driverlib_cpu1/.cproject create mode 100644 gpio_driverlib_cpu1/.project create mode 100644 gpio_driverlib_cpu1/.settings/org.eclipse.cdt.codan.core.prefs create mode 100644 gpio_driverlib_cpu1/.settings/org.eclipse.core.resources.prefs create mode 100644 gpio_driverlib_cpu1/2837xD_FLASH_lnk_cpu1.cmd create mode 100644 gpio_driverlib_cpu1/2837xD_RAM_lnk_cpu1.cmd create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/F2837xD_CodeStartBranch.asm.9982C06611A2C0D7.idx create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.c.E7CB02094E34E1A6.idx create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/device.h.E9CAB133E05C7633.idx create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/driverlib.h.87B503574AD85612.idx create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/.cache/clangd/index/gpio_driverlib_cpu1.c.23D1B9BF748D0959.idx create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/.clangd/compile_commands.json create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/ccsObjs.opt create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/device/F2837xD_CodeStartBranch.obj create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/device/device.d create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/device/device.obj create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/device/subdir_rules.mk create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/device/subdir_vars.mk create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/gpio_driverlib_cpu1.d create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/gpio_driverlib_cpu1.map create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/gpio_driverlib_cpu1.obj create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/gpio_driverlib_cpu1.out create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/gpio_driverlib_cpu1_linkInfo.xml create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/makefile create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/objects.mk create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/sources.mk create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/subdir_rules.mk create mode 100644 gpio_driverlib_cpu1/CPU1_RAM/subdir_vars.mk create mode 100644 gpio_driverlib_cpu1/device/F2837xD_CodeStartBranch.asm create mode 100644 gpio_driverlib_cpu1/device/device.c create mode 100644 gpio_driverlib_cpu1/device/device.h create mode 100644 gpio_driverlib_cpu1/device/driverlib.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/adc.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/adc.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/asysctl.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/asysctl.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/can.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/can.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Debug/driverlib.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Debug/driverlib_coff.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Debug/driverlib_eabi.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Release/driverlib.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Release/driverlib_coff.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/Release/driverlib_eabi.lib create mode 100644 gpio_driverlib_cpu1/device/driverlib/ccs/driverlib.projectspec create mode 100644 gpio_driverlib_cpu1/device/driverlib/cla.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/cla.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/clb.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/clb.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/cmpss.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/cmpss.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/cpu.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/cputimer.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/cputimer.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/dac.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/dac.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/dcsm.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/dcsm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/debug.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/dma.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/dma.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/ecap.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/ecap.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/emif.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/emif.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/epwm.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/epwm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/eqep.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/eqep.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/flash.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/flash.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/gpio.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/gpio.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/hrpwm.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/hrpwm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/hw_reg_inclusive_terminology.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/i2c.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/i2c.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_adc.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_asysctl.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_can.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_cla.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_clb.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_clbxbar.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_cmpss.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_cputimer.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_dac.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_dcsm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_dma.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_ecap.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_emif.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_epwm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_epwmxbar.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_eqep.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_flash.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_gpio.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_hic.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_hrpwm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_i2c.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_inputxbar.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_ints.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_ipc.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_mcbsp.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_memcfg.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_memmap.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_nmi.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_otp.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_outputxbar.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_pie.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_sci.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_sdfm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_spi.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_sysctl.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_types.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_upp.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_usb.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_xbar.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/inc/hw_xint.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/interrupt.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/interrupt.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/ipc.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/ipc.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/mcbsp.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/mcbsp.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/memcfg.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/memcfg.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/pin_map.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/pin_map_legacy.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/sci.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/sci.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/sdfm.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/sdfm.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/spi.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/spi.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/sysctl.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/sysctl.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/upp.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/upp.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/usb.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/usb.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/version.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/version.h create mode 100644 gpio_driverlib_cpu1/device/driverlib/xbar.c create mode 100644 gpio_driverlib_cpu1/device/driverlib/xbar.h create mode 100644 gpio_driverlib_cpu1/gpio_driverlib_cpu1.c create mode 100644 gpio_driverlib_cpu1/targetConfigs/TMS320F28377D.ccxml create mode 100644 gpio_driverlib_cpu1/targetConfigs/readme.txt diff --git a/gpio_bitfield_cpu2/.ccsproject b/gpio_bitfield_cpu2/.ccsproject new file mode 100644 index 0000000..e089904 --- /dev/null +++ b/gpio_bitfield_cpu2/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu2/.clangd b/gpio_bitfield_cpu2/.clangd new file mode 100644 index 0000000..657a761 --- /dev/null +++ b/gpio_bitfield_cpu2/.clangd @@ -0,0 +1,8 @@ +# This is an auto-generated file - do not add it to source-control + +CompileFlags: + CompilationDatabase: CPU2_RAM/.clangd + +Diagnostics: + Suppress: '*' + diff --git a/gpio_bitfield_cpu2/.cproject b/gpio_bitfield_cpu2/.cproject new file mode 100644 index 0000000..377ea92 --- /dev/null +++ b/gpio_bitfield_cpu2/.cproject @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu2/.project b/gpio_bitfield_cpu2/.project new file mode 100644 index 0000000..e46a80f --- /dev/null +++ b/gpio_bitfield_cpu2/.project @@ -0,0 +1,33 @@ + + + gpio_bitfield_cpu2 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + + + + driverlib.lib + 1 + COM_TI_C2000WARE_INSTALL_DIR/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_INSTALL_DIR%7D/driverlib/f2837xd/driverlib + + + diff --git a/gpio_bitfield_cpu2/.settings/org.eclipse.cdt.codan.core.prefs b/gpio_bitfield_cpu2/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/gpio_bitfield_cpu2/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/gpio_bitfield_cpu2/.settings/org.eclipse.core.resources.prefs b/gpio_bitfield_cpu2/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..99f26c0 --- /dev/null +++ b/gpio_bitfield_cpu2/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,2 @@ +eclipse.preferences.version=1 +encoding/=UTF-8 diff --git a/gpio_bitfield_cpu2/2837xD_FLASH_lnk_cpu2.cmd b/gpio_bitfield_cpu2/2837xD_FLASH_lnk_cpu2.cmd new file mode 100644 index 0000000..8c6a609 --- /dev/null +++ b/gpio_bitfield_cpu2/2837xD_FLASH_lnk_cpu2.cmd @@ -0,0 +1,148 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x0000A2, length = 0x00035E + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(8) + .text : > FLASHB PAGE = 0, ALIGN(8) + codestart : > BEGIN PAGE = 0, ALIGN(8) + + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + + /* Initalized sections go in Flash */ + .switch : > FLASHB PAGE = 0, ALIGN(8) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + +#if defined(__TI_EABI__) + .init_array : > FLASHB, PAGE = 0, ALIGN(8) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : > FLASHF, PAGE = 0, ALIGN(8) +#else + .pinit : > FLASHB, PAGE = 0, ALIGN(8) + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : >> FLASHF PAGE = 0, ALIGN(8) +#endif + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #if defined(__TI_EABI__) + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #else + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_bitfield_cpu2/2837xD_RAM_lnk_cpu2.cmd b/gpio_bitfield_cpu2/2837xD_RAM_lnk_cpu2.cmd new file mode 100644 index 0000000..bca4726 --- /dev/null +++ b/gpio_bitfield_cpu2/2837xD_RAM_lnk_cpu2.cmd @@ -0,0 +1,104 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x0000A2, length = 0x00035E + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x0000A0 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >>RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .stack : > RAMM1, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .init_array : > RAMM0, PAGE = 0 + .const : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 +#endif + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + 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zX#SM%b9MF>bnW9S&7GU!C-h@|$=YAMVe4cH7>X-%lYoKDP?VZhEDoe^3k5RDi~T#s z$fcsip#=(m2q;R;Nd&Qqi;|1i17m}MA0iGSxe!c{5m3MmV=yo%BA9##CO3j9hG4QH zn1TqV0)h!j7f>JsV=ypCBbXuxCNMd{fCP-ez#xZU$|INvzcNT6M3oRsP6U$;!4yR> zfe91_WMB*i21x`{7Qy62FhQXS1spI21A{VxDS%)y!I?}dUWX-8ja-Gy-U)R^K+^v1;G+yM9!DNxmR&6Q86g{WxVfdYftSJ*%fkXRzgX* zw{W&|Son+IN&8eeet!-5~SG!K-uJXAp5Bl6U-TYSDz3~;k_X1l-|$z}50~<{ z@qpq=$eh)j6HEYQAfPBUtymn$gsEfXLYL1;1gR`8N-kCg(#%4UMnbVa6kk1L5)@z% j07*fBAdJDlker*61Crt6<7Hy!U}a-r=H}w$VdMt@LL%(N literal 0 HcmV?d00001 diff --git a/gpio_bitfield_cpu2/CPU2_RAM/.clangd/compile_commands.json b/gpio_bitfield_cpu2/CPU2_RAM/.clangd/compile_commands.json new file mode 100644 index 0000000..41fff5e --- /dev/null +++ b/gpio_bitfield_cpu2/CPU2_RAM/.clangd/compile_commands.json @@ -0,0 +1,17 @@ +[ + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/CPU2_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -DDEBUG -DCPU1", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/device/F2837xD_CodeStartBranch.asm" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/CPU2_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -DDEBUG -DCPU1 -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/device/device.c" + }, + { + "directory" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/CPU2_RAM", + "command" : "clang++ -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2\" -I\"/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/device\" -I\"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/\" -I\"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include\" -DDEBUG -DCPU1 -xc", + "file" : "/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_bitfield_cpu2/gpio_bitfield_cpu2.c" + } +] diff --git a/gpio_bitfield_cpu2/device/F2837xD_CodeStartBranch.asm b/gpio_bitfield_cpu2/device/F2837xD_CodeStartBranch.asm new file mode 100644 index 0000000..1fdab30 --- /dev/null +++ b/gpio_bitfield_cpu2/device/F2837xD_CodeStartBranch.asm @@ -0,0 +1,112 @@ +;//########################################################################### +;// +;// FILE: F2837xD_CodeStartBranch.asm +;// +;// TITLE: Branch for redirecting code execution after boot. +;// +;// For these examples, code_start is the first code that is executed after +;// exiting the boot ROM code. +;// +;// The codestart section in the linker cmd file is used to physically place +;// this code at the correct memory location. This section should be placed +;// at the location the BOOT ROM will re-direct the code to. For example, +;// for boot to FLASH this code will be located at 0x3f7ff6. +;// +;// In addition, the example F2837xD projects are setup such that the codegen +;// entry point is also set to the code_start label. This is done by linker +;// option -e in the project build options. When the debugger loads the code, +;// it will automatically set the PC to the "entry point" address indicated by +;// the -e linker option. In this case the debugger is simply assigning the PC, +;// it is not the same as a full reset of the device. +;// +;// The compiler may warn that the entry point for the project is other then +;// _c_init00. _c_init00 is the C environment setup and is run before +;// main() is entered. The code_start code will re-direct the execution +;// to _c_init00 and thus there is no worry and this warning can be ignored. +;// +;//########################################################################### +;// +;// $Release Date: $ +;// $Copyright: +;// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +;// +;// Redistribution and use in source and binary forms, with or without +;// modification, are permitted provided that the following conditions +;// are met: +;// +;// Redistributions of source code must retain the above copyright +;// notice, this list of conditions and the following disclaimer. +;// +;// Redistributions in binary form must reproduce the above copyright +;// notice, this list of conditions and the following disclaimer in the +;// documentation and/or other materials provided with the +;// distribution. +;// +;// Neither the name of Texas Instruments Incorporated nor the names of +;// its contributors may be used to endorse or promote products derived +;// from this software without specific prior written permission. +;// +;// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +;// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +;// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +;// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +;// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +;// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +;// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +;// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +;// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +;// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;// $ +;//########################################################################### + +*********************************************************************** + +WD_DISABLE .set 1 ;set to 1 to disable WD, else set to 0 + + .ref _c_int00 + .global code_start + +*********************************************************************** +* Function: codestart section +* +* Description: Branch to code starting point +*********************************************************************** + + .sect "codestart" + .retain + +code_start: + .if WD_DISABLE == 1 + LB wd_disable ;Branch to watchdog disable code + .else + LB _c_int00 ;Branch to start of boot._asm in RTS library + .endif + +;end codestart section + +*********************************************************************** +* Function: wd_disable +* +* Description: Disables the watchdog timer +*********************************************************************** + .if WD_DISABLE == 1 + + .text +wd_disable: + SETC OBJMODE ;Set OBJMODE for 28x object code + EALLOW ;Enable EALLOW protected register access + MOVZ DP, #7029h>>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/gpio_bitfield_cpu2/device/device.c b/gpio_bitfield_cpu2/device/device.c new file mode 100644 index 0000000..b64b33d --- /dev/null +++ b/gpio_bitfield_cpu2/device/device.c @@ -0,0 +1,706 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#include "inc/hw_ipc.h" + +#ifdef CMDTOOL +#include "device_cmd.h" +#endif + +#ifdef __cplusplus +using std::memcpy; +#endif + +#define PASS 0 +#define FAIL 1 + +uint32_t Example_Result = FAIL; +uint32_t Example_PassCount = 0; +uint32_t Example_Fail = 0; + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef CMDTOOL + CMD_init(); +#endif + +#ifdef _FLASH +#ifndef CMDTOOL + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); +#endif + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + + // + // Configure Analog Trim in case of untrimmed or TMX sample + // + if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) && + (HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U)) + { + Device_configureTMXAnalogTrim(); + } + + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the Device_init function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // Sysctl_deviceCal is a wrapper function for Device_Cal + // + SysCtl_deviceCal(); +#endif + +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); + + // + // Initialize result parameter as FAIL + // + Example_Result = FAIL; +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +#ifdef CPU1 +//***************************************************************************** +// +// Function to implement Analog trim of TMX devices +// +//***************************************************************************** +void Device_configureTMXAnalogTrim(void) +{ + // + // Enable ADC clock + // + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + // + // Configure ADC reference trim for TMX devices + // + EALLOW; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU; + + // + // Configure ADC offset trim. The user should generate the trim values + // by following the instructions in the "ADC Zero Offset Calibration" + // section in device TRM. The below lines needs to be uncommented and + // updated with the correct trim values. + // +// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U; + + // + // Configure internal oscillator trim. If the internal oscillator trim + // contains all zeros, the user can adjust the lowest 10 bits of the + // oscillator trim register between 1 (minimum) and 1023 (maximum) + // while observing the system clock on the XCLOCKOUT pin. The below + // lines needs to be uncommented and updated with the correct trim values. + // +// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U; +// } +// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U; +// } + + EDIS; + + // + // Disable ADC clock + // + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD); +} + +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +Device_bootCPU2(uint32_t bootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) & + 0x80000000U)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & + C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) || + ((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U)) + { + + } + + if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (bootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + // + //SCIA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_29_SCITXDA); + GPIO_setMasterCore(29, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setMasterCore(28, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + + // + //SPI-A connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + EDIS; + + GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_16_SPISIMOA); + GPIO_setMasterCore(16, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_17_SPISOMIA); + GPIO_setMasterCore(17, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_18_SPICLKA); + GPIO_setMasterCore(18, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_19_GPIO19); + GPIO_setMasterCore(19, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + + // + //I2CA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_32_SDAA); + GPIO_setMasterCore(32, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_33_SCLA); + GPIO_setMasterCore(33, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC); + GPIO_setMasterCore(pin, GPIO_CORE_CPU2); + } + + GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_69_GPIO69); + GPIO_setMasterCore(69, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_70_GPIO70); + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + GPIO_setMasterCore(71, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_71_CANTXA); + GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC); + + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_70_CANRXA); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + + + GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + // + // Set CANA Bit-Clock Source Select = SYSCLK and enable CAN + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + SYSCTL_CLKSRCCTL2_CANABCLKSEL_M; + EDIS; + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U; + + } + return returnStatus; +} +#endif // #ifdef CPU1 +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(const char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} + +void Example_setResultPass(void) +{ + Example_Result = PASS; +} + +void Example_setResultFail(void) +{ + Example_Result = FAIL; +} + +void Example_done(void) +{ + while(1); +} diff --git a/gpio_bitfield_cpu2/device/device.h b/gpio_bitfield_cpu2/device/device.h new file mode 100644 index 0000000..ec143e5 --- /dev/null +++ b/gpio_bitfield_cpu2/device/device.h @@ -0,0 +1,394 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9 +#else +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 +#endif + + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX +#else +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX +#endif + +// +// GPIO assignment for CAN-A and CAN-B +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX +#else +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//I2CA GPIO pins +#define DEVICE_GPIO_PIN_SDAA 104 +#define DEVICE_GPIO_PIN_SCLA 105 + +#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA +#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA + + +//I2CB GPIO pins +#define DEVICE_GPIO_PIN_SDAB 40 +#define DEVICE_GPIO_PIN_SCLB 41 + +#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB +#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB + +#endif + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +// +// The macros that can be used as parameter to the function Device_bootCPU2 +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU + +// +// Other macros that are needed for the Device_bootCPU2 function +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U + +// +// Macros used as return value by the Device_bootCPU2 function +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +extern uint32_t Example_PassCount; +extern uint32_t Example_Fail; + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup device_api +//! @{ +// +//***************************************************************************** +//***************************************************************************** +// +//! @brief Function to initialize the device. Primarily initializes system control to a +//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +//! and enabling the clocks to the peripherals. +//! +//! \param None. +//! \return None. +// +//***************************************************************************** +extern void Device_init(void); +//***************************************************************************** +//! +//! +//! @brief Function to turn on all peripherals, enabling reads and writes to the +//! peripherals' registers. +//! +//! Note that to reduce power, unused peripherals should be disabled. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableAllPeripherals(void); +//***************************************************************************** +//! +//! +//! @brief Function to disable pin locks on GPIOs. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_initGPIO(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package: +//! GPIOs Grp Bits +//! 95-132 C 31 +//! D 31:0 +//! E 4:0 +//! 134-168 E 31:6 +//! F 8:0 +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package: +//! GPIOs Grp Bits +//! 0-1 A 1:0 +//! 5-9 A 9:5 +//! 22-40 A 31:22 +//! B 8:0 +//! 44-57 B 25:12 +//! 67-68 C 4:3 +//! 74-77 C 13:10 +//! 79-83 C 19:15 +//! 93-168 C 31:29 +//! D 31:0 +//! E 31:0 +//! F 8:0 +//! @param None +//! @return None +// +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the +//! 176PTP package. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullups(void); +#ifdef CPU1 +//***************************************************************************** +//! +//! @brief Function to implement Analog trim of TMX devices +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_configureTMXAnalogTrim(void); +//***************************************************************************** +//! @brief Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +extern uint16_t Device_bootCPU2(uint32_t ulBootMode); +#endif +//***************************************************************************** +//! +//! @brief Error handling function to be called when an ASSERT is violated +//! +//! @param *filename File name in which the error has occurred +//! @param line Line number within the file +//! @return None +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); +extern void Example_setResultPass(void); +extern void Example_setResultFail(void); +extern void Example_done(void); + +// +// End of file +// diff --git a/gpio_bitfield_cpu2/device/driverlib.h b/gpio_bitfield_cpu2/device/driverlib.h new file mode 100644 index 0000000..932ace6 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib.h @@ -0,0 +1,87 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "clb.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "ipc.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "pin_map_legacy.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#include "driver_inclusive_terminology_mapping.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/gpio_bitfield_cpu2/device/driverlib/adc.c b/gpio_bitfield_cpu2/device/driverlib/adc.c new file mode 100644 index 0000000..9e74809 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/adc.c @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: adc.c +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "adc.h" + +//***************************************************************************** +// +// Defines for locations of ADC calibration functions in OTP for use in +// ADC_setMode() ONLY. Not intended for use by application code. +// +//***************************************************************************** +// +// The following functions calibrate the ADC linearity. Use them in the +// ADC_setMode() function only. +// +#define ADC_calADCAINL 0x0703B4U +#define ADC_calADCBINL 0x0703B2U +#define ADC_calADCCINL 0x0703B0U +#define ADC_calADCDINL 0x0703AEU + +// +// This function looks up the ADC offset trim for a given condition. Use this +// in the ADC_setMode() function only. +// +#define ADC_getOffsetTrim 0x0703ACU + +//***************************************************************************** +// +// ADC_setMode +// +//***************************************************************************** +void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Check for correct signal mode & resolution. In this device: + // Single ended signal conversions are supported in 12-bit mode only + // Differential signal conversions are supported in 16-bit mode only + // + if(signalMode == ADC_MODE_SINGLE_ENDED) + { + ASSERT(resolution == ADC_RESOLUTION_12BIT); + } + else + { + ASSERT(resolution == ADC_RESOLUTION_16BIT); + } + + + // + // Apply the resolution and signalMode to the specified ADC. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) | + ((uint16_t)resolution | (uint16_t)signalMode); + EDIS; + + // + // Apply INL and offset trims + // + ADC_setINLTrim(base); + ADC_setOffsetTrim(base); +} + +//***************************************************************************** +// +// ADC_setINLTrim +// +//***************************************************************************** +void +ADC_setINLTrim(uint32_t base) +{ + ADC_Resolution resolution; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + + EALLOW; + switch(base) + { + case ADCA_BASE: + if(HWREGH(ADC_calADCAINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCAINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCB_BASE: + if(HWREGH(ADC_calADCBINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCBINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCC_BASE: + if(HWREGH(ADC_calADCCINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCCINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCD_BASE: + if(HWREGH(ADC_calADCDINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCDINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + default: + // + // Invalid base address! Do nothing! + // + break; + } + + // + // Apply linearity trim workaround for 12-bit resolution + // + if(resolution == ADC_RESOLUTION_12BIT) + { + // + // 12-bit linearity trim workaround + // + HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U; + } + EDIS; +} + +//***************************************************************************** +// +// ADC_setOffsetTrim +// +//***************************************************************************** +void +ADC_setOffsetTrim(uint32_t base) +{ + uint16_t offsetIndex = 0U; + uint16_t offsetTrim = 0U; + ADC_Resolution resolution; + ADC_SignalMode signalMode; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + signalMode = (ADC_SignalMode) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE); + + switch(base) + { + case ADCA_BASE: + offsetIndex = (uint16_t)(0U * 4U); + break; + case ADCB_BASE: + offsetIndex = (uint16_t)(1U * 4U); + break; + case ADCC_BASE: + offsetIndex = (uint16_t)(2U * 4U); + break; + case ADCD_BASE: + offsetIndex = (uint16_t)(3U * 4U); + break; + default: + // + // Invalid base address! + // + offsetIndex = 0U; + break; + } + + // + // Offset trim function is programmed into OTP, so call it + // + if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU) + { + // + // Calculate the index into OTP table of offset trims and call + // function to return the correct offset trim + // + offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) + + (2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U)); + + offsetTrim = + (*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex); + } + else + { + // + // Offset trim function is not populated, so set offset trim to 0 + // + offsetTrim = 0U; + } + + // + // Apply the offset trim. Offset Trim is not updated here in case of TMX or + // untrimmed devices. The default trims for TMX devices should be handled in + // Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim() + // APIs for more details. + // + if(offsetTrim > 0x0U) + { + EALLOW; + HWREGH(base + ADC_O_OFFTRIM) = offsetTrim; + EDIS; + } +} + + +//***************************************************************************** +// +// ADC_setPPBTripLimits +// +//***************************************************************************** +void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit) +{ + uint32_t ppbHiOffset; + uint32_t ppbLoOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536)); + ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536)); + + // + // Get the offset to the appropriate trip limit registers. + // + ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPHI; + ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPLO; + + EALLOW; + + // + // Set the trip high limit. + // + HWREG(base + ppbHiOffset) = + (HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK); + + // + // Set the trip low limit. + // + HWREG(base + ppbLoOffset) = + (HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK); + + EDIS; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/adc.h b/gpio_bitfield_cpu2/device/driverlib/adc.h new file mode 100644 index 0000000..136638d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/adc.h @@ -0,0 +1,2098 @@ +//########################################################################### +// +// FILE: adc.h +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ADC_H +#define ADC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup adc_api ADC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_adc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define ADC_NUM_INTERRUPTS 4U + +#define ADC_SOCxCTL_OFFSET_BASE ADC_O_SOC0CTL +#define ADC_RESULTx_OFFSET_BASE ADC_O_RESULT0 +#define ADC_INTSELxNy_OFFSET_BASE ADC_O_INTSEL1N2 +#define ADC_PPBxRESULT_OFFSET_BASE ADC_O_PPB1RESULT + + +#define ADC_PPBxCONFIG_STEP (ADC_O_PPB2CONFIG - ADC_O_PPB1CONFIG) +#define ADC_PPBxTRIPHI_STEP (ADC_O_PPB2TRIPHI - ADC_O_PPB1TRIPHI) +#define ADC_PPBxTRIPLO_STEP (ADC_O_PPB2TRIPLO - ADC_O_PPB1TRIPLO) +#define ADC_PPBxOFFCAL_STEP (ADC_O_PPB2OFFCAL - ADC_O_PPB1OFFCAL) +#define ADC_PPBxOFFREF_STEP (ADC_O_PPB2OFFREF - ADC_O_PPB1OFFREF) +#define ADC_PPBxSTAMP_STEP (ADC_O_PPB2STAMP - ADC_O_PPB1STAMP) + +#define ADC_PPBTRIP_MASK ((uint32_t)ADC_PPB1TRIPHI_LIMITHI_M |\ + (uint32_t)ADC_PPB1TRIPHI_HSIGN) +// +// Slope of the temperature sensor based in degrees C in fixed point Q15 format +// +#define ADC_getTempSlope() (*(int16_t (*)(void))0x7036E)() + +// +// Offset of the temp sensor output at 0 degrees C +// +#define ADC_getTempOffset() (*(int16_t (*)(void))0x70372)() + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(), +// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and +// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also +// make up the enumerated bit field returned by ADC_getPPBEventStatus(). +// +//***************************************************************************** +#define ADC_EVT_TRIPHI 0x0001U //!< Trip High Event +#define ADC_EVT_TRIPLO 0x0002U //!< Trip Low Event +#define ADC_EVT_ZERO 0x0004U //!< Zero Crossing Event +#endif + +//***************************************************************************** +// +// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter. +// These values can be OR'd together to trigger multiple SOCs at a time. +// +//***************************************************************************** +#define ADC_FORCE_SOC0 0x0001U //!< SW trigger ADC SOC 0 +#define ADC_FORCE_SOC1 0x0002U //!< SW trigger ADC SOC 1 +#define ADC_FORCE_SOC2 0x0004U //!< SW trigger ADC SOC 2 +#define ADC_FORCE_SOC3 0x0008U //!< SW trigger ADC SOC 3 +#define ADC_FORCE_SOC4 0x0010U //!< SW trigger ADC SOC 4 +#define ADC_FORCE_SOC5 0x0020U //!< SW trigger ADC SOC 5 +#define ADC_FORCE_SOC6 0x0040U //!< SW trigger ADC SOC 6 +#define ADC_FORCE_SOC7 0x0080U //!< SW trigger ADC SOC 7 +#define ADC_FORCE_SOC8 0x0100U //!< SW trigger ADC SOC 8 +#define ADC_FORCE_SOC9 0x0200U //!< SW trigger ADC SOC 9 +#define ADC_FORCE_SOC10 0x0400U //!< SW trigger ADC SOC 10 +#define ADC_FORCE_SOC11 0x0800U //!< SW trigger ADC SOC 11 +#define ADC_FORCE_SOC12 0x1000U //!< SW trigger ADC SOC 12 +#define ADC_FORCE_SOC13 0x2000U //!< SW trigger ADC SOC 13 +#define ADC_FORCE_SOC14 0x4000U //!< SW trigger ADC SOC 14 +#define ADC_FORCE_SOC15 0x8000U //!< SW trigger ADC SOC 15 + + + +//***************************************************************************** +// +//! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_CLK_DIV_1_0 = 0U, //!< ADCCLK = (input clock) / 1.0 + ADC_CLK_DIV_2_0 = 2U, //!< ADCCLK = (input clock) / 2.0 + ADC_CLK_DIV_2_5 = 3U, //!< ADCCLK = (input clock) / 2.5 + ADC_CLK_DIV_3_0 = 4U, //!< ADCCLK = (input clock) / 3.0 + ADC_CLK_DIV_3_5 = 5U, //!< ADCCLK = (input clock) / 3.5 + ADC_CLK_DIV_4_0 = 6U, //!< ADCCLK = (input clock) / 4.0 + ADC_CLK_DIV_4_5 = 7U, //!< ADCCLK = (input clock) / 4.5 + ADC_CLK_DIV_5_0 = 8U, //!< ADCCLK = (input clock) / 5.0 + ADC_CLK_DIV_5_5 = 9U, //!< ADCCLK = (input clock) / 5.5 + ADC_CLK_DIV_6_0 = 10U, //!< ADCCLK = (input clock) / 6.0 + ADC_CLK_DIV_6_5 = 11U, //!< ADCCLK = (input clock) / 6.5 + ADC_CLK_DIV_7_0 = 12U, //!< ADCCLK = (input clock) / 7.0 + ADC_CLK_DIV_7_5 = 13U, //!< ADCCLK = (input clock) / 7.5 + ADC_CLK_DIV_8_0 = 14U, //!< ADCCLK = (input clock) / 8.0 + ADC_CLK_DIV_8_5 = 15U //!< ADCCLK = (input clock) / 8.5 +} ADC_ClkPrescale; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e resolution +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_RESOLUTION_12BIT = 0x00U, //!< 12-bit conversion resolution + ADC_RESOLUTION_16BIT = 0x40U //!< 16-bit conversion resolution +} ADC_Resolution; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e signalMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_MODE_SINGLE_ENDED = 0x00U, //!< Sample on single pin with VREFLO + ADC_MODE_DIFFERENTIAL = 0x80U //!< Sample on pair of pins +} ADC_SignalMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e trigger +//! parameter to specify the event that will trigger a conversion to start. +//! It is also used with ADC_setBurstModeConfig() and +//! ADC_triggerRepeaterSelect(). +// +//***************************************************************************** +typedef enum +{ + ADC_TRIGGER_SW_ONLY = 0U, //!< Software only + ADC_TRIGGER_CPU1_TINT0 = 1U, //!< CPU1 Timer 0, TINT0 + ADC_TRIGGER_CPU1_TINT1 = 2U, //!< CPU1 Timer 1, TINT1 + ADC_TRIGGER_CPU1_TINT2 = 3U, //!< CPU1 Timer 2, TINT2 + ADC_TRIGGER_GPIO = 4U, //!< GPIO, ADCEXTSOC + ADC_TRIGGER_EPWM1_SOCA = 5U, //!< ePWM1, ADCSOCA + ADC_TRIGGER_EPWM1_SOCB = 6U, //!< ePWM1, ADCSOCB + ADC_TRIGGER_EPWM2_SOCA = 7U, //!< ePWM2, ADCSOCA + ADC_TRIGGER_EPWM2_SOCB = 8U, //!< ePWM2, ADCSOCB + ADC_TRIGGER_EPWM3_SOCA = 9U, //!< ePWM3, ADCSOCA + ADC_TRIGGER_EPWM3_SOCB = 10U, //!< ePWM3, ADCSOCB + ADC_TRIGGER_EPWM4_SOCA = 11U, //!< ePWM4, ADCSOCA + ADC_TRIGGER_EPWM4_SOCB = 12U, //!< ePWM4, ADCSOCB + ADC_TRIGGER_EPWM5_SOCA = 13U, //!< ePWM5, ADCSOCA + ADC_TRIGGER_EPWM5_SOCB = 14U, //!< ePWM5, ADCSOCB + ADC_TRIGGER_EPWM6_SOCA = 15U, //!< ePWM6, ADCSOCA + ADC_TRIGGER_EPWM6_SOCB = 16U, //!< ePWM6, ADCSOCB + ADC_TRIGGER_EPWM7_SOCA = 17U, //!< ePWM7, ADCSOCA + ADC_TRIGGER_EPWM7_SOCB = 18U, //!< ePWM7, ADCSOCB + ADC_TRIGGER_EPWM8_SOCA = 19U, //!< ePWM8, ADCSOCA + ADC_TRIGGER_EPWM8_SOCB = 20U, //!< ePWM8, ADCSOCB + ADC_TRIGGER_EPWM9_SOCA = 21U, //!< ePWM9, ADCSOCA + ADC_TRIGGER_EPWM9_SOCB = 22U, //!< ePWM9, ADCSOCB + ADC_TRIGGER_EPWM10_SOCA = 23U, //!< ePWM10, ADCSOCA + ADC_TRIGGER_EPWM10_SOCB = 24U, //!< ePWM10, ADCSOCB + ADC_TRIGGER_EPWM11_SOCA = 25U, //!< ePWM11, ADCSOCA + ADC_TRIGGER_EPWM11_SOCB = 26U, //!< ePWM11, ADCSOCB + ADC_TRIGGER_EPWM12_SOCA = 27U, //!< ePWM12, ADCSOCA + ADC_TRIGGER_EPWM12_SOCB = 28U, //!< ePWM12, ADCSOCB + ADC_TRIGGER_CPU2_TINT0 = 29U, //!< CPU2 Timer 0, TINT0 + ADC_TRIGGER_CPU2_TINT1 = 30U, //!< CPU2 Timer 1, TINT1 + ADC_TRIGGER_CPU2_TINT2 = 31U //!< CPU2 Timer 2, TINT2 +} ADC_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e channel +//! parameter. This is the input pin on which the signal to be converted is +//! located. +// +//***************************************************************************** +typedef enum +{ + ADC_CH_ADCIN0 = 0U, //!< single-ended, ADCIN0 + ADC_CH_ADCIN1 = 1U, //!< single-ended, ADCIN1 + ADC_CH_ADCIN2 = 2U, //!< single-ended, ADCIN2 + ADC_CH_ADCIN3 = 3U, //!< single-ended, ADCIN3 + ADC_CH_ADCIN4 = 4U, //!< single-ended, ADCIN4 + ADC_CH_ADCIN5 = 5U, //!< single-ended, ADCIN5 + ADC_CH_ADCIN6 = 6U, //!< single-ended, ADCIN6 + ADC_CH_ADCIN7 = 7U, //!< single-ended, ADCIN7 + ADC_CH_ADCIN8 = 8U, //!< single-ended, ADCIN8 + ADC_CH_ADCIN9 = 9U, //!< single-ended, ADCIN9 + ADC_CH_ADCIN10 = 10U, //!< single-ended, ADCIN10 + ADC_CH_ADCIN11 = 11U, //!< single-ended, ADCIN11 + ADC_CH_ADCIN12 = 12U, //!< single-ended, ADCIN12 + ADC_CH_ADCIN13 = 13U, //!< single-ended, ADCIN13 + ADC_CH_ADCIN14 = 14U, //!< single-ended, ADCIN14 + ADC_CH_ADCIN15 = 15U, //!< single-ended, ADCIN15 + ADC_CH_ADCIN0_ADCIN1 = 0U, //!< differential, ADCIN0 and ADCIN1 + ADC_CH_ADCIN2_ADCIN3 = 2U, //!< differential, ADCIN2 and ADCIN3 + ADC_CH_ADCIN4_ADCIN5 = 4U, //!< differential, ADCIN4 and ADCIN5 + ADC_CH_ADCIN6_ADCIN7 = 6U, //!< differential, ADCIN6 and ADCIN7 + ADC_CH_ADCIN8_ADCIN9 = 8U, //!< differential, ADCIN8 and ADCIN9 + ADC_CH_ADCIN10_ADCIN11 = 10U, //!< differential, ADCIN10 and ADCIN11 + ADC_CH_ADCIN12_ADCIN13 = 12U, //!< differential, ADCIN12 and ADCIN13 + ADC_CH_ADCIN14_ADCIN15 = 14U //!< differential, ADCIN14 and ADCIN15 +} ADC_Channel; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setInterruptPulseMode() as the +//! \e pulseMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Occurs at the end of the acquisition window + ADC_PULSE_END_OF_ACQ_WIN = 0x00U, + //! Occurs at the end of the conversion + ADC_PULSE_END_OF_CONV = 0x04U +} ADC_PulseMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(), +//! and ADC_getInterruptStatus() as the \e adcIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_NUMBER1 = 0U, //!< ADCINT1 Interrupt + ADC_INT_NUMBER2 = 1U, //!< ADCINT2 Interrupt + ADC_INT_NUMBER3 = 2U, //!< ADCINT3 Interrupt + ADC_INT_NUMBER4 = 3U //!< ADCINT4 Interrupt +} ADC_IntNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e ppbNumber parameter for several +//! functions. +// +//***************************************************************************** +typedef enum +{ + ADC_PPB_NUMBER1 = 0U, //!< Post-processing block 1 + ADC_PPB_NUMBER2 = 1U, //!< Post-processing block 2 + ADC_PPB_NUMBER3 = 2U, //!< Post-processing block 3 + ADC_PPB_NUMBER4 = 3U //!< Post-processing block 4 +} ADC_PPBNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e socNumber parameter for several +//! functions. This value identifies the start-of-conversion (SOC) that a +//! function is configuring or accessing. Note that in some cases (for example, +//! ADC_setInterruptSource()) \e socNumber is used to refer to the +//! corresponding end-of-conversion (EOC). +// +//***************************************************************************** +typedef enum +{ + ADC_SOC_NUMBER0 = 0U, //!< SOC/EOC number 0 + ADC_SOC_NUMBER1 = 1U, //!< SOC/EOC number 1 + ADC_SOC_NUMBER2 = 2U, //!< SOC/EOC number 2 + ADC_SOC_NUMBER3 = 3U, //!< SOC/EOC number 3 + ADC_SOC_NUMBER4 = 4U, //!< SOC/EOC number 4 + ADC_SOC_NUMBER5 = 5U, //!< SOC/EOC number 5 + ADC_SOC_NUMBER6 = 6U, //!< SOC/EOC number 6 + ADC_SOC_NUMBER7 = 7U, //!< SOC/EOC number 7 + ADC_SOC_NUMBER8 = 8U, //!< SOC/EOC number 8 + ADC_SOC_NUMBER9 = 9U, //!< SOC/EOC number 9 + ADC_SOC_NUMBER10 = 10U, //!< SOC/EOC number 10 + ADC_SOC_NUMBER11 = 11U, //!< SOC/EOC number 11 + ADC_SOC_NUMBER12 = 12U, //!< SOC/EOC number 12 + ADC_SOC_NUMBER13 = 13U, //!< SOC/EOC number 13 + ADC_SOC_NUMBER14 = 14U, //!< SOC/EOC number 14 + ADC_SOC_NUMBER15 = 15U //!< SOC/EOC number 15 +} ADC_SOCNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e trigger parameter for the +//! ADC_setInterruptSOCTrigger() function. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_SOC_TRIGGER_NONE = 0U, //!< No ADCINT will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT1 = 1U, //!< ADCINT1 will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT2 = 2U //!< ADCINT2 will trigger the SOC +} ADC_IntSOCTrigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setSOCPriority() as the \e priMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_PRI_ALL_ROUND_ROBIN = 0U, //!< Round robin mode is used for all + ADC_PRI_SOC0_HIPRI = 1U, //!< SOC 0 hi pri, others in round robin + ADC_PRI_THRU_SOC1_HIPRI = 2U, //!< SOC 0-1 hi pri, others in round robin + ADC_PRI_THRU_SOC2_HIPRI = 3U, //!< SOC 0-2 hi pri, others in round robin + ADC_PRI_THRU_SOC3_HIPRI = 4U, //!< SOC 0-3 hi pri, others in round robin + ADC_PRI_THRU_SOC4_HIPRI = 5U, //!< SOC 0-4 hi pri, others in round robin + ADC_PRI_THRU_SOC5_HIPRI = 6U, //!< SOC 0-5 hi pri, others in round robin + ADC_PRI_THRU_SOC6_HIPRI = 7U, //!< SOC 0-6 hi pri, others in round robin + ADC_PRI_THRU_SOC7_HIPRI = 8U, //!< SOC 0-7 hi pri, others in round robin + ADC_PRI_THRU_SOC8_HIPRI = 9U, //!< SOC 0-8 hi pri, others in round robin + ADC_PRI_THRU_SOC9_HIPRI = 10U, //!< SOC 0-9 hi pri, others in round robin + ADC_PRI_THRU_SOC10_HIPRI = 11U, //!< SOC 0-10 hi pri, others in round robin + ADC_PRI_THRU_SOC11_HIPRI = 12U, //!< SOC 0-11 hi pri, others in round robin + ADC_PRI_THRU_SOC12_HIPRI = 13U, //!< SOC 0-12 hi pri, others in round robin + ADC_PRI_THRU_SOC13_HIPRI = 14U, //!< SOC 0-13 hi pri, others in round robin + ADC_PRI_THRU_SOC14_HIPRI = 15U, //!< SOC 0-14 hi pri, SOC15 in round robin + ADC_PRI_ALL_HIPRI = 16U //!< All priorities based on SOC number +} ADC_PriorityMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_configOSDetectMode() as the \e modeVal +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_OSDETECT_MODE_DISABLED = 0x0U,//!< Open/Shorts detection cir- + //!< cuit(O/S DC) is disabled + ADC_OSDETECT_MODE_VSSA = 0x1U,//!< O/S DC is enabled at zero + //!< scale + ADC_OSDETECT_MODE_VDDA = 0x2U,//!< O/S DC is enabled at full + //!< scale + ADC_OSDETECT_MODE_5BY12_VDDA = 0x3U,//!< O/S DC is enabled at 5/12 + //!< scale + ADC_OSDETECT_MODE_7BY12_VDDA = 0x4U,//!< O/S DC is enabled at 7/12 + //!< scale + ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5U,//!< O/S DC is enabled at 5K + //!< pulldown to VSSA + ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA = 0x6U,//!< O/S DC is enabled at 5K + //!< pullup to VDDA + ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7U //!< O/S DC is enabled at 7K + //!< pulldown to VSSA +} ADC_OSDetectMode; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an ADC base address. +//! +//! \param base specifies the ADC module base address. +//! +//! This function determines if a ADC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +ADC_isBaseValid(uint32_t base) +{ + return( + (base == ADCA_BASE) || + (base == ADCB_BASE) || + (base == ADCC_BASE) || + (base == ADCD_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Configures the analog-to-digital converter module prescaler. +//! +//! \param base is the base address of the ADC module. +//! \param clkPrescale is the ADC clock prescaler. +//! +//! This function configures the ADC module's ADCCLK. +//! +//! The \e clkPrescale parameter specifies the value by which the input clock +//! is divided to make the ADCCLK. The clkPrescale value can be specified with +//! any of the following enum values: +//! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_2_5, ..., +//! \b ADC_CLK_DIV_7_5, \b ADC_CLK_DIV_8_0, or \b ADC_CLK_DIV_8_5. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the configuration of the ADC module prescaler. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~ADC_CTL2_PRESCALE_M) | (uint16_t)clkPrescale; + EDIS; +} + +//***************************************************************************** +// +//! Configures a start-of-conversion (SOC) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the source that will cause the SOC. +//! \param channel is the number associated with the input signal. +//! \param sampleWindow is the acquisition window duration. +//! +//! This function configures the a start-of-conversion (SOC) in the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the event that causes the SOC such as software, a +//! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value +//! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as +//! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO, +//! \b ADC_TRIGGER_EPWM1_SOCA, and so on. +//! +//! The \e channel parameter specifies the channel to be converted. In +//! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is +//! the number identifying the pin between 0 and 15 inclusive. In differential +//! mode, two pins are used as inputs and are passed in the \e channel +//! parameter as \b ADC_CH_ADCIN0_ADCIN1, \b ADC_CH_ADCIN2_ADCIN3, ..., or +//! \b ADC_CH_ADCIN14_ADCIN15. +//! +//! The \e sampleWindow parameter is the acquisition window duration in SYSCLK +//! cycles. It should be a value between 1 and 512 cycles inclusive. The +//! selected duration must be at least as long as one ADCCLK cycle. Also, the +//! datasheet will specify a minimum window duration requirement in +//! nanoseconds. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, + ADC_Channel channel, uint32_t sampleWindow) +{ + uint32_t ctlRegAddr, mask; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((sampleWindow >= 1U) && (sampleWindow <= 512U)); + + mask = (ADC_SOC0CTL_CHSEL_M | ADC_SOC0CTL_TRIGSEL_M | ADC_SOC0CTL_ACQPS_M); + + // + // Calculate address for the SOC control register. + // + ctlRegAddr = base + ADC_SOCxCTL_OFFSET_BASE + ((uint32_t)socNumber * 2U); + + // + // Set the configuration of the specified SOC. + // + EALLOW; + + HWREG(ctlRegAddr) = (HWREG(ctlRegAddr) & ~(mask)) | + ((uint32_t)channel << ADC_SOC0CTL_CHSEL_S) | + ((uint32_t)trigger << ADC_SOC0CTL_TRIGSEL_S) | + (sampleWindow - 1U); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the interrupt SOC trigger of an SOC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the interrupt source that will cause the SOC. +//! +//! This function configures the interrupt start-of-conversion trigger in +//! the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the interrupt that causes a start of conversion or +//! none. It should be one of the following values. +//! +//! - \b ADC_INT_SOC_TRIGGER_NONE +//! - \b ADC_INT_SOC_TRIGGER_ADCINT1 +//! - \b ADC_INT_SOC_TRIGGER_ADCINT2 +//! +//! This functionality is useful for creating continuous conversions. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, + ADC_IntSOCTrigger trigger) +{ + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each SOC has a 2-bit field in this register. + // + shiftVal = (uint16_t)socNumber << 1U; + + // + // Set the configuration of the specified SOC. Not that we're treating + // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here. + // + EALLOW; + HWREG(base + ADC_O_INTSOCSEL1) = (HWREG(base + ADC_O_INTSOCSEL1) & + ~((uint32_t)ADC_INTSOCSEL1_SOC0_M << + shiftVal)) | + ((uint32_t)trigger << shiftVal); + EDIS; +} + +//***************************************************************************** +// +//! Sets the timing of the end-of-conversion pulse +//! +//! \param base is the base address of the ADC module. +//! \param pulseMode is the generation mode of the EOC pulse. +//! +//! This function configures the end-of-conversion (EOC) pulse generated by ADC. +//! This pulse will be generated either at the end of the acquisition window +//!(pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end of the +//! voltage conversion, one cycle prior to the ADC result latching into it's +//! result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode). +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the position of the pulse. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) = (HWREGH(base + ADC_O_CTL1) & + ~ADC_CTL1_INTPULSEPOS) | (uint16_t)pulseMode; + EDIS; +} + + + + +//***************************************************************************** +// +//! Powers up the analog-to-digital converter core. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers up the analog circuitry inside the analog core. +//! +//! \note Allow at least a 500us delay before sampling after calling this API. +//! If you enable multiple ADCs, you can delay after they all have begun +//! powering up. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the bit that powers up the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) |= ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Powers down the analog-to-digital converter module. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers down the analog circuitry inside the analog core. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the bit that powers down the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) &= ~ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Forces a SOC flag to a 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function forces the SOC flag associated with the SOC specified by +//! \e socNumber. This initiates a conversion once that SOC is given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to the corresponding SOC flag + // + HWREGH(base + ADC_O_SOCFRC1) = ((uint16_t)1U << (uint16_t)socNumber); +} + +//***************************************************************************** +// +//! Forces multiple SOC flags to 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socMask is the SOCs to be forced through software +//! +//! This function forces the SOCFRC1 flags associated with the SOCs specified +//! by \e socMask. This initiates a conversion once the desired SOCs are given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! Valid values for \e socMask parameter can be any of the individual +//! ADC_FORCE_SOCx values or any of their OR'd combination to trigger multiple +//! SOCs. +//! +//! \note To trigger SOC0, SOC1 and SOC2, value (ADC_FORCE_SOC0 | +//! ADC_FORCE_SOC1 | ADC_FORCE_SOC2) should be passed as socMask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceMultipleSOC(uint32_t base, uint16_t socMask) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to desired SOCs + // + HWREGH(base + ADC_O_SOCFRC1) = socMask; +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt status for the analog-to-digital +//! converter. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt status for the given interrupt number of the ADC module. +//! +//! \return \b true if the interrupt flag for the specified interrupt number is +//! set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTFLG) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt sources so that they no +//! longer assert. If not in continuous mode, this function must be called +//! before any further interrupt pulses may occur. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt. + // + HWREGH(base + ADC_O_INTFLGCLR) = (uint16_t)1U << (uint16_t)adcIntNum; + +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt overflow status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt overflow status for the +//! analog-to-digital converter. An overflow condition is generated +//! irrespective of the continuous mode. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt overflow status for the given interrupt number. +//! +//! \return \b true if the interrupt overflow flag for the specified interrupt +//! number is set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTOVF) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt overflow sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt overflow sources so that +//! they no longer assert. If software tries to clear the overflow in the same +//! cycle that hardware tries to set the overflow, then hardware has priority. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupt overflow status of the ADC module +//! should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt overflow bit. + // + HWREGH(base + ADC_O_INTOVFCLR) = (uint16_t)1U << (uint16_t)adcIntNum; +} + +//***************************************************************************** +// +//! Reads the conversion result. +//! +//! \param resultBase is the base address of the ADC results. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function returns the conversion result that corresponds to the base +//! address passed into \e resultBase and the SOC passed into \e socNumber. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC's result is to be read. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the conversion result. +// +//***************************************************************************** +static inline uint16_t +ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the ADC result for the selected SOC. + // + return(HWREGH(resultBase + (uint32_t)ADC_RESULTx_OFFSET_BASE + + (uint32_t)socNumber)); +} + +//***************************************************************************** +// +//! Determines whether the ADC is busy or not. +//! +//! \param base is the base address of the ADC. +//! +//! This function allows the caller to determine whether or not the ADC is +//! busy and can sample another channel. +//! +//! \return Returns \b true if the ADC is sampling or \b false if all +//! samples are complete. +// +//***************************************************************************** +static inline bool +ADC_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Determine if the ADC is busy. + // + return((HWREGH(base + ADC_O_CTL1) & ADC_CTL1_ADCBSY) != 0U); +} + +//***************************************************************************** +// +//! Set SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! \param trigger the source that will cause the burst conversion sequence. +//! \param burstSize is the number of SOCs converted during a burst sequence. +//! +//! This function configures the burst trigger and burstSize of an ADC module. +//! Burst mode allows a single trigger to walk through the round-robin SOCs one +//! or more at a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Instead, the source specified through the \e trigger parameter will +//! cause a burst of \e burstSize conversions to occur. +//! +//! The \e trigger parameter takes the same values as the ADC_setupSOC() API +//! The \e burstSize parameter should be a value between 1 and 16 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(((uint16_t)trigger & ~((uint16_t)0x1FU)) == 0U); + ASSERT((burstSize >= 1U) && (burstSize <= 16U)); + + // + // Write the burst mode configuration to the register. + // + EALLOW; + + regValue = (uint16_t)trigger | ((burstSize - 1U) << + ADC_BURSTCTL_BURSTSIZE_S); + + HWREGH(base + ADC_O_BURSTCTL) = (HWREGH(base + ADC_O_BURSTCTL) & + ~((uint16_t)ADC_BURSTCTL_BURSTTRIGSEL_M | + ADC_BURSTCTL_BURSTSIZE_M)) | regValue; + + EDIS; +} + +//***************************************************************************** +// +//! Enables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function enables SOC burst mode operation of the ADC. Burst mode +//! allows a single trigger to walk through the round-robin SOCs one or more at +//! a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Use ADC_setBurstMode() to configure the burst trigger and size. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Enable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) |= ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function disables SOC burst mode operation of the ADC. SOCs in +//! round-robin mode will be triggered by the trigger configured using the +//! ADC_setupSOC() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Disable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) &= ~ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Sets the priority mode of the SOCs. +//! +//! \param base is the base address of the ADC. +//! \param priMode is the priority mode of the SOCs. +//! +//! This function sets the priority mode of the SOCs. There are three main +//! modes that can be passed in the \e priMode parameter +//! +//! - All SOCs are in round-robin mode. This means no SOC has an inherent +//! higher priority over another. This is selected by passing in the value +//! \b ADC_PRI_ALL_ROUND_ROBIN. +//! - All priorities are in high priority mode. This means that the priority of +//! the SOC is determined by its SOC number. This option is selected by passing +//! in the value \b ADC_PRI_ALL_HIPRI. +//! - A range of SOCs are assigned high priority, with all others in round +//! robin mode. High priority mode means that an SOC with high priority will +//! interrupt the round robin wheel and insert itself as the next conversion. +//! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority, +//! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so +//! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high +//! priority. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + EALLOW; + + HWREGH(base + ADC_O_SOCPRICTL) = (HWREGH(base + ADC_O_SOCPRICTL) & + ~ADC_SOCPRICTL_SOCPRIORITY_M) | + (uint16_t)priMode; + + EDIS; +} + +//***************************************************************************** +// +//! Configures Open/Shorts Detection Circuit Mode. +//! +//! \param base is the base address of the ADC. +//! \param modeVal is the desired open/shorts detection circuit mode. +//! +//! This function configures the open/shorts detection circuit mode of the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal) +{ + // + // Configure open/shorts detection circuit mode. + // + EALLOW; + HWREGH(base + ADC_O_OSDETECT) = ((HWREGH(base + ADC_O_OSDETECT) & + (~ADC_OSDETECT_DETECTCFG_M)) | + (uint16_t)modeVal); + EDIS; +} + +//***************************************************************************** +// +//! Configures a post-processing block (PPB) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function associates a post-processing block with a SOC. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. The \e socNumber +//! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15 +//! specifying which SOC is to be configured on the ADC module specified by +//! \e base. +//! +//! \note You can have more that one PPB associated with the same SOC, but a +//! PPB can only be configured to correspond to one SOC at a time. Also note +//! that when you have multiple PPBs for the same SOC, the calibration offset +//! that actually gets applied will be that of the PPB with the highest number. +//! Since SOC0 is the default for all PPBs, look out for unintentional +//! overwriting of a lower numbered PPB's offset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Write the configuration to the register. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1CONFIG_CONFIG_M) | + ((uint16_t)socNumber & ADC_PPB1CONFIG_CONFIG_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function enables the indicated ADC PPB event sources. This will allow +//! the specified events to propagate through the X-BAR to a pin or to an ePWM +//! module. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Enable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) |= evtFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function disables the indicated ADC PPB event sources. This will stop +//! the specified events from propagating through the X-BAR to other modules. +//! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Disable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Enable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) |= intFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt source to be disabled. +//! +//! This function disables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Disable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) &= ~(intFlags << + ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Gets the current ADC event status. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the event status for the analog-to-digital converter. +//! +//! \return Returns the current event status, enumerated as a bit field of +//! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the event status for the specified post-processing block. + // + return((HWREGH(base + ADC_O_EVTSTAT) >> ((uint16_t)ppbNumber * 4U)) & + 0x7U); +} + +//***************************************************************************** +// +//! Clears ADC event flags. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event source to be cleared. +//! +//! This function clears the indicated ADC PPB event flags. After an event +//! occurs this function must be called to allow additional events to be +//! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Clear the specified event interrupts. + // + HWREGH(base + ADC_O_EVTCLR) |= evtFlags << ((uint16_t)ppbNumber * 4U); +} + + +//***************************************************************************** +// +//! Reads the processed conversion result from the PPB. +//! +//! \param resultBase is the base address of the ADC results. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the processed conversion result that corresponds to +//! the base address passed into \e resultBase and the PPB passed into +//! \e ppbNumber. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the signed 32-bit conversion result. +// +//***************************************************************************** +static inline int32_t +ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the result of selected PPB. + // + return((int32_t)HWREG(resultBase + (uint32_t)ADC_PPBxRESULT_OFFSET_BASE + + ((uint32_t)ppbNumber * 2UL))); +} + +//***************************************************************************** +// +//! Reads sample delay time stamp from a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the sample delay time stamp. This delay is the number +//! of system clock cycles between the SOC being triggered and when it began +//! converting. +//! +//! \return Returns the delay time stamp. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate delay. + // + ppbOffset = (ADC_PPBxSTAMP_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1STAMP; + + // + // Return the delay time stamp. + // + return(HWREGH(base + ppbOffset) & ADC_PPB2STAMP_DLYSTAMP_M); +} + +//***************************************************************************** +// +//! Sets the post processing block offset correction. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 10-bit signed value subtracted from ADC the output. +//! +//! This function sets the PPB offset correction value. This value can be used +//! to digitally remove any system-level offset inherent in the ADCIN circuit +//! before it is stored in the appropriate result register. The \e offset +//! parameter is \b subtracted from the ADC output and is a signed value from +//! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC +//! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC +//! output + 512. +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation, allowing the raw ADC result to be passed unchanged into the +//! result register. +//! +//! \note If multiple PPBs are applied to the same SOC, the offset that will be +//! applied will be that of the PPB with the highest number. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, + int16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFCAL_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFCAL; + + // + // Write the offset amount. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1OFFCAL_OFFCAL_M) | + ((uint16_t)offset & ADC_PPB1OFFCAL_OFFCAL_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the post processing block reference offset. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 16-bit unsigned value subtracted from ADC the output. +//! +//! This function sets the PPB reference offset value. This can be used to +//! either calculate the feedback error or convert a unipolar signal to bipolar +//! by subtracting a reference value. The result will be stored in the +//! appropriate PPB result register which can be read using ADC_readPPBResult(). +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation and will pass the ADC result to the PPB result register +//! unchanged. +//! +//! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset +//! parameter. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFREF_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFREF; + + // + // Write the offset amount. + // + HWREGH(base + ppbOffset) = offset; +} + +//***************************************************************************** +// +//! Enables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function enables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When enabled, a two's complement +//! will be performed on the output of the offset subtraction before it is +//! stored in the appropriate PPB result register. In other words, the PPB +//! result will be the reference offset value minus the the ADC result value +//! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Enable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) |= ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function disables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When disabled, a two's complement +//! will \b NOT be performed on the output of the offset subtraction before it +//! is stored in the appropriate PPB result register. In other words, the PPB +//! result will be the ADC result value minus the reference offset value +//! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Disable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) &= ~ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Enables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables the indicated ADC interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1E << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables the indicated ADC interrupt source. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt. Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1E << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the source EOC for an analog-to-digital converter interrupt. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function sets which conversion is the source of an ADC interrupt. +//! +//! The \e intTrigger number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which EOC is to be configured on the ADC module +//! specified by \e base. Refer \b ADC_SOCNumber enum for valid values for +//! this input. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, + uint16_t intTrigger) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(intTrigger < 16U); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Set the specified ADC interrupt source. + // + EALLOW; + + HWREGH(intRegAddr) = + (HWREGH(intRegAddr) & ~(ADC_INTSEL1N2_INT1SEL_M << shiftVal)) | + ((uint16_t)intTrigger << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Enables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will be generated for the specified +//! ADC interrupt whenever an EOC pulse is generated irrespective of whether or +//! not the flag bit is set. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1CONT << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will not be generated for the +//! specified ADC interrupt until the corresponding interrupt flag for the +//! previous interrupt occurrence has been cleared using +//! ADC_clearInterruptStatus(). +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1CONT << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees C +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees C. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees C. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureC(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)((((int32_t)temp + (int32_t)0x4000 + + ((int32_t)273 * (int32_t)0x8000)) / + (int32_t)0x8000) - (int32_t)273)); +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees K +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees K. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees K. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureK(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)(((int32_t)temp + (int32_t)0x4000 + ((int32_t)273 * + (int32_t)0x8000)) / (int32_t)0x8000)); +} + + +//***************************************************************************** +// +//! Configures the analog-to-digital converter resolution and signal mode. +//! +//! \param base is the base address of the ADC module. +//! \param resolution is the resolution of the converter (12 or 16 bits). +//! \param signalMode is the input signal mode of the converter. +//! +//! This function configures the ADC module's conversion resolution and input +//! signal mode and ensures that the corresponding trims are loaded. +//! +//! The \e resolution parameter specifies the resolution of the conversion. +//! It can be 12-bit or 16-bit specified by \b ADC_RESOLUTION_12BIT +//! or \b ADC_RESOLUTION_16BIT. +//! +//! The \e signalMode parameter specifies the signal mode. In single-ended +//! mode, which is indicated by \b ADC_MODE_SINGLE_ENDED, the input voltage is +//! sampled on a single pin referenced to VREFLO. In differential mode, which +//! is indicated by \b ADC_MODE_DIFFERENTIAL, the input voltage to the +//! converter is sampled on a pair of input pins, a positive and a negative. +//! +//! \b Note: In this device, single-ended signal conversions are supported +//! only in 12-bit resolution mode and differential signal +//! conversions are supported only in 16-bit resolution mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode); + + +//***************************************************************************** +// +//! Configures the offset trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the offset trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setOffsetTrim(uint32_t base); + +//***************************************************************************** +// +//! Configures the INL trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the INL trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setINLTrim(uint32_t base); + +//***************************************************************************** +// +//! Sets the windowed trip limits for a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param tripHiLimit is the value is the digital comparator trip high limit. +//! \param tripLoLimit is the value is the digital comparator trip low limit. +//! +//! This function sets the windowed trip limits for a PPB. These values set +//! the digital comparator so that when one of the values is exceeded, either a +//! high or low trip event will occur. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. +//! +//! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit +//! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is +//! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be +//! compared against bits 12:0 of the PPB result. +//! +//! \note On some devices, signed trip values do not work properly. See the +//! silicon errata for details. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ADC_H diff --git a/gpio_bitfield_cpu2/device/driverlib/asysctl.c b/gpio_bitfield_cpu2/device/driverlib/asysctl.c new file mode 100644 index 0000000..4f3d202 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/asysctl.c @@ -0,0 +1,43 @@ +//########################################################################### +// +// FILE: asysctl.c +// +// TITLE: C28x Driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "asysctl.h" diff --git a/gpio_bitfield_cpu2/device/driverlib/asysctl.h b/gpio_bitfield_cpu2/device/driverlib/asysctl.h new file mode 100644 index 0000000..40e6c5c --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/asysctl.h @@ -0,0 +1,160 @@ +//########################################################################### +// +// FILE: asysctl.h +// +// TITLE: C28x driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ASYSCTL_H +#define ASYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup asysctl_api ASysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_asysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enable temperature sensor. +//! +//! This function enables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_enableTemperatureSensor(void) +{ + EALLOW; + + // + // Set the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable temperature sensor. +//! +//! This function disables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_disableTemperatureSensor(void) +{ + EALLOW; + + // + // Clear the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the temperature sensor control register. +//! +//! \return None. +// +//***************************************************************************** +static inline void ASysCtl_lockTemperatureSensor(void) +{ + EALLOW; + + // + // Write a 1 to the lock bit in the LOCK register. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL; + + EDIS; +} + + + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ASYSCTL_H diff --git a/gpio_bitfield_cpu2/device/driverlib/can.c b/gpio_bitfield_cpu2/device/driverlib/can.c new file mode 100644 index 0000000..5a33a50 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/can.c @@ -0,0 +1,1122 @@ +//########################################################################### +// +// FILE: can.c +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#include "can.h" + +//***************************************************************************** +// +// CAN_initModule +// +//***************************************************************************** +void +CAN_initModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + HWREGH(base + CAN_O_CTL) |= ((uint16_t)CAN_CTL_INIT | + (uint16_t)CAN_INIT_PARITY_DISABLE); + + // + // Initialize the message RAM before using it. + // + CAN_initRAM(base); + + // + // Force module to reset state + // + + HWREGH(base + CAN_O_CTL) |= CAN_CTL_SWR; + + // + // Delay for 14 cycles + // + SysCtl_delay(1U); + + // + // Enable write access to the configuration registers + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_CCE; +} + +//***************************************************************************** +// +// CAN_setBitRate +// +//***************************************************************************** +void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime) +{ + uint16_t brp; + uint16_t tPhase; + uint16_t phaseSeg2; + uint16_t tSync = 1U; + uint16_t tProp = 2U; + uint16_t tSeg1; + uint16_t tSeg2; + uint16_t sjw; + uint16_t prescaler; + uint16_t prescalerExtension; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((bitTime > 7U) && (bitTime < 26U)); + ASSERT(bitRate <= 1000000U); + + // + // Calculate bit timing values + // + brp = (uint16_t)(clockFreq / (bitRate * bitTime)); + tPhase = bitTime - (tSync + tProp); + if((tPhase / 2U) <= 8U) + { + phaseSeg2 = tPhase / 2U; + } + else + { + phaseSeg2 = 8U; + } + tSeg1 = ((tPhase - phaseSeg2) + tProp) - 1U; + tSeg2 = phaseSeg2 - 1U; + if(phaseSeg2 > 4U) + { + sjw = 3U; + } + else + { + sjw = tSeg2; + } + prescalerExtension = ((brp - 1U) / 64U); + prescaler = ((brp - 1U) % 64U); + + // + // Set the calculated timing parameters + // + CAN_setBitTiming(base, prescaler, prescalerExtension, tSeg1, tSeg2, sjw); +} + +//***************************************************************************** +// +// CAN_setBitTiming +// +//***************************************************************************** +void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw) +{ + uint16_t savedInit; + uint32_t bitReg; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT(prescaler < 64U); + ASSERT((tSeg1 > 0U) && (tSeg1 < 16U)); + ASSERT(tSeg2 < 8U); + ASSERT(sjw < 4U); + ASSERT(prescalerExtension < 16U); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. + // State of the init bit should be saved so it can be restored at the end. + // + savedInit = HWREGH(base + CAN_O_CTL); + HWREGH(base + CAN_O_CTL) = savedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // + // Set the bit fields of the bit timing register + // + bitReg = (uint32_t)((uint32_t)prescaler & CAN_BTR_BRP_M); + bitReg |= (uint32_t)(((uint32_t)sjw << CAN_BTR_SJW_S) & CAN_BTR_SJW_M); + bitReg |= (uint32_t)(((uint32_t)tSeg1 << CAN_BTR_TSEG1_S) & + CAN_BTR_TSEG1_M); + bitReg |= (uint32_t)(((uint32_t)tSeg2 << CAN_BTR_TSEG2_S) & + CAN_BTR_TSEG2_M); + bitReg |= (uint32_t)(((uint32_t)prescalerExtension << CAN_BTR_BRPE_S) & + CAN_BTR_BRPE_M); + + HWREG_BP(base + CAN_O_BTR) = bitReg; + + // + // Clear the config change bit, and restore the init bit. + // + savedInit &= ~((uint16_t)CAN_CTL_CCE); + + HWREGH(base + CAN_O_CTL) = savedInit; +} + + +//***************************************************************************** +// +// CAN_clearInterruptStatus +// +//***************************************************************************** +void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intClr == CAN_INT_INT0ID_STATUS) || + ((intClr >= 1U) && (intClr <= 32U))); + + if(intClr == (uint32_t)CAN_INT_INT0ID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + HWREGH(base + CAN_O_ES); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMD_CLRINTPND bit. + // + // Send the clear pending interrupt command to the CAN controller. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CLRINTPND | + (intClr & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + } +} + +//***************************************************************************** +// +// CAN_setupMessageObject +// +//***************************************************************************** +void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen) +{ + uint32_t cmdMaskReg = 0U; + uint32_t maskReg = 0U; + uint32_t arbReg = 0U; + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + switch(msgType) + { + // + // Transmit message object. + // + case CAN_MSG_OBJ_TYPE_TX: + { + // + // Set message direction to transmit. + // + arbReg = CAN_IF1ARB_DIR; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case CAN_MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Set message direction to Tx for remote receivers. + // + arbReg = CAN_IF1ARB_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + msgCtrl = (uint32_t)((uint32_t)CAN_IF1MCTL_RMTEN | + (uint32_t)CAN_IF1MCTL_UMASK); + + break; + } + + // + // Transmit remote request message object (CAN_MSG_OBJ_TYPE_TX_REMOTE) + // or Receive message object (CAN_MSG_OBJ_TYPE_RX). + // + default: + { + // + // Set message direction to read. + // + arbReg = 0U; + + break; + } + } + + // + // Set values based on Extended Frame or Standard Frame + // + if(frame == CAN_MSG_FRAME_EXT) + { + // + // Configure the Mask Registers for 29 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = msgIDMask & CAN_IF1MSK_MSK_M; + } + + // + // Set the 29 bit version of the Identifier for this message + // object. Mark the message as valid and set the extended ID bit. + // + arbReg |= (msgID & CAN_IF1ARB_ID_M) | CAN_IF1ARB_MSGVAL | + CAN_IF1ARB_XTD; + } + else + { + // + // Configure the Mask Registers for 11 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = ((msgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); + } + + // + // Set the 11 bit version of the Identifier for this message + // object. The lower 18 bits are set to zero. Mark the message as + // valid. + // + arbReg |= ((msgID << CAN_IF1ARB_STD_ID_S) & CAN_IF1ARB_STD_ID_M) | + CAN_IF1ARB_MSGVAL; + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_EXT_FILTER); + + // + // The caller wants to filter on the message direction field. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_DIR_FILTER); + + // + // If any filtering is requested, set the UMASK bit to use mask register + // + if(((flags & CAN_MSG_OBJ_USE_ID_FILTER) | + (flags & CAN_MSG_OBJ_USE_DIR_FILTER) | + (flags & CAN_MSG_OBJ_USE_EXT_FILTER)) != 0U) + { + msgCtrl |= CAN_IF1MCTL_UMASK; + } + + // + // Set the data length for the transfers. This is applicable only for + // Tx mailboxes. For Rx mailboxes, dlc is updated on receving a frame. + // + if((msgType == CAN_MSG_OBJ_TYPE_TX) || + (msgType == CAN_MSG_OBJ_TYPE_RXTX_REMOTE)) + { + msgCtrl |= ((uint32_t)msgLen & CAN_IF1MCTL_DLC_M); + } + + // + // If this is a single transfer or the last mailbox of a FIFO, set EOB bit. + // If this is not the last entry in a FIFO, leave the EOB bit as 0. + // + if((flags & CAN_MSG_OBJ_FIFO) == 0U) + { + msgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_TX_INT_ENABLE); + + // + // Enable receive interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_RX_INT_ENABLE); + + // + // Set the Control, Arb, and Mask bit so that they get transferred to the + // Message object. + // + cmdMaskReg |= CAN_IF1CMD_ARB; + cmdMaskReg |= CAN_IF1CMD_CONTROL; + cmdMaskReg |= CAN_IF1CMD_MASK; + cmdMaskReg |= CAN_IF1CMD_DIR; + + // + // Write out the registers to program the message object. + // + HWREG_BP(base + CAN_O_IF1MSK) = maskReg; + HWREG_BP(base + CAN_O_IF1ARB) = arbReg; + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M); +} + +//***************************************************************************** +// +// CAN_sendMessage +// +//***************************************************************************** +void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_16bit +// +//***************************************************************************** +void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_16bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_32bit +// +//***************************************************************************** +void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_32bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_updateDLC +// +//***************************************************************************** +void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Update to the new data length + // + msgCtrl &= ~CAN_IF1MCTL_DLC_M; + msgCtrl |= (msgLen & CAN_IF1MCTL_DLC_M); + + // + // Write out to the register to program the message object + // + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + (CAN_IF1CMD_CONTROL | CAN_IF1CMD_DIR | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendRemoteRequestMessage +// +//***************************************************************************** +void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check configured DLC size with 0 as this is a remote frame + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == 0U); + + // + // Set Direction to write + // + // Set Tx Request Bit for this remote frame + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_readMessage +// +//***************************************************************************** +bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData) +{ + bool status; + uint16_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID != 0U)); + + // + // Set the Message Data A, Data B, and control values to be read + // on request for data from the message object. + // + // Transfer the message object to the message object IF register. + // + HWREG_BP(base + CAN_O_IF2CMD) = + ((uint32_t)CAN_IF2CMD_DATA_A | (uint32_t)CAN_IF2CMD_DATA_B | + (uint32_t)CAN_IF2CMD_CONTROL | (objID & CAN_IF2CMD_MSG_NUM_M) | + (uint32_t)CAN_IF2CMD_ARB); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == CAN_IF2CMD_BUSY) + { + } + + // + // Read out the IF control Register. + // + msgCtrl = HWREGH(base + CAN_O_IF2MCTL); + + // + // See if there is new data available. + // + if((msgCtrl & CAN_IF2MCTL_NEWDAT) == CAN_IF2MCTL_NEWDAT) + { + // + // Read out the data from the CAN registers. + // + CAN_readDataReg(msgData, (base + CAN_O_IF2DATA), + ((uint32_t)msgCtrl & CAN_IF2MCTL_DLC_M)); + + status = true; + + // + // Now clear out the new data flag + // + HWREG_BP(base + CAN_O_IF2CMD) = ((uint32_t)CAN_IF2CMD_TXRQST | + (objID & CAN_IF2CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == + CAN_IF2CMD_BUSY) + { + } + } + else + { + status = false; + } + + return(status); +} + +//***************************************************************************** +// +// CAN_readMessageWithID +// +//***************************************************************************** +bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData) +{ + bool status; + + // + // Check the pointers. + // + ASSERT(msgID != 0U); + ASSERT(frameType != 0U); + + // + //Read the message first this fills the IF2 registers + //with received message for that mailbox + // + status = CAN_readMessage(base, objID, msgData); + // + // See if there is new data available. + // + if(status) + { + if((HWREG_BP(base + CAN_O_IF2ARB) & CAN_IF2ARB_XTD) != 0U) + { + *frameType = CAN_MSG_FRAME_EXT; + *msgID = ((HWREG_BP(base + CAN_O_IF2ARB)) & CAN_IF2ARB_ID_M); + } + else + { + *frameType = CAN_MSG_FRAME_STD; + *msgID = (((HWREG_BP(base + CAN_O_IF2ARB)) & + CAN_IF2ARB_STD_ID_M) >> + CAN_IF2ARB_STD_ID_S); + } + } + + return(status); +} + +//***************************************************************************** +// +// CAN_transferMessage +// +//***************************************************************************** +void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction) +{ + uint32_t cmdMaskReg; + + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + ASSERT((interface == 1U) || (interface == 2U)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + cmdMaskReg = + ((uint32_t)CAN_IF1CMD_DATA_A | (uint32_t)CAN_IF1CMD_DATA_B | + (uint32_t)CAN_IF1CMD_TXRQST | (uint32_t)CAN_IF1CMD_CONTROL | + (uint32_t)CAN_IF1CMD_MASK | (uint32_t)CAN_IF1CMD_ARB) | + (direction ? CAN_IF1CMD_DIR : 0U); + + // + // Ensure this IF isn't busy + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set up the request for data from the message object. Transfer the + // message object to the message object specified by objID. + // + HWREG_BP(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) = + (cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } +} + +//***************************************************************************** +// +// CAN_clearMessage +// +//***************************************************************************** +void +CAN_clearMessage(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableMessageObject +// +//***************************************************************************** +void +CAN_disableMessageObject(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableAllMessageObjects +// +//***************************************************************************** +void +CAN_disableAllMessageObjects(uint32_t base) +{ + uint32_t objID; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Loop to disable all valid message objects + // + for(objID = 0x01UL; objID <= 0x20UL; objID++) + { + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); + } +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/can.h b/gpio_bitfield_cpu2/device/driverlib/can.h new file mode 100644 index 0000000..247d1df --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/can.h @@ -0,0 +1,1924 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef CAN_H +#define CAN_H + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup can_api CAN +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_can.h" +#include "debug.h" +#include "sysctl.h" + +// +// The key value for RAM initialization +// +#define CAN_RAM_INIT_KEY (0xAU) + +// +// RAM Initialization Register Mask +// +#define CAN_RAM_INIT_MASK (0x003FU) + +// +// The Parity disable key value +// +#define CAN_INIT_PARITY_DISABLE (0x1400U) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** +//***************************************************************************** +// +// These are the flags used by the flags parameter when calling +// the CAN_setupMessageObject() function. +// +//***************************************************************************** + +//! This indicates that transmit interrupts should be enabled, or are enabled. +#define CAN_MSG_OBJ_TX_INT_ENABLE CAN_IF1MCTL_TXIE + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define CAN_MSG_OBJ_RX_INT_ENABLE CAN_IF1MCTL_RXIE + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define CAN_MSG_OBJ_USE_ID_FILTER (0x00000001U) + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. +#define CAN_MSG_OBJ_USE_DIR_FILTER CAN_IF1MSK_MDIR + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. +#define CAN_MSG_OBJ_USE_EXT_FILTER CAN_IF1MSK_MXTD + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define CAN_MSG_OBJ_FIFO (0x00000002U) + +//! This indicates that a message object has no flags set. +#define CAN_MSG_OBJ_NO_FLAGS (0x00000000U) + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to +// CAN_enableInterrupt() and CAN_disableInterrupt(). +// +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR (0x00000008UL) + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS (0x00000004UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 (0x00000002UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 (0x00020000UL) + +//***************************************************************************** +// +// The following definitions contain all error or status indicators that can +// be returned when calling the CAN_getStatus() function. +// +//***************************************************************************** + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR (0x00000100U) + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF (0x00000080U) + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN (0x00000040U) + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS (0x00000020U) + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK (0x00000010U) + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK (0x00000008U) + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK (0x00000007U) + +//! There was no error. +#define CAN_STATUS_LEC_NONE (0x00000000U) + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF (0x00000001U) + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM (0x00000002U) + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK (0x00000003U) + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 (0x00000004U) + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 (0x00000005U) + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC (0x00000006U) + +//***************************************************************************** +// +// The following macros are added for the Global Interrupt EN/FLG/CLR +// register +// +//***************************************************************************** +//! CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 (0x00000001U) + +//! CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 (0x00000002U) + +//***************************************************************************** +// +// The following macros are added for accessing the interrupt register and +// the standard arbitration ID in the interface registers. +// +//***************************************************************************** +//! Status of INT0ID +#define CAN_INT_INT0ID_STATUS (0x8000U) + +//! IF1 Arbitration Standard ID Shift Offset +#define CAN_IF1ARB_STD_ID_S (18U) + +//! IF1 Arbitration Standard ID Mask +#define CAN_IF1ARB_STD_ID_M (0x1FFC0000U) + +//! IF2 Arbitration Standard ID Shift Offset +#define CAN_IF2ARB_STD_ID_S (18U) + +//! IF2 Arbitration Standard ID Mask +#define CAN_IF2ARB_STD_ID_M (0x1FFC0000U) + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! This data type is used to decide between STD_ID or EXT_ID for a mailbox. +//! This is used when calling the CAN_setupMessageObject() function. +// +//***************************************************************************** +typedef enum +{ + //! Set the message ID frame to standard. + CAN_MSG_FRAME_STD, + + //! Set the message ID frame to extended. + CAN_MSG_FRAME_EXT +} CAN_MsgFrameType; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CAN_setupMessageObject() API. +// +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + CAN_MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + CAN_MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + CAN_MSG_OBJ_TYPE_RX, + + //! Remote frame receive remote, with auto-transmit message object. + CAN_MSG_OBJ_TYPE_RXTX_REMOTE +} CAN_MsgObjType; + +//***************************************************************************** +// +//! This definition is used to determine the clock source that will +//! be set up via a call to the CAN_selectClockSource() API. +// +//***************************************************************************** +typedef enum +{ + //! Peripheral System Clock Source + CAN_CLOCK_SOURCE_SYS = 0x0, + + //! External Oscillator Clock Source + CAN_CLOCK_SOURCE_XTAL = 0x1, + + //! Auxiliary Clock Input Source + CAN_CLOCK_SOURCE_AUX = 0x2 +} CAN_ClockSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! +//! Checks a CAN base address. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CAN_isBaseValid(uint32_t base) +{ + return( + (base == CANA_BASE) || + (base == CANB_BASE) + ); +} +#endif + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_writeDataReg(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = data[idx]; + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 16bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_16bit(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = (uint32_t)((data[idx / 2UL]) >> ((idx % 2UL) * 8UL)); + + dataReg++; + } +} + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 32bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_32bit(const uint32_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = ((data[idx / 4UL]) >> ((idx % 4UL) * 8UL)); + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from the CAN Data registers to a buffer. +//! +//! \param data is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_readDataReg(uint16_t *data, const uint32_t address, uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Read out the data + // + data[idx] = HWREGB(dataReg); + + dataReg++; + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller's RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Performs the initialization of the RAM used for the CAN message objects. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_initRAM(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + HWREGH(base + CAN_O_RAM_INIT) = CAN_RAM_INIT_CAN_RAM_INIT | + CAN_RAM_INIT_KEY; + + while(!((HWREGH(base + CAN_O_RAM_INIT) & CAN_RAM_INIT_MASK) == + (CAN_RAM_INIT_RAM_INIT_DONE | CAN_RAM_INIT_KEY2 | + CAN_RAM_INIT_KEY0))) + { + // + // Wait until RAM Init is complete + // + } +} + +//***************************************************************************** +// +//! Select CAN Clock Source +//! +//! \param base is the base address of the CAN controller. +//! \param source is the clock source to use for the CAN controller. +//! +//! This function selects the specified clock source for the CAN controller. +//! +//! The \e source parameter can be any one of the following: +//! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock +//! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator +//! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_selectClockSource(uint32_t base, CAN_ClockSource source) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Determine the CAN controller and set specified clock source + // + EALLOW; + + switch(base) + { + case CANA_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANABCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANABCLKSEL_S); + break; + + case CANB_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S); + break; + + default: + + // + // Do nothing. Not a valid mode value. + // + break; + } + + EDIS; + SYSCTL_CLKSRCCTL_DELAY; +} + +//***************************************************************************** +// +//! Starts the CAN Module's Operations +//! +//! \param base is the base address of the CAN controller. +//! +//! This function starts the CAN module's operations after initialization, +//! which includes the CAN protocol controller state machine of the CAN core +//! and the message handler state machine to begin controlling the CAN's +//! internal data flow. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_startModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear Init and CCE bits + // + HWREGH(base + CAN_O_CTL) &= ~(CAN_CTL_INIT | CAN_CTL_CCE); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling +//! CAN_disableController(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CAN_enableController(). The state +//! of the CAN controller and the message objects in the controller are left as +//! they were before this call was made. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Enables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param mode are the the test modes to enable. +//! +//! Enables test modes within the controller. The following valid options for +//! \e mode can be OR'ed together: +//! - \b CAN_TEST_SILENT - Silent Mode +//! - \b CAN_TEST_LBACK - Loopback Mode +//! - \b CAN_TEST_EXL - External Loopback Mode +//! +//! \note Loopback mode and external loopback mode \b can \b not be +//! enabled at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableTestMode(uint32_t base, uint16_t mode) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((mode & (CAN_TEST_LBACK | CAN_TEST_EXL)) != + (CAN_TEST_LBACK | CAN_TEST_EXL)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Enable test mode and set the bits in the test register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_TEST; + HWREGH(base + CAN_O_TEST) |= mode; +} + +//***************************************************************************** +// +//! Disables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables test modes within the controller and clears the test bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableTestMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Clear the test mode enable bit + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_TEST; +} + +//***************************************************************************** +// +//! Get the current settings for the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing. +//! +//! \return Returns the value of the bit timing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getBitTiming(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read and return BTR register + // + return(HWREG_BP(base + CAN_O_BTR)); +} + +//***************************************************************************** +// +//! Enables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables direct access to the RAM while in Test mode. +//! +//! \note Test Mode must first be enabled to use this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) |= CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Disables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables direct access to the RAM while in Test mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) &= ~CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Sets the interruption debug mode of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param enable is a flag to enable or disable the interruption debug mode. +//! +//! This function sets the interruption debug mode of the CAN controller. When +//! the \e enable parameter is \b true, CAN will be configured to interrupt any +//! transmission or reception and enter debug mode immediately after it is +//! requested. When \b false, CAN will wait for a started transmission or +//! reception to be completed before entering debug mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptionDebugMode(uint32_t base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + if(enable) + { + // + // Enable interrupt debug support + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_IDS; + } + else + { + // + // Disable interrupt debug support + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_IDS; + } +} + + +//***************************************************************************** +// +//! Disables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the Auto-Bus-On feature of the CAN controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Enables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also +//! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Sets the time before a Bus-Off recovery sequence is started. +//! +//! \param base is the base address of the CAN controller. +//! \param onTime is number of clock cycles before a Bus-Off recovery sequence +//! is started. +//! +//! This function sets the number of clock cycles before a Bus-Off recovery +//! sequence is started by clearing the Init bit. +//! +//! \note To enable this functionality, use CAN_enableAutoBusOn(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setAutoBusOnTime(uint32_t base, uint32_t onTime) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set bus-off timer value + // + HWREG_BP(base + CAN_O_ABOTR) = onTime; +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Enable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e intFlags parameter has the same definition as in the +//! CAN_enableInterrupt() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Disable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Get the CAN controller Interrupt Line set for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! +//! Gets which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return Returns the value of the interrupt muxing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMux(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Get the interrupt muxing for the CAN peripheral + // + return(HWREG_BP(base + CAN_O_IP_MUX21)); +} + +//***************************************************************************** +// +//! Set the CAN controller Interrupt Line for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! \param mux bit packed representation of which message objects should +//! generate an interrupt on a given interrupt line. +//! +//! Selects which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptMux(uint32_t base, uint32_t mux) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the interrupt muxing for the CAN peripheral + // + HWREG_BP(base + CAN_O_IP_MUX21) = mux; +} + +//***************************************************************************** +// +//! Enables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Disables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +CAN_isRetryEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + return((bool)((HWREGH(base + CAN_O_CTL) & CAN_CTL_DAR) != CAN_CTL_DAR)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param base is the base address of the CAN controller. +//! \param rxCount is a pointer to storage for the receive error counter. +//! \param txCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e rxCount will hold the current receive error count +//! and \e txCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +static inline bool +CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) +{ + uint32_t canError = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the current count of transmit/receive errors. + // + canError = HWREG_BP(base + CAN_O_ERRC); + + // + // Extract the error numbers from the register value. + // + *rxCount = (canError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *txCount = (canError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; + + return((bool)((canError & CAN_ERRC_RP) != 0U)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error and status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the error and status register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint16_t +CAN_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return error and status register value + // + return(HWREGH(base + CAN_O_ES)); +} + +//***************************************************************************** +// +//! Reads the CAN controller TX request register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the TX request register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getTxRequests(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return Tx requests register value + // + return(HWREG_BP(base + CAN_O_TXRQ_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller new data status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the new data status register of the CAN controller for all message +//! objects. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getNewDataFlags(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return new data register value + // + return(HWREG_BP(base + CAN_O_NDAT_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller valid message object register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the valid message object register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getValidMessageObjects(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return the valid message register value + // + return(HWREG_BP(base + CAN_O_MVAL_21)); +} + +//***************************************************************************** +// +//! Get the CAN controller interrupt cause. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function returns the value of the interrupt register that indicates +//! the cause of the interrupt. +//! +//! \return Returns the value of the interrupt register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptCause(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read interrupt identifier status + // + return(HWREG_BP(base + CAN_O_INT)); +} + +//***************************************************************************** +// +//! Get the CAN controller pending interrupt message source. +//! +//! \param base is the base address of the CAN controller. +//! +//! Returns the value of the pending interrupts register that indicates +//! which messages are the source of pending interrupts. +//! +//! \return Returns the value of the pending interrupts register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMessageSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read message object interrupt status + // + return(HWREG_BP(base + CAN_O_IPEN_21)); +} + +//***************************************************************************** +// +//! CAN Global interrupt Enable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Enable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) |= intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Disable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) &= ~intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be cleared. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Clear the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_CLR) |= intFlags; +} + +//***************************************************************************** +// +//! Get the CAN Global Interrupt status. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Check if any interrupt bit is set in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bits are set. False, if +//! none of the requested bits are set. +// +//***************************************************************************** +static inline bool +CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Read and return the global interrupt flag register + // + return((bool)((HWREGH(base + CAN_O_GLB_INT_FLG) & intFlags) != 0U)); +} + +//***************************************************************************** +// +//! Initializes the CAN controller +//! +//! \param base is the base address of the CAN controller. +//! +//! This function initializes the message RAM, which also clears all the +//! message objects, and places the CAN controller in an init state. Write +//! access to the configuration registers is available as a result, allowing +//! the bit timing and message objects to be setup. +//! +//! \note To exit the initialization mode and start the CAN module, use the +//! CAN_startModule() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_initModule(uint32_t base); + +//***************************************************************************** +// +//! Sets the CAN Bit Timing based on requested Bit Rate. +//! +//! \param base is the base address of the CAN controller. +//! \param clockFreq is the CAN module clock frequency before the bit rate +//! prescaler (Hertz) +//! \param bitRate is the desired bit rate (bits/sec) +//! \param bitTime is the number of time quanta per bit required for desired +//! bit time (Tq) and must be in the range from 8 to 25 +//! +//! This function sets the CAN bit timing values for the bit rate passed in the +//! \e bitRate and \e bitTime parameters based on the \e clockFreq parameter. The +//! CAN bit clock is calculated to be an average timing value that should work +//! for most systems. If tighter timing requirements are needed, then the +//! CAN_setBitTiming() function is available for full customization of all of +//! the CAN bit timing values. +//! +//! \note Not all bit-rate and bit-time combinations are valid. +//! For combinations that would yield the correct bit-rate, +//! refer to the DCAN_CANBTR_values.xlsx file in the "docs" directory. +//! The CANBTR register values calculated by the function CAN_setBitRate +//! may not be suitable for your network parameters. If this is the case +//! and you have computed the correct values for your network, you could +//! directly write those parameters in CANBTR register using the +//! function CAN_setBitTiming. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime); + +//***************************************************************************** +// +//! Manually set the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! \param prescaler is the baud rate prescaler +//! \param prescalerExtension is the baud rate prescaler extension +//! \param tSeg1 is the time segment 1 +//! \param tSeg2 is the time segment 2 +//! \param sjw is the synchronization jump width +//! +//! This function sets the various timing parameters for the CAN bus bit +//! timing: baud rate prescaler, prescaler extension, time segment 1, +//! time segment 2, and the Synchronization Jump Width. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw); + + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param base is the base address of the CAN controller. +//! \param intClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e intClr parameter should be either a number from 1 to 32 to clear a +//! specific message object interrupt or can be the following: +//! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); + +//***************************************************************************** +// +//! Setup a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to configure (1-32). +//! \param msgID is the CAN message identifier used for the 11 or 29 bit +//! identifiers +//! \param frame is the CAN ID frame type +//! \param msgType is the message object type +//! \param msgIDMask is the CAN message identifier mask used when identifier +//! filtering is enabled +//! \param flags is the various flags and settings to be set for the message +//! object +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! +//! This function sets the various values required for a message object. +//! +//! The \e frame parameter can be one of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! +//! The \e msgType parameter can be one of the following values: +//! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message +//! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message +//! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message +//! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with +//! auto-transmit +//! +//! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags +//! are required or the parameter can be a logical OR of any of the following +//! values: +//! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts +//! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts +//! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID +//! (Standard or Extended) +//! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use Extended Identifier Bit for filtering +//! (Only among Extended IDs will be accepted) +//! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of +//! the transfer +//! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO +//! structure and isn't the final message +//! object in FIFO +//! +//! If filtering is based on message identifier (for Standard or Extended IDs) +//! specified by the \e msgIDMask parameter, the value \b CAN_MSG_OBJ_USE_ID_FILTER +//! has to be logically ORed with the \e flag parameter. +//! If \b CAN_MSG_OBJ_USE_EXT_FILTER is ORed with the \e flag parameter, +//! only extended identifier frames are accepted which can further be masked +//! by using the flag above. +//! +//! \note The \b msgLen Parameter for the Receive Message Object is a "don't +//! care" but its value should be between 0-8 due to the assert. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 16 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 32 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object while dynamically updating data length +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable and can be used to dynamically update the data length +//! for every subsequent call of this function. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Remote Request Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! +//! This function is used to transmit a remote request message object. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function with CAN_MSG_OBJ_TYPE_TX_REMOTE +//! as msgType flag. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Reads the data in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param msgData is a pointer to the array to store the message data +//! +//! This function is used to read the data contents of the specified message +//! object in the CAN controller. The data returned is stored in the +//! \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! -# If the DLC of the received message is larger than the \e msgData +//! buffer provided, then it is possible for a buffer overflow to occur. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData); + +//***************************************************************************** +// +//! Reads the data and Message ID in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param frameType is a pointer to the CAN_MsgFrameType to store the message +//! type that has been received in the mailbox +//! The \e frameType parameter shall be filled as of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! This parameter is filled when return value is true for this function. +//! \param msgID is a pointer to storage for the received Message ID +//! Filled when the return value is true for this function. +//! \param msgData is a pointer to the array to store the message data +//! Filled with read Data when the return value is true for this function. +//! +//! This function is used to read the data contents and the Message ID +//! of the specified message object in the CAN controller.The Message ID returned +//! is stored in the \e msgID parameter and its type in \e frameType parameter. +//! The data returned is stored in the \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData); + + + +//***************************************************************************** +// +//! Transfers a CAN message between the IF registers and Message RAM. +//! +//! \param base is the base address of the CAN controller. +//! \param interface is the interface to use for the transfer. Valid value are +//! 1 or 2. +//! \param objID is the object number to transfer (1-32). +//! \param direction is the direction of data transfer. False is Message RAM +//! to IF, True is IF to Message RAM. +//! +//! This function transfers the contents of the interface registers to message +//! RAM or vice versa depending on the value passed to direction. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction); + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function frees(disables) the specified message object from use. Once +//! a message object has been cleared, it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables specific message object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function disables the specific message object. Once the message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableMessageObject(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables all message objects +//! +//! \param base is the base address of the CAN controller. +//! +//! This function disables all message objects. Once a message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. All message objects are disabled automatically on +//! reset, however this function can be used to restart CAN operations +//! without an external reset. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableAllMessageObjects(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CAN_H diff --git a/gpio_bitfield_cpu2/device/driverlib/ccs/Debug/driverlib.lib b/gpio_bitfield_cpu2/device/driverlib/ccs/Debug/driverlib.lib new file mode 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100644 index 0000000..d933af4 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cla.c @@ -0,0 +1,89 @@ +//########################################################################### +// +// FILE: cla.c +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cla.h" + +//***************************************************************************** +// +// CLA_setTriggerSource() +// +//***************************************************************************** +void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger) +{ + uint32_t srcSelReg; + uint32_t shiftVal; + + // + // Calculate the shift value for the specified task. + // + shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U; + + // + // Calculate the register address for the specified task. + // + if(taskNumber <= CLA_TASK_4) + { + // + // Tasks 1-4 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1; + } + else + { + // + // Tasks 5-8 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2; + } + + EALLOW; + + // + // Write trigger selection to the appropriate register. + // + HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M + << shiftVal); + HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal); + + EDIS; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/cla.h b/gpio_bitfield_cpu2/device/driverlib/cla.h new file mode 100644 index 0000000..fee905c --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cla.h @@ -0,0 +1,984 @@ +//########################################################################### +// +// FILE: cla.h +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLA_H +#define CLA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cla_api CLA +//! \brief This module is used for configurating CLA. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "cpu.h" +#include "debug.h" +#include "inc/hw_cla.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CLA_NUM_EOT_INTERRUPTS (8U) + + +//***************************************************************************** +// +// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(), +// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt() +// as the taskFlags parameter. +// +//***************************************************************************** +#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag +#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag +#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag +#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag +#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag +#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag +#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag +#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag +#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag + +//***************************************************************************** +// +//! Values that can be passed to CLA_getPendingTaskFlag(), +//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(), +//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt() +//! as the taskNumber parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TASK_1, //!< CLA Task 1 + CLA_TASK_2, //!< CLA Task 2 + CLA_TASK_3, //!< CLA Task 3 + CLA_TASK_4, //!< CLA Task 4 + CLA_TASK_5, //!< CLA Task 5 + CLA_TASK_6, //!< CLA Task 6 + CLA_TASK_7, //!< CLA Task 7 + CLA_TASK_8 //!< CLA Task 8 +} CLA_TaskNumber; + +#ifdef __TMS320C28XX__ // These enums are only accessible by C28x +//***************************************************************************** +// +//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1 + CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2 + CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3 + CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4 + CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5 + CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6 + CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7 + CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8 +} CLA_MVECTNumber; + +//***************************************************************************** +// +//! Values that can be passed to CLA_setTriggerSource() as the \e trigger +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software + + CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1 + CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2 + CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3 + CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4 + CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT + CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1 + CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2 + CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3 + CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4 + CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT + CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1 + CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2 + CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3 + CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4 + CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT + CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1 + CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2 + CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3 + CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4 + CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT + + CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1 + CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2 + CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3 + CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4 + CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5 + + CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT + CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT + CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT + CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT + CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT + CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT + CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT + CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT + CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT + CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT + CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT + CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT + + + CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0 + CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1 + CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2 + + CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA + CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA + CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB + CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB + + CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT + CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT + CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT + CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT + CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT + CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT + + CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT + CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT + CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT + + + CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT + CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT + + + + CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT + + CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT + CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT + CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT + CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT + CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT + CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT + + + + + + CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT + CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT + CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT + CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT + +} CLA_Trigger; +#endif // __TMS320C28XX__ + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a CLA base address. +//! +//! \param base is the base address of the CLA controller. +//! +//! This function determines if a CLA controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CLA_isBaseValid(uint32_t base) +{ + return(base == CLA1_BASE); +} +#endif + +#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x +//***************************************************************************** +// +//! Map CLA Task Interrupt Vector +//! +//! \param base is the base address of the CLA controller. +//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8) +//! the value of claIntVect can be any of the following: +//! - \b CLA_MVECT_1 - Task Interrupt Vector 1 +//! - \b CLA_MVECT_2 - Task Interrupt Vector 2 +//! - \b CLA_MVECT_3 - Task Interrupt Vector 3 +//! - \b CLA_MVECT_4 - Task Interrupt Vector 4 +//! - \b CLA_MVECT_5 - Task Interrupt Vector 5 +//! - \b CLA_MVECT_6 - Task Interrupt Vector 6 +//! - \b CLA_MVECT_7 - Task Interrupt Vector 7 +//! - \b CLA_MVECT_8 - Task Interrupt Vector 8 +//! \param claTaskAddr is the start address of the code for task +//! +//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is +//! triggered, the CLA loads the MVECTx register of the task in question +//! to the MPC (CLA program counter) and begins execution from that point. +//! The CLA has a 16-bit address bus, and can therefore, access the lower +//! 64 KW space. The MVECTx registers take an address anywhere in this space. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect, + uint16_t claTaskAddr) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + HWREGH(base + (uint16_t)claIntVect) = claTaskAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Hard Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a hard reset of the CLA and set all CLA registers +//! to their default state. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performHardReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Hard reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! Soft Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a soft reset of the CLA. This will stop the +//! current task, clear the MIRUN flag and clear all bits in the MIER register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performSoftReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Soft reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! IACK enable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function enables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! IACK disable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function disables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! Query task N to see if it is flagged and pending execution +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the interrupt flag register +//! corresponds to a CLA task. The corresponding bit is automatically set +//! when the task is triggered (either from a peripheral, through software, or +//! through the MIFRC register). The bit gets cleared when the CLA starts to +//! execute the flagged task. +//! +//! \return \b True if the queried task has been triggered but pending +//! execution. +// +//***************************************************************************** +static inline bool +CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the interrupt flag register (MIFR) +//! +//! \return the value of Interrupt Flag Register (MIFR) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllPendingTaskFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Flag Register (MIFR) since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIFR); + + // + // Return the Interrupt Flag Register value + // + return(status); +} + +//***************************************************************************** +// +//! Get status of Task n Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the overflow flag register +//! corresponds to a CLA task, This bit is set when an interrupt overflow event +//! has occurred for the specific task. +//! +//! \return True if any of task interrupt overflow has occurred. +// +//***************************************************************************** +static inline bool +CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the Interrupt Overflow Flag Register +//! +//! \return the value of Interrupt Overflow Flag Register(MIOVF) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskOverflowFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return Interrupt Overflow Flag Register(MIOVF) since that is what + // was requested. + // + status = HWREGH(base + CLA_O_MIOVF); + + // + // Return the Interrupt Overflow Flag Register + // + return(status); +} + +//***************************************************************************** +// +//! Clear the task interrupt flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to clear all flags. +//! +//! This function is used to manually clear bits in the interrupt +//! flag (MIFR) register +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + //Modify protected register + // + EALLOW; + + // + // Clear the task interrupt flag + // + HWREGH(base + CLA_O_MICLR) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Force a CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be forced +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to force all tasks. +//! +//! This function forces a task through software. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Force the task interrupt. + // + HWREGH(base + CLA_O_MIFRC) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enable CLA task(s) +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to enable all tasks +//! +//! This function allows an incoming interrupt or main CPU software to +//! start the corresponding CLA task. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable CLA task + // + HWREGH(base + CLA_O_MIER) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disable CLA task interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to disable all tasks +//! +//! This function disables CLA task interrupt by setting the MIER register bit +//! to 0, while the corresponding task is executing this will have no effect +//! on the task. The task will continue to run until it hits the MSTOP +//! instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Disable CLA task interrupt + // + HWREGH(base + CLA_O_MIER) &= ~taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Get the value of a task run status +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the Interrupt Run Status +//! Register which indicates whether the task is currently executing +//! +//! \return True if the task is executing. +// +//***************************************************************************** +static inline bool +CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get the value of all task run status +//! +//! \param base is the base address of the CLA controller. +//! +//! This function indicates which task is currently executing. +//! +//! \return the value of Interrupt Run Status Register (MIRUN) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskRunStatus(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Run Status Register since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIRUN); + + // + // Return the Interrupt Run Status Register (MIRUN) + // + return(status); +} +#endif // #ifdef __TMS320C28XX__ + +// +// These functions are accessible only from the CLA (Type - 1/2) +// +#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) +//***************************************************************************** +// +//! Enable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks +//! +//! This function enables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its +//! ability to generate an end-of-task interrupt +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags; + + __medis(); +} + +//***************************************************************************** +// +//! Disable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all +//! tasks +//! +//! This function disables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 0 to the task's bit in the +//! CLA1SOFTINTEN register. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Disabling a given task's software interrupt ability allows that +//! task to generate an End-of-Task interrupt to the main CPU. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags; + + __medis(); +} +//***************************************************************************** +// +//! Force a particular Task's Software Interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the task's whose software +//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks +//! +//! This function forces the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1INTFRC register. +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! -# This function will set the INTFRC bit for a task, but does not check +//! that its SOFTINT bit is set. It falls to the user to ensure that software +//! interrupt for a given task is enabled before it can be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Force Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags; + + __medis(); +} + +#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) + +// +// These functions can only be called from the C28x +// +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! Configures CLA task triggers. +//! +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. +//! \param trigger is the trigger source to be assigned to the selected task. +//! +//! This function configures the trigger source of a CLA task. The +//! \e taskNumber parameter indicates which task is being configured, and the +//! \e trigger parameter is the interrupt source from a specific peripheral +//! interrupt (or software) that will trigger the task. +//! +//! \return None. +// +//***************************************************************************** +extern void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger); + +#endif //#ifdef __TMS320C28XX__ +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLA_H diff --git a/gpio_bitfield_cpu2/device/driverlib/clb.c b/gpio_bitfield_cpu2/device/driverlib/clb.c new file mode 100644 index 0000000..2e79cb4 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/clb.c @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: clb.c +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "clb.h" + +//***************************************************************************** +// +// CLB_configCounterLoadMatch +// +//***************************************************************************** +void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, uint32_t match2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + switch(counterID) + { + case CLB_CTR0: + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2); + break; + + case CLB_CTR1: + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2); + break; + + case CLB_CTR2: + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2); + break; + + default: + // + // Invalid counterID value + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// CLB_clearFIFOs +// +//***************************************************************************** +void CLB_clearFIFOs(uint32_t base) +{ + uint16_t i; + + ASSERT(CLB_isBaseValid(base)); + + for(i = 0U; i < CLB_FIFO_SIZE; i++) + { + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U; + } + + HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U; +} + +//***************************************************************************** +// +// CLB_writeFIFOs +// +//***************************************************************************** +void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Clear the FIFO and pointer + // + CLB_clearFIFOs(base); + + // + // Write data into the FIFO. + // + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0U)) = pullData[0U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1U)) = pullData[1U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2U)) = pullData[2U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3U)) = pullData[3U]; +} + +//***************************************************************************** +// +// CLB_readFIFOs +// +//***************************************************************************** +void CLB_readFIFOs(uint32_t base , uint32_t pushData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Read data from the FIFO. + // + pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0U)) ; + pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1U)) ; + pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2U)) ; + pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3U)) ; +} + + diff --git a/gpio_bitfield_cpu2/device/driverlib/clb.h b/gpio_bitfield_cpu2/device/driverlib/clb.h new file mode 100644 index 0000000..37cb68f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/clb.h @@ -0,0 +1,1290 @@ +//########################################################################### +// +// FILE: clb.h +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLB_H +#define CLB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup clb_api CLB +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clb.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Address offsets from LOGICCFG to LOGICCTL and DATAEXCH register memory maps +// +//***************************************************************************** +#define CLB_LOGICCTL 0x0100U +#define CLB_DATAEXCH 0x0200U + +//***************************************************************************** +// +// Address offsets for CLB-internal memory space +// +//***************************************************************************** +#define CLB_ADDR_COUNTER_0_LOAD 0x0U +#define CLB_ADDR_COUNTER_1_LOAD 0x1U +#define CLB_ADDR_COUNTER_2_LOAD 0x2U + +#define CLB_ADDR_COUNTER_0_MATCH1 0x4U +#define CLB_ADDR_COUNTER_1_MATCH1 0x5U +#define CLB_ADDR_COUNTER_2_MATCH1 0x6U + +#define CLB_ADDR_COUNTER_0_MATCH2 0x8U +#define CLB_ADDR_COUNTER_1_MATCH2 0x9U +#define CLB_ADDR_COUNTER_2_MATCH2 0xAU + +#define CLB_ADDR_HLC_R0 0xCU +#define CLB_ADDR_HLC_R1 0xDU +#define CLB_ADDR_HLC_R2 0xEU +#define CLB_ADDR_HLC_R3 0xFU + +#define CLB_ADDR_HLC_BASE 0x20U +#define CLB_NUM_HLC_INSTR 31U + +//***************************************************************************** +// +// PUSH/PULL FIFO size (32-bit registers) +// +//***************************************************************************** +#define CLB_FIFO_SIZE 4U + +//***************************************************************************** +// +// Key to enable writes to the CLB registers +// +//***************************************************************************** +#define CLB_LOCK_KEY 0x5A5AU + +//***************************************************************************** +// +// Shift and masks needed by the API for Input selection +// +//***************************************************************************** +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U + +//***************************************************************************** +// +//! Values that can be passed to control the CLB output enable signal. It can +//! be passed to CLB_setOutputMask() as the \e outputMask parameter. +// +//***************************************************************************** +#define CLB_OUTPUT_00 0x00000001U //!< Mask for CLB OUTPUT ENABLE/DISABLE 0 +#define CLB_OUTPUT_01 0x00000002U //!< Mask for CLB OUTPUT ENABLE/DISABLE 1 +#define CLB_OUTPUT_02 0x00000004U //!< Mask for CLB OUTPUT ENABLE/DISABLE 2 +#define CLB_OUTPUT_03 0x00000008U //!< Mask for CLB OUTPUT ENABLE/DISABLE 3 +#define CLB_OUTPUT_04 0x00000010U //!< Mask for CLB OUTPUT ENABLE/DISABLE 4 +#define CLB_OUTPUT_05 0x00000020U //!< Mask for CLB OUTPUT ENABLE/DISABLE 5 +#define CLB_OUTPUT_06 0x00000040U //!< Mask for CLB OUTPUT ENABLE/DISABLE 6 +#define CLB_OUTPUT_07 0x00000080U //!< Mask for CLB OUTPUT ENABLE/DISABLE 7 +#define CLB_OUTPUT_08 0x00000100U //!< Mask for CLB OUTPUT ENABLE/DISABLE 8 +#define CLB_OUTPUT_09 0x00000200U //!< Mask for CLB OUTPUT ENABLE/DISABLE 9 +#define CLB_OUTPUT_10 0x00000400U //!< Mask for CLB OUTPUT ENABLE/DISABLE 10 +#define CLB_OUTPUT_11 0x00000800U //!< Mask for CLB OUTPUT ENABLE/DISABLE 11 +#define CLB_OUTPUT_12 0x00001000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 12 +#define CLB_OUTPUT_13 0x00002000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 13 +#define CLB_OUTPUT_14 0x00004000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 14 +#define CLB_OUTPUT_15 0x00008000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 15 +#define CLB_OUTPUT_16 0x00010000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 16 +#define CLB_OUTPUT_17 0x00020000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 17 +#define CLB_OUTPUT_18 0x00040000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 18 +#define CLB_OUTPUT_19 0x00080000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 19 +#define CLB_OUTPUT_20 0x00100000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 20 +#define CLB_OUTPUT_21 0x00200000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 21 +#define CLB_OUTPUT_22 0x00400000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 22 +#define CLB_OUTPUT_23 0x00800000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 23 +#define CLB_OUTPUT_24 0x01000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 24 +#define CLB_OUTPUT_25 0x02000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 25 +#define CLB_OUTPUT_26 0x04000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 26 +#define CLB_OUTPUT_27 0x08000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 27 +#define CLB_OUTPUT_28 0x10000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 28 +#define CLB_OUTPUT_29 0x20000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 29 +#define CLB_OUTPUT_30 0x40000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 30 +#define CLB_OUTPUT_31 0x80000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 31 + +//***************************************************************************** +// +//! Values that can be passed to select CLB input signal +// +//***************************************************************************** +typedef enum +{ + CLB_IN0 = 0, //!< Input 0 + CLB_IN1 = 1, //!< Input 1 + CLB_IN2 = 2, //!< Input 2 + CLB_IN3 = 3, //!< Input 3 + CLB_IN4 = 4, //!< Input 4 + CLB_IN5 = 5, //!< Input 5 + CLB_IN6 = 6, //!< Input 6 + CLB_IN7 = 7 //!< Input 7 +} CLB_Inputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB output signal. It can be passed to +//! CLB_configOutputLUT() as the \e outID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_OUT0 = 0, //!< Output 0 + CLB_OUT1 = 1, //!< Output 1 + CLB_OUT2 = 2, //!< Output 2 + CLB_OUT3 = 3, //!< Output 3 + CLB_OUT4 = 4, //!< Output 4 + CLB_OUT5 = 5, //!< Output 5 + CLB_OUT6 = 6, //!< Output 6 + CLB_OUT7 = 7 //!< Output 7 +} CLB_Outputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB counter. It can be passed to +//! CLB_configCounterLoadMatch() as the \e counterID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_CTR0 = 0, //!< Counter 0 + CLB_CTR1 = 1, //!< Counter 1 + CLB_CTR2 = 2 //!< Counter 2 +} CLB_Counters; + +//***************************************************************************** +// +//! Values that can be passed to CLB_getRegister() as the \e registerID +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_REG_HLC_R0 = CLB_O_DBG_R0, //!< HLC R0 register + CLB_REG_HLC_R1 = CLB_O_DBG_R1, //!< HLC R1 register + CLB_REG_HLC_R2 = CLB_O_DBG_R2, //!< HLC R2 register + CLB_REG_HLC_R3 = CLB_O_DBG_R3, //!< HLC R3 register + CLB_REG_CTR_C0 = CLB_O_DBG_C0, //!< Counter 0 register + CLB_REG_CTR_C1 = CLB_O_DBG_C1, //!< Counter 1 register + CLB_REG_CTR_C2 = CLB_O_DBG_C2 //!< Counter 2 register +} CLB_Register; + +//***************************************************************************** +// +//! Values that can be passed to CLB_selectInputFilter() as the \e filterType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_FILTER_NONE = 0, //!< No filtering + CLB_FILTER_RISING_EDGE = 1, //!< Rising edge detect + CLB_FILTER_FALLING_EDGE = 2, //!< Falling edge detect + CLB_FILTER_ANY_EDGE = 3 //!< Any edge detect +} CLB_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGPInputMux() as the \e gpMuxCfg +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GP_IN_MUX_EXTERNAL = 0, //!< Use external input path + CLB_GP_IN_MUX_GP_REG = 1 //!< Use CLB_GP_REG bit value as input +} CLB_GPInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configLocalInputMux() as the +//! \e localMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_LOCAL_IN_MUX_GLOBAL_IN = 0, //!< Global input mux selection + CLB_LOCAL_IN_MUX_EPWM_DCAEVT1 = 1, //!< EPWMx DCAEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCAEVT2 = 2, //!< EPWMx DCAEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT1 = 3, //!< EPWMx DCBEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT2 = 4, //!< EPWMx DCBEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCAH = 5, //!< EPWMx DCAH + CLB_LOCAL_IN_MUX_EPWM_DCAL = 6, //!< EPWMx DCAL + CLB_LOCAL_IN_MUX_EPWM_DCBH = 7, //!< EPWMx DCBH + CLB_LOCAL_IN_MUX_EPWM_DCBL = 8, //!< EPWMx DCBL + CLB_LOCAL_IN_MUX_EPWM_OST = 9, //!< EPWMx OST + CLB_LOCAL_IN_MUX_EPWM_CBC = 10, //!< EPWMx CBC + CLB_LOCAL_IN_MUX_ECAP_ECAPIN = 11, //!< ECAPx ECAPIN + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT = 12, //!< ECAPx ECAP_OUT + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN = 13, //!< ECAPx ECAP_OUT_EN + CLB_LOCAL_IN_MUX_ECAP_CEVT1 = 14, //!< ECAPx CEVT1 + CLB_LOCAL_IN_MUX_ECAP_CEVT2 = 15, //!< ECAPx CEVT2 + CLB_LOCAL_IN_MUX_ECAP_CEVT3 = 16, //!< ECAPx CEVT3 + CLB_LOCAL_IN_MUX_ECAP_CEVT4 = 17, //!< ECAPx CEVT4 + CLB_LOCAL_IN_MUX_EQEP_EQEPA = 18, //!< EQEPx EQEPA + CLB_LOCAL_IN_MUX_EQEP_EQEPB = 19, //!< EQEPx EQEPB + CLB_LOCAL_IN_MUX_EQEP_EQEPI = 20, //!< EQEPx EQEPI + CLB_LOCAL_IN_MUX_EQEP_EQEPS = 21, //!< EQEPx EQEPS + CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC = 22, //!< CPU1.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC = 23, //!< CPU2.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU1_HALT = 24, //!< CPU1.HALT + CLB_LOCAL_IN_MUX_CPU2_HALT = 25, //!< CPU2.HALT +} CLB_LocalInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGlobalInputMux() as the +//! \e globalMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GLOBAL_IN_MUX_EPWM1A = 0, //!< EPWM1A + CLB_GLOBAL_IN_MUX_EPWM1A_OE = 1, //!< EPWM1A trip output + CLB_GLOBAL_IN_MUX_EPWM1B = 2, //!< EPWM1B + CLB_GLOBAL_IN_MUX_EPWM1B_OE = 3, //!< EPWM1B trip output + CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO = 4, //!< EPWM1 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD = 5, //!< EPWM1 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR = 6, //!< EPWM1 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM1_TBCLK = 7, //!< EPWM1 TBCLK + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA = 8, //!< EPWM1 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB = 9, //!< EPWM1 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC = 10, //!< EPWM1 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD = 11, //!< EPWM1 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM1A_AQ = 12, //!< EPWM1A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_AQ = 13, //!< EPWM1B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1A_DB = 14, //!< EPWM1A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_DB = 15, //!< EPWM1B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM2A = 16, //!< EPWM2A + CLB_GLOBAL_IN_MUX_EPWM2A_OE = 17, //!< EPWM2A trip output + CLB_GLOBAL_IN_MUX_EPWM2B = 18, //!< EPWM2B + CLB_GLOBAL_IN_MUX_EPWM2B_OE = 19, //!< EPWM2B trip output + CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO = 20, //!< EPWM2 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD = 21, //!< EPWM2 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR = 22, //!< EPWM2 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM2_TBCLK = 23, //!< EPWM2 TBCLK + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA = 24, //!< EPWM2 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB = 25, //!< EPWM2 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC = 26, //!< EPWM2 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD = 27, //!< EPWM2 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM2A_AQ = 28, //!< EPWM2A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_AQ = 29, //!< EPWM2B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2A_DB = 30, //!< EPWM2A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_DB = 31, //!< EPWM2B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM3A = 32, //!< EPWM3A + CLB_GLOBAL_IN_MUX_EPWM3A_OE = 33, //!< EPWM3A trip output + CLB_GLOBAL_IN_MUX_EPWM3B = 34, //!< EPWM3B + CLB_GLOBAL_IN_MUX_EPWM3B_OE = 35, //!< EPWM3B trip output + CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO = 36, //!< EPWM3 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD = 37, //!< EPWM3 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR = 38, //!< EPWM3 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM3_TBCLK = 39, //!< EPWM3 TBCLK + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA = 40, //!< EPWM3 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB = 41, //!< EPWM3 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC = 42, //!< EPWM3 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD = 43, //!< EPWM3 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM3A_AQ = 44, //!< EPWM3A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_AQ = 45, //!< EPWM3B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3A_DB = 46, //!< EPWM3A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_DB = 47, //!< EPWM3B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM4A = 48, //!< EPWM4A + CLB_GLOBAL_IN_MUX_EPWM4A_OE = 49, //!< EPWM4A trip output + CLB_GLOBAL_IN_MUX_EPWM4B = 50, //!< EPWM4B + CLB_GLOBAL_IN_MUX_EPWM4B_OE = 51, //!< EPWM4B trip output + CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO = 52, //!< EPWM4 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD = 53, //!< EPWM4 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR = 54, //!< EPWM4 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM4_TBCLK = 55, //!< EPWM4 TBCLK + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA = 56, //!< EPWM4 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB = 57, //!< EPWM4 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC = 58, //!< EPWM4 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD = 59, //!< EPWM4 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM4A_AQ = 60, //!< EPWM4A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_AQ = 61, //!< EPWM4B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4A_DB = 62, //!< EPWM4A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_DB = 63, //!< EPWM4B DB submodule output + + CLB_GLOBAL_IN_MUX_CLB_AUXSIG0 = 64, //!< CLB X-BAR AUXSIG0 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG1 = 65, //!< CLB X-BAR AUXSIG1 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG2 = 66, //!< CLB X-BAR AUXSIG2 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG3 = 67, //!< CLB X-BAR AUXSIG3 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG4 = 68, //!< CLB X-BAR AUXSIG4 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG5 = 69, //!< CLB X-BAR AUXSIG5 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG6 = 70, //!< CLB X-BAR AUXSIG6 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG7 = 71, //!< CLB X-BAR AUXSIG7 + +} CLB_GlobalInputMux; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +// +//! +//! Checks the CLB base address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CLB_isBaseValid(uint32_t base) +{ + return( + (base == CLB1_BASE) || + (base == CLB2_BASE) || + (base == CLB3_BASE) || + (base == CLB4_BASE) + ); +} + +//***************************************************************************** +// +//! +//! Checks the CLB internal memory address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the address is valid and \b false otherwise. +// +//***************************************************************************** +static inline bool CLB_isAddressValid(uint32_t address) +{ + return(address <= (CLB_ADDR_HLC_BASE + CLB_NUM_HLC_INSTR)); +} +#endif + +//***************************************************************************** +// +//! Set global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Clear global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function disables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) &= ~CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enable CLB lock. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the lock bit of the lock register. The lock can only +//! be set once and can only be cleared by a device reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableLock(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Setting the lock bit requires key 0x5A5A to be written at the same time + // + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOCK) = + (uint32_t)CLB_LOCK_LOCK | ((uint32_t)CLB_LOCK_KEY << CLB_LOCK_KEY_S); + EDIS; +} + +//***************************************************************************** +// +//! Write value to address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param address is the address of CLB internal memory. +//! \param value is the value to write to specified address. +//! +//! This function writes the specified value to CLB internal memory. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_writeInterface(uint32_t base, uint32_t address, + uint32_t value) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(CLB_isAddressValid(address)); + + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_ADDR) = address; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_DATA) = value; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_LOAD_EN; + EDIS; +} + +//***************************************************************************** +// +//! Select input filter type. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param filterType is the selected type of filter applied to the input. +//! +//! This function configures the filter selection for the specified input. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e filterType parameter can have one enumeration value from +//! CLB_FilterType. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectInputFilter(uint32_t base, CLB_Inputs inID, + CLB_FilterType filterType) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 2-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID << 1; + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) & + ~(CLB_INPUT_FILTER_FIN0_M << shiftVal)) | + ((uint16_t)filterType << shiftVal); +} + +//***************************************************************************** +// +//! Enables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function enables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) |= + (1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Disables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function disables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) &= + ~(1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Configures the general purpose input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param gpMuxCfg is the mux selection for the general purpose input mux. +//! +//! This function configures the general purpose input mux. The \e gpMuxCfg +//! parameter can select either the use of an external input signal +//! (\b CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit +//! as an input (\b CLB_GP_IN_MUX_GP_REG). +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \sa CLB_setGPREG() to write to the CLB_GP_REG. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGPInputMux(uint32_t base, CLB_Inputs inID, + CLB_GPInputMux gpMuxCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) & + ~(CLB_IN_MUX_SEL_0_SEL_GP_IN_0 << (uint16_t)inID)) | + ((uint16_t)gpMuxCfg << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Sets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param gpRegVal is the value to be written to CLB_GP_REG. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setGPREG(uint32_t base, uint32_t gpRegVal) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG) = gpRegVal; +} + +//***************************************************************************** +// +//! Gets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return CLB_GP_REG value. +// +//***************************************************************************** +static inline uint32_t CLB_getGPREG(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG)); +} + +//***************************************************************************** +// +//! Configures the local input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param localMuxCfg is the mux selection for the local input mux. +//! +//! This function configures the local input mux for the specified input +//! signal. +//! +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e localMuxCfg parameter can have one enumeration value from +//! CLB_LocalInputMux. +//! +//! \note The local input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLocalInputMux(uint32_t base, CLB_Inputs inID, + CLB_LocalInputMux localMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each local input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } + else + { + // + // Calculating shift amount for inputs > input3 + // + shiftVal -= 4U * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Configures the global input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param globalMuxCfg is the mux selection for the global input mux. +//! +//! This function configures the global input mux for the specified input +//! signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e globalMuxCfg parameter can have one enumeration value from +//! CLB_GlobalInputMux. +//! +//! \note The global input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGlobalInputMux(uint32_t base, CLB_Inputs inID, + CLB_GlobalInputMux globalMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } + else + { + shiftVal -= 4U * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Controls the output enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outputMask is a mask of the outputs to be enabled. +//! \param enable is a switch to decide if the CLB outputs need to be enabled +//! or not. +//! +//! This function is used to enable and disable CLB outputs by writing a mask +//! to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the +//! corresponding output is enabled; when a bit is 0, the output is disabled. +//! +//! The \e outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x +//! values that correspond to the CLB OUTPUT ENABLE for the respective outputs. +//! The \e enable parameter can have one of the values from: +//! false: Disable the respective CLB outputs +//! true: Enable the respective CLB outputs +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setOutputMask(uint32_t base, uint32_t outputMask , + bool enable) +{ + ASSERT(CLB_isBaseValid(base)); + + if(enable == true) + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) |= outputMask; + } + else + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) &= ~outputMask; + } +} + +//***************************************************************************** +// +//! Reads the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the value in the interrupt tag register which is a 6-bit +//! constant set by the HLC. +// +//***************************************************************************** +static inline uint16_t CLB_getInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG)); +} + +//***************************************************************************** +// +//! Clears the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the interrupt tag register, setting it to 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_clearInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG) = 0U; +} + +//***************************************************************************** +// +//! Selects LUT4 inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4In0 is the value for LUT4 input signal 0. Generated by tool as +//! \b TILEx_CFG_LUT4_IN0. +//! \param lut4In1 is the value for LUT4 input signal 1. Generated by tool as +//! \b TILEx_CFG_LUT4_IN1. +//! \param lut4In2 is the value for LUT4 input signal 2. Generated by tool as +//! \b TILEx_CFG_LUT4_IN2. +//! \param lut4In3 is the value for LUT4 input signal 3. Generated by tool as +//! \b TILEx_CFG_LUT4_IN3. +//! +//! This function configures the LUT4 block's input signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectLUT4Inputs(uint32_t base, uint32_t lut4In0, + uint32_t lut4In1, uint32_t lut4In2, + uint32_t lut4In3) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_IN0) = lut4In0; + HWREG(base + CLB_O_LUT4_IN1) = lut4In1; + HWREG(base + CLB_O_LUT4_IN2) = lut4In2; + HWREG(base + CLB_O_LUT4_IN3) = lut4In3; + EDIS; +} + +//***************************************************************************** +// +//! Configures LUT4 functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4Fn10 is the equation value for LUT4 blocks 0 and 1. Generated by +//! tool as \b TILEx_CFG_LUT4_FN10. +//! \param lut4Fn2 is the equation value for LUT4 block2. Generated by tool as +//! \b TILEx_CFG_LUT4_FN2. +//! +//! This function configures the LUT4 block's equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLUT4Function(uint32_t base, uint32_t lut4Fn10, + uint32_t lut4Fn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_FN1_0) = lut4Fn10; + HWREG(base + CLB_O_LUT4_FN2) = lut4Fn2; + EDIS; +} + +//***************************************************************************** +// +//! Selects FSM inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param external0 is the value for FSM external 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN0. +//! \param external1 is the value for FSM external 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN1. +//! \param extra0 is the value for FSM extra 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN0. +//! \param extra1 is the value for FSM extra 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN1. +//! +//! This function configures the FSM block's external inputs and extra external +//! inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectFSMInputs(uint32_t base, uint32_t external0, + uint32_t external1, uint32_t extra0, + uint32_t extra1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_EXTERNAL_IN0) = external0; + HWREG(base + CLB_O_FSM_EXTERNAL_IN1) = external1; + HWREG(base + CLB_O_FSM_EXTRA_IN0) = extra0; + HWREG(base + CLB_O_FSM_EXTRA_IN1) = extra1; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM LUT function. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param fsmLutFn10 is the value for FSM 0 & FSM 1 LUT function. Generated +//! by tool as \b TILEx_CFG_FSM_LUT_FN10. +//! \param fsmLutFn2 is the value for FSM 2 LUT function. Generated by tool as +//! \b TILEx_CFG_FSM_LUT_FN2. +//! +//! This function configures the FSM block's LUT equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMLUTFunction(uint32_t base, uint32_t fsmLutFn10, + uint32_t fsmLutFn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_LUT_FN1_0) = fsmLutFn10; + HWREG(base + CLB_O_FSM_LUT_FN2) = fsmLutFn2; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM next state. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param nextState0 is the value for FSM 0's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_0. +//! \param nextState1 is the value for FSM 1's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_1. +//! \param nextState2 is the value for FSM 2's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_2. +//! +//! This function configures the FSM's next state equation. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMNextState(uint32_t base, uint32_t nextState0, + uint32_t nextState1, + uint32_t nextState2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_NEXT_STATE_0) = nextState0; + HWREG(base + CLB_O_FSM_NEXT_STATE_1) = nextState1; + HWREG(base + CLB_O_FSM_NEXT_STATE_2) = nextState2; + EDIS; +} + +//***************************************************************************** +// +//! Selects Counter inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param reset is the value for counter's reset inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_RESET. +//! \param event is the value for counter's event inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_EVENT. +//! \param mode0 is the value for counter's mode 0 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_0. +//! \param mode1 is the value for counter's mode 1 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_1. +//! +//! This function selects the input signals to the counter block. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectCounterInputs(uint32_t base, uint32_t reset, + uint32_t event, uint32_t mode0, + uint32_t mode1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_COUNT_RESET) = reset; + HWREG(base + CLB_O_COUNT_EVENT) = event; + HWREG(base + CLB_O_COUNT_MODE_0) = mode0; + HWREG(base + CLB_O_COUNT_MODE_1) = mode1; + EDIS; +} + +//***************************************************************************** +// +//! Configures Counter and FSM modes. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param miscCtrl is the value to represent counter and FSM modes. +//! Generated by tool as \b TILEx_CFG_MISC_CONTROL. +//! +//! This function configures the counter mode, particularly add/shift, load +//! modes. The function also configures whether the FSM should use state inputs +//! or an extra external input. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configMiscCtrlModes(uint32_t base, uint32_t miscCtrl) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_MISC_CONTROL) = miscCtrl; + EDIS; +} + +//***************************************************************************** +// +//! Configures Output LUT functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outID is the specified CLB tile output signal. +//! \param outputCfg is the value for the output LUT signal function and input +//! signal selections. Generated by tool as \b TILEx_CFG_OUTLUT_n where +//! n is the output number. +//! +//! This function configures the input signals and equations of the output LUT +//! corresponding to the /e outID parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configOutputLUT(uint32_t base, CLB_Outputs outID, + uint32_t outputCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_OUTPUT_LUT_0 + (sizeof(uint32_t) * outID)) = outputCfg; + EDIS; +} + +//***************************************************************************** +// +//! Configures HLC event selection. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param eventSel is the value for HLC event selection. Generated by tool as +//! \b TILEx_HLC_EVENT_SEL. +//! +//! This function configures the event selection for the High Level Controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configHLCEventSelect(uint32_t base, uint32_t eventSel) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_HLC_EVENT_SEL) = eventSel; + EDIS; +} + +//***************************************************************************** +// +//! Program HLC instruction. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param instructionNum is the index into the HLC instruction memory. For +//! example, a value of 0 corresponds to instruction 0 of event 0, +//! a value of 1 corresponds to instruction 1 of event 0, and so on up +//! to a value of 31 which corresponds to instruction 7 of event 3. +//! \param instruction is the instruction to be programmed. Generated by tool +//! as \b TILEx_HLCINSTR_n where n is the instruction number. +//! +//! This function configures the CLB internal memory corresponding to the +//! specified HLC instruction number with the given instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_programHLCInstruction(uint32_t base, + uint32_t instructionNum, + uint32_t instruction) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(instructionNum < 32U); + + CLB_writeInterface(base, CLB_ADDR_HLC_BASE + instructionNum, instruction); +} + +//***************************************************************************** +// +//! Set HLC registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param r0Init is the value to write to HLC register R0. Generated by tool +//! as \b TILEx_HLC_R0_INIT. +//! \param r1Init is the value to write to HLC register R1. Generated by tool +//! as \b TILEx_HLC_R1_INIT. +//! \param r2Init is the value to write to HLC register R2. Generated by tool +//! as \b TILEx_HLC_R2_INIT. +//! \param r3Init is the value to write to HLC register R3. Generated by tool +//! as \b TILEx_HLC_R3_INIT. +//! +//! This function configures the CLB internal memory corresponding to the HLC +//! registers R0-R3 with the specified values. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setHLCRegisters(uint32_t base, uint32_t r0Init, + uint32_t r1Init, uint32_t r2Init, + uint32_t r3Init) +{ + ASSERT(CLB_isBaseValid(base)); + + CLB_writeInterface(base, CLB_ADDR_HLC_R0, r0Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R1, r1Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R2, r2Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R3, r3Init); +} + +//***************************************************************************** +// +//! Get HLC or counter register values. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param registerID is the internal register from which to read. Can be +//! either an HLC register (\b CLB_REG_HLC_Rn) or a counter value +//! (\b CLB_REG_CTR_Cn). +//! +//! \return Returns the value in the specified HLC register or counter. +// +//***************************************************************************** +static inline uint32_t CLB_getRegister(uint32_t base, CLB_Register registerID) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + (uint32_t)registerID)); +} + +//***************************************************************************** +// +//! Get output status. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the output status of various components within the CLB tile +//! such as a counter match or LUT output. Use the \b CLB_DBG_OUT_* +//! masks from hw_clb.h to decode the bits. +// +//***************************************************************************** +static inline uint32_t CLB_getOutputStatus(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_DBG_OUT)); +} + +//***************************************************************************** +// +//! Configures Counter load and match. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param counterID is the specified counter unit. +//! \param load is the value for counter's load mode. Generated by tool as +//! \b TILEx_COUNTER_n_LOAD_VAL where n is the counter number. +//! \param match1 is the value for counter's match 1. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH1_VAL where n is the counter number. +//! \param match2 is the value for counter's match 2. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH2_VAL where n is the counter number. +//! +//! This function configures the CLB internal memory corresponding to the +//! counter block's load and match values. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, + uint32_t match2); + +//***************************************************************************** +// +//! Clear FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the PUSH/PULL FIFOs as well as its pointers. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_clearFIFOs(uint32_t base); + +//***************************************************************************** +// +//! Configure the FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pullData[] is a pointer to an array of bytes which needs to be +//! written into the FIFO. The 0th FIFO data is in the 0th index. +//! +//! This function writes to the PULL FIFO. This also clears the FIFOs and +//! its pointer using the CLB_clearFIFOs() API prior to writing to +//! the FIFO. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_writeFIFOs(uint32_t base, const uint32_t pullData[]); + +//***************************************************************************** +// +//! Read FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pushData[] is a pointer to an array of bytes which needs to be +//! read from the FIFO. +//! +//! This function reads from the PUSH FIFO. The 0th FIFO data would be in +//! the 0th index. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_readFIFOs(uint32_t base , uint32_t pushData[]); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLB_H diff --git a/gpio_bitfield_cpu2/device/driverlib/cmpss.c b/gpio_bitfield_cpu2/device/driverlib/cmpss.c new file mode 100644 index 0000000..88f9e5f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cmpss.c @@ -0,0 +1,223 @@ +//########################################################################### +// +// FILE: cmpss.c +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cmpss.h" + +//***************************************************************************** +// +// CMPSS_configFilterHigh +// +//***************************************************************************** +void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPHFILCTL) & + ~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the high comparator. + // + HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configFilterLow +// +//***************************************************************************** +void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPLFILCTL) & + ~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the low comparator. + // + HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configLatchOnPWMSYNC +// +//***************************************************************************** +void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // If the highEnable is true, set the bit that will enable PWMSYNC to reset + // the high comparator digital filter latch. If not, clear the bit. + // + EALLOW; + + if(highEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + } + + // + // If the lowEnable is true, set the bit that will enable PWMSYNC to reset + // the low comparator digital filter latch. If not, clear the bit. + // + if(lowEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + } + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configRamp +// +//***************************************************************************** +void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M); + ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U)); + + EALLOW; + + // + // Write the ramp generator source to the register + // + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S); + + // + // Set or clear the bit that determines from where the max ramp value + // should be loaded. + // + if(useRampValShdw) + { + HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL; + } + else + { + HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL; + } + + EDIS; + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal; + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal; + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal; +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/cmpss.h b/gpio_bitfield_cpu2/device/driverlib/cmpss.h new file mode 100644 index 0000000..25625c3 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cmpss.h @@ -0,0 +1,1325 @@ +//########################################################################### +// +// FILE: cmpss.h +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CMPSS_H +#define CMPSS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmpss_api CMPSS +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_cmpss.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CMPSS_HICMP_CTL_M (CMPSS_COMPCTL_COMPHSOURCE | \ + CMPSS_COMPCTL_COMPHINV | \ + CMPSS_COMPCTL_ASYNCHEN) + +#define CMPSS_LOCMP_CTL_M (CMPSS_COMPCTL_COMPLSOURCE | \ + CMPSS_COMPCTL_COMPLINV | \ + CMPSS_COMPCTL_ASYNCLEN) + +#ifndef DOXYGEN_PDF_IGNORE + + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configLowComparator() and +// CMPSS_configHighComparator() as the config parameter. +// +//***************************************************************************** +// +// Comparator negative input source +// +//! Input driven by internal DAC +#define CMPSS_INSRC_DAC 0x0000U +//! Input driven by external pin +#define CMPSS_INSRC_PIN 0x0001U + +// +// Extra options +// +//! Comparator output is inverted +#define CMPSS_INV_INVERTED 0x0002U +//! Asynch comparator output feeds into OR with latched digital filter output +#define CMPSS_OR_ASYNC_OUT_W_FILT 0x0040U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configOutputsLow() and +// CMPSS_configOutputsHigh() as the config parameter. +// +//***************************************************************************** +// +// Signal driving CTRIPOUT +// +//! Asynchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_SYNC_COMP 0x0010U +//! Filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_FILTER 0x0020U +//! Latched filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_LATCH 0x0030U + +// +// Signal driving CTRIP +// +//! Asynchronous comparator output drives CTRIP +#define CMPSS_TRIP_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIP +#define CMPSS_TRIP_SYNC_COMP 0x0004U +//! Filter output drives CTRIP +#define CMPSS_TRIP_FILTER 0x0008U +//! Latched filter output drives CTRIP +#define CMPSS_TRIP_LATCH 0x000CU + +//***************************************************************************** +// +// Values that can be returned by CMPSS_getStatus(). +// +//***************************************************************************** +//! High digital filter output +#define CMPSS_STS_HI_FILTOUT 0x0001U +//! Latched value of high digital filter output +#define CMPSS_STS_HI_LATCHFILTOUT 0x0002U +//! Low digital filter output +#define CMPSS_STS_LO_FILTOUT 0x0100U +//! Latched value of low digital filter output +#define CMPSS_STS_LO_LATCHFILTOUT 0x0200U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configDAC() the config parameter. +// +//***************************************************************************** +// +// When is DAC value loaded from shadow register +// +//! DAC value updated from SYSCLK +#define CMPSS_DACVAL_SYSCLK 0x0000U +//! DAC value updated from PWMSYNC +#define CMPSS_DACVAL_PWMSYNC 0x0080U + +// +// DAC reference voltage +// +//! VDDA is the voltage reference +#define CMPSS_DACREF_VDDA 0x0000U +//! VDAC is the voltage reference +#define CMPSS_DACREF_VDAC 0x0020U + +// +// DAC value source +// +//! DAC value updated from shadow register +#define CMPSS_DACSRC_SHDW 0x0000U +//! DAC value is updated from the ramp register +#define CMPSS_DACSRC_RAMP 0x0001U +#endif + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configRamp() +// as the pwmSyncSrc parameter. +// +//***************************************************************************** +#define CMPSS_PWMSYNC1 1U //!< PWMSYNC1 +#define CMPSS_PWMSYNC2 2U //!< PWMSYNC2 +#define CMPSS_PWMSYNC3 3U //!< PWMSYNC3 +#define CMPSS_PWMSYNC4 4U //!< PWMSYNC4 +#define CMPSS_PWMSYNC5 5U //!< PWMSYNC5 +#define CMPSS_PWMSYNC6 6U //!< PWMSYNC6 +#define CMPSS_PWMSYNC7 7U //!< PWMSYNC7 +#define CMPSS_PWMSYNC8 8U //!< PWMSYNC8 +#define CMPSS_PWMSYNC9 9U //!< PWMSYNC9 +#define CMPSS_PWMSYNC10 10U //!< PWMSYNC10 +#define CMPSS_PWMSYNC11 11U //!< PWMSYNC11 +#define CMPSS_PWMSYNC12 12U //!< PWMSYNC12 + + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks the CMPSS base address. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function determines if a CMPSS base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CMPSS_isBaseValid(uint32_t base) +{ + return( + (base == CMPSS1_BASE) || + (base == CMPSS2_BASE) || + (base == CMPSS3_BASE) || + (base == CMPSS4_BASE) || + (base == CMPSS5_BASE) || + (base == CMPSS6_BASE) || + (base == CMPSS7_BASE) || + (base == CMPSS8_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function enables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) |= CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function disables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Clear the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) &= ~CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the high comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPH or +//! CTRIPOUTH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configHighComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_HICMP_CTL_M) | config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the low comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPL or +//! CTRIPOUTL. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configLowComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_LOCMP_CTL_M) | (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTH: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPH: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsHigh(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTHSEL_M | + CMPSS_COMPCTL_CTRIPHSEL_M)) | + config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTL: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPL: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsLow(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTLSEL_M | + CMPSS_COMPCTL_CTRIPLSEL_M)) | + (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current comparator status. +//! +//! \param base is the base address of the comparator module. +//! +//! This function returns the current status for the comparator, specifically +//! the digital filter output and latched digital filter output. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b CMPSS_STS_HI_FILTOUT - High digital filter output +//! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter +//! output +//! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output +//! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output +// +//***************************************************************************** +static inline uint16_t +CMPSS_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Return contents of the status register. + // + return(HWREGH(base + CMPSS_O_COMPSTS)); +} + +//***************************************************************************** +// +//! Sets the configuration for the internal comparator DACs. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the internal DAC. +//! +//! This function configures the comparator's internal DAC. The \e config +//! parameter is the result of a logical OR operation between the +//! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx. +//! +//! The \b CMPSS_DACVAL_xxx term can take on the following values to specify +//! when the DAC value is loaded from its shadow register: +//! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock. +//! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync. +//! +//! The \b CMPSS_DACREF_xxx term can take on the following values to specify +//! which voltage supply is used as reference for the DACs: +//! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC. +//! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC. +//! +//! The \b CMPSS_DACSRC_xxx term can take on the following values to specify +//! the DAC value source for the high comparator's internal DAC: +//! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register. +//! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register +//! +//! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to +//! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect +//! the high comparator's internal DAC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configDAC(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~(CMPSS_COMPDACCTL_SWLOADSEL | CMPSS_COMPDACCTL_SELREF | + CMPSS_COMPDACCTL_DACSOURCE)) | config; + EDIS; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the high +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueHigh(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACHVALS) = value; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the low +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueLow(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACLVALS) = value; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the high comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterHigh() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the high comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) |= CMPSS_CTRIPHFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the low comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterLow() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the low comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) |= CMPSS_CTRIPLFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the high comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueHigh() writes. +//! +//! \return Returns the value driven by the internal DAC of the high comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACHVALA)); +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the low comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueLow() writes. +//! +//! \return Returns the value driven by the internal DAC of the low comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACLVALA)); +} + +//***************************************************************************** +// +//! Causes a software reset of the high comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the high comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Causes a software reset of the low comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the low comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! \param value the ramp maximum reference value. +//! +//! This function sets the ramp maximum reference value that will be loaded +//! into the ramp generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setMaxRampValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp maximum reference value that will be +//! loaded into the ramp generator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getMaxRampValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the maximum ramp value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPMAXREFA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the ramp decrement value. +//! +//! This function sets the value that is subtracted from the ramp value on +//! every system clock cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDecValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp decrement value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDecValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp decrement value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDECVALA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the 13-bit ramp delay value. +//! +//! This function sets the value that configures the number of system clock +//! cycles to delay the start of the ramp generator decrementer after a PWMSYNC +//! event is received. Delay value can be no greater than 8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDelayValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 8192U); + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp delay value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDelayValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp delay value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDLYA)); +} + +//***************************************************************************** +// +//! Configures sync source for comparator +//! +//! \param base is the base address of the comparator module. +//! \param syncSource is the desired EPWMxSYNCPER source +//! +//! This function configures desired EPWMxSYNCPER source for comparator +//! blocks. Configured EPWMxSYNCPER signal can be used to synchronize loading +//! of DAC input value from shadow to active register. It can also be used to +//! synchronize Ramp generator, if applicable. Refer to device manual to check +//! if Ramp generator is available in the desired CMPSS instance. +//! +//! Valid values for \e syncSource parameter can be 1 to n, where n represents +//! the maximum number of EPWMSYNCPER signals available on the device. For +//! instance, passing 2 into \e syncSource will select EPWM2SYNCPER. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configureSyncSource(uint32_t base, uint16_t syncSource) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp delay value to the shadow register. + // + EALLOW; + HWREGH(base + CMPSS_O_COMPDACCTL) = (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(syncSource - 1U) << + CMPSS_COMPDACCTL_RAMPSOURCE_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the comparator hysteresis settings. +//! +//! \param base is the base address of the comparator module. +//! \param value is the amount of hysteresis on the comparator inputs. +//! +//! This function sets the amount of hysteresis on the comparator inputs. The +//! \e value parameter indicates the amount of hysteresis desired. Passing in 0 +//! results in none, passing in 1 results in typical hysteresis, passing in 2 +//! results in 2x of typical hysteresis, and so on where \e value x of typical +//! hysteresis is the amount configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setHysteresis(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value <= 4U); + + // + // Read the ramp delay value from the register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPHYSCTL) = value; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the high +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configHighComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterHigh() +//! -# Initialize the sample values using CMPSS_initFilterHigh() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsHigh() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the low +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configLowComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterLow() +//! -# Initialize the sample values using CMPSS_initFilterLow() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsLow() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures whether or not the digital filter latches are reset by PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! \param highEnable indicates filter latch settings in the high comparator. +//! \param lowEnable indicates filter latch settings in the low comparator. +//! +//! This function configures whether or not the digital filter latches in both +//! the high and low comparators should be reset by PWMSYNC. If the +//! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset +//! the high comparator's digital filter latch. If it is false, the ability of +//! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter +//! has the same effect on the low comparator's digital filter latch. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable); + +//***************************************************************************** +// +//! Configures the comparator subsystem's ramp generator. +//! +//! \param base is the base address of the comparator module. +//! \param maxRampVal is the ramp maximum reference value. +//! \param decrementVal value is the ramp decrement value. +//! \param delayVal is the ramp delay value. +//! \param pwmSyncSrc is the number of the PWMSYNC source. +//! \param useRampValShdw indicates if the max ramp shadow should be used. +//! +//! This function configures many of the main settings of the comparator +//! subsystem's ramp generator. The \e maxRampVal parameter should be passed +//! the ramp maximum reference value that will be loaded into the ramp +//! generator. The \e decrementVal parameter should be passed the decrement +//! value that will be subtracted from the ramp generator on each system clock +//! cycle. The \e delayVal parameter should be passed the 13-bit number of +//! system clock cycles the ramp generator should delay before beginning to +//! decrement the ramp generator after a PWMSYNC signal is received. +//! +//! These three values may be be set individually using the +//! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and +//! CMPSS_setRampDelayValue() APIs. +//! +//! The number of the PWMSYNC signal to be used to reset the ramp generator +//! should be specified by passing it into the \e pwmSyncSrc parameter. For +//! instance, passing a CMPSS_PWMSYNCx into \e pwmSyncSrc will select PWMSYNCx. +//! +//! To indicate whether the ramp generator should reset with the value from the +//! ramp max reference value shadow register or with the latched ramp max +//! reference value, use the \e useRampValShdw parameter. Passing it \b true +//! will result in the latched value being bypassed. The ramp generator will be +//! loaded right from the shadow register. A value of \b false will load the +//! ramp generator from the latched value. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CMPSS_H diff --git a/gpio_bitfield_cpu2/device/driverlib/cpu.h b/gpio_bitfield_cpu2/device/driverlib/cpu.h new file mode 100644 index 0000000..3e7385b --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cpu.h @@ -0,0 +1,172 @@ +//########################################################################### +// +// FILE: cpu.h +// +// TITLE: Useful C28x CPU defines. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CPU_H +#define CPU_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +// +// External reference to the interrupt flag register (IFR) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IFR; +#endif + +// +// External reference to the interrupt enable register (IER) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IER; +#endif + +// +// Define to enable interrupts +// +#ifndef EINT +#define EINT __asm(" clrc INTM") +#endif + +// +// Define to disable interrupts +// +#ifndef DINT +#define DINT __asm(" setc INTM") +#endif + +// +// Define to enable debug events +// +#ifndef ERTM +#define ERTM __asm(" clrc DBGM") +#endif + +// +// Define to disable debug events +// +#ifndef DRTM +#define DRTM __asm(" setc DBGM") +#endif + +// +// Define to allow writes to protected registers +// +#ifndef EALLOW +#ifndef __TMS320C28XX_CLA__ +#define EALLOW __eallow() +#else +#define EALLOW __meallow() +#endif // __TMS320C28XX_CLA__ +#endif // EALLOW + +// +// Define to disable writes to protected registers +// +#ifndef EDIS +#ifndef __TMS320C28XX_CLA__ +#define EDIS __edis() +#else +#define EDIS __medis() +#endif // __TMS320C28XX_CLA__ +#endif // EDIS + +// +// Define for emulation stop +// +#ifndef ESTOP0 +#define ESTOP0 __asm(" ESTOP0") +#endif + +// +// Define for emulation stop +// +#ifndef ESTOP1 +#define ESTOP1 __asm(" ESTOP1") +#endif + +// +// Define for no operation +// +#ifndef NOP +#define NOP __asm(" NOP") +#endif + +// +// Define for putting processor into a low-power mode +// +#ifndef _DUAL_HEADERS +#ifndef IDLE +#define IDLE __asm(" IDLE") +#endif +#else +#define IDLE_ASM __asm(" IDLE"); +#endif + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// +//***************************************************************************** +extern void __eallow(void); +extern void __edis(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CPU_H diff --git a/gpio_bitfield_cpu2/device/driverlib/cputimer.c b/gpio_bitfield_cpu2/device/driverlib/cputimer.c new file mode 100644 index 0000000..5d12934 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cputimer.c @@ -0,0 +1,61 @@ +//############################################################################# +// +// FILE: cputimer.c +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "cputimer.h" + +//***************************************************************************** +// +// CPUTimer_setEmulationMode +// +//***************************************************************************** +void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode) +{ + ASSERT(CPUTimer_isBaseValid(base)); + // + // Write to FREE_SOFT bits of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) = + (HWREGH(base + CPUTIMER_O_TCR) & + ~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) | + (uint16_t)mode; +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/cputimer.h b/gpio_bitfield_cpu2/device/driverlib/cputimer.h new file mode 100644 index 0000000..71a7501 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/cputimer.h @@ -0,0 +1,509 @@ +//############################################################################# +// +// FILE: cputimer.h +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef CPUTIMER_H +#define CPUTIMER_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup cputimer_api CPUTimer +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_cputimer.h" +#include "debug.h" +#include "sysctl.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +//! Values that can be passed to CPUTimer_setEmulationMode() as the +//! \e mode parameter. +// +//**************************************************************************** +typedef enum +{ + //! Denotes that the timer will stop after the next decrement + CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000, + //! Denotes that the timer will stop when it reaches zero + CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400, + //! Denotes that the timer will run free + CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800 +}CPUTimer_EmulationMode; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e source parameter. +// +//***************************************************************************** +typedef enum +{ + //! System Clock Source + CPUTIMER_CLOCK_SOURCE_SYS = 0x0, + //! Internal Oscillator 1 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1, + //! Internal Oscillator 2 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2, + //! External Clock Source + CPUTIMER_CLOCK_SOURCE_XTAL = 0x3, + //! Auxiliary PLL Clock Source + CPUTIMER_CLOCK_SOURCE_AUX = 0x6 +} CPUTimer_ClockSource; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1 + CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2 + CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4 + CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8 + CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16 +} CPUTimer_Prescaler; + +//***************************************************************************** +// +//! \internal +//! Checks CPU timer base address. +//! +//! \param base specifies the Timer module base address. +//! +//! This function determines if a CPU timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CPUTimer_isBaseValid(uint32_t base) +{ + return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) || + (base == CPUTIMER2_BASE)); +} +#endif + +//***************************************************************************** +// +//! Clears CPU timer overflow flag. +//! +//! \param base is the base address of the timer module. +//! +//! This function clears the CPU timer overflow flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_clearOverflowFlag(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIF bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; +} + +//***************************************************************************** +// +//! Disables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function disables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_disableInterrupt(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TIE bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Enables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function enables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_enableInterrupt(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIE bit of TCR register + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Reloads CPU timer counter. +//! +//! \param base is the base address of the timer module. +//! +//! This function reloads the CPU timer counter with the values contained in +//! the CPU timer period register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_reloadTimerCounter(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TRB bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; +} + +//***************************************************************************** +// +//! Stops CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function stops the CPU timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_stopTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TSS bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function doesn't reset the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_resumeTimer(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function reloads the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_startTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Reload the timer counter + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Sets CPU timer period. +//! +//! \param base is the base address of the timer module. +//! \param periodCount is the CPU timer period count. +//! +//! This function sets the CPU timer period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Load the MSB period Count + // + HWREG(base + CPUTIMER_O_PRD) = periodCount; +} + +//***************************************************************************** +// +//! Returns the current CPU timer counter value. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the current CPU timer counter value. +//! +//! \return Returns the current CPU timer count value. +// +//***************************************************************************** +static inline uint32_t CPUTimer_getTimerCount(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Get the TIMH:TIM registers value + // + return(HWREG(base + CPUTIMER_O_TIM)); +} + +//***************************************************************************** +// +//! Set CPU timer pre-scaler value. +//! +//! \param base is the base address of the timer module. +//! \param prescaler is the CPU timer pre-scaler value. +//! +//! This function sets the pre-scaler value for the CPU timer. For every value +//! of (prescaler + 1), the CPU timer counter decrements by 1. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Writes to TPR.TDDR and TPRH.TDDRH bits + // + HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U; + HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ; +} + +//***************************************************************************** +// +//! Return the CPU timer overflow status. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the CPU timer overflow status. +//! +//! \return Returns true if the CPU timer has overflowed, false if not. +// +//***************************************************************************** +static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Check if TIF bits of register TCR are set + // + return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) == + CPUTIMER_TCR_TIF) ? true : false); +} + +//***************************************************************************** +// +//! Select CPU Timer 2 Clock Source and Prescaler +//! +//! \param base is the base address of the timer module. +//! \param source is the clock source to use for CPU Timer 2 +//! \param prescaler is the value that configures the selected clock source +//! relative to the system clock +//! +//! This function selects the specified clock source and prescaler value +//! for the CPU timer (CPU timer 2 only). +//! +//! The \e source parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock +//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock +//! +//! The \e prescaler parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1 +//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2 +//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4 +//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8 +//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16 +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_selectClockSource(uint32_t base, + CPUTimer_ClockSource source, + CPUTimer_Prescaler prescaler) +{ + ASSERT(base == CPUTIMER2_BASE); + + // + // Set source and prescaler for CPU Timer 2 + // + if(base == CPUTIMER2_BASE) + { + EALLOW; + + // + // Set Clock Source + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | (uint16_t)source; + SYSCTL_REGWRITE_DELAY; + + // + // Set Clock Prescaler + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M) | + ((uint16_t)prescaler < 0.0F); + + // + // Get the sign-extended offset trim value + // + oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^ + (uint16_t)0x80) - (uint16_t)0x80; + + // + // Calculate new offset trim value if DAC is operating at a reference + // voltage other than 2.5v. + // + newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) * + (int16_t)oldOffsetTrim); + + // + // Check if the new offset trim value is valid + // + ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128)); + + // + // Set the new offset trim value + // + EALLOW; + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | + (int16_t)newOffsetTrim; + + EDIS; + +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/dac.h b/gpio_bitfield_cpu2/device/driverlib/dac.h new file mode 100644 index 0000000..fcd866a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/dac.h @@ -0,0 +1,604 @@ +//########################################################################### +// +// FILE: dac.h +// +// TITLE: C28x DAC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DAC_H +#define DAC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dac_api DAC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dac.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +// +// A 8-bit register mask +// +#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask + +// +// Lock Key +// +#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are defines for the reg parameter of the +// DAC_lockRegister() and DAC_isRegisterLocked() functions. +// +//***************************************************************************** +#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register +#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register +#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! Values that can be passed to DAC_setReferenceVoltage() as the \e source +//! parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_REF_VDAC = 0, //!< VDAC reference voltage + DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage +}DAC_ReferenceVoltage; + +//***************************************************************************** +// +//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK + DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL +}DAC_LoadMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks DAC base address. +//! +//! \param base specifies the DAC module base address. +//! +//! This function determines if an DAC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DAC_isBaseValid(uint32_t base) +{ + return( + (base == DACA_BASE) || + (base == DACB_BASE) || + (base == DACC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Get the DAC Revision value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC revision value. +//! +//! \return Returns the DAC revision value. +// +//***************************************************************************** +static inline uint16_t +DAC_getRevision(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the revision value. + // + return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M); +} + +//***************************************************************************** +// +//! Sets the DAC Reference Voltage +//! +//! \param base is the DAC module base address +//! \param source is the selected reference voltage +//! +//! This function sets the DAC reference voltage. +//! +//! The \e source parameter can have the following value: +//! - \b DAC_REF_VDAC - The VDAC reference voltage +//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the reference voltage + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_DACREFSEL) | (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC Load Mode +//! +//! \param base is the DAC module base address +//! \param mode is the selected load mode +//! +//! This function sets the DAC load mode. +//! +//! The \e mode parameter can have one of two values: +//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK +//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setLoadMode(uint32_t base, DAC_LoadMode mode) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the load mode + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_LOADMODE) | (uint16_t)mode; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC PWMSYNC Signal +//! +//! \param base is the DAC module base address +//! \param signal is the selected PWM signal +//! +//! This function sets the DAC PWMSYNC signal. +//! +//! The \e signal parameter must be set to a number that represents the PWM +//! signal that will be set. For instance, passing 2 into \e signal will +//! select PWM sync signal 2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setPWMSyncSignal(uint32_t base, uint16_t pwmSignal) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((pwmSignal > 0U) && (pwmSignal < 17U)); + + // + // Set the PWM sync signal + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_SYNCSEL_M) | + ((uint16_t)(pwmSignal - 1U) << + DAC_CTL_SYNCSEL_S); + + EDIS; +} + +//***************************************************************************** +// +//! Get the DAC Active Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC active output value. +//! +//! \return Returns the DAC active output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getActiveValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the active value + // + return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M); +} + +//***************************************************************************** +// +//! Set the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! \param value is the 12-bit code to be loaded into the active value register +//! +//! This function sets the DAC shadow output value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setShadowValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT(value <= DAC_VALS_DACVALS_M); + + // + // Set the shadow value + // + HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) & + ~DAC_VALS_DACVALS_M) | + (uint16_t)(value & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Get the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC shadow output value. +//! +//! \return Returns the DAC shadow output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getShadowValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the shadow value + // + return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Enable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function enables the DAC output. +//! +//! \note A delay is required after enabling the DAC. Further details +//! regarding the exact delay time length can be found in the device datasheet. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_enableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Enable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function disables the DAC output. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_disableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Disable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Set DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param offset is the specified value for the offset trim +//! +//! This function sets the DAC offset trim. The \e offset value should be a +//! signed number in the range of -128 to 127. +//! +//! \note The offset should not be modified unless specifically indicated by +//! TI Errata or other documentation. Modifying the offset value could cause +//! this module to operate outside of the datasheet specifications. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setOffsetTrim(uint32_t base, int16_t offset) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((offset > -129) && (offset < 128)); + + // + // Set the offset trim value + // + EALLOW; + + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset; + + EDIS; +} + +//***************************************************************************** +// +//! Get DAC Offset Trim +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC offset trim value. +//! +//! \return None. +// +//***************************************************************************** +static inline int16_t +DAC_getOffsetTrim(uint32_t base) +{ + uint16_t value; + + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the sign-extended offset trim value + // + value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) - + (uint16_t)0x80; + + return((int16_t)value); +} + +//***************************************************************************** +// +//! Lock write-access to DAC Register +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC registers +//! +//! This function locks the write-access to the specified DAC register. Only a +//! system reset can unlock the register once locked. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_lockRegister(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Lock the specified registers + // + EALLOW; + + HWREGH(base + DAC_O_LOCK) |= (DAC_LOCK_KEY | reg); + + EDIS; +} + +//***************************************************************************** +// +//! Check if DAC Register is locked +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC register locks to check +//! +//! This function checks if write-access has been locked on the specified DAC +//! register. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return Returns \b true if any of the registers specified are locked, and +//! \b false if all specified registers aren't locked. +// +//***************************************************************************** +static inline bool +DAC_isRegisterLocked(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Return the lock status on the specified registers + // + return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U)); +} + +//***************************************************************************** +// +//! Tune DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param referenceVoltage is the reference voltage the DAC +//! module is operating at. +//! +//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage +//! value should be a floating point number in the range specified in the +//! device data manual. +//! +//! \note Use this function to adjust the DAC offset trim if operating +//! at a reference voltage other than 2.5v. Since this function modifies +//! the DAC offset trim register, it should only be called once after +//! Device_cal. If it is called multiple times after Device_cal, the offset +//! value scaled would be the wrong value. +//! +//! \return None. +// +//***************************************************************************** +extern void +DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DAC_H diff --git a/gpio_bitfield_cpu2/device/driverlib/dcsm.c b/gpio_bitfield_cpu2/device/driverlib/dcsm.c new file mode 100644 index 0000000..808027a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/dcsm.c @@ -0,0 +1,377 @@ +//############################################################################# +// +// FILE: dcsm.c +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "dcsm.h" + +//***************************************************************************** +// +// DCSM_unlockZone1CSM +// +//***************************************************************************** +void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3; + } +} + +//***************************************************************************** +// +// DCSM_unlockZone2CSM +// +//***************************************************************************** +void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3; + } +} +//***************************************************************************** +// +// DCSM_getZone1FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t) + ((regValue >> (uint16_t)sector) & + 0x01U)); + } + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone1RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >> + (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_getZone2FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >> + (uint16_t)sector) & 0x01U)); + } + + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone2RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z2_BASE + + DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_claimZoneSemaphore +// +//***************************************************************************** +bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) | + (uint16_t)zone; + EDIS; + + // + // If the calling function was unable to claim the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ? + true : false); +} + +//***************************************************************************** +// +// DCSM_releaseZoneSemaphore +// +//***************************************************************************** +bool +DCSM_releaseZoneSemaphore(void) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S); + EDIS; + + // + // If the calling function was unable to release the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false); +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/dcsm.h b/gpio_bitfield_cpu2/device/driverlib/dcsm.h new file mode 100644 index 0000000..d181fa7 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/dcsm.h @@ -0,0 +1,669 @@ +//############################################################################# +// +// FILE: dcsm.h +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef DCSM_H +#define DCSM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dcsm_api DCSM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dcsm.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the unlockZone1CSM() and unlockZone2CSM(). +// These are not parameters for any function. +// These are not intended for application code. +// +//***************************************************************************** + +#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset +#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset +#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset +#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset +#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset +#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset +#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset +#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset + +//***************************************************************************** +// +// Register key defines. +// +//***************************************************************************** +#define FLSEM_KEY 0xA5U //!< Zone semaphore key + +//***************************************************************************** +// +//! Data structures to hold password keys. +// +//***************************************************************************** +typedef struct +{ + uint32_t csmKey0; + uint32_t csmKey1; + uint32_t csmKey2; + uint32_t csmKey3; +} DCSM_CSMPasswordKey; + +//***************************************************************************** +// +//! Values to distinguish the status of RAM or FLASH sectors. These values +//! describe which zone the memory location belongs too. +//! These values can be returned from DCSM_getRAMZone(), +//! DCSM_getFlashSectorZone(). +// +//***************************************************************************** +typedef enum +{ + DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible + DCSM_MEMORY_ZONE1, //!< Zone 1 + DCSM_MEMORY_ZONE2, //!< Zone 2 + DCSM_MEMORY_FULL_ACCESS //!< Full access +} DCSM_MemoryStatus; + +//***************************************************************************** +// +//! Values to pass to DCSM_claimZoneSemaphore(). These values are used +//! to describe the zone that can write to Flash Wrapper registers. +// +//***************************************************************************** +typedef enum +{ + DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1 + DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2 +} DCSM_SemaphoreZone; + +//***************************************************************************** +// +//! Values to distinguish the security status of the zones. +//! These values can be returned from DCSM_getZone1CSMSecurityStatus(), +//! DCSM_getZone2CSMSecurityStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_STATUS_SECURE, //!< Secure + DCSM_STATUS_UNSECURE, //!< Unsecure + DCSM_STATUS_LOCKED, //!< Locked +} DCSM_SecurityStatus; + +//***************************************************************************** +// +// Values to distinguish the status of the Control Registers. These values +// describe can be used with the return values of +// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus(). +// +//***************************************************************************** +#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros +#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones +#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure +#define DCSM_ARMED 0x40U //!< CSM is armed + +//***************************************************************************** +// +//! Values to decribe the EXEONLY Status. +//! These values are returned from to DCSM_getZone1RAMEXEStatus(), +//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(), +//! DCSM_getZone2FlashEXEStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_PROTECTED, //!< Protected + DCSM_UNPROTECTED, //!< Unprotected + DCSM_INCORRECT_ZONE //!< Incorrect Zone +}DCSM_EXEOnlyStatus; + +//***************************************************************************** +// +//! Values to distinguish RAM Module. +//! These values can be passed to DCSM_getZone1RAMEXEStatus() +//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone(). +// +//***************************************************************************** +typedef enum +{ + // + //C28x RAMs + // + DCSM_RAMLS0, //!< RAMLS0 + DCSM_RAMLS1, //!< RAMLS1 + DCSM_RAMLS2, //!< RAMLS2 + DCSM_RAMLS3, //!< RAMLS3 + DCSM_RAMLS4, //!< RAMLS4 + DCSM_RAMLS5, //!< RAMLS5 + DCSM_RAMD0, //!< RAMD0 + DCSM_RAMD1, //!< RAMD1 + DCSM_CLA = 14U //!> + shift) & 0x03U); + return((DCSM_MemoryStatus)ramStatus); +} + +//***************************************************************************** +// +//! Returns the security zone a flash sector belongs to +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function returns the security zone a flash sector belongs to. +//! +//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible , +//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if +//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section +//! doesn't belong to any zone (or if the section is unsecure).. +// +//***************************************************************************** +static inline DCSM_MemoryStatus +DCSM_getFlashSectorZone(DCSM_Sector sector) +{ + uint32_t sectStat; + uint16_t shift; + + // + // Get the Sector status register for the specific bank + // + sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT); + shift = (uint16_t)sector * 2U; + + // + //Read the SECTSTAT register for the specific Flash Sector. + // + return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U))); +} + +//***************************************************************************** +// +//! Read Zone 1 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 1 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone1LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Read Zone 2 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 2 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone2LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Unlocks Zone 1 CSM. +//! +//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the +//! CSM password for zone 1. +//! +//! This function unlocks the CSM password. It first reads the +//! four password locations in the User OTP. If any of the password values is +//! different from 0xFFFFFFFF, it unlocks the device by writing the provided +//! passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey); + +//***************************************************************************** +// +//! Unlocks Zone 2 CSM. +//! +//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM +//! password for zone 2. +//! +//! This function unlocks the CSM password. It first reads +//! the four password locations in the User OTP. If any of the password values +//! is different from 0xFFFFFFFF, it unlocks the device by writing the +//! provided passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey); +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Claims the zone semaphore which allows access to the Flash Wrapper register +//! for that zone. +//! +//! \param zone is the zone which is trying to claim the semaphore which allows +//! access to the Flash Wrapper registers. +//! +//! \return Returns true for a successful semaphore capture, false if it was +//! unable to capture the semaphore. +// +//***************************************************************************** +extern bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone); + +//***************************************************************************** +// +//! Releases the zone semaphore. +//! +//! \return Returns true if it was successful in releasing the zone semaphore +//! and false if it was unsuccessful in releasing the zone semaphore. +//! +//! \note If the calling function is not in the right zone to be able +//! to access this register, it will return a false. +// +//***************************************************************************** +extern bool +DCSM_releaseZoneSemaphore(void); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DCSM_H diff --git a/gpio_bitfield_cpu2/device/driverlib/debug.h b/gpio_bitfield_cpu2/device/driverlib/debug.h new file mode 100644 index 0000000..5a2f93a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/debug.h @@ -0,0 +1,91 @@ +//########################################################################### +// +// FILE: debug.h +// +// TITLE: Assert definition macro for debug. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DEBUG_H +#define DEBUG_H + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. It is the +// application's responsibility to define the __error__ function. +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#ifdef __TMS320C28XX__ +// +// When called from C28x application +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } \ + while((_Bool)0) +#else +// +// When called from CLA application. Update as needed. +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __mdebugstop(); \ + } \ + } \ + while((_Bool)0) +#endif +#else +#define ASSERT(expr) +#endif + +#endif // DEBUG_H diff --git a/gpio_bitfield_cpu2/device/driverlib/dma.c b/gpio_bitfield_cpu2/device/driverlib/dma.c new file mode 100644 index 0000000..ea591b1 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/dma.c @@ -0,0 +1,370 @@ +//########################################################################### +// +// FILE: dma.c +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "dma.h" + +//***************************************************************************** +// +// DMA_configAddresses +// +//***************************************************************************** +void DMA_configAddresses(uint32_t base, const void *destAddr, + const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configBurst +// +//***************************************************************************** +void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((size >= 1U) && (size <= 32U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up BURST registers. + // + HWREGH(base + DMA_O_BURST_SIZE) = size - 1U; + HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep; + HWREGH(base + DMA_O_DST_BURST_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configTransfer +// +//***************************************************************************** +void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(transferSize <= 0x10000U); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up TRANSFER registers. + // + HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U); + HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep; + HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configWrap +// +//***************************************************************************** +void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up WRAP registers. + // + HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U); + HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep; + + HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U); + HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configMode +// +//***************************************************************************** +void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up trigger selection in the CMA/CLA trigger source selection + // registers. These are considered part of system control. + // + switch(base) + { + case DMA_CH1_BASE: + // + // Channel 1 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH1_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U; + break; + + case DMA_CH2_BASE: + // + // Channel 2 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH2_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U; + break; + + case DMA_CH3_BASE: + // + // Channel 3 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH3_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U; + break; + + case DMA_CH4_BASE: + // + // Channel 4 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH4_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U; + break; + + case DMA_CH5_BASE: + // + // Channel 5 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH5_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U; + break; + + case DMA_CH6_BASE: + // + // Channel 6 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH6_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U; + break; + + default: + // + // Invalid base. + // + break; + } + + // + // Write the configuration to the mode register. + // + HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS | + DMA_MODE_ONESHOT); + HWREGH(base + DMA_O_MODE) |= config; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configChannel +// +//***************************************************************************** +void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(((transfParams->configSize == DMA_CFG_SIZE_16BIT) || + (transfParams->configSize == DMA_CFG_SIZE_32BIT)) && + ((transfParams->transferMode == DMA_CFG_ONESHOT_DISABLE) || + (transfParams->transferMode == DMA_CFG_ONESHOT_ENABLE)) && + ((transfParams->reinitMode == DMA_CFG_CONTINUOUS_DISABLE) || + (transfParams->reinitMode == DMA_CFG_CONTINUOUS_ENABLE))); + + // + // Configure DMA Channel + // + DMA_configAddresses(base, (const void *)transfParams->destAddr, + (const void *)transfParams->srcAddr); + + // + // Configure the size of each burst and the address step size + // + DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep, + transfParams->destBurstStep); + + // + // Configure the transfer size and the address step that is + // made after each burst. + // + DMA_configTransfer(base, transfParams->transferSize, + transfParams->srcTransferStep, + transfParams->destTransferStep); + + // + // Configure the DMA channel's wrap settings + // + DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep, + transfParams->destWrapSize, transfParams->destWrapStep); + + // + // Configure the DMA channel's trigger and mode + // + DMA_configMode(base, transfParams->transferTrigger, + transfParams->transferMode | transfParams->reinitMode | + transfParams->configSize); + + // + // Enable the selected peripheral trigger to start a DMA transfer + // + DMA_enableTrigger(base); + + if(transfParams->enableInterrupt) + { + // + // Set the channel interrupt mode + // + DMA_setInterruptMode(base, transfParams->interruptMode); + + // + // Enable the indicated DMA channel interrupt source + // + DMA_enableInterrupt(base); + } + else + { + // + // Disable the indicated DMA channel interrupt source + // + DMA_disableInterrupt(base); + } +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/dma.h b/gpio_bitfield_cpu2/device/driverlib/dma.h new file mode 100644 index 0000000..ae57689 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/dma.h @@ -0,0 +1,1171 @@ +//########################################################################### +// +// FILE: dma.h +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DMA_H +#define DMA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dma_api DMA +//! \brief This module is used for DMA configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dma.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to DMA_configMode() as the config parameter. +// +//***************************************************************************** +//! Only one burst transfer performed per trigger. +#define DMA_CFG_ONESHOT_DISABLE 0U +//! Burst transfers occur without additional event triggers after the first. +#define DMA_CFG_ONESHOT_ENABLE DMA_MODE_ONESHOT + +//! DMA channel will be disabled at the end of a transfer. +#define DMA_CFG_CONTINUOUS_DISABLE 0U +//! DMA reinitializes when the transfer count is zero and waits for a trigger. +#define DMA_CFG_CONTINUOUS_ENABLE DMA_MODE_CONTINUOUS + +//! DMA transfers 16 bits at a time. +#define DMA_CFG_SIZE_16BIT 0U +//! DMA transfers 32 bits at a time. +#define DMA_CFG_SIZE_32BIT DMA_MODE_DATASIZE + +//***************************************************************************** +// +//! Values that can be passed to DMA_configMode() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + DMA_TRIGGER_SOFTWARE = 0, + + DMA_TRIGGER_ADCA1 = 1, + DMA_TRIGGER_ADCA2 = 2, + DMA_TRIGGER_ADCA3 = 3, + DMA_TRIGGER_ADCA4 = 4, + DMA_TRIGGER_ADCAEVT = 5, + DMA_TRIGGER_ADCB1 = 6, + DMA_TRIGGER_ADCB2 = 7, + DMA_TRIGGER_ADCB3 = 8, + DMA_TRIGGER_ADCB4 = 9, + DMA_TRIGGER_ADCBEVT = 10, + DMA_TRIGGER_ADCC1 = 11, + DMA_TRIGGER_ADCC2 = 12, + DMA_TRIGGER_ADCC3 = 13, + DMA_TRIGGER_ADCC4 = 14, + DMA_TRIGGER_ADCCEVT = 15, + DMA_TRIGGER_ADCD1 = 16, + DMA_TRIGGER_ADCD2 = 17, + DMA_TRIGGER_ADCD3 = 18, + DMA_TRIGGER_ADCD4 = 19, + DMA_TRIGGER_ADCDEVT = 20, + + DMA_TRIGGER_XINT1 = 29, + DMA_TRIGGER_XINT2 = 30, + DMA_TRIGGER_XINT3 = 31, + DMA_TRIGGER_XINT4 = 32, + DMA_TRIGGER_XINT5 = 33, + + DMA_TRIGGER_EPWM1SOCA = 36, + DMA_TRIGGER_EPWM1SOCB = 37, + DMA_TRIGGER_EPWM2SOCA = 38, + DMA_TRIGGER_EPWM2SOCB = 39, + DMA_TRIGGER_EPWM3SOCA = 40, + DMA_TRIGGER_EPWM3SOCB = 41, + DMA_TRIGGER_EPWM4SOCA = 42, + DMA_TRIGGER_EPWM4SOCB = 43, + DMA_TRIGGER_EPWM5SOCA = 44, + DMA_TRIGGER_EPWM5SOCB = 45, + DMA_TRIGGER_EPWM6SOCA = 46, + DMA_TRIGGER_EPWM6SOCB = 47, + DMA_TRIGGER_EPWM7SOCA = 48, + DMA_TRIGGER_EPWM7SOCB = 49, + DMA_TRIGGER_EPWM8SOCA = 50, + DMA_TRIGGER_EPWM8SOCB = 51, + DMA_TRIGGER_EPWM9SOCA = 52, + DMA_TRIGGER_EPWM9SOCB = 53, + DMA_TRIGGER_EPWM10SOCA = 54, + DMA_TRIGGER_EPWM10SOCB = 55, + DMA_TRIGGER_EPWM11SOCA = 56, + DMA_TRIGGER_EPWM11SOCB = 57, + DMA_TRIGGER_EPWM12SOCA = 58, + DMA_TRIGGER_EPWM12SOCB = 59, + + DMA_TRIGGER_TINT0 = 68, + DMA_TRIGGER_TINT1 = 69, + DMA_TRIGGER_TINT2 = 70, + + DMA_TRIGGER_MCBSPAMXEVT = 71, + DMA_TRIGGER_MCBSPAMREVT = 72, + DMA_TRIGGER_MCBSPBMXEVT = 73, + DMA_TRIGGER_MCBSPBMREVT = 74, + + + DMA_TRIGGER_SDFM1FLT1 = 95, + DMA_TRIGGER_SDFM1FLT2 = 96, + DMA_TRIGGER_SDFM1FLT3 = 97, + DMA_TRIGGER_SDFM1FLT4 = 98, + + DMA_TRIGGER_SDFM2FLT1 = 99, + DMA_TRIGGER_SDFM2FLT2 = 100, + DMA_TRIGGER_SDFM2FLT3 = 101, + DMA_TRIGGER_SDFM2FLT4 = 102, + + + DMA_TRIGGER_SPIATX = 109, + DMA_TRIGGER_SPIARX = 110, + DMA_TRIGGER_SPIBTX = 111, + DMA_TRIGGER_SPIBRX = 112, + DMA_TRIGGER_SPICTX = 113, + DMA_TRIGGER_SPICRX = 114, + + DMA_TRIGGER_CLB1INT = 127, + DMA_TRIGGER_CLB2INT = 128, + DMA_TRIGGER_CLB3INT = 129, + DMA_TRIGGER_CLB4INT = 130, + +} DMA_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setInterruptMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! DMA interrupt is generated at the beginning of a transfer + DMA_INT_AT_BEGINNING, + //! DMA interrupt is generated at the end of a transfer + DMA_INT_AT_END +} DMA_InterruptMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after current read-write access is completed + DMA_EMULATION_STOP, + //! Continue DMA operation regardless of emulation suspend + DMA_EMULATION_FREE_RUN +} DMA_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_configChannel() as the +//! configure parameter. +// +//***************************************************************************** +typedef struct +{ + DMA_Trigger transferTrigger; //DMA transfer triggers + DMA_InterruptMode interruptMode; //Channel interrupt mode + //! enableInterrupt can have a value 1(Enable) or 0(Disable) + bool enableInterrupt; //Enable/Disable interrupt mode + //! configSize can have a value DMA_CFG_SIZE_16BIT/32BIT + uint32_t configSize; //Data bus width (16 or 32 bits) + //! transferMode can have a value DMA_CFG_ONESHOT_DISABLE/ENABLE + uint32_t transferMode; //Burst transfer mode + //! reinitMode can have a value DMA_CFG_CONTINUOUS_DISABLE/ENABLE + uint32_t reinitMode; //DMA reinitialization mode + //! burstSize value range from 1 word to 32 sixteen-bit words. + uint32_t burstSize; //Number of words transferred per burst + //! transferSize value range from 1 to 65536 + uint32_t transferSize; //Number of bursts per transfer + //! Number of bursts to be transferred before a wrap of the source address + //! occurs. srcWrapSize value range from 1 to 65536 + uint32_t srcWrapSize; + //! Number of bursts to be transferred before a wrap of the destination + //! address occurs. destWrapSize value range from 1 to 65536 + uint32_t destWrapSize; + uint32_t destAddr; //destination address + uint32_t srcAddr; //source address + //! Amount to inc or dec the source address after each word of a burst. + //! srcBurstStep can have only signed values from -4096 to 4095 + int16_t srcBurstStep; + //! Amount to inc or dec the destination address after each word of a burst. + //! destBurstStep can have only signed values from -4096 to 4095 + int16_t destBurstStep; + //! Amount to inc or dec the source address after each burst of a transfer. + //! srcTransferStep can have only signed values from -4096 to 4095 + int16_t srcTransferStep; + //! Amount to inc or dec the destination address after each burst of a + //! transfer. destTransferStep can have only signed values from -4096 to 4095 + int16_t destTransferStep; + //! Amount to inc or dec the source address when the wrap occurs. + //! srcWrapStep can have only signed values from -4096 to 4095 + int16_t srcWrapStep; + //! Amount to inc or dec the destination address when the wrap occurs. + //! destWrapStep can have only signed values from -4096 to 4095 + int16_t destWrapStep; + +} DMA_ConfigParams; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an DMA channel base address. +//! +//! \param base specifies the DMA channel base address. +//! +//! This function determines if a DMA channel base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DMA_isBaseValid(uint32_t base) +{ + return((base == DMA_CH1_BASE) || (base == DMA_CH2_BASE) || + (base == DMA_CH3_BASE) || (base == DMA_CH4_BASE) || + (base == DMA_CH5_BASE) || (base == DMA_CH6_BASE)); +} +#endif + +//***************************************************************************** +// +//! Initializes the DMA controller to a known state. +//! +//! This function configures does a hard reset of the DMA controller in order +//! to put it into a known state. The function also sets the DMA to run free +//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_initController(void) +{ + EALLOW; + + // + // Set the hard reset bit. One NOP is required after HARDRESET. + // + HWREGH(DMA_BASE + DMA_O_CTRL) |= DMA_CTRL_HARDRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Channel Soft Reset +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function does a soft reset to place the channel into its default state +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_triggerSoftReset(uint32_t base) +{ + EALLOW; + + // + // Set the soft reset bit. One NOP is required after SOFTRESET. + // + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_SOFTRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Sets DMA emulation mode. +//! +//! \param mode is the emulation mode to be selected. +//! +//! This function sets the behavior of the DMA operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is +//! completed. +//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setEmulationMode(DMA_EmulationMode mode) +{ + EALLOW; + + // + // Set emulation mode + // + if(mode == DMA_EMULATION_STOP) + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) &= ~DMA_DEBUGCTRL_FREE; + } + else + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) |= DMA_DEBUGCTRL_FREE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables peripherals to trigger a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the selected peripheral trigger to start a DMA +//! transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables peripherals from triggering a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the selected peripheral trigger from starting a DMA +//! transfer on the specified channel. This also disables the use of the +//! software force using the DMA_forceTrigger() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Clear the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Force a peripheral trigger to a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function sets the peripheral trigger flag and if triggering a DMA +//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be +//! forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_forceTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger force bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTFRC; + EDIS; +} + +//***************************************************************************** +// +//! Clears a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears the peripheral trigger flag. Normally, you would use +//! this function when initializing the DMA for the first time. The flag is +//! cleared automatically when the DMA starts the first burst of a transfer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearTriggerFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write a one to the clear bit to clear the peripheral trigger flag. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Transfer Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Transfer Status Flag is set, which +//! means a DMA transfer has begun. +//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTransferStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Transfer Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_TRANSFERSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Burst Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Burst Status Flag is set, which +//! means a DMA burst has begun. +//! This flag is cleared when BURST_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Burst Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getBurstStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Burst Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_BURSTSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Run Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Run Status Flag is set, which +//! means the DMA channel is enabled. +//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and +//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit +//! is set. +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getRunStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Run Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_RUNSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Overflow Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Overflow Flag is set, which +//! means peripheral event trigger was received while Peripheral Event Trigger +//! Flag was already set. +//! This flag can be cleared by writing to ERRCLR bit, using the function +//! DMA_clearErrorFlag(). +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getOverflowFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Overflow Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_OVRFLG) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if a peripheral trigger event has occurred +//! The flag is automatically cleared when the first burst transfer begins, but +//! if needed, it can be cleared using DMA_clearTriggerFlag(). +//! +//! \return Returns \b true if a peripheral trigger event has occurred and its +//! flag is set. Returns \b false otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTriggerFlagStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the peripheral trigger flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_PERINTFLG) != 0U); +} + +//***************************************************************************** +// +//! Starts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function starts the DMA running, typically after you have configured +//! it. It will wait for the first trigger event to start operation. To halt +//! the channel use DMA_stopChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_startChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the run bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_RUN; + EDIS; +} + +//***************************************************************************** +// +//! Halts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function halts the DMA at its current state and any current read-write +//! access is completed. To start the channel again use DMA_startChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_stopChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the halt bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_HALT; + EDIS; +} + +//***************************************************************************** +// +//! Enables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Enables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. An overrun is when a peripheral +//! event trigger is received by the DMA before a previous trigger on that +//! channel had been serviced and its flag had been cleared. +//! +//! Note that this is the same interrupt signal as the interrupt that gets +//! generated at the beginning/end of a transfer. That interrupt must first be +//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to +//! be generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Clears the DMA channel error flags. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears both the DMA channel's sync error flag and its +//! overrun error flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearErrorFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write to the error clear bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_ERRCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the interrupt generation mode of a DMA channel interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param mode is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e mode parameter +//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the +//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be +//! generated at the beginning of a new transfer. Generating at the beginning +//! of a new transfer is the default behavior. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Write the selected interrupt generation mode to the register. + // + if(mode == DMA_INT_AT_END) + { + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTMODE; + } + else + { + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTMODE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DMA channel priority mode. +//! +//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e ch1IsHighPri +//! parameter is \b false, the DMA channels are serviced in round-robin mode. +//! This is the default behavior. +//! +//! If \b true, channel 1 will be given higher priority than the other +//! channels. This means that if a channel 1 trigger occurs, the current word +//! transfer on any other channel is completed and channel 1 is serviced for +//! the complete burst count. The lower-priority channel's interrupted transfer +//! will then resume. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setPriorityMode(bool ch1IsHighPri) +{ + EALLOW; + + // + // Write the selected priority mode to the register. + // + if(ch1IsHighPri) + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) |= + DMA_PRIORITYCTRL1_CH1PRIORITY; + } + else + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) &= + ~DMA_PRIORITYCTRL1_CH1PRIORITY; + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the source address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *srcAddr is a source address. +//! +//! This function configures the source address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configSourceAddress(uint32_t base, const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the destination address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! +//! This function configures the destinaton address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configDestAddress(uint32_t base, const void *destAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Setup DMA to transfer data on the specified channel. +//! +//! \param base is Base address of the DMA channel control register +//! \param *transfParams configuration parameter +//! Refer struct #DMA_ConfigParams +//! +//! This function configures the DMA transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams); + +//***************************************************************************** +// +//! Configures the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! \param *srcAddr is a source address. +//! +//! This function configures the source and destination addresses of a DMA +//! channel. The parameters are pointers to the data to be transferred. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr); + +//***************************************************************************** +// +//! Configures the DMA channel's burst settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param size is the number of words transferred per burst. +//! \param srcStep is the amount to increment or decrement the source address +//! after each word of a burst. +//! \param destStep is the amount to increment or decrement the destination +//! address after each word of a burst. +//! +//! This function configures the size of each burst and the address step size. +//! +//! The \e size parameter is the number of words that will be transferred +//! during a single burst. Possible amounts range from 1 word to 32 words. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred word of a burst. Only signed values from -4096 to 4095 are +//! valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's transfer settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param transferSize is the number of bursts per transfer. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the transfer size and the address step that is +//! made after each burst. +//! +//! The \e transferSize parameter is the number of bursts per transfer. If DMA +//! channel interrupts are enabled, they will occur after this number of bursts +//! have completed. The maximum number of bursts is 65536. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred burst of a transfer. Only signed values from -4096 to 4095 are +//! valid. If a wrap occurs, these step values will be ignored. Wrapping is +//! configured with DMA_configWrap(). +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's wrap settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param srcWrapSize is the number of bursts to be transferred before a wrap +//! of the source address occurs. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destWrapSize is the number of bursts to be transferred before a wrap +//! of the destination address occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the DMA channel's wrap settings. +//! +//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts +//! that are to be transferred before their respective addresses are wrapped. +//! The maximum wrap size is 65536 bursts. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses when the wrap +//! occurs. Only signed values from -4096 to 4095 are valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel trigger and mode. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param trigger is the interrupt source that triggers a DMA transfer. +//! \param config is a bit field of several configuration selections. +//! +//! This function configures the DMA channel's trigger and mode. +//! +//! The \e trigger parameter is the interrupt source that will trigger the +//! start of a DMA transfer. +//! +//! The \e config parameter is the logical OR of the following values: +//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled, +//! the subsequent burst transfers occur without additional event triggers +//! after the first event trigger. If disabled, only one burst transfer is +//! performed per event trigger. +//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled +//! the DMA reinitializes when the transfer count is zero and waits for the +//! next interrupt event trigger. If disabled, the DMA stops and clears the +//! run status bit. +//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects +//! whether the databus width is 16 or 32 bits. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DMA_H diff --git a/gpio_bitfield_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h b/gpio_bitfield_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h new file mode 100644 index 0000000..00e9ac6 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/driver_inclusive_terminology_mapping.h @@ -0,0 +1,109 @@ +#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ +#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ + + +//***************************************************************************** +// CLB +//***************************************************************************** +#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL +#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL +#define SPI_MODE_MASTER SPI_MODE_CONTROLLER +#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD +#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD + +#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW +#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH + +#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity + + +//***************************************************************************** +// Interrupt +//***************************************************************************** +#define Interrupt_enableMaster Interrupt_enableGlobal +#define Interrupt_disableMaster Interrupt_disableGlobal + + +//***************************************************************************** +// SysCtrl +//***************************************************************************** +#define SysCtl_AccessMaster SysCtl_AccessController +#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA +#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA +#define SysCtl_selectSecMaster SysCtl_selectSecController + + +//***************************************************************************** +// GPIO +//***************************************************************************** +#define GPIO_setMasterCore GPIO_setControllerCore + + + +//***************************************************************************** +// Memcfg +//***************************************************************************** +#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel +#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY +#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1 +#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel + +#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel +#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1 +#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2 +#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel + +//***************************************************************************** +// EMIF +//***************************************************************************** +#define EMIF_MasterSelect EMIF_ControllerSelect +#define EMIF_selectMaster EMIF_selectController +#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG +#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G +#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G +#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2 + + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE +#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE +#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE +#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE +#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET +#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET +#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR +#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET + +#define I2C_initMaster I2C_initController +#define I2C_setSlaveAddress I2C_setTargetAddress +#define I2C_setOwnSlaveAddress I2C_setOwnAddress + + +//***************************************************************************** +// SDFM +//***************************************************************************** +#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt +#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt +#define SDFM_enableMasterFilter SDFM_enableMainFilter +#define SDFM_disableMasterFilter SDFM_disableMainFilter + +#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG + +#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */ diff --git a/gpio_bitfield_cpu2/device/driverlib/ecap.c b/gpio_bitfield_cpu2/device/driverlib/ecap.c new file mode 100644 index 0000000..4a48441 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/ecap.c @@ -0,0 +1,61 @@ +//########################################################################### +// +// FILE: ecap.c +// +// TITLE: C28x ECAP driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ecap.h" + +//***************************************************************************** +// +// ECAP_setEmulationMode +// +//***************************************************************************** +void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to FREE/SOFT bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) | + ((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S)); +} diff --git a/gpio_bitfield_cpu2/device/driverlib/ecap.h b/gpio_bitfield_cpu2/device/driverlib/ecap.h new file mode 100644 index 0000000..577d7a8 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/ecap.h @@ -0,0 +1,1164 @@ +//########################################################################### +// +// FILE: ecap.h +// +// TITLE: C28x ECAP driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef ECAP_H +#define ECAP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ecap_api eCAP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Includes +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ecap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// eCAP minimum and maximum values +// +//***************************************************************************** +#define ECAP_MAX_PRESCALER_VALUE 32U // Maximum Pre-scaler value + +//***************************************************************************** +// +// Values that can be passed to ECAP_enableInterrupt(), +// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as +// the intFlags parameter and returned by ECAP_getInterruptSource(). +// +//***************************************************************************** +//! Event 1 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_1 0x2U +//! Event 2 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_2 0x4U +//! Event 3 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_3 0x8U +//! Event 4 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_4 0x10U +//! Counter overflow ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_OVERFLOW 0x20U +//! Counter equals period ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_PERIOD 0x40U +//! Counter equals compare ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_COMPARE 0x80U + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEmulationMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! TSCTR is stopped on emulation suspension + ECAP_EMULATION_STOP = 0x0U, + //! TSCTR runs until 0 before stopping on emulation suspension + ECAP_EMULATION_RUN_TO_ZERO = 0x1U, + //! TSCTR is not affected by emulation suspension + ECAP_EMULATION_FREE_RUN = 0x2U +}ECAP_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setCaptureMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! eCAP operates in continuous capture mode + ECAP_CONTINUOUS_CAPTURE_MODE = 0U, + //! eCAP operates in one shot capture mode + ECAP_ONE_SHOT_CAPTURE_MODE = 1U +}ECAP_CaptureMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(), +//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(), +//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVENT_1 = 0U, //!< eCAP event 1 + ECAP_EVENT_2 = 1U, //!< eCAP event 2 + ECAP_EVENT_3 = 2U, //!< eCAP event 3 + ECAP_EVENT_4 = 3U //!< eCAP event 4 +}ECAP_Events; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! sync out on the sync in signal and software force + ECAP_SYNC_OUT_SYNCI = 0x00U, + //! sync out on counter equals period + ECAP_SYNC_OUT_COUNTER_PRD = 0x40U, + //! Disable sync out signal + ECAP_SYNC_OUT_DISABLED = 0x80U +}ECAP_SyncOutMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high + ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low +}ECAP_APWMPolarity; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity + ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity +}ECAP_EventPolarity; + +//***************************************************************************** +// +//! \internal +//! Checks eCAP base address. +//! +//! \param base specifies the eCAP module base address. +//! +//! This function determines if an eCAP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool ECAP_isBaseValid(uint32_t base) +{ + return( + (base == ECAP1_BASE) || + (base == ECAP2_BASE) || + (base == ECAP3_BASE) || + (base == ECAP4_BASE) || + (base == ECAP5_BASE) || + (base == ECAP6_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the input prescaler. +//! +//! \param base is the base address of the ECAP module. +//! \param preScalerValue is the pre scaler value for ECAP input +//! +//! This function divides the ECAP input scaler. The pre scale value is +//! doubled inside the module. For example a preScalerValue of 5 will divide +//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1. +//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPrescaler(uint32_t base, + uint16_t preScalerValue) +{ + ASSERT(ECAP_isBaseValid(base)); + + ASSERT(preScalerValue < ECAP_MAX_PRESCALER_VALUE); + + + // + // Write to PRESCALE bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_PRESCALE_M)) | + (preScalerValue << ECAP_ECCTL1_PRESCALE_S)); +} + +//***************************************************************************** +// +//! Sets the Capture event polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! \param polarity is the polarity of the event. +//! +//! This function sets the polarity of a given event. The value of event +//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to +//! the four available events.For each event the polarity value determines the +//! edge on which the capture is activated. For a rising edge use a polarity +//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of +//! \b ECAP_EVNT_FALLING_EDGE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPolarity(uint32_t base, + ECAP_Events event, + ECAP_EventPolarity polarity) +{ + + uint16_t shift; + + ASSERT(ECAP_isBaseValid(base)); + + shift = ((uint16_t)event) << 1U; + + + // + // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL + // + HWREGH(base + ECAP_O_ECCTL1) = + (HWREGH(base + ECAP_O_ECCTL1) & ~(1U << shift)) | + ((uint16_t)polarity << shift); +} + +//***************************************************************************** +// +//! Sets the capture mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the capture mode. +//! \param event is the event number at which the counter stops or wraps. +//! +//! This function sets the eCAP module to a continuous or one-shot mode. +//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or +//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode +//! respectively. +//! +//! The value of event determines the event number at which the counter stops +//! (in one-shot mode) or the counter wraps (in continuous mode). The value of +//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding +//! to the valid event numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setCaptureMode(uint32_t base, + ECAP_CaptureMode mode, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to CONT/ONESHT + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_CONT_ONESHT)) | + (uint16_t)mode); + + // + // Write to STOP_WRAP + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_STOP_WRAP_M)) | + (((uint16_t)event) << ECAP_ECCTL2_STOP_WRAP_S )); +} + +//***************************************************************************** +// +//! Re-arms the eCAP module. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function re-arms the eCAP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_reArm(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to RE-ARM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_REARM; +} + +//***************************************************************************** +// +//! Enables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be enabled. +//! +//! This function sets and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + + // + // Set bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be disabled. +//! +//! This function clears and disables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableInterrupt(uint32_t base, + uint16_t intFlags) +{ + + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Clear bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) &= ~intFlags; +} + +//***************************************************************************** +// +//! Returns the interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP interrupt flag. The following are valid +//! interrupt sources corresponding to the eCAP interrupt flag. +//! +//! \return Returns the eCAP interrupt that has occurred. The following are +//! valid return values. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \note - User can check if a combination of various interrupts have occurred +//! by ORing the above return values. +// +//***************************************************************************** +static inline uint16_t ECAP_getInterruptSource(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of ECFLG register + // + return(HWREGH(base + ECAP_O_ECFLG) & 0xFEU); +} + +//***************************************************************************** +// +//! Returns the Global interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP Global interrupt flag. +//! +//! \return Returns true if there is a global eCAP interrupt, false otherwise. +// +//***************************************************************************** +static inline bool ECAP_getGlobalInterruptStatus(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of Global interrupt bit + // + return((HWREGH(base + ECAP_O_ECFLG) & 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Clears interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function clears eCAP interrupt flags. The following are valid +//! interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + // + // Write to ECCLR register + // + HWREGH(base + ECAP_O_ECCLR) = intFlags; +} + +//***************************************************************************** +// +//! Clears global interrupt flag +//! +//! \param base is the base address of the ECAP module. +//! +//! This function clears the global interrupt bit. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearGlobalInterrupt(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to INT bit + // + HWREGH(base + ECAP_O_ECCLR) = ECAP_ECCLR_INT; +} + +//***************************************************************************** +// +//! Forces interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function forces and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_forceInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Write to ECFRC register + // + HWREGH(base + ECAP_O_ECFRC) = intFlags; +} + +//***************************************************************************** +// +//! Sets eCAP in Capture mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCaptureMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Sets eCAP in APWM mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in APWM mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableAPWMMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Enables counter reset on an event. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function enables the base timer, TSCTR, to be reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) |= 1U << ((2U * (uint16_t)event) + 1U); +} + +//***************************************************************************** +// +//! Disables counter reset on events. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function disables the base timer, TSCTR, from being reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) &= ~(1U << ((2U * (uint16_t)event) + 1U)); +} + +//***************************************************************************** +// +//! Enables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) |= ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Disables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Sets a phase shift value count. +//! +//! \param base is the base address of the ECAP module. +//! \param shiftCount is the phase shift value. +//! +//! This function writes a phase shift value to be loaded into the main time +//! stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CTRPHS + // + HWREG(base + ECAP_O_CTRPHS) = shiftCount; +} + +//***************************************************************************** +// +//! Enable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Disable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Load time stamp counter +//! +//! \param base is the base address of the ECAP module. +//! +//! This function forces the value in the phase shift counter register to be +//! loaded into Time stamp counter register. +//! Make sure to enable loading of Time stamp counter by calling +//! ECAP_enableLoadCounter() function before calling this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_loadCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SWSYNC + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SWSYNC; +} + +//***************************************************************************** +// +//! Configures Sync out signal mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the sync out mode. +//! +//! This function sets the sync out mode. Valid parameters for mode are: +//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event. +//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period. +//! - ECAP_SYNC_OUT_DISABLED - Disable sync out. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setSyncOutMode(uint32_t base, + ECAP_SyncOutMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCO_SEL + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_SYNCO_SEL_M)) | + (uint16_t)mode); +} + +//***************************************************************************** +// +//! Stops Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function stops the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_stopCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Starts Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function starts the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_startCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Set eCAP APWM polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param polarity is the polarity of APWM +//! +//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for +//! polarity are: +//! - ECAP_APWM_ACTIVE_HIGH - For active high. +//! - ECAP_APWM_ACTIVE_LOW - For active low. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPolarity(uint32_t base, + ECAP_APWMPolarity polarity) +{ + ASSERT(ECAP_isBaseValid(base)); + + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & ~ECAP_ECCTL2_APWMPOL) | + (uint16_t)polarity); +} + +//***************************************************************************** +// +//! Set eCAP APWM period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the period count for APWM. +//! +//! This function sets the period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP1 + // + HWREG(base + ECAP_O_CAP1) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the on or off time count of the APWM waveform depending +//! on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on +//! time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP2 + // + HWREG(base + ECAP_O_CAP2) = compareCount; +} + +//***************************************************************************** +// +//! Load eCAP APWM shadow period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the shadow period count for APWM. +//! +//! This function sets the shadow period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowPeriod(uint32_t base, + uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP3 + // + HWREG(base + ECAP_O_CAP3) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM shadow on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the shadow on or off time count of the APWM waveform +//! depending on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity() , is active high then compareCount determines the +//! on time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowCompare(uint32_t base, + uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP4 + // + HWREG(base + ECAP_O_CAP4) = compareCount; +} + +//***************************************************************************** +// +//! Returns the time base counter value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the time base counter value. +//! +//! \return Returns the time base counter value. +// +//***************************************************************************** +static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Read the Time base counter value + // + return(HWREG(base + ECAP_O_TSCTR)); +} + +//***************************************************************************** +// +//! Returns event time stamp. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! +//! This function returns the current time stamp count of the given event. +//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return Event time stamp value or 0 if \e event is invalid. +// +//***************************************************************************** +static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event) +{ + uint32_t count; + + ASSERT(ECAP_isBaseValid(base)); + + + switch(event) + { + case ECAP_EVENT_1: + + // + // Read CAP1 register + // + count = HWREG(base + ECAP_O_CAP1); + break; + + case ECAP_EVENT_2: + // + // Read CAP2 register + // + count = HWREG(base + ECAP_O_CAP2); + break; + + case ECAP_EVENT_3: + + // + // Read CAP3 register + // + count = HWREG(base + ECAP_O_CAP3); + break; + + case ECAP_EVENT_4: + + // + // Read CAP4 register + // + count = HWREG(base + ECAP_O_CAP4); + break; + + default: + + // + // Invalid event parameter + // + count = 0U; + break; + } + + return(count); +} + +//***************************************************************************** +// +//! Configures emulation mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the emulation mode. +//! +//! This function configures the eCAP counter, TSCTR, to the desired emulation +//! mode when emulation suspension occurs. Valid inputs for mode are: +//! - ECAP_EMULATION_STOP - Counter is stopped immediately. +//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0. +//! - ECAP_EMULATION_FREE_RUN - Counter is not affected. +//! +//! \return None. +// +//***************************************************************************** +extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ECAP_H diff --git a/gpio_bitfield_cpu2/device/driverlib/emif.c b/gpio_bitfield_cpu2/device/driverlib/emif.c new file mode 100644 index 0000000..a862104 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/emif.c @@ -0,0 +1,46 @@ +//########################################################################### +// +// FILE: emif.c +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "emif.h" + diff --git a/gpio_bitfield_cpu2/device/driverlib/emif.h b/gpio_bitfield_cpu2/device/driverlib/emif.h new file mode 100644 index 0000000..7177421 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/emif.h @@ -0,0 +1,1369 @@ +//########################################################################### +// +// FILE: emif.h +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EMIF_H +#define EMIF_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup emif_api EMIF +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_emif.h" +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines to specify access protection to EMIF_setAccessProtection(). +// +//***************************************************************************** +//! This flag is used to specify whether CPU fetches are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_FETCHPROT MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 + +//! This flag is used to specify whether CPU writes are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_CPUWRPROT MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 + +//! This flag is used to specify whether DMA writes are allowed/blocked +//! for EMIF. It is valid only for EMIF1 instance. +#define EMIF_ACCPROT0_DMAWRPROT MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF1ACCPROT0 register that aren't +// associated with EMIF1 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF1 \ + ((uint16_t)MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1) + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF2ACCPROT0 register that aren't +// associated with EMIF2 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF2 \ + ((uint16_t)MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 |\ + (uint16_t)MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2) + +//***************************************************************************** +// +// Define to mask out the bits in the ASYNC_CSx_CR register that +// aren't associated with async configuration. +// +//***************************************************************************** +#define EMIF_ASYNC_CS_CR_MASK ((uint32_t)EMIF_ASYNC_CS2_CR_R_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_TA_M) + +//***************************************************************************** +// +// Define to mask out the bits in the INT_MSK register that aren't associated +// with interrupts. +// +//***************************************************************************** +#define EMIF_ASYNC_INT_MASK ((uint16_t)EMIF_INT_MSK_SET_AT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_LT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_WR_MASK_SET_M) + +//***************************************************************************** +// +// Defines to specify interrupt sources to EMIF_enableAsyncInterrupt() and +// EMIF_disableAsyncInterrupt().Three interrupts are available for asynchronous +// memory interface: Masked Asyncronous Timeout(AT) to indicate EMxWAIT signal +// remains active even after maximum wait cycles are reached. Masked Line Trap +// (LT) to indicate illegal memory access or invalid cache line size. +// Masked Wait Rise(WR) to indicate rising edge on EMxWAIT is detected. +// +//***************************************************************************** +//! This flag is used to allow/block EMIF to generate Masked Asynchronous +//! Timeout interrupt. +#define EMIF_ASYNC_INT_AT EMIF_INT_MSK_SET_AT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Line Trap +//! interrupt. +#define EMIF_ASYNC_INT_LT EMIF_INT_MSK_SET_LT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Wait Rise +//! interrupt. +#define EMIF_ASYNC_INT_WR EMIF_INT_MSK_SET_WR_MASK_SET_M + +//***************************************************************************** +// +// Define for key for EMIF1MSEL register that enables the register write. +// +//***************************************************************************** +#define EMIF_MSEL_KEY 0x93A5CE70U + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_CR register that aren't +// associated with SDRAM configuration parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_CR_MASK ((uint32_t)EMIF_SDRAM_CR_PAGESIGE_M | \ + (uint32_t)EMIF_SDRAM_CR_IBANK_M | \ + (uint32_t)EMIF_SDRAM_CR_BIT_11_9_LOCK | \ + (uint32_t)EMIF_SDRAM_CR_CL_M | \ + (uint32_t)EMIF_SDRAM_CR_NM | \ + (uint32_t)EMIF_SDRAM_CR_SR) + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_TR register that aren't +// associated with SDRAM timings parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_TR_MASK ((uint32_t)EMIF_SDRAM_TR_T_RRD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RC_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RAS_M | \ + (uint32_t)EMIF_SDRAM_TR_T_WR_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RCD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RP_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RFC_M) + +//***************************************************************************** +// +//! Values that can be passed to EMIF_setAsyncMode(), +//! EMIF_setAsyncTimingParams(), EMIF_setAsyncDataBusWidth(), +//! EMIF_enableAsyncExtendedWait() and EMIF_disableAsyncExtendedWait() +//! as the \e offset parameter. Three chip selects are available in +//! asynchronous memory interface so there are three configuration registers +//! available for each EMIF instance. All the three chip select offsets are +//! valid for EMIF1 while only EMIF_ASYNC_CS2_OFFSET is valid for EMIF2. +// +//***************************************************************************** +typedef enum +{ + EMIF_ASYNC_CS2_OFFSET = EMIF_O_ASYNC_CS2_CR, //! It is valid only for EMIF1 instance and not for EMIF2 instance. +//! Valid value for configBase parameter is EMIF1CONFIG_BASE. Valid +//! values for select parameter can be \e EMIF_CONTROLLER_CPU1_NG, +//! \e EMIF_CONTROLLER_CPU1_G, \e EMIF_CONTROLLER_CPU2_G or +//! \e EMIF_CONTROLLER_CPU1_NG2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_selectController(uint32_t configBase, EMIF_ControllerSelect select) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase)); + + // + // Sets the bits that enables EMIF1 controller selection. + // + EALLOW; + HWREG(configBase + MEMCFG_O_EMIF1MSEL) = (EMIF_MSEL_KEY | (uint32_t)select); + EDIS; +} + +//***************************************************************************** +// +//! Sets the access protection. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! \param access is the required access protection configuration. +//! +//! This function sets the access protection for an EMIF instance from CPU +//! and DMA. The \e access parameter can be any of \b EMIF_ACCPROT0_FETCHPROT, +//! \b EMIF_ACCPROT0_CPUWRPROT \b EMIF_ACCPROT0_DMAWRPROT values or their +//! combination. EMIF_ACCPROT0_DMAWRPROT value is valid as access parameter +//! for EMIF1 instance only . +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAccessProtection(uint32_t configBase, uint16_t access) +{ + uint16_t temp; + // + // Check the arguments. + // + + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + if(configBase == EMIF1CONFIG_BASE) + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF1); + temp = EMIF_ACCPROT0_MASK_EMIF1; + } + else + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF2); + temp = EMIF_ACCPROT0_MASK_EMIF2; + } + + // + // Sets the bits that enables access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) = + (HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) & ~(temp)) | access; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function commits the access protection for an EMIF instance from +//! CPU & DMA. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_commitAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that commits access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1COMMIT) |= + MEMCFG_EMIF1COMMIT_COMMIT_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Locks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function locks the write to access configuration fields i.e +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_lockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that locks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) |= MEMCFG_EMIF1LOCK_LOCK_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function unlocks the write to access configuration fields such as +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_unlockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that unlocks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) &= + ~((uint16_t)MEMCFG_EMIF1LOCK_LOCK_EMIF1); + EDIS; +} + +//***************************************************************************** +// +// Prototypes for Asynchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Selects the asynchronous mode of operation. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param mode is the desired mode of operation for external memory. +//! +//! +//! This function sets the mode of operation for asynchronous memory +//! between Normal or Strobe mode. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values for param \e mode can be \e EMIF_ASYNC_STROBE_MODE or +//! \e EMIF_ASYNC_NORMAL_MODE. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMode(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncMode mode) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async mode of operation. + // + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) + & ~((uint32_t)EMIF_ASYNC_CS2_CR_SS)) + | (uint32_t)mode; +} + +//***************************************************************************** +// +//! Enables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of the +//! EMIF instance +//! +//! This function enables the extended wait mode for an asynchronous +//! external memory.Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that enables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) | + EMIF_ASYNC_CS2_CR_EW; +} + +//***************************************************************************** +// +//! Disables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! This function disables the extended wait mode for an asynchronous external +//! memory.Valid values for param \e offset can be \e EMIF_ASYNC_CS2_OFFSET, +//! \e EMIF_ASYNC_CS3_OFFSET & \e EMIF_ASYNC_C43_OFFSET for EMIF1 and +//! \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) + { + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that disables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) & + ~((uint32_t)EMIF_ASYNC_CS2_CR_EW); +} + +//***************************************************************************** +// +//! Sets the wait polarity. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param polarity is desired wait polarity. +//! +//! This function sets the wait polarity for an asynchronous external memory. +//! Valid values for param \e polarity can be \e EMIF_ASYNC_WAIT_POLARITY_LOW +//! or \e EMIF_ASYNC_WAIT_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncWaitPolarity(uint32_t base, EMIF_AsyncWaitPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the polarity for async extended wait mode. + // + HWREG(base + EMIF_O_ASYNC_WCCR) = (HWREG(base + EMIF_O_ASYNC_WCCR) + & ~((uint32_t)EMIF_ASYNC_WCCR_WP0)) + | (uint32_t)polarity; +} + +//***************************************************************************** +// +//! Sets the Maximum Wait Cycles. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param value is the desired maximum wait cycles. +//! +//! This function sets the maximum wait cycles for extended asynchronous cycle. +//! Valid values for parameter \e value lies b/w 0x0U-0xFFU or 0-255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMaximumWaitCycles(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(value <= (EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)); + + // + // Sets the bit that enables extended wait mode. + // + HWREGH(base + EMIF_O_ASYNC_WCCR) = (HWREGH(base + EMIF_O_ASYNC_WCCR) + & ~((uint16_t)EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)) + | value; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Memory Timing Characteristics. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param tParam is the desired timing parameters. +//! +//! This function sets timing characteristics for an external asynchronous +//! memory to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET and +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 & EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncTimingParams(uint32_t base, EMIF_AsyncCSOffset offset, + const EMIF_AsyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory timing parameters. + // + temp = (tParam->turnArnd << EMIF_ASYNC_CS2_CR_TA_S) | + (tParam->rHold << EMIF_ASYNC_CS2_CR_R_HOLD_S) | + (tParam->rStrobe << EMIF_ASYNC_CS2_CR_R_STROBE_S) | + (tParam->rSetup << EMIF_ASYNC_CS2_CR_R_SETUP_S) | + (tParam->wHold << EMIF_ASYNC_CS2_CR_W_HOLD_S) | + (tParam->wStrobe << EMIF_ASYNC_CS2_CR_W_STROBE_S) | + (tParam->wSetup << EMIF_ASYNC_CS2_CR_W_SETUP_S); + + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) & + ~EMIF_ASYNC_CS_CR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Data Bus Width. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param width is the data bus width of the memory. +//! +//! This function sets the data bus size for an external asynchronous memory +//! to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values of param \e width can be \e EMIF_ASYNC_DATA_WIDTH_8, +//! \e EMIF_ASYNC_DATA_WIDTH_16 or \e EMIF_ASYNC_DATA_WIDTH_32. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncDataBusWidth(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncDataWidth width) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory data bus width. + // + HWREGH(base + (uint32_t)offset) = (HWREGH(base + (uint32_t)offset) + & ~((uint16_t)EMIF_ASYNC_CS2_CR_ASIZE_M)) + | (uint32_t)width; +} + +//***************************************************************************** +// +// Prototypes for Interrupt Handling +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for desired interrupts. +//! +//! This function enables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or their +//! combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that enables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_SET) = intFlags; +} + +//***************************************************************************** +// +//! Disables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for interrupts to be disabled. +//! +//! This function disables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or +//! their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that disables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_CLR) = intFlags; + +} + +//***************************************************************************** +// +//! Gets the interrupt status. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function gets the interrupt status for an EMIF instance. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +static inline uint16_t +EMIF_getAsyncInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets the async memory interrupt status. + // + return(HWREGH(base + EMIF_O_INT_MSK) & EMIF_ASYNC_INT_MASK); +} + +//***************************************************************************** +// +//! Clears the interrupt status for an EMIF instance. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for the interrupt status to be cleared. +//! +//! This function clears the interrupt status for an EMIF instance. +//! The \e intFlags parameter can be any of \b EMIF_INT_MSK_SET_AT_MASK_SET, +//! \b EMIF_INT_MSK_SET_LT_MASK_SET, or \b EMIF_INT_MSK_SET_WR_MASK_SET_M +//! values or their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_clearAsyncInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bit that clears desired async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK) = intFlags; +} + +//***************************************************************************** +// +// Prototypes for Synchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Sets the Synchronous Memory Timing Parameters. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tParam is parameters from memory datasheet in \e ns. +//! +//! This function sets the timing characteristics for an external +//! synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncTimingParams(uint32_t base, const EMIF_SyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets sync memory timing parameters. + // + temp = ((tParam->tRrd << EMIF_SDRAM_TR_T_RRD_S) + & EMIF_SDRAM_TR_T_RRD_M) + | ((tParam->tRc << EMIF_SDRAM_TR_T_RC_S) + & EMIF_SDRAM_TR_T_RC_M) + | ((tParam->tRas << EMIF_SDRAM_TR_T_RAS_S) + & EMIF_SDRAM_TR_T_RAS_M) + | ((tParam->tWr << EMIF_SDRAM_TR_T_WR_S) + & EMIF_SDRAM_TR_T_WR_M) + | ((tParam->tRcd << EMIF_SDRAM_TR_T_RCD_S) + & EMIF_SDRAM_TR_T_RCD_M) + | ((tParam->tRp << EMIF_SDRAM_TR_T_RP_S) + & EMIF_SDRAM_TR_T_RP_M) + | ((tParam->tRfc << EMIF_SDRAM_TR_T_RFC_S) + & EMIF_SDRAM_TR_T_RFC_M); + + HWREG(base + EMIF_O_SDRAM_TR) = (HWREG(base + EMIF_O_SDRAM_TR) & + ~EMIF_SYNC_SDRAM_TR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the SDRAM Self Refresh Exit Timing. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tXs is the desired timing value. +//! +//! This function sets the self refresh exit timing for an external +//! synchronous memory to be interfaced. tXs values must lie between +//! 0x0U-0x1FU or 0-31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncSelfRefreshExitTmng(uint32_t base, uint16_t tXs) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(tXs <= EMIF_SDR_EXT_TMNG_T_XS_M); + + // + // Sets the self refresh exit timing for sync memory. + // + HWREGH(base + EMIF_O_SDR_EXT_TMNG) = (HWREGH(base + EMIF_O_SDR_EXT_TMNG) + & ~((uint16_t)EMIF_SDR_EXT_TMNG_T_XS_M)) + | tXs; +} + +//***************************************************************************** +// +//! Sets the SDR Refresh Rate. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param refRate is the refresh rate. +//! +//! This function sets the refresh rate for an external synchronous memory +//! to be interfaced. Valid values for refRate lies b/w 0x0U-0x1FFFU or +//! 0-8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncRefreshRate(uint32_t base, uint16_t refRate) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(refRate <= EMIF_SDRAM_RCR_REFRESH_RATE_M); + + // + // Sets the sync memory refresh rate. + // + HWREGH(base + EMIF_O_SDRAM_RCR) = (HWREGH(base + EMIF_O_SDRAM_RCR) + & (~(uint16_t)EMIF_SDRAM_RCR_REFRESH_RATE_M)) + | refRate; +} + +//***************************************************************************** +// +//! Sets the Synchronous Memory configuration parameters. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param config is the desired configuration parameters. +//! +//! This function sets configuration parameters like CL, NM, IBANK +//! and PAGESIZE for an external synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncMemoryConfig(uint32_t base, const EMIF_SyncConfig *config) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the sync memory configuration bits. + // + temp = ((uint32_t)config->casLatency | (uint32_t)config->iBank | + (uint32_t)config->narrowMode | (uint32_t)config->pageSize); + + HWREG(base + EMIF_O_SDRAM_CR) = (HWREG(base + EMIF_O_SDRAM_CR) & + ~EMIF_SYNC_SDRAM_CR_MASK) | temp; +} + +//***************************************************************************** +// +// Prototypes for EMIF Low Power Modes +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_SR; +} + +//***************************************************************************** +// +//! Disables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_SR); +} + +//***************************************************************************** +// +//! Enables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function Enables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PD; +} + +//***************************************************************************** +// +//! Disables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PD); +} + +//***************************************************************************** +// +//! Enables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PDWR; +} + +//***************************************************************************** +// +//! Disables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PDWR); +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of SDRAM accesses +//! from a controller(CPUx/CPUx.DMA). +//! +//! \return \e Returns total number of accesses to SDRAM. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_AR)); + +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses which require activate command. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of accesses to SDRAM which +//! require activate command. +//! +//!\return \e Returns total number of accesses to SDRAM which require activate. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalActivateAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory which requires activate command. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_ACTR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EMIF_H diff --git a/gpio_bitfield_cpu2/device/driverlib/epwm.c b/gpio_bitfield_cpu2/device/driverlib/epwm.c new file mode 100644 index 0000000..76e09bb --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/epwm.c @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: epwm.c +// +// TITLE: C28x EPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "epwm.h" + +//***************************************************************************** +// +// EPWM_setEmulationMode +// +//***************************************************************************** +void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode) +{ + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to FREE_SOFT bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) | + ((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S)); +} + +//***************************************************************************** +// +// EPWM_configureSignal +// +//***************************************************************************** +void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams) +{ + float32_t tbClkInHz = 0.0F; + uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U; + + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Valid values in the function for TBCTR Mode are UP, DOWN + // and UP-DOWN count. + // + ASSERT((uint16_t)signalParams->tbCtrMode <= 2U); + + // + // Configure EPWM clock Divider + // + SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv); + + // + // Configure Time Base counter Clock + // + EPWM_setClockPrescaler(base, signalParams->tbClkDiv, + signalParams->tbHSClkDiv); + + // + // Configure Time Base Counter Mode + // + EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode); + + // + // Calculate TBCLK, TBPRD and CMPx values to be configured for + // achieving desired signal + // + tbClkInHz = ((float32_t)signalParams->sysClkInHz / + (float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv + + (uint16_t)signalParams->tbClkDiv))); + + if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4) + { + tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv); + } + else + { + tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv); + } + + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)(signalParams->dutyValA * + (float32_t)(tbPrdVal + 1U)); + cmpBVal = (uint16_t)(signalParams->dutyValB * + (float32_t)(tbPrdVal + 1U)); + } + else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValA * (float32_t)(tbPrdVal + 1U))); + cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValB * (float32_t)(tbPrdVal + 1U))); + } + else + { + tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz)); + cmpAVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValA * + (float32_t)tbPrdVal))) + 0.5f); + cmpBVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValB * + (float32_t)tbPrdVal))) + 0.5f); + } + + // + // Configure TBPRD value + // + EPWM_setTimeBasePeriod(base, tbPrdVal); + + // + // Default Configurations. + // + EPWM_disablePhaseShiftLoad(base); + EPWM_setPhaseShift(base, 0U); + EPWM_setTimeBaseCounter(base, 0U); + + // + // Setup shadow register load on ZERO + // + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_A, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_B, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + // + // Set Compare values + // + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, + cmpAVal); + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, + cmpBVal); + + // + // Set actions for ePWMxA & ePWMxB + // + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + + } + } + else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } + else + { + // + // Clear PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/epwm.h b/gpio_bitfield_cpu2/device/driverlib/epwm.h new file mode 100644 index 0000000..ada9b80 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/epwm.h @@ -0,0 +1,7496 @@ +//############################################################################# +// +// FILE: epwm.h +// +// TITLE: C28x EPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef EPWM_H +#define EPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup epwm_api ePWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_epwm.h" +#include "cpu.h" +#include "debug.h" +#include "sysctl.h" + + +// +// Time Base Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setEmulationMode() as the +//! \e emulationMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Stop after next Time Base counter increment or decrement + EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0, + //! Stop when counter completes whole cycle + EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1, + //! Free run + EPWM_EMULATION_FREE_RUN = 2 +} EPWM_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCountModeAfterSync() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event + EPWM_COUNT_MODE_UP_AFTER_SYNC = 1 //!< Count up after sync event +} EPWM_SyncCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_CLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_CLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_CLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_CLOCK_DIVIDER_8 = 3, //!< Divide clock by 8 + EPWM_CLOCK_DIVIDER_16 = 4, //!< Divide clock by 16 + EPWM_CLOCK_DIVIDER_32 = 5, //!< Divide clock by 32 + EPWM_CLOCK_DIVIDER_64 = 6, //!< Divide clock by 64 + EPWM_CLOCK_DIVIDER_128 = 7 //!< Divide clock by 128 +} EPWM_ClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e highSpeedPrescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_HSCLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_HSCLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_HSCLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_HSCLOCK_DIVIDER_6 = 3, //!< Divide clock by 6 + EPWM_HSCLOCK_DIVIDER_8 = 4, //!< Divide clock by 8 + EPWM_HSCLOCK_DIVIDER_10 = 5, //!< Divide clock by 10 + EPWM_HSCLOCK_DIVIDER_12 = 6, //!< Divide clock by 12 + EPWM_HSCLOCK_DIVIDER_14 = 7 //!< Divide clock by 14 +} EPWM_HSClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setSyncOutPulseMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Sync pulse is generated by software + EPWM_SYNC_OUT_PULSE_ON_SOFTWARE = 0, + //! Sync pulse is passed from EPWMxSYNCIN + EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN = 0, + //! Sync pulse is generated when time base counter equals zero + EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO = 1, + //! Sync pulse is generated when time base counter equals compare B value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B = 2, + //! Sync pulse is disabled + EPWM_SYNC_OUT_PULSE_DISABLED = 4, + //! Sync pulse is generated when time base counter equals compare C value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C = 5, + //! Sync pulse is generated when time base counter equals compare D value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D = 6 +} EPWM_SyncOutPulseMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setPeriodLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! PWM Period register access is through shadow register + EPWM_PERIOD_SHADOW_LOAD = 0, + //! PWM Period register access is directly + EPWM_PERIOD_DIRECT_LOAD = 1 +} EPWM_PeriodLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTimeBaseCounterMode() as the +//! \e counterMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_MODE_UP = 0, //!< Up - count mode + EPWM_COUNTER_MODE_DOWN = 1, //!< Down - count mode + EPWM_COUNTER_MODE_UP_DOWN = 2, //!< Up - down - count mode + EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter +} EPWM_TimeBaseCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectPeriodLoadEvent() as the +//! \e shadowLoadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow to active load occurs when time base counter reaches 0 + EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0, + //! Shadow to active load occurs when time base counter reaches 0 and a + //! SYNC occurs + EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1, + //! Shadow to active load occurs only when a SYNC occurs + EPWM_SHADOW_LOAD_MODE_SYNC = 2 +} EPWM_PeriodShadowLoadMode; + +//***************************************************************************** +// +// Values that can be returned by the EPWM_getTimeBaseCounterDirection() +// +//***************************************************************************** +//! Time base counter is counting up +//! +#define EPWM_TIME_BASE_STATUS_COUNT_UP 1U +//! Time base counter is counting down +//! +#define EPWM_TIME_BASE_STATUS_COUNT_DOWN 0U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_WITH_EPWM_1 = 0, //!< link current ePWM with ePWM1 + EPWM_LINK_WITH_EPWM_2 = 1, //!< link current ePWM with ePWM2 + EPWM_LINK_WITH_EPWM_3 = 2, //!< link current ePWM with ePWM3 + EPWM_LINK_WITH_EPWM_4 = 3, //!< link current ePWM with ePWM4 + EPWM_LINK_WITH_EPWM_5 = 4, //!< link current ePWM with ePWM5 + EPWM_LINK_WITH_EPWM_6 = 5, //!< link current ePWM with ePWM6 + EPWM_LINK_WITH_EPWM_7 = 6, //!< link current ePWM with ePWM7 + EPWM_LINK_WITH_EPWM_8 = 7, //!< link current ePWM with ePWM8 + EPWM_LINK_WITH_EPWM_9 = 8, //!< link current ePWM with ePWM9 + EPWM_LINK_WITH_EPWM_10 = 9, //!< link current ePWM with ePWM10 + EPWM_LINK_WITH_EPWM_11 = 10, //!< link current ePWM with ePWM11 + EPWM_LINK_WITH_EPWM_12 = 11 //!< link current ePWM with ePWM12 +} EPWM_CurrentLink; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_TBPRD = 0U, //!< link TBPRD registers + EPWM_LINK_COMP_A = 4U, //!< link COMPA registers + EPWM_LINK_COMP_B = 8U, //!< link COMPB registers + EPWM_LINK_COMP_C = 12U, //!< link COMPC registers + EPWM_LINK_COMP_D = 16U, //!< link COMPD registers + EPWM_LINK_GLDCTL2 = 28U //!< link GLDCTL2 registers +} EPWM_LinkComponent; + +// +// Counter Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to the EPWM_getCounterCompareShadowStatus(), +//! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(), +//! EPWM_disableCounterCompareShadowLoadMode() +//! as the \e compModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_COMPARE_A = 0, //!< Counter compare A + EPWM_COUNTER_COMPARE_B = 2, //!< Counter compare B + EPWM_COUNTER_COMPARE_C = 5, //!< Counter compare C + EPWM_COUNTER_COMPARE_D = 7 //!< Counter compare D +} EPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_COMP_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_COMP_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_COMP_LOAD_ON_SYNC_ONLY = 8 +} EPWM_CounterCompareLoadMode; + +// +// Action Qualifier Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and +//! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A + EPWM_ACTION_QUALIFIER_B = 2 //!< Action Qualifier B +} EPWM_ActionQualifierModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_AQ_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_AQ_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_AQ_LOAD_ON_SYNC_ONLY = 8 +} EPWM_ActionQualifierLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and +//! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, //!< Digital compare event A 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, //!< Digital compare event A 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, //!< Digital compare event B 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, //!< Digital compare event B 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, //!< Trip zone 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, //!< Trip zone 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, //!< Trip zone 3 + EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7 //!< ePWM sync +} EPWM_ActionQualifierTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierAction() as the \e +//! event parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0, + //! Time base counter equals period + EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2, + //! Time base counter up equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4, + //! Time base counter down equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6, + //! Time base counter up equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8, + //! Time base counter down equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10, + //! T1 event on count up + EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1, + //! T1 event on count down + EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3, + //! T2 event on count up + EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5, + //! T2 event on count down + EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7 +} EPWM_ActionQualifierOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierSWAction(), +//! EPWM_setActionQualifierAction() as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_NO_CHANGE = 0, //!< No change in the output pins + EPWM_AQ_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_OUTPUT_HIGH = 2, //!< Set output pins to High + EPWM_AQ_OUTPUT_TOGGLE = 3 //!< Toggle the output pins +} EPWM_ActionQualifierOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceAction() +//! as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_SW_DISABLED = 0, //!< Software forcing disabled + EPWM_AQ_SW_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_SW_OUTPUT_HIGH = 2 //!< Set output pins to High +} EPWM_ActionQualifierSWOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierActionComplete() +//! as the \e action parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0, + //! Time base counter equals zero and set output pins to low + EPWM_AQ_OUTPUT_LOW_ZERO = 0x1, + //! Time base counter equals zero and set output pins to high + EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2, + //! Time base counter equals zero and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3, + //! Time base counter equals period and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0, + //! Time base counter equals period and set output pins to low + EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4, + //! Time base counter equals period and set output pins to high + EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8, + //! Time base counter equals period and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC, + //! Time base counter up equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00, + //! Time base counter up equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10, + //! Time base counter up equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20, + //! Time base counter up equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30, + //! Time base counter down equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00, + //! Time base counter down equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40, + //! Time base counter down equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80, + //! Time base counter down equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0, + //! Time base counter up equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000, + //! Time base counter up equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100, + //! Time base counter up equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200, + //! Time base counter up equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300, + //! Time base counter down equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000, + //! Time base counter down equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400, + //! Time base counter down equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800, + //! Time base counter down equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00 +} EPWM_ActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to +//! EPWM_setAdditionalActionQualifierActionComplete() as the \e action +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! T1 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0, + //! T1 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1, + //! T1 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2, + //! T1 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3, + //! T1 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0, + //! T1 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4, + //! T1 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8, + //! T1 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC, + //! T2 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00, + //! T2 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10, + //! T2 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20, + //! T2 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30, + //! T2 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00, + //! T2 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40, + //! T2 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80, + //! T2 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0 +} EPWM_AdditionalActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_forceActionQualifierSWAction(), +//! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction() +//! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output + EPWM_AQ_OUTPUT_B = 2 //!< ePWMxB output +} EPWM_ActionQualifierOutputModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode() +//! as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow mode load when counter equals zero + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0, + //! Shadow mode load when counter equals period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1, + //! Shadow mode load when counter equals zero or period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! No shadow load mode. Immediate mode only. + EPWM_AQ_SW_IMMEDIATE_LOAD = 3 +} EPWM_ActionQualifierContForce; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandOutputSwapMode() +//! as the \e output parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_OUTPUT_A = 1, //!< DB output is ePWMA + EPWM_DB_OUTPUT_B = 0 //!< DB output is ePWMB +} EPWM_DeadBandOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity(), +//! EPWM_setDeadBandDelayMode() as the \e delayMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode + EPWM_DB_FED = 0 //!< DB FED (Falling Edge Delay) mode +} EPWM_DeadBandDelayMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity as the +//! \e polarity parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted + EPWM_DB_POLARITY_ACTIVE_LOW = 1 //!< DB polarity is inverted +} EPWM_DeadBandPolarity; + +//***************************************************************************** +// +// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(), +// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter. +// +//***************************************************************************** +//! Input signal is ePWMA +//! +#define EPWM_DB_INPUT_EPWMA 0U +//! Input signal is ePWMB +//! +#define EPWM_DB_INPUT_EPWMB 1U +//! Input signal is the output of Rising Edge delay +//! +#define EPWM_DB_INPUT_DB_RED 2U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as +//! the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_DB_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_DB_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_DB_LOAD_FREEZE = 3 +} EPWM_DeadBandControlLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_RED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_RED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_RED_LOAD_FREEZE = 3 +} EPWM_RisingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_FED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_FED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_FED_LOAD_FREEZE = 3 +} EPWM_FallingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandCounterClock() as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Dead band counter runs at TBCLK rate + EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0, + //! Dead band counter runs at 2*TBCLK rate + EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1 +} EPWM_DeadBandClockMode; + +// +// Trip Zone +// +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneSignals() and +// EPWM_disableTripZoneSignals() as the tzSignal parameter. +// +//***************************************************************************** +//! TZ1 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC1 0x1U +//! TZ2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC2 0x2U +//! TZ3 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC3 0x4U +//! TZ4 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC4 0x8U +//! TZ5 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC5 0x10U +//! TZ6 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC6 0x20U +//! DCAEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCAEVT2 0x40U +//! DCBEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCBEVT2 0x80U +//! One-shot TZ1 +//! +#define EPWM_TZ_SIGNAL_OSHT1 0x100U +//! One-shot TZ2 +//! +#define EPWM_TZ_SIGNAL_OSHT2 0x200U +//! One-shot TZ3 +//! +#define EPWM_TZ_SIGNAL_OSHT3 0x400U +//! One-shot TZ4 +//! +#define EPWM_TZ_SIGNAL_OSHT4 0x800U +//! One-shot TZ5 +//! +#define EPWM_TZ_SIGNAL_OSHT5 0x1000U +//! One-shot TZ6 +//! +#define EPWM_TZ_SIGNAL_OSHT6 0x2000U +//! One-shot DCAEVT1 +//! +#define EPWM_TZ_SIGNAL_DCAEVT1 0x4000U +//! One-shot DCBEVT1 +//! +#define EPWM_TZ_SIGNAL_DCBEVT1 0x8000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcType parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A + EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A + EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B + EPWM_TZ_DC_OUTPUT_B2 = 9 //!< Digital Compare output 2 B +} EPWM_TripZoneDigitalCompareOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_EVENT_DC_DISABLED = 0, //!< Event is disabled + EPWM_TZ_EVENT_DCXH_LOW = 1, //!< Event when DCxH low + EPWM_TZ_EVENT_DCXH_HIGH = 2, //!< Event when DCxH high + EPWM_TZ_EVENT_DCXL_LOW = 3, //!< Event when DCxL low + EPWM_TZ_EVENT_DCXL_HIGH = 4, //!< Event when DCxL high + EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low +} EPWM_TripZoneDigitalCompareOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_EVENT_TZA = 0, //!< TZ1 - TZ6, DCAEVT2, DCAEVT1 + EPWM_TZ_ACTION_EVENT_TZB = 2, //!< TZ1 - TZ6, DCBEVT2, DCBEVT1 + EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1) + EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2) + EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1) + EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2) +} EPWM_TripZoneEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the +//! \e tzAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ACTION_DISABLE = 3 //!< Disable action +} EPWM_TripZoneAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvAction() as the +//! \e tzAdvEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9, + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0 +} EPWM_TripZoneAdvancedEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(), +//! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction() +//! as the \e tzAdvDCAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ADV_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ADV_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ADV_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ADV_ACTION_TOGGLE = 3, //!< Toggle the output + EPWM_TZ_ADV_ACTION_DISABLE = 7 //!< Disable action +} EPWM_TripZoneAdvancedAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and +//! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital Compare event A/B 1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0, + //! Digital Compare event A/B 1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3, + //! Digital Compare event A/B 2 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6, + //! Digital Compare event A/B 2 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9 +} EPWM_TripZoneAdvDigitalCompareEvent; + + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneInterrupt()and +// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle interrupt +//! +#define EPWM_TZ_INTERRUPT_CBC 0x2U +//! Trip Zones One Shot interrupt +//! +#define EPWM_TZ_INTERRUPT_OST 0x4U +//! Digital Compare A Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT1 0x8U +//! Digital Compare A Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT2 0x10U +//! Digital Compare B Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT1 0x20U +//! Digital Compare B Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be returned by EPWM_getTripZoneFlagStatus() . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle flag +//! +#define EPWM_TZ_FLAG_CBC 0x2U +//! Trip Zones One Shot flag +//! +#define EPWM_TZ_FLAG_OST 0x4U +//! Digital Compare A Event 1 flag +//! +#define EPWM_TZ_FLAG_DCAEVT1 0x8U +//! Digital Compare A Event 2 flag +//! +#define EPWM_TZ_FLAG_DCAEVT2 0x10U +//! Digital Compare B Event 1 flag +//! +#define EPWM_TZ_FLAG_DCBEVT1 0x20U +//! Digital Compare B Event 2 flag +//! +#define EPWM_TZ_FLAG_DCBEVT2 0x40U + +//***************************************************************************** +// +// Value can be passed to EPWM_clearTripZoneFlag() as the +// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus(). +// +//***************************************************************************** +//! Trip Zone interrupt +//! +#define EPWM_TZ_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag() +// as the tzCbcFlag parameter and returned by +// EPWM_getCycleByCycleTripZoneFlagStatus(). +// +//***************************************************************************** +//! CBC flag 1 +//! +#define EPWM_TZ_CBC_FLAG_1 0x1U +//! CBC flag 2 +//! +#define EPWM_TZ_CBC_FLAG_2 0x2U +//! CBC flag 3 +//! +#define EPWM_TZ_CBC_FLAG_3 0x4U +//! CBC flag 4 +//! +#define EPWM_TZ_CBC_FLAG_4 0x8U +//! CBC flag 5 +//! +#define EPWM_TZ_CBC_FLAG_5 0x10U +//! CBC flag 6 +//! +#define EPWM_TZ_CBC_FLAG_6 0x20U +//! CBC flag Digital compare event A2 +//! +#define EPWM_TZ_CBC_FLAG_DCAEVT2 0x40U +//! CBC flag Digital compare event B2 +//! +#define EPWM_TZ_CBC_FLAG_DCBEVT2 0x80U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as +// the tzCbcFlag parameter and returned by the +// EPWM_getOneShotTripZoneFlagStatus() . +// +//***************************************************************************** +//! OST flag OST1 +//! +#define EPWM_TZ_OST_FLAG_OST1 0x1U +//! OST flag OST2 +//! +#define EPWM_TZ_OST_FLAG_OST2 0x2U +//! OST flag OST3 +//! +#define EPWM_TZ_OST_FLAG_OST3 0x4U +//! OST flag OST4 +//! +#define EPWM_TZ_OST_FLAG_OST4 0x8U +//! OST flag OST5 +//! +#define EPWM_TZ_OST_FLAG_OST5 0x10U +//! OST flag OST6 +//! +#define EPWM_TZ_OST_FLAG_OST6 0x20U +//! OST flag Digital compare event A1 +//! +#define EPWM_TZ_OST_FLAG_DCAEVT1 0x40U +//! OST flag Digital compare event B1 +//! +#define EPWM_TZ_OST_FLAG_DCBEVT1 0x80U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as +//! the \e clearMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Clear CBC pulse when counter equals zero + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0, + //! Clear CBC pulse when counter equals period + EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1, + //! Clear CBC pulse when counter equals zero or period + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2 +} EPWM_CycleByCycleTripZoneClearMode; + +//***************************************************************************** +// +// Values that can be passed to EPWM_forceTripZoneEvent() as the +// tzForceEvent parameter. +// +//***************************************************************************** +//! Force Cycle By Cycle trip event +//! +#define EPWM_TZ_FORCE_EVENT_CBC 0x2U +//! Force a One-Shot Trip Event +//! +#define EPWM_TZ_FORCE_EVENT_OST 0x4U +//! Force Digital Compare Output A Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT1 0x8U +//! Force Digital Compare Output A Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT2 0x10U +//! Force Digital Compare Output B Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT1 0x20U +//! Force Digital Compare Output B Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be passed to EPWM_setInterruptSource() as the +// interruptSource parameter. +// +//***************************************************************************** +//! Time-base counter is disabled +//! +#define EPWM_INT_TBCTR_DISABLED 0U +//! Time-base counter equal to zero +//! +#define EPWM_INT_TBCTR_ZERO 1U +//! Time-base counter equal to period +//! +#define EPWM_INT_TBCTR_PERIOD 2U +//! Time-base counter equal to zero or period +//! +#define EPWM_INT_TBCTR_ZERO_OR_PERIOD 3U +//! time-base counter equal to CMPA when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPA 4U +//! time-base counter equal to CMPC when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPC 8U +//! time-base counter equal to CMPA when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPA 5U +//! time-base counter equal to CMPC when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPC 10U +//! time-base counter equal to CMPB when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPB 6U +//! time-base counter equal to CMPD when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPD 12U +//! time-base counter equal to CMPB when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPB 7U +//! time-base counter equal to CMPD when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPD 14U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_enableADCTrigger(), +//! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(), +//! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(), +//! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(), +//! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(), +//! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(), +//! EPWM_forceADCTrigger() as the \e adcSOCType parameter +// +//***************************************************************************** +typedef enum +{ + EPWM_SOC_A = 0, //!< SOC A + EPWM_SOC_B = 1 //!< SOC B +} EPWM_ADCStartOfConversionType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setADCTriggerSource() as the +//! \e socSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Event is based on DCxEVT1 + EPWM_SOC_DCxEVT1 = 0, + //! Time-base counter equal to zero + EPWM_SOC_TBCTR_ZERO = 1, + //! Time-base counter equal to period + EPWM_SOC_TBCTR_PERIOD = 2, + //! Time-base counter equal to zero or period + EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3, + //! Time-base counter equal to CMPA when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPA = 4, + //! Time-base counter equal to CMPC when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPC = 8, + //! Time-base counter equal to CMPA when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPA = 5, + //! Time-base counter equal to CMPC when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPC = 10, + //! Time-base counter equal to CMPB when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPB = 6, + //! Time-base counter equal to CMPD when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPD = 12, + //! Time-base counter equal to CMPB when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPB = 7, + //! Time-base counter equal to CMPD when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPD = 14 +} EPWM_ADCStartOfConversionSource; + +// +// Digital Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput(), +//! EPWM_enableDigitalCompareTripCombinationInput(), +//! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TYPE_DCAH = 0, //!< Digital Compare A High + EPWM_DC_TYPE_DCAL = 1, //!< Digital Compare A Low + EPWM_DC_TYPE_DCBH = 2, //!< Digital Compare B High + EPWM_DC_TYPE_DCBL = 3 //!< Digital Compare B Low +} EPWM_DigitalCompareType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput() +//! as the \e tripSource parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TRIP_TRIPIN1 = 0, //!< Trip 1 + EPWM_DC_TRIP_TRIPIN2 = 1, //!< Trip 2 + EPWM_DC_TRIP_TRIPIN3 = 2, //!< Trip 3 + EPWM_DC_TRIP_TRIPIN4 = 3, //!< Trip 4 + EPWM_DC_TRIP_TRIPIN5 = 4, //!< Trip 5 + EPWM_DC_TRIP_TRIPIN6 = 5, //!< Trip 6 + EPWM_DC_TRIP_TRIPIN7 = 6, //!< Trip 7 + EPWM_DC_TRIP_TRIPIN8 = 7, //!< Trip 8 + EPWM_DC_TRIP_TRIPIN9 = 8, //!< Trip 9 + EPWM_DC_TRIP_TRIPIN10 = 9, //!< Trip 10 + EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11 + EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12 + EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14 + EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15 + EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected +} EPWM_DigitalCompareTripInput; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput(), +// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput +// parameter. +// +//***************************************************************************** +//! Combinational Trip 1 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN1 0x1U +//! Combinational Trip 2 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN2 0x2U +//! Combinational Trip 3 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN3 0x4U +//! Combinational Trip 4 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN4 0x8U +//! Combinational Trip 5 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN5 0x10U +//! Combinational Trip 6 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN6 0x20U +//! Combinational Trip 7 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN7 0x40U +//! Combinational Trip 8 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN8 0x80U +//! Combinational Trip 9 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN9 0x100U +//! Combinational Trip 10 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN10 0x200U +//! Combinational Trip 11 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN11 0x400U +//! Combinational Trip 12 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN12 0x800U +//! Combinational Trip 14 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN14 0x2000U +//! Combinational Trip 15 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN15 0x4000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the +//! the \e blankingPulse parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals period + EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0, + //! Time base counter equals zero + EPWM_DC_WINDOW_START_TBCTR_ZERO = 1, + //! Time base counter equals zero or period + EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2 +} EPWM_DigitalCompareBlankingPulse; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareFilterInput() +//! as the \e filterInput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1 + EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2 + EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1 + EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3 //!< DC filter signal source is DCBEVT2 +} EPWM_DigitalCompareFilterInput; + +//***************************************************************************** +// +//! Values that can be assigned to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent() +//! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent() +//! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A + EPWM_DC_MODULE_B = 1 //!< Digital Compare Module B +} EPWM_DigitalCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1 + EPWM_DC_EVENT_2 = 1 //!< Digital Compare Event number 2 +} EPWM_DigitalCompareEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource() as the +//! \e dcEventSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Signal source is unfiltered (DCAEVT1/2) + EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0, + //! Signal source is filtered (DCEVTFILT) + EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1 +} EPWM_DigitalCompareEventSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the +//! \e syncMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! DC input signal is synced with TBCLK + EPWM_DC_EVENT_INPUT_SYNCED = 0, + //! DC input signal is not synced with TBCLK + EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1 +} EPWM_DigitalCompareSyncMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setGlobalLoadTrigger() as the +//! \e loadTrigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter is equal to zero + EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0, + //! Load when counter is equal to period + EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1, + //! Load when counter is equal to zero or period + EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2, + //! Load on sync event + EPWM_GL_LOAD_PULSE_SYNC = 0x3, + //! Load on sync event or when counter is equal to zero + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4, + //! Load on sync event or when counter is equal to period + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5, + //! Load on sync event or when counter is equal to period or zero + EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6, + //! Load on global force + EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF +} EPWM_GlobalLoadTrigger; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableGlobalLoadRegisters(), +// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter. +// +//***************************************************************************** +//! Global load TBPRD:TBPRDHR +//! +#define EPWM_GL_REGISTER_TBPRD_TBPRDHR 0x1U +//! Global load CMPA:CMPAHR +//! +#define EPWM_GL_REGISTER_CMPA_CMPAHR 0x2U +//! Global load CMPB:CMPBHR +//! +#define EPWM_GL_REGISTER_CMPB_CMPBHR 0x4U +//! Global load CMPC +//! +#define EPWM_GL_REGISTER_CMPC 0x8U +//! Global load CMPD +//! +#define EPWM_GL_REGISTER_CMPD 0x10U +//! Global load DBRED:DBREDHR +//! +#define EPWM_GL_REGISTER_DBRED_DBREDHR 0x20U +//! Global load DBFED:DBFEDHR +//! +#define EPWM_GL_REGISTER_DBFED_DBFEDHR 0x40U +//! Global load DBCTL +//! +#define EPWM_GL_REGISTER_DBCTL 0x80U +//! Global load AQCTLA/A2 +//! +#define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 0x100U +//! Global load AQCTLB/B2 +//! +#define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 0x200U +//! Global load AQCSFRC +//! +#define EPWM_GL_REGISTER_AQCSFRC 0x400U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyTriggerSource() as the \e +//! trigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Valley capture trigged by software + EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U, + //! Valley capture trigged by when counter is equal to zero + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U, + //! Valley capture trigged by when counter is equal period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U, + //! Valley capture trigged when counter is equal to zero or period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U, + //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U, + //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U, + //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U, + //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U +} EPWM_ValleyTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge + EPWM_VALLEY_COUNT_STOP_EDGE = 1 //!< Valley count stop edge +} EPWM_ValleyCounterEdge; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Delay value equals the offset value defines by software + EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U, + //! Delay value equals the sum of the Hardware counter value and the offset + //! value defines by software + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U, + //! Delay value equals the the Hardware counter shifted by + //! (1 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U, + //! Delay value equals the the Hardware counter shifted by + //! (2 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U, + //! Delay value equals the the Hardware counter shifted by + //! (4 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U +} EPWM_ValleyDelayMode; + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode() +//! as the \e edgeMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_MODE_RISING = 0, //!< Digital Compare Edge filter low + //!< to high edge mode + EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high + //!< to low edge mode + EPWM_DC_EDGEFILT_MODE_BOTH = 2 //!< Digital Compare Edge filter both + //!< edges mode +} EPWM_DigitalCompareEdgeFilterMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount() +//! as the \e edgeCount parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_EDGECNT_0 = 0, //!< Digital Compare Edge filter edge + //!< count = 0 + EPWM_DC_EDGEFILT_EDGECNT_1 = 1, //!< Digital Compare Edge filter edge + //!< count = 1 + EPWM_DC_EDGEFILT_EDGECNT_2 = 2, //!< Digital Compare Edge filter edge + //!< count = 2 + EPWM_DC_EDGEFILT_EDGECNT_3 = 3, //!< Digital Compare Edge filter edge + //!< count = 3 + EPWM_DC_EDGEFILT_EDGECNT_4 = 4, //!< Digital Compare Edge filter edge + //!< count = 4 + EPWM_DC_EDGEFILT_EDGECNT_5 = 5, //!< Digital Compare Edge filter edge + //!< count = 5 + EPWM_DC_EDGEFILT_EDGECNT_6 = 6, //!< Digital Compare Edge filter edge + //!< count = 6 + EPWM_DC_EDGEFILT_EDGECNT_7 = 7 //!< Digital Compare Edge filter edge + //!< count = 7 +} EPWM_DigitalCompareEdgeFilterEdgeCount; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_configureSignal() as the +//! \e signalParams parameter. +// +//***************************************************************************** +typedef struct +{ + float32_t freqInHz; //!< Desired Signal Frequency(in Hz) + float32_t dutyValA; //!< Desired ePWMxA Signal Duty + float32_t dutyValB; //!< Desired ePWMxB Signal Duty + bool invertSignalB; //!< Invert ePWMxB Signal if true + float32_t sysClkInHz; //!< SYSCLK Frequency(in Hz) + SysCtl_EPWMCLKDivider epwmClkDiv; //!< EPWM Clock Divider + EPWM_TimeBaseCountMode tbCtrMode; //!< Time Base Counter Mode + EPWM_ClockDivider tbClkDiv; //!< Time Base Counter Clock Divider + EPWM_HSClockDivider tbHSClkDiv; //!< Time Base Counter HS Clock Divider +} EPWM_SignalParams; + +//***************************************************************************** +// +// Functions APIs shared with HRPWM module +// +//***************************************************************************** + +// +// Period Control related API +// +#define EPWM_setSyncPulseSource HRPWM_setSyncPulseSource + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks ePWM base address. +//! +//! \param base specifies the ePWM module base address. +//! +//! This function determines if an ePWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool EPWM_isBaseValid(uint32_t base) +{ + return( + (base == EPWM1_BASE) || + (base == EPWM2_BASE) || + (base == EPWM3_BASE) || + (base == EPWM4_BASE) || + (base == EPWM5_BASE) || + (base == EPWM6_BASE) || + (base == EPWM7_BASE) || + (base == EPWM8_BASE) || + (base == EPWM9_BASE) || + (base == EPWM10_BASE) || + (base == EPWM11_BASE) || + (base == EPWM12_BASE) + ); +} +#endif + +// +// Time Base Sub Module related APIs +// +//***************************************************************************** +// +//! Set the time base count +//! +//! \param base is the base address of the EPWM module. +//! \param count is the time base count value. +//! +//! This function sets the 16 bit counter value of the time base counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounter(uint32_t base, uint16_t count) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBCTR register + // + HWREGH(base + EPWM_O_TBCTR) = count; +} + +//***************************************************************************** +// +//! Set count mode after phase shift sync +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the count mode. +//! +//! This function sets the time base count to count up or down after a new +//! phase value set by the EPWM_setPhaseShift(). The count direction is +//! determined by the variable mode. Valid inputs for mode are: +//! - EPWM_COUNT_MODE_UP_AFTER_SYNC - Count up after sync +//! - EPWM_COUNT_MODE_DOWN_AFTER_SYNC - Count down after sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC) + { + // + // Set PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSDIR; + } + else + { + // + // Clear PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSDIR; + } +} + +//***************************************************************************** +// +//! Set the time base clock and the high speed time base clock count pre-scaler +//! +//! \param base is the base address of the EPWM module. +//! \param prescaler is the time base count pre scale value. +//! \param highSpeedPrescaler is the high speed time base count pre scale +//! value. +//! +//! This function sets the pre scaler(divider)value for the time base clock +//! counter and the high speed time base clock counter. +//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X, +//! where X is 1,2,4,8,16, 32,64 or 128. +//! The actual numerical values for these macros represent values 0,1...7. +//! The equation for the output clock is: +//! TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler) +//! +//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half +//! SYSCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, + EPWM_HSClockDivider highSpeedPrescaler) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CLKDIV and HSPCLKDIV bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & + ~(EPWM_TBCTL_CLKDIV_M | EPWM_TBCTL_HSPCLKDIV_M)) | + (((uint16_t)prescaler << EPWM_TBCTL_CLKDIV_S) | + ((uint16_t)highSpeedPrescaler << EPWM_TBCTL_HSPCLKDIV_S))); +} + +//***************************************************************************** +// +//! Force a software sync pulse +//! +//! \param base is the base address of the EPWM module. +//! +//! This function causes a single software initiated sync pulse. Make sure the +//! appropriate mode is selected using EPWM_setupSyncOutputMode() before using +//! this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceSyncPulse(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SWFSYNC bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_SWFSYNC; +} + +//***************************************************************************** +// +//! Set up the sync out pulse event +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the sync out mode. +//! +//! This function set the sync out pulse mode. +//! Valid values for mode are: +//! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync pulse is generated by software +//! when EPWM_forceSyncPulse() +//! function is called or by EPWMxSYNCI +//! signal. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO - sync pulse is generated when +//! time base counter equals zero. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B - sync pulse is generated when +//! time base counter equals compare +//! B value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C - sync pulse is generated when +//! time base counter equals compare +//! C value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D - sync pulse is generated when +//! time base counter equals compare +//! D value. +//! - EPWM_SYNC_OUT_PULSE_DISABLED - sync pulse is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setSyncOutPulseMode(uint32_t base, EPWM_SyncOutPulseMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // No extended mode support + // + if(mode < EPWM_SYNC_OUT_PULSE_DISABLED) + { + // + // Write to SYNCOSEL bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_SYNCOSEL_M)) | + ((uint16_t)mode << EPWM_TBCTL_SYNCOSEL_S)); + } + // + // Extended modes and sync out disable mode + // + else + { + // + // Write 0x3 to SYNCOSEL to enable selection from SYNCOSELX + // + HWREGH(base + EPWM_O_TBCTL) = HWREGH(base + EPWM_O_TBCTL) | + EPWM_TBCTL_SYNCOSEL_M; + + // + // Write to SYNCOSELX bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_SYNCOSELX_M)) | + (((uint16_t)mode & 0x3U) << EPWM_TBCTL2_SYNCOSELX_S)); + } +} + +//***************************************************************************** +// +//! Set PWM period load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the PWM period load mode. +//! +//! This function sets the load mode for the PWM period. If loadMode is set to +//! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count +//! register) accesses the shadow register. If loadMode is set to +//! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the +//! register directly. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(loadMode == EPWM_PERIOD_SHADOW_LOAD) + { + // + // Clear PRDLD + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PRDLD; + } + else + { + // + // Set PRDLD + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PRDLD; + } +} + +//***************************************************************************** +// +//! Enable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of phase shift when the appropriate sync +//! event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Disable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of phase shift. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Set time base counter mode +//! +//! \param base is the base address of the EPWM module. +//! \param counterMode is the time base counter mode. +//! +//! This function sets up the time base counter mode. +//! Valid values for counterMode are: +//! - EPWM_COUNTER_MODE_UP - Up - count mode. +//! - EPWM_COUNTER_MODE_DOWN - Down - count mode. +//! - EPWM_COUNTER_MODE_UP_DOWN - Up - down - count mode. +//! - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CTRMODE bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_CTRMODE_M)) | + ((uint16_t)counterMode)); +} + +//***************************************************************************** +// +//! Set shadow to active period load on sync mode +//! +//! \param base is the base address of the EPWM module. +//! \param shadowLoadMode is the shadow to active load mode. +//! +//! This function sets up the shadow to active Period register load mode with +//! respect to a sync event. Valid values for shadowLoadMode are: +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when +//! time base counter reaches 0. +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when +//! time base counter reaches 0 and a +//! SYNC occurs. +//! - EPWM_SHADOW_LOAD_MODE_SYNC - shadow to active load occurs only +//! when a SYNC occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_selectPeriodLoadEvent(uint32_t base, + EPWM_PeriodShadowLoadMode shadowLoadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to PRDLDSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_PRDLDSYNC_M)) | + ((uint16_t)shadowLoadMode << EPWM_TBCTL2_PRDLDSYNC_S)); +} +//***************************************************************************** +// +//! Enable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Disable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) &= ~EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Start one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function propagates a one shot sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNC; +} + +//***************************************************************************** +// +//! Returns time base counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the current value of the time base counter. +//! +//! \return returns time base counter value +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterValue(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Returns TBCTR value + // + return(HWREGH(base + EPWM_O_TBCTR)); +} + +//***************************************************************************** +// +//! Return time base counter maximum status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the status of the time base max counter. +//! +//! \return Returns true if the counter has reached 0xFFFF. +//! Returns false if the counter hasn't reached 0xFFFF. +// +//***************************************************************************** +static inline bool +EPWM_getTimeBaseCounterOverflowStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if CTRMAX bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRMAX) == + EPWM_TBSTS_CTRMAX) ? true : false); +} + +//***************************************************************************** +// +//! Clear max time base counter event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the max time base counter latch event. The latch event +//! occurs when the time base counter reaches its maximum value of 0xFFFF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CTRMAX bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_CTRMAX; +} + +//***************************************************************************** +// +//! Return external sync signal status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the external sync signal status. +//! +//! \return Returns true if if an external sync signal event +//! Returns false if there is no event. +// +//***************************************************************************** +static inline bool +EPWM_getSyncStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if SYNCI bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_SYNCI) == + EPWM_TBSTS_SYNCI) ? true : false); +} + +//***************************************************************************** +// +//! Clear external sync signal event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the external sync signal latch event. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearSyncEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SYNCI bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_SYNCI; +} + +//***************************************************************************** +// +//! Return time base counter direction. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the direction of the time base counter. +//! +//! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting +//! up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is +//! counting down. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterDirection(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return CTRDIR bit + // + return(HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRDIR); +} + +//***************************************************************************** +// +//! Sets the phase shift offset counter value. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the phase shift count value. +//! +//! This function sets the 16 bit time-base counter phase of the ePWM relative +//! to the time-base that is supplying the synchronization input signal. Call +//! the EPWM_enablePhaseShiftLoad() function to enable loading of the +//! phaseCount phase shift value when a sync event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPHS bit + // + HWREG(base + EPWM_O_TBPHS) = + ((HWREG(base + EPWM_O_TBPHS) & + ~((uint32_t)EPWM_TBPHS_TBPHS_M)) | + ((uint32_t)phaseCount << EPWM_TBPHS_TBPHS_S)); +} + +//***************************************************************************** +// +//! Sets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is period count value. +//! +//! This function sets the period of the PWM count. The value of periodCount is +//! the value written to the register. User should map the desired period or +//! frequency of the waveform into the correct periodCount. +//! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate +//! parameter to set the load mode of the Period count. periodCount has a +//! maximum valid value of 0xFFFF +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPRD bit + // + HWREGH(base + EPWM_O_TBPRD) = periodCount; +} + +//***************************************************************************** +// +//! Gets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the period of the PWM count. +//! +//! \return The period count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read from TBPRD bit + // + return(HWREGH(base + EPWM_O_TBPRD)); +} + +//***************************************************************************** +// +//! Sets the EPWM links. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmLink is the ePWM instance to link with. +//! \param linkComp is the ePWM component to link. +//! +//! This function links the component defined in linkComp in the current ePWM +//! instance with the linkComp component of the ePWM instance defined by +//! epwmLink. A change (a write) in the value of linkComp component of epwmLink +//! instance, causes a change in the current ePWM linkComp component. +//! For example if the current ePWM is ePWM3 and the values of epwmLink and +//! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively, +//! then a write to COMPC register in ePWM1, will result in a simultaneous +//! write to COMPC register in ePWM3. +//! Valid values for epwmLink are: +//! - EPWM_LINK_WITH_EPWM_1 - link current ePWM with ePWM1 +//! - EPWM_LINK_WITH_EPWM_2 - link current ePWM with ePWM2 +//! - EPWM_LINK_WITH_EPWM_3 - link current ePWM with ePWM3 +//! - EPWM_LINK_WITH_EPWM_4 - link current ePWM with ePWM4 +//! - EPWM_LINK_WITH_EPWM_5 - link current ePWM with ePWM5 +//! - EPWM_LINK_WITH_EPWM_6 - link current ePWM with ePWM6 +//! - EPWM_LINK_WITH_EPWM_7 - link current ePWM with ePWM7 +//! - EPWM_LINK_WITH_EPWM_8 - link current ePWM with ePWM8 +//! - EPWM_LINK_WITH_EPWM_9 - link current ePWM with ePWM9 +//! - EPWM_LINK_WITH_EPWM_10 - link current ePWM with ePWM10 +//! - EPWM_LINK_WITH_EPWM_11 - link current ePWM with ePWM11 +//! - EPWM_LINK_WITH_EPWM_12 - link current ePWM with ePWM12 +//! +//! Valid values for linkComp are: +//! - EPWM_LINK_TBPRD - link TBPRD:TBPRDHR registers +//! - EPWM_LINK_COMP_A - link COMPA registers +//! - EPWM_LINK_COMP_B - link COMPB registers +//! - EPWM_LINK_COMP_C - link COMPC registers +//! - EPWM_LINK_COMP_D - link COMPD registers +//! - EPWM_LINK_GLDCTL2 - link GLDCTL2 registers +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, + EPWM_LinkComponent linkComp) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + uint32_t registerOffset; + registerOffset = base + EPWM_O_XLINK; + + // + // Configure EPWM links + // + HWREG(registerOffset) = + ((HWREG(registerOffset) & ~((uint32_t)EPWM_XLINK_TBPRDLINK_M << (uint32_t)linkComp)) | + ((uint32_t)epwmLink << (uint32_t)linkComp)); +} + + +//***************************************************************************** +// +//! Sets up the Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets up the counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! - loadMode +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule, + EPWM_CounterCompareLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t loadModeOffset; + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + syncModeOffset = 10U; + loadModeOffset = 0U; + shadowModeOffset = 4U; + } + else + { + syncModeOffset = 12U; + loadModeOffset = 2U; + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(registerOffset) = ((HWREGH(registerOffset) & + ~((0x3U << syncModeOffset) | // Clear sync mode + (0x3U << loadModeOffset) | // Clear load mode + (0x1U << shadowModeOffset))) | // shadow mode + ((((uint16_t)loadMode >> 2U) << syncModeOffset) | + (((uint16_t)loadMode & 0x3U) << loadModeOffset))); +} + +//***************************************************************************** +// +//! Disable Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! +//! This function disables counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + shadowModeOffset = 4U; + } + else + { + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Disable shadow load mode. + // + HWREGH(registerOffset) = (HWREGH(registerOffset) | + (0x1U << shadowModeOffset)); +} + +//***************************************************************************** +// +//! Set counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! \param compCount is the counter compare count value. +//! +//! This function sets the counter compare value for counter compare registers. +//! The maximum value for compCount is 0xFFFF. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, + uint16_t compCount) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Write to the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Write to COMPA or COMPB bits + // + HWREGH(base + registerOffset + 0x1U) = compCount; + } + else + { + // + // Write to COMPC or COMPD bits + // + HWREGH(base + registerOffset) = compCount; + } +} + +//***************************************************************************** +// +//! Get counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function gets the counter compare value for counter compare registers. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return The counter compare count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule) +{ + uint32_t registerOffset; + uint16_t compCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Read from the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Read COMPA or COMPB bits + // + compCount = (uint16_t)((HWREG(base + registerOffset) & + 0xFFFF0000UL) >> 16U); + } + else + { + // + // Read COMPC or COMPD bits + // + compCount = HWREGH(base + registerOffset); + } + return(compCount); +} + +//***************************************************************************** +// +//! Return the counter compare shadow register full status. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function returns the counter Compare shadow register full status flag. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return Returns true if the shadow register is full. +//! Returns false if the shadow register is not full. +// +//***************************************************************************** +static inline bool +EPWM_getCounterCompareShadowStatus(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Check the validity of input. + // COMPA and COMPB are valid input arguments. + // + ASSERT((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)); + + // + // Read the value of SHDWAFULL or SHDWBFULL bit + // + return((((HWREG(base + EPWM_O_CMPCTL) >> + ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) & + 0x1U) == 0x1U) ? true:false); +} + +// +// Action Qualifier module related APIs +// +//***************************************************************************** +// +//! Sets the Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! - loadMode +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter +//! equals zero +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter +//! equals period +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when +//! counter equals zero or period +//! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule, + EPWM_ActionQualifierLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + syncModeOffset = 8U + (uint16_t)aqModule; + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(base + EPWM_O_AQCTL) = ((HWREGH(base + EPWM_O_AQCTL) & + (~((0x3U << (uint16_t)aqModule) | + (0x3U << (uint16_t)syncModeOffset))) | + (0x1U << shadowModeOffset)) | + ((((uint16_t)loadMode >> 2U) << + syncModeOffset) | (((uint16_t)loadMode & + 0x3U) << (uint16_t)aqModule))); +} + +//***************************************************************************** +// +//! Disable Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! +//! This function disables the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule) +{ + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Disable shadow load mode. Action qualifier is loaded on + // immediate mode only. + // + HWREGH(base + EPWM_O_AQCTL) &= ~(1U << shadowModeOffset); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T1 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T1. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT1TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T1 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T1SEL_M)) | + ((uint16_t)trigger)); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T2 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T2. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT2TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T2 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T2SEL_M)) | + ((uint16_t)trigger << EPWM_AQTSRCSEL_T2SEL_S)); +} + +//***************************************************************************** +// +//! Set up Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! \param event is the event that causes a change in output. +//! +//! This function sets up the Action Qualifier output on ePWM A or ePWMB, +//! depending on the value of epwmOutput, to a value specified by outPut based +//! on the input events - specified by event. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! - event +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals +//! zero +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals +//! period +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals +//! COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down +//! equals COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals +//! COMPB +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down +//! equals COMPB +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output, + EPWM_ActionQualifierOutputEvent event) +{ + uint32_t registerOffset; + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // If the event occurs on T1 or T2 events + // + if(((uint16_t)event & 0x1U) == 1U) + { + // + // Write to T1U,T1D,T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = + ((HWREGH(base + registerTOffset) & ~(3U << ((uint16_t)event - 1U))) | + ((uint16_t)output << ((uint16_t)event - 1U))); + } + else + { + // + // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~(3U << (uint16_t)event)) | + ((uint16_t)output << (uint16_t)event)); + } +} + +//***************************************************************************** +// +//! Set up Action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Action Qualifier output on ePWMA or ePWMB, +//! depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different time base counter scenarios +//! should be OR'd together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! - action +//! - When time base counter equals zero +//! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero +//! and toggle the output pins +//! - When time base counter equals period +//! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period +//! and toggle the output pins +//! - When time base counter equals CMPA during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPA during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPB during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals +//! COMPB and toggle output pins +//! - When time base counter equals CMPB during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals +//! COMPB and toggle output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each time base +//! counter scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + + // + // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Set up Additional action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Additional Action Qualifier output on ePWMA or +//! ePWMB depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different event scenarios should be OR'd +//! together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - action +//! - When T1 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 - T1 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T1 - T1 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T1 - T1 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T1 - T1 event on count up +//! and toggle the output pins +//! - When T1 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T1 - T1 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T1 - T1 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 - T1 event on count down +//! and toggle the output pins +//! - When T2 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up +//! and toggle the output pins +//! - When T2 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down +//! and toggle the output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each event +//! scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // Write to T1U, T1D, T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Sets up Action qualifier continuous software load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the mode for shadow to active load mode. +//! +//! This function sets up the AQCFRSC register load mode for continuous +//! software force reload mode. The software force actions are determined by +//! the EPWM_setActionQualifierContSWForceAction() function. +//! Valid values for mode are: +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter +//! equals zero +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter +//! equals period +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter +//! equals zero or period +//! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, + EPWM_ActionQualifierContForce mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action qualifier software action reload mode. + // Write to RLDCSF bit + // + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_RLDCSF_M) | + ((uint16_t)mode << EPWM_AQSFRC_RLDCSF_S)); +} + +//***************************************************************************** +// +//! Triggers a continuous software forced event. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function triggers a continuous software forced Action Qualifier output +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for the parameters are: +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_SW_DISABLED - Software forcing disabled. +//! - EPWM_AQ_SW_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_SW_OUTPUT_HIGH - Set output pins to High +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierSWOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a continuous software forced output + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFB_M) | + ((uint16_t)output << EPWM_AQCSFRC_CSFB_S)) ; + } +} + +//***************************************************************************** +// +//! Set up one time software forced Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function sets up the one time software forced Action Qualifier output +//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value +//! specified by outPut. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the one time software forced action + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFB_M) | + ((uint16_t)output << EPWM_AQSFRC_ACTSFB_S)); + } +} + +//***************************************************************************** +// +//! Triggers a one time software forced event on Action qualifier +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! +//! This function triggers a one time software forced Action Qualifier event +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for epwmOutput are: +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a software forced event + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFA; + } + else + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFB; + } +} + +// +// Dead Band Module related APIs +// +//***************************************************************************** +// +//! Sets Dead Band signal output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param output is the ePWM Dead Band output. +//! \param enableSwapMode is the output swap mode. +//! +//! This function sets up the output signal swap mode. For example if the +//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then +//! the ePWM A output gets its signal from the ePWM B signal path. Valid values +//! for the input variables are: +//! - output +//! - EPWM_DB_OUTPUT_A - ePWM output A +//! - EPWM_DB_OUTPUT_B - ePWM output B +//! - enableSwapMode +//! - true - the output is swapped +//! - false - the output and the signal path are the same. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, + bool enableSwapMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)output + EPWM_DBCTL_OUTSWAP_S); + + if(enableSwapMode) + { + // + // Set the appropriate outswap bit to swap output + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band signal output mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param enableDelayMode is the dead band delay mode. +//! +//! This function sets up the dead band delay mode. The delayMode variable +//! determines if the applied delay is Rising Edge or Falling Edge. The +//! enableDelayMode determines if a dead band delay should be applied. +//! Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - enableDelayMode +//! - true - Falling edge or Rising edge delay is applied. +//! - false - Dead Band delay is bypassed. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, + bool enableDelayMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)delayMode + EPWM_DBCTL_OUT_MODE_S); + + if(enableDelayMode) + { + // + // Set the appropriate outmode bit to enable Dead Band delay + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~ mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band delay polarity. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param polarity is the polarity of the delayed signal. +//! +//! This function sets up the polarity as determined by the variable polarity +//! of the Falling Edge or Rising Edge delay depending on the value of +//! delayMode. Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - polarity +//! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted. +//! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayPolarity(uint32_t base, + EPWM_DeadBandDelayMode delayMode, + EPWM_DeadBandPolarity polarity) +{ + uint16_t shift; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shift = (((uint16_t)delayMode ^ 0x1U) + EPWM_DBCTL_POLSEL_S); + + // + // Set the appropriate polsel bits for dead band polarity + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~ (1U << shift)) | + ((uint16_t)polarity << shift)); +} + +//***************************************************************************** +// +//! Sets Rising Edge Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB( Valid for both Falling +//! Edge and Rising Edge) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB)); + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S))) | + (input << EPWM_DBCTL_IN_MODE_S)); +} + +//***************************************************************************** +// +//! Sets Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising +//! Edge delay. +//! (Valid only for Falling Edge delay) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB) || + (input == EPWM_DB_INPUT_DB_RED)); + + if(input == EPWM_DB_INPUT_DB_RED) + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) |= EPWM_DBCTL_DEDB_MODE; + } + else + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) &= ~EPWM_DBCTL_DEDB_MODE; + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S + 1U))) | + (input << (EPWM_DBCTL_IN_MODE_S + 1U))); + } +} + +//***************************************************************************** +// +//! Set the Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Dead Band control register shadow +//! load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandControlShadowLoadMode(uint32_t base, + EPWM_DeadBandControlLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode and setup the load event + // + HWREGH(base + EPWM_O_DBCTL2) = + ((HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_LOADDBCTLMODE_M) | + (EPWM_DBCTL2_SHDWDBCTLMODE | (uint16_t)loadMode)); +} + +//***************************************************************************** +// +//! Disable Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Dead Band control register shadow +//! load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDeadBandControlShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow load mode. Only immediate load mode only. + // + HWREGH(base + EPWM_O_DBCTL2) = + (HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_SHDWDBCTLMODE); +} + +//***************************************************************************** +// +//! Set the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function sets the Rising Edge Delay register shadow load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_RisingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Set-up the load mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADREDMODE_M) | + ((uint16_t)EPWM_DBCTL_SHDWDBREDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADREDMODE_S))); + +} + +//***************************************************************************** +// +//! Disable the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Rising Edge Delay register shadow load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBREDMODE); + +} + +//***************************************************************************** +// +//! Set the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function enables and sets the Falling Edge Delay register shadow load +//! mode. Valid values for the \e loadMode parameters are: +//! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_FallingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Setup the load mode. + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADFEDMODE_M) | + (EPWM_DBCTL_SHDWDBFEDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADFEDMODE_S))); + +} + +//***************************************************************************** +// +//! Disables the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Falling Edge Delay register shadow load mode. +//! Valid values for the parameters are: +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBFEDMODE); +} + +//***************************************************************************** +// +//! Sets Dead Band Counter clock rate. +//! +//! \param base is the base address of the EPWM module. +//! \param clockMode is the Dead Band counter clock mode. +//! +//! This function sets up the Dead Band counter clock rate with respect to +//! TBCLK (ePWM time base counter). +//! Valid values for clockMode are: +//! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK +//! (ePWM Time Base Counter) rate. +//! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK +//! (twice ePWM Time Base Counter)rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandCounterClock(uint32_t base, + EPWM_DeadBandClockMode clockMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DB clock mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_HALFCYCLE) | + ((uint16_t)clockMode << 15U)); +} + +//***************************************************************************** +// +//! Set ePWM RED count +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the RED(Rising Edge Delay) count. +//! +//! This function sets the RED (Rising Edge Delay) count value. +//! The value of redCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(redCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBRED) = redCount; +} + +//***************************************************************************** +// +//! Set ePWM FED count +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the FED(Falling Edge Delay) count. +//! +//! This function sets the FED (Falling Edge Delay) count value. +//! The value of fedCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(fedCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBFED) = fedCount; +} + +// +// Chopper module related APIs +// +//***************************************************************************** +// +//! Enable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CHPEN bit. Enable Chopper + // + HWREGH(base + EPWM_O_PCCTL) |= EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Disable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear CHPEN bit. Disable Chopper + // + HWREGH(base + EPWM_O_PCCTL) &= ~EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Set chopper duty cycle. +//! +//! \param base is the base address of the EPWM module. +//! \param dutyCycleCount is the chopping clock duty cycle count. +//! +//! This function sets the chopping clock duty cycle. The value of +//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted +//! to the actual chopper duty cycle value base on the following equation: +//! chopper duty cycle = (dutyCycleCount + 1) / 8 +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(dutyCycleCount < 7U); + + // + // Set the chopper duty cycle + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & ~EPWM_PCCTL_CHPDUTY_M) | + (dutyCycleCount << EPWM_PCCTL_CHPDUTY_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param freqDiv is the chopping clock frequency divider. +//! +//! This function sets the scaler for the chopping clock frequency. The value +//! of freqDiv should be less than 8. The chopping clock frequency is altered +//! based on the following equation. +//! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(freqDiv < 8U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_CHPFREQ_M) | + (freqDiv << EPWM_PCCTL_CHPFREQ_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param firstPulseWidth is the width of the first pulse. +//! +//! This function sets the first pulse width of chopper output waveform. The +//! value of firstPulseWidth should be less than 0x10. The value of the first +//! pulse width in seconds is given using the following equation: +//! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(firstPulseWidth < 16U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_OSHTWTH_M) | + (firstPulseWidth << EPWM_PCCTL_OSHTWTH_S)); +} + +// +// Trip Zone module related APIs +// +//***************************************************************************** +// +//! Enables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function enables the Trip Zone signals specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) |= tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Disables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function disables the Trip Zone signal specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) &= ~tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Set Digital compare conditions that cause Trip Zone event. +//! +//! \param base is the base address of the EPWM module. +//! \param dcType is the Digital compare output type. +//! \param dcEvent is the Digital Compare output event. +//! +//! This function sets up the Digital Compare output Trip Zone event sources. +//! The dcType variable specifies the event source to be whether Digital +//! Compare output A or Digital Compare output B. The dcEvent parameter +//! specifies the event that causes Trip Zone. +//! Valid values for the parameters are: +//! - dcType +//! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A +//! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A +//! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B +//! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B +//! - dcEvent +//! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled +//! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low +//! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high +//! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low +//! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high +//! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high +//! DCxH low +//! +//! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, + EPWM_TripZoneDigitalCompareOutput dcType, + EPWM_TripZoneDigitalCompareOutputEvent dcEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set Digital Compare Events conditions that cause a Digital Compare trip + // + EALLOW; + HWREGH(base + EPWM_O_TZDCSEL) = + ((HWREGH(base + EPWM_O_TZDCSEL) & ~(0x7U << (uint16_t)dcType)) | + ((uint16_t)dcEvent << (uint16_t)dcType)); + EDIS; +} + +//***************************************************************************** +// +//! Enable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the advanced actions of the Trip Zone events. The +//! advanced features combine the trip zone events with the direction of the +//! counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Advanced feature. Set ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Disable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the advanced actions of the Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Advanced feature. clear ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) &= ~EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzEvent is the Trip Zone event type. +//! \param tzAction is the Trip zone Action. +//! +//! This function sets the Trip Zone Action to be taken when a Trip Zone event +//! occurs. +//! Valid values for the parameters are: +//! - tzEvent +//! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2) +//! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1) +//! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1 +//! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1 +//! - tzAction +//! - EPWM_TZ_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ACTION_HIGH - high output +//! - EPWM_TZ_ACTION_LOW - low low +//! - EPWM_TZ_ACTION_DISABLE - disable action +//! +//! \note Disable the advanced Trip Zone event using +//! EPWM_disableTripZoneAdvAction() before calling this function. +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzEvent parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, + EPWM_TripZoneAction tzAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL) = + ((HWREGH(base + EPWM_O_TZCTL) & ~(0x3U << (uint16_t)tzEvent)) | + ((uint16_t)tzAction << (uint16_t)tzEvent)) ; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvEvent is the Trip Zone event type. +//! \param tzAdvAction is the Trip zone Action. +//! +//! This function sets the Advanced Trip Zone Action to be taken when an +//! advanced Trip Zone event occurs. +//! +//! Valid values for the parameters are: +//! - tzAdvEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting up +//! - tzAdvAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzAdvEvent parameter. +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, + EPWM_TripZoneAdvancedAction tzAdvAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) = + ((HWREGH(base + EPWM_O_TZCTL2) & ~(0x7U << (uint16_t)tzAdvEvent)) | + ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMA. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCA) = + ((HWREGH(base + EPWM_O_TZCTLDCA) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMB. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCB) = + ((HWREGH(base + EPWM_O_TZCTLDCB) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function enables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Enable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) |= tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Disable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function disables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Disable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) &= ~tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Gets the Trip Zone status flag +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the Trip Zone status flag. +//! +//! \return The function returns the following or the bitwise OR value +//! of the following values. +//! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated +//! due to the following TZ events. +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag +// +//*************************************************************************** +static inline uint16_t +EPWM_getTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZFLG) & 0x7FU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone Cycle by Cycle flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific Cycle by Cycle Trip Zone flag +//! status. +//! +//! \return The function returns the following values. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare +//! event B2 +// +//*************************************************************************** +static inline uint16_t +EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Cycle By Cycle Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZCBCFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone One Shot flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific One Shot Trip Zone flag status. +//! +//! \return The function returns the bitwise OR of the following flags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital +//! compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital +//! compare event B1 +// +//*************************************************************************** +static inline uint16_t +EPWM_getOneShotTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the One Shot Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZOSTFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Set the Trip Zone CBC pulse clear event. +//! +//! \param base is the base address of the EPWM module. +//! \param clearEvent is the CBC trip zone clear event. +//! +//! This function set the event which automatically clears the +//! CBC (Cycle by Cycle) latch. +//! Valid values for clearEvent are: +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter +//! equals zero +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter +//! equals period +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter +//! equals zero or period +//! +//! \return None. +// +//************************************************************************** +static inline void +EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, + EPWM_CycleByCycleTripZoneClearMode clearEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Cycle by Cycle Trip Latch mode + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) = + ((HWREGH(base + EPWM_O_TZCLR) & ~EPWM_TZCLR_CBCPULSE_M) | + ((uint16_t)clearEvent << EPWM_TZCLR_CBCPULSE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Clear Trip Zone flag +//! +//! \param base is the base address of the EPWM module. +//! \param tzFlags is the Trip Zone flags. +//! +//! This function clears the Trip Zone flags +//! Valid values for tzFlags are: +//! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag +//! +//! \b note: A bitwise OR of the valid values can be passed as the tzFlags +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzFlags <= 0x80U); + + // + // Clear Trip zone event flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) |= tzFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone Cycle by Cycle flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzCBCFlags is the CBC flag to be cleared. +//! +//! This function clears the specific Cycle by Cycle Trip Zone flag. +//! The following are valid values for tzCBCFlags. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare +//! event B2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzCBCFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCBCCLR) |= tzCBCFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone One Shot flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzOSTFlags is the OST flags to be cleared. +//! +//! This function clears the specific One Shot (OST) Trip Zone flag. +//! The following are valid values for tzOSTFlags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzOSTFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZOSTCLR) |= tzOSTFlags; + EDIS; +} + +//***************************************************************************** +// +//! Force Trip Zone events. +//! +//! \param base is the base address of the EPWM module. +//! \param tzForceEvent is the forced Trip Zone event. +//! +//! This function forces a Trip Zone event. +//! Valid values for tzForceEvent are: +//! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event +//! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event +//! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzForceEvent & 0xFF81U)== 0U); + + // + // Force a Trip Zone event + // + EALLOW; + HWREGH(base + EPWM_O_TZFRC) |= tzForceEvent; + EDIS; +} + +// +// Event Trigger related APIs +// +//***************************************************************************** +// +//! Enable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! disable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt source. +//! +//! \param base is the base address of the EPWM module. +//! \param interruptSource is the ePWM interrupt source. +//! +//! This function sets the ePWM interrupt source. +//! Valid values for interruptSource are: +//! - EPWM_INT_TBCTR_DISABLED - Time-base counter is disabled +//! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is incrementing +//! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource) +{ + uint16_t intSource; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(((interruptSource > 0U) && (interruptSource < 9U)) || + (interruptSource == 10U) || (interruptSource == 12U) || + (interruptSource == 14U)); + + if((interruptSource == EPWM_INT_TBCTR_U_CMPC) || + (interruptSource == EPWM_INT_TBCTR_U_CMPD) || + (interruptSource == EPWM_INT_TBCTR_D_CMPC) || + (interruptSource == EPWM_INT_TBCTR_D_CMPD)) + { + // + // Shift the interrupt source by 1 + // + intSource = interruptSource >> 1U; + + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTSELCMP; + } + else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) || + (interruptSource == EPWM_INT_TBCTR_U_CMPB) || + (interruptSource == EPWM_INT_TBCTR_D_CMPA) || + (interruptSource == EPWM_INT_TBCTR_D_CMPB)) + { + intSource = interruptSource; + + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTSELCMP; + } + else + { + intSource = interruptSource; + } + + // + // Set the interrupt source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_INTSEL_M) | intSource); +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the event count for interrupt scale +//! +//! This function sets the interrupt event count that determines the number of +//! events that have to occur before an interrupt is issued. +//! Maximum value for eventCount is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Enable advanced feature of interrupt every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_INTPSSEL; + HWREGH(base + EPWM_O_ETINTPS) = + ((HWREGH(base + EPWM_O_ETINTPS) & ~EPWM_ETINTPS_INTPRD2_M) | + eventCount); +} + +//***************************************************************************** +// +//! Return the interrupt status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt status. +//! \b Note This function doesn't return the Trip Zone status. +//! +//! \return Returns true if ePWM interrupt was generated. +//! Returns false if no interrupt was generated +// +//***************************************************************************** +static inline bool +EPWM_getEventTriggerInterruptStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return INT bit of ETFLG register + // + return(((HWREGH(base + EPWM_O_ETFLG) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear interrupt flag. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the ePWM interrupt flag. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearEventTriggerInterruptFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear INT bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= EPWM_ETCLR_INT; +} + +//***************************************************************************** +// +//! Enable Pre-interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt counter to be pre-interrupt loaded +//! with a count value. +//! +//! \note This is valid only for advanced/expanded interrupt mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Disable interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt counter from being loaded with +//! pre-interrupt count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= ~EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Force a software pre interrupt event counter load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces the ePWM interrupt counter to be loaded with the +//! contents set by EPWM_setPreInterruptEventCount(). +//! +//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is +//! is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITFRC; +} + +//***************************************************************************** +// +//! Set interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM interrupt count. eventCount is the value of the +//! pre-interrupt value that is to be loaded. The maximum value of eventCount +//! is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the Pre-interrupt event count + // + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_INTINIT_M) | + (uint16_t)(eventCount & 0xFU)); +} + +//***************************************************************************** +// +//! Get the interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt event count. +//! +//! \return The interrupt event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getInterruptEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the interrupt event count + // + return(((HWREGH(base + EPWM_O_ETINTPS) & EPWM_ETINTPS_INTCNT2_M) >> + EPWM_ETINTPS_INTCNT2_S)); +} + +//***************************************************************************** +// +//! Force ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces an ePWM interrupt. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceEventTriggerInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set INT bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= EPWM_ETFRC_INT; +} + +// +// ADC SOC configuration related APIs +// +//***************************************************************************** +// +//! Enable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM module to trigger an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Disable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM module from triggering an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC source. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param socSource is the SOC source. +//! +//! This function sets the ePWM ADC SOC source. +//! Valid values for socSource are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - socSource +//! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1 +//! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is incrementing +//! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerSource(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + EPWM_ADCStartOfConversionSource socSource) +{ + uint16_t source; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + source = (uint16_t)socSource >> 1U; + } + else + { + source = (uint16_t)socSource; + } + + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the SOC source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCASEL_M) | + (source << EPWM_ETSEL_SOCASEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCASELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCASELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } + else + { + // + // Enable the comparator selection + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCBSEL_M) | + (source << EPWM_ETSEL_SOCBSEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBSELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBSELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param preScaleCount is the event count number. +//! +//! This function sets the SOC event count that determines the number of +//! events that have to occur before an SOC is issued. +//! Valid values for the parameters are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - preScaleCount +//! - [1 - 15] - Generate SOC pulse every preScaleCount +//! up to 15 events. +//! +//! \note A preScaleCount value of 0 disables the prescale. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventPrescale(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t preScaleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(preScaleCount < 16U); + + // + // Enable advanced feature of SOC every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_SOCPSSEL; + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the count for SOC A + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCAPRD2_M) | + preScaleCount); + } + else + { + // + // Set the count for SOC B + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCBPRD2_M) | + (preScaleCount << EPWM_ETSOCPS_SOCBPRD2_S)); + } +} + +//***************************************************************************** +// +//! Return the SOC event status. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC status. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return Returns true if the selected adcSOCType SOC was generated. +//! Returns false if the selected adcSOCType SOC was not generated. +// +//***************************************************************************** +static inline bool +EPWM_getADCTriggerFlagStatus(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC A/ B status + // + return((((HWREGH(base + EPWM_O_ETFLG) >> + ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear SOC flag. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function clears the ePWM SOC flag. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearADCTriggerFlag(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear SOC A/B bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +//***************************************************************************** +// +//! Enable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM SOC event counter which is set by the +//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before +//! an SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 14U); +} + +//***************************************************************************** +// +//! Disable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM SOC event counter from being loaded before +//! an SOC event (only an SOC event causes an increment of the counter value). +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= + ~(1U << ((uint16_t)adcSOCType + 14U)); +} + +//***************************************************************************** +// +//! Force a software pre SOC event counter load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type +//! +//! This function forces the ePWM SOC counter to be loaded with the +//! contents set by EPWM_setPreADCStartOfConversionEventCount(). +//! +//! \note make sure the EPWM_enableADCTriggerEventCountInit() +//! function is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 11U); +} + +//***************************************************************************** +// +//! Set ADC Trigger count values. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM ADC Trigger count values. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! The eventCount has a maximum value of 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventCountInitValue(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the ADC Trigger event count + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCAINIT_M) | + (uint16_t)(eventCount << EPWM_ETCNTINIT_SOCAINIT_S)); + } + else + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCBINIT_M) | + (eventCount << EPWM_ETCNTINIT_SOCBINIT_S)); + } +} + +//***************************************************************************** +// +//! Get the SOC event count. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC event count. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return The SOC event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getADCTriggerEventCount(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + uint16_t eventCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC event count + // + if(adcSOCType == EPWM_SOC_A) + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCACNT2_S) & 0xFU; + } + else + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCBCNT2_S) & 0xFU; + } + return(eventCount); +} + +//***************************************************************************** +// +//! Force SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function forces an ePWM SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SOC A/B bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +// +// Digital Compare module related APIs +// +//***************************************************************************** +// +//! Set the DC trip input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripSource is the tripSource. +//! \param dcType is the Digital Compare type. +//! +//! This function sets the trip input to the Digital Compare (DC). For a given +//! dcType the function sets the tripSource to be the input to the DC. +//! Valid values for the parameter are: +//! - tripSource +//! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13 +//! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input +//! is enabled by the following function +//! EPWM_enableDigitalCompareTripCombinationInput() +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_selectDigitalCompareTripInput(uint32_t base, + EPWM_DigitalCompareTripInput tripSource, + EPWM_DigitalCompareType dcType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + EPWM_O_DCTRIPSEL) = + ((HWREGH(base + EPWM_O_DCTRIPSEL) & ~(0xFU << ((uint16_t)dcType << 2U))) | + ((uint16_t)tripSource << ((uint16_t)dcType << 2U))); + EDIS; +} + +// +// DCFILT +// +//***************************************************************************** +// +//! Enable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Disable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Window inverse mode. This will +//! invert the blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Window inverse mode. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare filter blanking pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param blankingPulse is Pulse that starts blanking window. +//! +//! This function sets the input pulse that starts the Digital Compare blanking +//! window. +//! Valid values for blankingPulse are: +//! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero +//! or period. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareBlankingEvent(uint32_t base, + EPWM_DigitalCompareBlankingPulse blankingPulse) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC blanking event + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_PULSESEL_M) | + ((uint16_t)((uint32_t)blankingPulse << EPWM_DCFCTL_PULSESEL_S))); + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter input. +//! +//! \param base is the base address of the EPWM module. +//! \param filterInput is Digital Compare signal source. +//! +//! This function sets the signal input source that will be filtered by the +//! Digital Compare module. +//! Valid values for filterInput are: +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2 +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareFilterInput(uint32_t base, + EPWM_DigitalCompareFilterInput filterInput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the signal source that will be filtered + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_SRCSEL_M) | + ((uint16_t)filterInput)); + EDIS; +} + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Enable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Edge filter to generate event +//! after configured number of edges. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Edge filter. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Mode. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeMode is Digital Compare Edge filter mode. +//! +//! This function sets the Digital Compare Event filter mode. Valid values +//! for edgeMode are: +//! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge +//! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge +//! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, + EPWM_DigitalCompareEdgeFilterMode edgeMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter mode + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + (HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_EDGEMODE_M) | + ((uint16_t)edgeMode << EPWM_DCFCTL_EDGEMODE_S); + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeCount is Digital Compare event filter count +//! +//! This function sets the Digital Compare Event filter Edge Count to generate +//! events. Valid values for edgeCount can be: +//! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event +//! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter edge count + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = (HWREGH(base + EPWM_O_DCFCTL) & + ~EPWM_DCFCTL_EDGECOUNT_M) | + (edgeCount << EPWM_DCFCTL_EDGECOUNT_S); + EDIS; +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the configured Digital Compare Edge filter edge +//! count required to generate events. It can return values from 0-7. +//! +//! \return Returns the configured DigitalCompare Edge filter edge count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return configured DC edge filter edge count + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGECOUNT_M) >> + EPWM_DCFCTL_EDGECOUNT_S); +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge filter captured edge count status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the count of edges captured by Digital Compare Edge +//! filter. It can return values from 0-7. +//! +//! \return Returns the count of captured edges +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return captured edge count by DC Edge filter + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGESTATUS_M) >> + EPWM_DCFCTL_EDGESTATUS_S); +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window offset +//! +//! \param base is the base address of the EPWM module. +//! \param windowOffsetCount is blanking window offset length. +//! +//! This function sets the offset between window start pulse and blanking +//! window in TBCLK count. +//! The function take a 16bit count value for the offset value. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window offset in TBCLK counts + // + HWREGH(base + EPWM_O_DCFOFFSET) = windowOffsetCount; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window length +//! +//! \param base is the base address of the EPWM module. +//! \param windowLengthCount is blanking window length. +//! +//! This function sets up the Digital Compare filter blanking window length in +//! TBCLK count.The function takes a 16bit count value for the window length. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window length in TBCLK counts + // + HWREGH(base + EPWM_O_DCFWINDOW) = windowLengthCount; +} + +//***************************************************************************** +// +//! Return DC filter blanking window offset count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window offset count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Offset count + // + return(HWREGH(base + EPWM_O_DCFOFFSETCNT)); +} + +//***************************************************************************** +// +//! Return DC filter blanking window length count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window length count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Length count + // + return(HWREGH(base + EPWM_O_DCFWINDOWCNT)); +} + +//***************************************************************************** +// +//! Set up the Digital Compare Event source. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param dcEventSource is the - Digital Compare Event source. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - dcEventSource +//! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered +//! \note The signal source for this option is DCxEVTy, where the +//! value of x is dependent on dcModule and the value of y is +//! dependent on dcEvent. Possible signal sources are DCAEVT1, +//! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both +//! dcModule and dcEvent. +//! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered +//! The signal source for this option is DCxEVTy. +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSource(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareEventSource dcEventSource) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event 1 source source + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SRCSEL) | + (uint16_t)dcEventSource); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2SRCSEL) | + ((uint16_t)dcEventSource << 8U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare input sync mode. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param syncMode is the Digital Compare Event sync mode. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - syncMode +//! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with +//! TBCLK +//! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with +//! TBCLK +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSyncMode(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareSyncMode syncMode) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event sync mode + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1FRCSYNCSEL) | + ((uint16_t)syncMode << 1U)); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2FRCSYNCSEL) | + ((uint16_t)syncMode << 9U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate sync out pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate sync out +//! pulse +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating synch +//! out pulse. +//! The following are valid values for the \e dcModule parameters. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +// +// DC capture mode +// +//***************************************************************************** +// +//! Enables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disable the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Set the Time Base Counter Capture mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableShadowMode is the shadow read mode flag. +//! +//! This function sets the mode the Time Base Counter value is read from. If +//! enableShadowMode is true, CPU reads of the DCCAP register will return the +//! shadow register contents.If enableShadowMode is false, CPU reads of the +//! DCCAP register will return the active register contents. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(enableShadowMode) + { + // + // Enable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_SHDWMODE; + } + else + { + // + // Disable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_SHDWMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Capture event status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC capture event status. +//! +//! \return Returns true if a DC capture event has occurs. +//! Returns false if no DC Capture event has occurred. +//! +//! \return None. +// +//***************************************************************************** +static inline bool +EPWM_getDigitalCompareCaptureStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC compare status + // + return((HWREGH(base + EPWM_O_DCCAPCTL) & EPWM_DCCAPCTL_CAPSTS) == + EPWM_DCCAPCTL_CAPSTS); +} + +//***************************************************************************** +// +//! Clears DC capture latched status flag +//! +//! \param base is the base address of the EPWM module. +//! This function is used to clear the CAPSTS (set) condition. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_clearDigitalCompareCaptureStatusFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear digital compare capture status flag + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPCLR; + EDIS; +} + +//***************************************************************************** +// +//! Configures DC capture operating mode +//! +//! \param base is the base address of the EPWM module. +//! \param disableClearMode is the clear mode bit. +//! +//! This function is used to configure the DC capture operating mode. If +//! \e disableClearMode is false, the TBCNT value is captured in active register +//! on occurance of DCEVTFILT event. The trip events are ignored until next +//! PRD or ZRO event re-triggers the capture mechanism. +//! If \e disableClearMode is true, the TBCNT value is captured, CAPSTS flag is +//! set and further trips are ignored until CAPSTS bit is cleared. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_configureDigitalCompareCounterCaptureMode(uint32_t base, + bool disableClearMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(disableClearMode) + { + // + // Disable DC counter auto-clear on PULSESEL event + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPMODE; + } + else + { + // + // Enable DC counter clear on PULSESEL events + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Time Base Counter capture value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC Time Base Counter capture value. The value +//! read is determined by the mode as set in the +//! EPWM_setTimeBaseCounterReadMode() function. +//! +//! \return Returns the DC Time Base Counter Capture count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareCaptureCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC Time Base Counter Capture count value + // + return(HWREGH(base + EPWM_O_DCCAP)); +} + +//***************************************************************************** +// +//! Enable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function enables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | tripInput); + + // + // Enable the combination input + // + HWREGH(base + EPWM_O_DCTRIPSEL) = + (HWREGH(base + EPWM_O_DCTRIPSEL) | (0xFU << ((uint16_t)dcType << 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Disable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function disables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~tripInput); + EDIS; +} + +// +// Valley switching +// +//***************************************************************************** +// +//! Enable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Start valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function starts Valley Capture sequence. +//! +//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger +//! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPSTART bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPSTART; + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger. +//! +//! \param base is the base address of the EPWM module. +//! \param trigger is the Valley counter trigger. +//! +//! This function sets the trigger value that initiates Valley Capture sequence +//! +//! \b Set the number of Trigger source events for starting and stopping the +//! valley capture using EPWM_setValleyTriggerEdgeCounts(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TRIGSEL bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_TRIGSEL_M) | + ((uint16_t)trigger << 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger source count. +//! +//! \param base is the base address of the EPWM module. +//! \param startCount +//! \param stopCount +//! +//! This function sets the number of trigger events required to start and stop +//! the valley capture count. +//! Maximum values for both startCount and stopCount is 15 corresponding to the +//! 15th edge of the trigger event. +//! +//! \b Note: +//! A startCount value of 0 prevents starting the valley counter. +//! A stopCount value of 0 prevents the valley counter from stopping. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, + uint16_t stopCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((startCount < 16U) && (stopCount < 16U)); + + // + // Write to STARTEDGE and STOPEDGE bits + // + EALLOW; + HWREGH(base + EPWM_O_VCNTCFG) = + ((HWREGH(base + EPWM_O_VCNTCFG) & + ~(EPWM_VCNTCFG_STARTEDGE_M | EPWM_VCNTCFG_STOPEDGE_M)) | + (startCount | (stopCount << 8U))); + EDIS; +} + +//***************************************************************************** +// +//! Enable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set Valley delay values. +//! +//! \param base is the base address of the EPWM module. +//! \param delayOffsetValue is the software defined delay offset value. +//! +//! This function sets the Valley delay value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to SWVDELVAL bits + // + HWREGH(base + EPWM_O_SWVDELVAL) = delayOffsetValue; +} + +//***************************************************************************** +// +//! Set Valley delay mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Valley delay mode. +//! +//! This function sets the Valley delay mode values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to VDELAYDIV bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_VDELAYDIV_M) | + ((uint16_t)delayMode << 7U)); + EDIS; +} + +//***************************************************************************** +// +//! Get the valley edge status bit. +//! +//! \param base is the base address of the EPWM module. +//! \param edge is the start or stop edge. +//! +//! This function returns the status of the start or stop valley status +//! depending on the value of edge. +//! If a start or stop edge has occurred, the function returns true, if not it +//! returns false. +//! +//! \return Returns true if the specified edge has occurred, +//! Returns false if the specified edge has not occurred. +// +//***************************************************************************** +static inline bool +EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(edge == EPWM_VALLEY_COUNT_START_EDGE) + { + // + // Returns STARTEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STARTEDGESTS) == + EPWM_VCNTCFG_STARTEDGESTS ) ? true : false); + } + else + { + // + // Returns STOPEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STOPEDGESTS) == + EPWM_VCNTCFG_STOPEDGESTS) ? true : false); + } +} + +//***************************************************************************** +// +//! Get the Valley Counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the valley time base count value which is captured +//! upon occurrence of the stop edge condition selected by +//! EPWM_setValleyTriggerSource() and by the stopCount variable of the +//! EPWM_setValleyTriggerEdgeCounts() function. +//! +//! \return Returns the valley base time count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read VCNTVAL register + // + return(HWREGH(base + EPWM_O_VCNTVAL)); +} + +//***************************************************************************** +// +//! Get the Valley delay value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the hardware valley delay count. +//! +//! \return Returns the valley delay count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read HWVDELVAL register + // + return(HWREGH(base + EPWM_O_HWVDELVAL)); +} + +//***************************************************************************** +// +//! Enable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Global shadow to active load mode of registers. +//! The trigger source for loading shadow to active is determined by +//! EPWM_setGlobalLoadTrigger() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Disable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Global shadow to active load mode of registers. +//! Loading shadow to active is determined individually. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled individually + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Set the Global shadow load pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param loadTrigger is the pulse that causes global shadow load. +//! +//! This function sets the pulse that causes Global shadow to active load. +//! Valid values for the loadTrigger parameter are: +//! +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal +//! to zero +//! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal +//! to period +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal +//! to zero or period +//! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when +//! counter is equal to zero +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when +//! counter is equal to period +//! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when +//! counter is equal to period +//! or zero +//! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Global shadow to active load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDMODE_M) | + ((uint16_t)loadTrigger << EPWM_GLDCTL_GLDMODE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! \param prescalePulseCount is the pulse event counts. +//! +//! This function sets the number of Global Load pulse events that have to +//! occurred before a global load pulse is issued. Valid values for +//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7 +//! representing 7 events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(prescalePulseCount < 8U); + + // + // Set the number of counts that have to occur before + // a load strobe is issued + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDPRD_M) | + (prescalePulseCount << EPWM_GLDCTL_GLDPRD_S)); + EDIS; +} + +//***************************************************************************** +// +//! Return the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the number of Global Load pulse events that have +//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +EPWM_getGlobalLoadEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the number of events that have occurred + // + return((HWREGH(base + EPWM_O_GLDCTL) >> EPWM_GLDCTL_GLDCNT_S) & 0x7U); +} + +//***************************************************************************** +// +//! Enable continuous global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables global continuous shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Enable One shot global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables a one time global shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Set One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function sets a one time global shadow to active load pulse. The pulse +//! propagates to generate a load signal if any of the events set by +//! EPWM_setGlobalLoadTrigger() occur. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadOneShotLatch(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set a one shot Global shadow load pulse. + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_OSHTLD; + EDIS; +} + +//***************************************************************************** +// +//! Force a software One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces a software a one time global shadow to active load +//! pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceGlobalLoadOneShotEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Force a Software Global shadow load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_GFRCLD; + EDIS; +} + +//***************************************************************************** +// +//! Enable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function enables the register specified by loadRegister to be globally +//! loaded. +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) |= loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Disable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function disables the register specified by loadRegister from being +//! loaded globally. The shadow to active load happens as specified by the +//! register control +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded by individual + // register configuration setting + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) &= ~loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Set emulation mode +//! +//! \param base is the base address of the EPWM module. +//! \param emulationMode is the emulation mode. +//! +//! This function sets the emulation behaviours of the time base counter. Valid +//! values for emulationMode are: +//! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter +//! increment or decrement. +//! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole +//! cycle. +//! - EPWM_EMULATION_FREE_RUN - Free run. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode); + +//***************************************************************************** +// +//! Configures ePWM signal with desired frequency & duty +//! +//! \param base is the base address of the EPWM module. +//! \param signalParams is the desired signal parameters. +//! +//! This function configures the ePWM module to generate a signal with +//! desired frequency & duty. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EPWM_H diff --git a/gpio_bitfield_cpu2/device/driverlib/eqep.c b/gpio_bitfield_cpu2/device/driverlib/eqep.c new file mode 100644 index 0000000..64caf47 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/eqep.c @@ -0,0 +1,149 @@ +//########################################################################### +// +// FILE: eqep.c +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "eqep.h" + +//***************************************************************************** +// +// EQEP_setCompareConfig +// +//***************************************************************************** +void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the compare match value + // + HWREG(base + EQEP_O_QPOSCMP) = compareValue; + + // + // Set the shadow register settings and pulse width. + // + regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW | + EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U); + + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(EQEP_QPOSCTL_PCSPW_M | + EQEP_QPOSCTL_PCLOAD | + EQEP_QPOSCTL_PCSHDW)) | regValue; + + // + // Set position compare sync-output mode. + // + regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL); + + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SOEN | + EQEP_QDECCTL_SPSEL)) | regValue; +} + +//***************************************************************************** +// +// EQEP_setInputPolarity +// +//***************************************************************************** +void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Configure QEPA signal + // + if(invertQEPA) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP; + } + + // + // Configure QEPB signal + // + if(invertQEPB) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP; + } + + // + // Configure index signal + // + if(invertIndex) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP; + } + + // + // Configure strobe signal + // + if(invertStrobe) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP; + } +} diff --git a/gpio_bitfield_cpu2/device/driverlib/eqep.h b/gpio_bitfield_cpu2/device/driverlib/eqep.h new file mode 100644 index 0000000..4f1eaa2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/eqep.h @@ -0,0 +1,1691 @@ +//########################################################################### +// +// FILE: eqep.h +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EQEP_H +#define EQEP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eqep_api eQEP +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_eqep.h" +#include "inc/hw_types.h" +#include "debug.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to EQEP_setDecoderConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Operation Mode +// +#define EQEP_CONFIG_QUADRATURE 0x0000U //!< Quadrature-clock mode +#define EQEP_CONFIG_CLOCK_DIR 0x4000U //!< Direction-count mode +#define EQEP_CONFIG_UP_COUNT 0x8000U //!< Up-count mode, QDIR = 1 +#define EQEP_CONFIG_DOWN_COUNT 0xC000U //!< Down-count mode, QDIR = 0 + +// +// Resolution +// +#define EQEP_CONFIG_2X_RESOLUTION 0x0000U //!< Count rising and falling edge +#define EQEP_CONFIG_1X_RESOLUTION 0x0800U //!< Count rising edge only + +// +// Swap QEPA and QEPB +// +#define EQEP_CONFIG_NO_SWAP 0x0000U //!< Do not swap QEPA and QEPB +#define EQEP_CONFIG_SWAP 0x0400U //!< Swap QEPA and QEPB + +// +// Index pulse gating option +// +#define EQEP_CONFIG_IGATE_DISABLE 0x0000U //!< Disable gating of Index pulse +#define EQEP_CONFIG_IGATE_ENABLE 0x0200U //!< Gate the index pin with strobe + +//***************************************************************************** + +// +// Values that can be passed to EQEP_setCompareConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Sync pulse pin +// +#define EQEP_COMPARE_NO_SYNC_OUT 0x0000U //!< Disable sync output +#define EQEP_COMPARE_IDX_SYNC_OUT 0x2000U //!< Sync output on index pin +#define EQEP_COMPARE_STROBE_SYNC_OUT 0x3000U //!< Sync output on strobe pin + +// +// Shadow register use +// +#define EQEP_COMPARE_NO_SHADOW 0x0000U //!< Disable shadow of QPOSCMP +#define EQEP_COMPARE_LOAD_ON_ZERO 0x8000U //!< Load on QPOSCNT = 0 +#define EQEP_COMPARE_LOAD_ON_MATCH 0xC000U //!< Load on QPOSCNT = QPOSCMP + +//***************************************************************************** +// +// Values that can be passed to EQEP_enableInterrupt(), +// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the +// intFlags parameter and returned by EQEP_clearInterruptStatus(). +// +//***************************************************************************** +#define EQEP_INT_GLOBAL 0x0001U //!< Global interrupt flag +#define EQEP_INT_POS_CNT_ERROR 0x0002U //!< Position counter error +#define EQEP_INT_PHASE_ERROR 0x0004U //!< Quadrature phase error +#define EQEP_INT_DIR_CHANGE 0x0008U //!< Quadrature direction change +#define EQEP_INT_WATCHDOG 0x0010U //!< Watchdog time-out +#define EQEP_INT_UNDERFLOW 0x0020U //!< Position counter underflow +#define EQEP_INT_OVERFLOW 0x0040U //!< Position counter overflow +#define EQEP_INT_POS_COMP_READY 0x0080U //!< Position-compare ready +#define EQEP_INT_POS_COMP_MATCH 0x0100U //!< Position-compare match +#define EQEP_INT_STROBE_EVNT_LATCH 0x0200U //!< Strobe event latch +#define EQEP_INT_INDEX_EVNT_LATCH 0x0400U //!< Index event latch +#define EQEP_INT_UNIT_TIME_OUT 0x0800U //!< Unit time-out + +//***************************************************************************** +// +// Values that can be returned by EQEP_getStatus(). +// +//***************************************************************************** +//! Unit position event detected +#define EQEP_STS_UNIT_POS_EVNT 0x0080U +//! Direction was clockwise on first index event +#define EQEP_STS_DIR_ON_1ST_IDX 0x0040U +//! Direction is CW (forward) +#define EQEP_STS_DIR_FLAG 0x0020U +//! Direction was CW on index +#define EQEP_STS_DIR_LATCH 0x0010U +//! Capture timer overflow +#define EQEP_STS_CAP_OVRFLW_ERROR 0x0008U +//! Direction changed between position capture events +#define EQEP_STS_CAP_DIR_ERROR 0x0004U +//! First index pulse occurred +#define EQEP_STS_1ST_IDX_FLAG 0x0002U +//! Position counter error +#define EQEP_STS_POS_CNT_ERROR 0x0001U + +//***************************************************************************** +// +// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter. +// +//***************************************************************************** + +// +// Position counter latch event +// +#define EQEP_LATCH_CNT_READ_BY_CPU 0x0000U //!< On position counter read +#define EQEP_LATCH_UNIT_TIME_OUT 0x0004U //!< On unit time-out event + +// +// Strobe position counter latch event +// +//! On rising edge of strobe +#define EQEP_LATCH_RISING_STROBE 0x0000U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_LATCH_EDGE_DIR_STROBE 0x0040U + +// +// Index position counter latch event +// +#define EQEP_LATCH_RISING_INDEX 0x0010U //!< On rising edge of index +#define EQEP_LATCH_FALLING_INDEX 0x0020U //!< On falling edge of index + +#define EQEP_LATCH_SW_INDEX_MARKER 0x0030U //!< On software index marker + +//***************************************************************************** +// +// Values that can be passed to EQEP_setPositionInitMode() as the initMode +// parameter. +// +//***************************************************************************** +#define EQEP_INIT_DO_NOTHING 0x0000U //!< Action is disabled + +// +// Strobe events +// +//! On rising edge of strobe +#define EQEP_INIT_RISING_STROBE 0x0800U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_INIT_EDGE_DIR_STROBE 0x0C00U + +// +// Index events +// +#define EQEP_INIT_RISING_INDEX 0x0200U //!< On rising edge of index +#define EQEP_INIT_FALLING_INDEX 0x0300U //!< On falling edge of index +#endif + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Reset position on index pulse + EQEP_POSITION_RESET_IDX = 0x0000, + //! Reset position on maximum position + EQEP_POSITION_RESET_MAX_POS = 0x1000, + //! Reset position on the first index pulse + EQEP_POSITION_RESET_1ST_IDX = 0x2000, + //! Reset position on a unit time event + EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000 +} EQEP_PositionResetMode; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale +//! parameter. CAPCLK is the capture timer clock frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1 + EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2 + EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4 + EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8 + EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16 + EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32 + EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64 + EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128 +} EQEP_CAPCLKPrescale; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale +//! parameter. UPEVNT is the unit position event frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1 + EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2 + EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4 + EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8 + EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16 + EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32 + EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64 + EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128 + EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256 + EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512 + EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024 + EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048 +} EQEP_UPEVNTPrescale; + + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately + EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover + EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend +}EQEP_EmulationMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an eQEP base address. +//! +//! \param base specifies the eQEP module base address. +//! +//! This function determines if a eQEP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +EQEP_isBaseValid(uint32_t base) +{ + return( + (base == EQEP1_BASE) || + (base == EQEP2_BASE) || + (base == EQEP3_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the enhanced quadrature encoder pulse +//! (eQEP) module. The module must be configured before it is enabled. +//! +//! \sa EQEP_setConfig() +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_QPEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module. +//! +//! \param base is the base address of the enhanced quadrature encoder pulse +//! (eQEP) module +//! +//! This function disables operation of the eQEP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_QPEN); +} + +//***************************************************************************** +// +//! Configures eQEP module's quadrature decoder unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module decoder unit. +//! +//! This function configures the operation of the eQEP module's quadrature +//! decoder unit. The \e config parameter provides the configuration +//! of the decoder and is the logical OR of several values: +//! +//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify +//! if both rising and falling edges should be counted or just rising edges. +//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR, +//! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if +//! quadrature signals are being provided on QEPA and QEPB, if a direction +//! signal and a clock are being provided, or if the direction should be +//! hard-wired for a single direction with QEPA used for input. +//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the +//! signals provided on QEPA and QEPB should be swapped before being +//! processed. +//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify +//! if the gating of the index pulse should be enabled or disabled +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setDecoderConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the new decoder configuration to the hardware. + // + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SWAP | + EQEP_QDECCTL_XCR | + EQEP_QDECCTL_QSRC_M | + EQEP_QDECCTL_IGATE)) | config; +} + +//***************************************************************************** +// +//! Configures eQEP module position counter unit. +//! +//! \param base is the base address of the eQEP module. +//! \param mode is the configuration for the eQEP module position counter. +//! \param maxPosition specifies the maximum position value. +//! +//! This function configures the operation of the eQEP module position +//! counter. The \e mode parameter determines the event on which the position +//! counter gets reset. It should be passed one of the following values: +//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS, +//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT. +//! +//! \e maxPosition is the maximum value of the position counter and is +//! the value used to reset the position capture when moving in the reverse +//! (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, + uint32_t maxPosition) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the position counter reset configuration to the hardware. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~EQEP_QEPCTL_PCRM_M) | (uint16_t)mode; + + // + // Set the maximum position. + // + HWREG(base + EQEP_O_QPOSMAX) = maxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPosition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSCNT)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the position counter. + // + HWREG(base + EQEP_O_QPOSCNT) = position; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +static inline int16_t +EQEP_getDirection(uint32_t base) +{ + int16_t direction; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the direction of rotation. + // + if((HWREGH(base + EQEP_O_QEPSTS) & EQEP_QEPSTS_QDF) != 0U) + { + direction = 1; + } + else + { + direction = -1; + } + + return(direction); +} + +//***************************************************************************** +// +//! Enables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the interrupt status for the eQEP module +//! module. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +// +//***************************************************************************** +static inline uint16_t +EQEP_getInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + return(HWREGH(base + EQEP_O_QFLG)); +} + +//***************************************************************************** +// +//! Clears eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In +//! order to get any further eQEP interrupts, this flag must be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QCLR) = intFlags; +} + +//***************************************************************************** +// +//! Forces individual eQEP module interrupts. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be forced. +//! +//! This function forces eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR +//! - \b EQEP_INT_PHASE_ERROR +//! - \b EQEP_INT_DIR_CHANGE +//! - \b EQEP_INT_WATCHDOG +//! - \b EQEP_INT_UNDERFLOW +//! - \b EQEP_INT_OVERFLOW +//! - \b EQEP_INT_POS_COMP_READY +//! - \b EQEP_INT_POS_COMP_MATCH +//! - \b EQEP_INT_STROBE_EVNT_LATCH +//! - \b EQEP_INT_INDEX_EVNT_LATCH +//! - \b EQEP_INT_UNIT_TIME_OUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_forceInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Force the specified interrupts. + // + HWREGH(base + EQEP_O_QFRC) |= intFlags; +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the error indicator for the eQEP module. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +static inline bool +EQEP_getError(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the error indicator. + // + return((HWREGH(base + EQEP_O_QFLG) & EQEP_QFLG_PHE) != 0U); +} + +//***************************************************************************** +// +//! Returns content of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the contents of the status register. The value it +//! returns is an OR of the following values: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward +//! movement) occurred on the first index event +//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation +//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last +//! index event marker +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred +//! +//! \return Returns the value of the QEP status register. +// +//***************************************************************************** +static inline uint16_t +EQEP_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the status register. + // + return(HWREGH(base + EQEP_O_QEPSTS) & 0x00FFU); +} + +//***************************************************************************** +// +//! Clears selected fields of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! \param statusFlags is the bit mask of the status flags to be cleared. +//! +//! This function clears the status register fields indicated by +//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of +//! the following: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! +//! \note Only the above status fields can be cleared. All others are +//! read-only, non-sticky fields. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearStatus(uint32_t base, uint16_t statusFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QEPSTS) = statusFlags; +} + +//***************************************************************************** +// +//! Configures eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! \param capPrescale is the prescaler setting of the eQEP capture timer clk. +//! \param evntPrescale is the prescaler setting of the unit position event +//! frequency. +//! +//! This function configures the operation of the eQEP module edge-capture +//! unit. The \e capPrescale parameter provides the configuration of the eQEP +//! capture timer clock rate. It determines by which power of 2 between 1 and +//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in +//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For +//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock +//! frequency that is SYSCLKOUT/32. +//! +//! The \e evntPrescale parameter determines how frequently a unit position +//! event occurs. The macro that can be passed this parameter is in the format +//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock +//! periods between unit position events. For example, +//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event +//! frequency of QCLK/16. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, + EQEP_UPEVNTPrescale evntPrescale) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write new prescaler configurations to the appropriate registers. + // + HWREGH(base + EQEP_O_QCAPCTL) = + (HWREGH(base + EQEP_O_QCAPCTL) & + ~(EQEP_QCAPCTL_UPPS_M | EQEP_QCAPCTL_CCPS_M)) | + ((uint16_t)evntPrescale | (uint16_t)capPrescale); +} + +//***************************************************************************** +// +//! Enables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) |= EQEP_QCAPCTL_CEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) &= ~(EQEP_QCAPCTL_CEN); +} + +//***************************************************************************** +// +//! Gets the encoder capture period. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the period count value between the last successive +//! eQEP position events. +//! +//! \return The period count value between the last successive position events. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriod(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture period. + // + return(HWREGH(base + EQEP_O_QCPRD)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the time base for the edge capture unit. +//! +//! \return The capture timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture timer value. + // + return(HWREGH(base + EQEP_O_QCTMR)); +} + +//***************************************************************************** +// +//! Enables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's position-compare unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) |= EQEP_QPOSCTL_PCE; +} + +//***************************************************************************** +// +//! Disables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's position-compare +//! unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) &= ~(EQEP_QPOSCTL_PCE); +} + +//***************************************************************************** +// +//! Configures the position-compare unit's sync output pulse width. +//! +//! \param base is the base address of the eQEP module. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the width of the sync output pulse. The width of +//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The +//! maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the pulse width. + // + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(uint16_t)EQEP_QPOSCTL_PCSPW_M) | + (cycles - 1U); +} + +//***************************************************************************** +// +//! Loads the eQEP module unit timer period as number of SYSCLK cycles. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function sets the unit time-out interrupt when it matches the value +//! specified by \e period +//! The unit timer is clocked by SYSCLKOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_loadUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; +} + +//***************************************************************************** +// +//! Enables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function enables operation of the eQEP module's peripheral unit timer. +//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out +//! interrupt when it matches the value specified by \e period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; + + // + // Enable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_UTE; +} + +//***************************************************************************** +// +//! Disables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral +//! unit timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableUnitTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_UTE); +} + +//***************************************************************************** +// +//! Enables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is watchdog period value at which a time-out will occur if +//! no quadrature-clock event is detected. +//! +//! This function enables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \note When selecting \e period, note that the watchdog timer is clocked +//! from SYSCLKOUT/64. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableWatchdog(uint32_t base, uint16_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the timeout count for the eQEP peripheral watchdog timer. + // + HWREGH(base + EQEP_O_QWDPRD) = period; + + // + // Enable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_WDE; +} + +//***************************************************************************** +// +//! Disables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableWatchdog(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_WDE); +} + +//***************************************************************************** +// +//! Sets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! \param value is the value to be written to the watchdog timer. +//! +//! This function sets the eQEP module's watchdog timer value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the value to the watchdog timer register. + // + HWREGH(base + EQEP_O_QWDTMR) = value; +} + +//***************************************************************************** +// +//! Gets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! \return Returns the current watchdog timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getWatchdogTimerValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Read the value from the watchdog timer register. + // + return(HWREGH(base + EQEP_O_QWDTMR)); +} + +//***************************************************************************** +// +//! Configures the mode in which the position counter is initialized. +//! +//! \param base is the base address of the eQEP module. +//! \param initMode is the configuration for initializing the position count. +//! See below for a description of this parameter. +//! +//! This function configures the events on which the position count can be +//! initialized. The \e initMode parameter provides the mode as either +//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following +//! strobe events, index events, or a logical OR of both a strobe event and an +//! index event. +//! +//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify +//! which strobe event will initialize the position counter. +//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify +//! which index event will initialize the position counter. +//! +//! Use EQEP_setSWPositionInit() to cause a software initialization and +//! EQEP_setInitialPosition() to set the value that gets loaded into the +//! position counter upon initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionInitMode(uint32_t base, uint16_t initMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the init mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_IEI_M | EQEP_QEPCTL_SEI_M)) | + initMode; +} + +//***************************************************************************** +// +//! Sets the software initialization of the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param initialize is a flag to specify if software initialization of the +//! position counter is enabled. +//! +//! This function does a software initialization of the position counter when +//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit +//! is cleared and no action is taken. +//! +//! The init value to be loaded into the position counter can be set with +//! EQEP_setInitialPosition(). Additional initialization causes can be +//! configured with EQEP_setPositionInitMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setSWPositionInit(uint32_t base, bool initialize) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set or clear the software initialization bit. + // + if(initialize) + { + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_SWI; + } + else + { + HWREGH(base + EQEP_O_QEPCTL) &= ~EQEP_QEPCTL_SWI; + } +} + +//***************************************************************************** +// +//! Sets the init value for the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the value to be written to the position counter upon. +//! initialization. +//! +//! This function sets the init value for position of the encoder. See +//! EQEP_setPositionInitMode() to set the initialization cause or +//! EQEP_setSWPositionInit() to cause a software initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setInitialPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write position to position counter init register + // + HWREG(base + EQEP_O_QPOSINIT) = position; +} + +//***************************************************************************** +// +//! Configures the quadrature modes in which the position count can be latched. +//! +//! \param base is the base address of the eQEP module. +//! \param latchMode is the configuration for latching of the position count +//! and several other registers. See below for a description of this +//! parameter. +//! +//! This function configures the events on which the position count and several +//! other registers can be latched. The \e latchMode parameter provides the +//! mode as the logical OR of several values. +//! +//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify +//! the event that latches the position counter. This latch register can be +//! read using EQEP_getPositionLatch(). The capture timer and capture +//! period are also latched based on this setting, and can be read using +//! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch(). +//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE +//! specify which strobe event will latch the position counter into the +//! strobe position latch register. This register can be read with +//! EQEP_getStrobePositionLatch(). +//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or +//! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the +//! position counter into the index position latch register. This register +//! can be read with EQEP_getIndexPositionLatch(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setLatchMode(uint32_t base, uint32_t latchMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the latch mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_QCLM | EQEP_QEPCTL_IEL_M | + EQEP_QEPCTL_SEL)) | latchMode; +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on an index event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the index position latch register. The +//! position counter is latched into this register on either a rising index +//! edge, a falling index edge, or a software index marker. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on an index event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getIndexPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSILAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a strobe event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the strobe position latch register. The +//! position counter can be configured to be latched into this register on +//! rising strobe edges only or on rising strobe edges while moving clockwise +//! and falling strobe edges while moving counter-clockwise. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on a strobe event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getStrobePositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a unit time-out event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the position latch register. The +//! position counter is latched into this register either on a unit time-out +//! event. +//! +//! \return The position count latch register value. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture timer latch register. The +//! capture timer value is latched into this register either on a unit time-out +//! event or upon the CPU reading the eQEP position counter. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The edge-capture timer latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimerLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCTMRLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture period latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture period latch register. The +//! capture period value is latched into this register either on a unit +//! time-out event or upon the CPU reading the eQEP position counter. This is +//! configured using EQEP_setLatchMode(). +//! +//! \return The edge-capture period latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriodLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCPRDLAT)); +} + +//***************************************************************************** +// +//! Set the emulation mode of the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! \param emuMode is the mode operation upon an emulation suspend. +//! +//! This function sets the eQEP module's emulation mode. This mode determines +//! how the timers are affected by an emulation suspend. Valid values for the +//! \e emuMode parameter are the following: +//! +//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog +//! counter, unit timer, and capture timer all stop immediately. +//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog +//! counter, unit timer all count until period rollover. The capture timer +//! counts until the next unit period event. +//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter, +//! unit timer, and capture timer are all unaffected by an emulation suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the emulation mode to the FREE_SOFT bits. + // + HWREGH(base + EQEP_O_QEPCTL) = + (HWREGH(base + EQEP_O_QEPCTL) & ~EQEP_QEPCTL_FREE_SOFT_M) | + ((uint16_t)emuMode << EQEP_QEPCTL_FREE_SOFT_S); +} + +//***************************************************************************** +// +//! Configures eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module +//! position-compare unit. See below for a description of this parameter. +//! \param compareValue is the value to which the position count value is +//! compared for a position-compare event. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the operation of the eQEP module position-compare +//! unit. The \e config parameter provides the configuration of the +//! position-compare unit and is the logical OR of several values: +//! +//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or +//! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse +//! and which pin should be used. +//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or +//! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when +//! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP. +//! +//! The \e cycles is used to select the width of the sync output pulse. The +//! width of the resulting pulse will be \e cycles * 4 * the width of a +//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \note You can set the sync pulse width independently using the +//! EQEP_setComparePulseWidth() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles); + +//***************************************************************************** +// +//! Sets the polarity of the eQEP module's input signals. +//! +//! \param base is the base address of the eQEP module. +//! \param invertQEPA is the flag to negate the QEPA input. +//! \param invertQEPB is the flag to negate the QEPA input. +//! \param invertIndex is the flag to negate the index input. +//! \param invertStrobe is the flag to negate the strobe input. +//! +//! This function configures the polarity of the inputs to the eQEP module. To +//! negate the polarity of any of the input signals, pass \b true into its +//! corresponding parameter in this function. Pass \b false to leave it as-is. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EQEP_H diff --git a/gpio_bitfield_cpu2/device/driverlib/flash.c b/gpio_bitfield_cpu2/device/driverlib/flash.c new file mode 100644 index 0000000..372b77b --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/flash.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: flash.c +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "flash.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc"); +#endif + +//***************************************************************************** +// +// Flash_initModule +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT(waitstates <= 0xFU); + + // + // Set the bank power up delay so that the bank will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Set the bank fallback power mode to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Power up flash bank and pump and this also sets the fall back mode of + // flash and pump as active + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); + + // + // Disable cache and prefetch mechanism before changing wait states + // + Flash_disableCache(ctrlBase); + Flash_disablePrefetch(ctrlBase); + + // + // Set waitstates according to frequency. + // + Flash_setWaitstates(ctrlBase, waitstates); + + + // + // Enable cache and prefetch mechanism to improve performance of code + // executed from flash. + // + Flash_enableCache(ctrlBase); + Flash_enablePrefetch(ctrlBase); + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash_enableECC(eccBase); + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + + FLASH_DELAY_CONFIG; +} + +//***************************************************************************** +// +// Flash_powerDown +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_powerDown(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank power up delay so that it will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Power down the flash bank. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP); + + // + // Power down the flash pump. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP); +} + +//***************************************************************************** +// +// Flash_wakeFromLPM +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_wakeFromLPM(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank fallback power modes to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Set the flash pump power mode to active. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); +} diff --git a/gpio_bitfield_cpu2/device/driverlib/flash.h b/gpio_bitfield_cpu2/device/driverlib/flash.h new file mode 100644 index 0000000..a60a2f2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/flash.h @@ -0,0 +1,1671 @@ +//########################################################################### +// +// FILE: flash.h +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH_H +#define FLASH_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif +#ifndef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +//! \addtogroup flash_api Flash +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_flash.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc"); +#endif + + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK = 0x0 //!< Bank +} Flash_BankNumber; + +//***************************************************************************** +// +//! Values that can be passed to Flash_claimPumpSemaphore() in order to claim +//! the pump semaphore. +// +//***************************************************************************** +typedef enum +{ + FLASH_CPU1_WRAPPER = 0x2, //!< CPU1 Wrapper + FLASH_CPU2_WRAPPER = 0x1 //!< CPU2 Wrapper +}Flash_PumpOwnership; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode + FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode +} Flash_BankPowerMode; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode +} Flash_PumpPowerMode; + +//***************************************************************************** +// +//! Type that correspond to values returned from Flash_getLowErrorStatus() and +//! Flash_getHighErrorStatus() determining the error status code. +// +//***************************************************************************** +typedef enum +{ + FLASH_NO_ERR = 0x0, //!< No error + FLASH_FAIL_0 = 0x1, //!< Fail on 0 + FLASH_FAIL_1 = 0x2, //!< Fail on 1 + FLASH_UNC_ERR = 0x4 //!< Uncorrectable error +} Flash_ErrorStatus; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getLowErrorType() and +//! Flash_getHighErrorType() determining the error type. +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_ERR = 0x0, //!< Data error + FLASH_ECC_ERR = 0x1 //!< ECC error +} Flash_ErrorType; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getECCTestSingleBitErrorType(). +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_BITS = 0x0, //!< Data bits + FLASH_CHECK_BITS = 0x1 //!< ECC bits +} Flash_SingleBitErrorIndicator; + +//***************************************************************************** +// +// Values that can be passed to Flash_clearLowErrorStatus and +// Flash_clearHighErrorStatus. +// +//***************************************************************************** +#define FLASH_FAIL_0_CLR 0x1 //!< Fail-0 clear +#define FLASH_FAIL_1_CLR 0x2 //!< Fail-1 clear +#define FLASH_UNC_ERR_CLR 0x4 //!< Uncorrectable error Clear + +//***************************************************************************** +// +// Values that can be returned from Flash_getInterruptFlag and +// Flash_getECCTestStatus. +// +//***************************************************************************** +#define FLASH_NO_ERROR 0x0 //!< No error +#define FLASH_SINGLE_ERROR 0x1 //!< Single bit error +#define FLASH_UNC_ERROR 0x2 //!< Uncorrectable error + +//***************************************************************************** +// +// Delay instruction that allows for register configuration to complete. +// +//***************************************************************************** +#define FLASH_DELAY_CONFIG __asm(" RPT #7 || NOP") + +//***************************************************************************** +// +// Key value for claiming the pump semaphore. +// +//***************************************************************************** +#define FLASH_PUMP_KEY 0x5A5A0000UL //!< Pump semaphore key + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function determines if a flash wrapper control base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isCtrlBaseValid(uint32_t ctrlBase) +{ + return((ctrlBase == FLASH0CTRL_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the ECC registers. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function determines if a flash wrapper ECC base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isECCBaseValid(uint32_t eccBase) +{ + return((eccBase == FLASH0ECC_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash pump semaphore base address. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! This function determines if a flash pump semaphore base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isPumpSemBaseValid(uint32_t pumpSemBase) +{ + return((pumpSemBase == FLASHPUMPSEMAPHORE_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the random read wait state amount. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param waitstates is the wait-state value. +//! +//! This function sets the number of wait states for a flash read access. The +//! \e waitstates parameter is a number between 0 and 15. It is \b important +//! to look at your device's datasheet for information about what the required +//! minimum flash wait-state is for your selected SYSCLK frequency. +//! +//! By default the wait state amount is configured to the maximum 15. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // waitstates is 4 bits wide. + // + ASSERT(waitstates <= 0xFU); + + EALLOW; + // + // Write flash read wait-state amount to appropriate register. + // + HWREG(ctrlBase + FLASH_O_FRDCNTL) = + (HWREG(ctrlBase + FLASH_O_FRDCNTL) & + ~(uint32_t)FLASH_FRDCNTL_RWAIT_M) | + ((uint32_t)waitstates << FLASH_FRDCNTL_RWAIT_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of a flash bank. +//! +//! \param ctrlBase is the base address of the flash wrapper registers. +//! \param bank is the flash bank that is being configured. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode of the flash bank specified by +//! them \e bank parameter. The power mode is specified by the \e powerMode +//! parameter with one of the following values: +//! +//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled. +//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference +//! enabled. +//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled. +//! +//! +//! Note: There is only one Flash_BankNumber value on this device (FLASH_BANK). +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank, + Flash_BankPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FBFALLBACK) = + (HWREG(ctrlBase + FLASH_O_FBFALLBACK) & + ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t)bank * 2U))) | + ((uint32_t)powerMode << ((uint32_t)bank * 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of the charge pump. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode flash charge pump. +//! +//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled. +//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PMPPWR) | (uint32_t)powerMode; + EDIS; +} + +//***************************************************************************** +// +//! Enables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Write the key value 0xA to ECC_ENABLE register. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0xAU; + EDIS; +} + +//***************************************************************************** +// +//! Disables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Clear ECC enable field with the one's complement of the key. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0x5U; + EDIS; +} + + +//***************************************************************************** +// +//! Sets the bank power up delay. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param delay is the number of HCLK cycles. +//! +//! This function sets the VREADST delay to ensure that the requisite delay is +//! introduced for the flash pump/bank to come out of low-power mode, so that +//! the flash/OTP is ready for CPU access. +//! +//! Note: Refer to TRM before configuring VREADST. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setBankPowerUpDelay(uint32_t ctrlBase, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(delay <= 0xFF); + + EALLOW; + + // + // Write period to the BAGP of the FBAC register. + // + HWREG(ctrlBase + FLASH_O_FBAC) = (HWREG(ctrlBase + FLASH_O_FBAC) & + ~(uint32_t)FLASH_FBAC_VREADST_M) | delay; + EDIS; +} + +//***************************************************************************** +// +//! Sets the pump wake up time. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump +//! to wakeup. +//! +//! This function sets the wakeup time with \e sysclkCycles parameter. +//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump +//! exits sleep power mode, it will take sysclkCycles to wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide) + // + ASSERT( sysclkCycles <= 8190U ); + + EALLOW; + + // + // Write sysclkCycles/2 to PSLEEP of the FPAC1 register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PSLEEP_M) | + (((uint32_t)sysclkCycles / (uint32_t)2) << + (uint32_t)FLASH_FPAC1_PSLEEP_S); + EDIS; +} + +//***************************************************************************** +// +//! Reads the bank active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param bank is the flash bank that is being used. +//! +//! \return Returns \b true if the Bank is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + uint32_t bitMask = (uint32_t)FLASH_FBPRDY_BANKRDY << (uint32_t)bank; + // + // Return the BANKXRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & bitMask) == bitMask) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + +//***************************************************************************** +// +//! Reads the pump active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return Returns \b true if the Pump is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isPumpReady(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + + // + // Return the PUMPRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & + (uint32_t)FLASH_FBPRDY_PUMPRDY) == FLASH_FBPRDY_PUMPRDY) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + + +//***************************************************************************** +// +//! Gets the single error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the single error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC base. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the error status of the Lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the lower 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the low error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getLowErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the Low Error Status bits + // + errorStatus = (HWREG(eccBase + FLASH_O_ERR_STATUS) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error status of the Upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the upper 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the high error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getHighErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the High Error Status bits + // + errorStatus = ((HWREG(eccBase + FLASH_O_ERR_STATUS) >> 16U) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error position of the lower 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the lower 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the lower error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getLowErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_L_M) >> + FLASH_ERR_POS_ERR_POS_L_S); +} + +//***************************************************************************** +// +//! Gets the error position of the upper 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the upper 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the upper error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getHighErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_H_M) >> + FLASH_ERR_POS_ERR_POS_H_S); +} + +//***************************************************************************** +// +//! Gets the error type of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the lower 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the lower 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getLowErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_L) + == FLASH_ERR_POS_ERR_TYPE_L) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} + +//***************************************************************************** +// +//! Gets the error type of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the upper 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the upper 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getHighErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_H) + == FLASH_ERR_POS_ERR_TYPE_H) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} +//***************************************************************************** +// +//! Clears the errors status of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus); + EDIS; +} + +//***************************************************************************** +// +//! Clears the errors status of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus << 16U); + EDIS; +} + +//***************************************************************************** +// +//! Gets the single bit error count. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error count. +// +//***************************************************************************** +static inline uint32_t +Flash_getErrorCount(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_ERR_CNT) & + (uint32_t)FLASH_ERR_CNT_ERR_CNT_M); +} + +//***************************************************************************** +// +//! Sets the single bit error threshold. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param threshold is the single bit error threshold. Valid ranges are from +//! 0-65535. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_THRESHOLD) = ((uint32_t)threshold & + (uint32_t)FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M); + EDIS; +} + +//***************************************************************************** +// +//! Gets the error interrupt. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the type of error interrupt that occurred. The +//! values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the interrupt flag. +// +//***************************************************************************** +static inline uint32_t +Flash_getInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_ERR_INTFLG) & (uint32_t)0x3U)); +} + +//***************************************************************************** +// +//! Clears the single error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearSingleErrorInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Clears the uncorrectable error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearUncorrectableInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_UNC_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data Low Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the low double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAL_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data High Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the high double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAH_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the test address register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param address is a 32-bit value containing an address. Bits 21-3 will be +//! used as the flash word (128-bit) address. +//! +//! This function left shifts the address 1 bit to convert it to a byte address +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestAddress(uint32_t eccBase, uint32_t address) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Left shift the address 1 bit to make it byte-addressable + // + uint32_t byteAddress = address << 1; + + EALLOW; + + // + // Write bits 21-3 to the register. + // + HWREG(eccBase + FLASH_O_FADDR_TEST) = byteAddress; + + EDIS; + +} + +//***************************************************************************** +// +//! Sets the ECC test bits for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param ecc is a 32-bit value. The least significant 8 bits are used as +//! the ECC Control Bits in the ECC Test. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + ASSERT( ecc <= 255U ); + EALLOW; + + // + // Write the 8 ECC Control Bits. + // + HWREG(eccBase + FLASH_O_FECC_TEST) = + ((uint32_t)ecc & (uint32_t)FLASH_FECC_TEST_ECC_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_enableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [63:0] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectLowECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [127:64] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectHighECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Performs the ECC calculation on the test block. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_performECCCalculation(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_DO_ECC_CALC; + EDIS; +} + +//***************************************************************************** +// +//! Gets the ECC Test data out high 63:32 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC TEst data out High. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTH_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test data out low 31:0 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test data out Low. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTL_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test status. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the ECC test status. The values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the ECC test status. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestStatus(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS)) & (uint32_t)0x3U); +} + +//***************************************************************************** +// +//! Gets the ECC Test single bit error position. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test single bit error position. If the error type +//! is check bits than the position can range from 0 to 7. If the error type +//! is data bits than the position can range from 0 to 63. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the position bits and shift it to the right. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_DATA_ERR_POS_M) >> + FLASH_FECC_STATUS_DATA_ERR_POS_S); +} + +//***************************************************************************** +// +//! Gets the single bit error type. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error type as a +//! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS +//! indicate where the single bit error occurred. +// +//***************************************************************************** +static inline Flash_SingleBitErrorIndicator +Flash_getECCTestSingleBitErrorType(uint32_t eccBase) +{ + uint32_t errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the ERR_TYPE bit to see where the single bit error was. + // + errorType = ((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_ERR_TYPE) >> 8U); + return((Flash_SingleBitErrorIndicator)errorType); +} + +//***************************************************************************** +// +//! Claim the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! \param wrapper is the Flash_PumpOwnership wrapper claiming the pump +//! semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_claimPumpSemaphore(uint32_t pumpSemBase, Flash_PumpOwnership wrapper) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Block until the pump semaphore is claimed. + // + EALLOW; + while((HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) + & FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M) != wrapper) + { + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = + FLASH_PUMP_KEY | (uint32_t)wrapper; + } + EDIS; +} + +//***************************************************************************** +// +//! Release the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_releasePumpSemaphore(uint32_t pumpSemBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Relinquish the pump semaphore. + // + EALLOW; + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = FLASH_PUMP_KEY; + EDIS; +} + +//***************************************************************************** +// +//! Initializes the flash control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param waitstates is the wait-state value. +//! +//! This function initializes the flash control registers. At reset bank and +//! pump are in sleep. A flash access will power up the bank and pump +//! automatically. This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! This function also sets the number of wait-states for a flash access +//! (see Flash_setWaitstates() for more details), and enables cache, the +//! prefetch mechanism, and ECC. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates); + + +//***************************************************************************** +// +//! Powers down the flash. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function powers down the flash bank(s) and the flash pump. +//! +//! Note: For this device, you must claim the flash pump semaphore before +//! calling this function and powering down the pump. Afterwards, you may want +//! to relinquish the flash pump. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_powerDown(uint32_t ctrlBase); + +//***************************************************************************** +// +//! Wakes the flash from low power mode. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_wakeFromLPM(uint32_t ctrlBase); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +#endif // #ifdef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // FLASH_H diff --git a/gpio_bitfield_cpu2/device/driverlib/gpio.c b/gpio_bitfield_cpu2/device/driverlib/gpio.c new file mode 100644 index 0000000..be20285 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/gpio.c @@ -0,0 +1,489 @@ +//########################################################################### +// +// FILE: gpio.c +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "gpio.h" + +//***************************************************************************** +// +// GPIO_setDirectionMode +// +//***************************************************************************** +void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Set the data direction + // + if(pinIO == GPIO_DIR_MODE_OUT) + { + // + // Output + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask; + } + else + { + // + // Input + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getDirectionMode +// +//***************************************************************************** +GPIO_Direction +GPIO_getDirectionMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >> + (pin % 32U)) & 1U))); + +} + +//***************************************************************************** +// +// GPIO_setInterruptPin +// +//***************************************************************************** +void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum) +{ + XBAR_InputNum input; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + // + // Pick the X-BAR input that corresponds to the requested XINT. + // + switch(extIntNum) + { + case GPIO_INT_XINT1: + input = XBAR_INPUT4; + break; + + case GPIO_INT_XINT2: + input = XBAR_INPUT5; + break; + + case GPIO_INT_XINT3: + input = XBAR_INPUT6; + break; + + case GPIO_INT_XINT4: + input = XBAR_INPUT13; + break; + + case GPIO_INT_XINT5: + input = XBAR_INPUT14; + break; + + default: + // + // Invalid interrupt. Shouldn't happen if enum value is used. + // XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for + // a bad value. + // + input = XBAR_INPUT1; + break; + } + + if(input != XBAR_INPUT1) + { + XBAR_setInputPin(input, (uint16_t)pin); + } +} + +//***************************************************************************** +// +// GPIO_setPadConfig +// +//***************************************************************************** +void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Enable open drain if necessary + // + if((pinType & GPIO_PIN_TYPE_OD) != 0U) + { + gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask; + } + + // + // Enable pull-up if necessary + // + if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U) + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask; + } + + // + // Invert polarity if necessary + // + if((pinType & GPIO_PIN_TYPE_INVERT) != 0U) + { + gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getPadConfig +// +//***************************************************************************** +uint32_t +GPIO_getPadConfig(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + uint32_t pinTypeRes; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + pinTypeRes = GPIO_PIN_TYPE_STD; + + // + // Get open drain value + // + if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_OD; + } + + // + // Get pull-up value + // + if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_PULLUP; + } + + // + // Get polarity value + // + if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_INVERT; + } + + return(pinTypeRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationMode +// +//***************************************************************************** +void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Write the input qualification mode to the register. + // + EALLOW; + + gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt; + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getQualificationMode +// +//***************************************************************************** +GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t qualRes; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Read the qualification mode register and shift and mask to get the + // value for the specified pin. + // + qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) & + (uint32_t)GPIO_GPAQSEL1_GPIO0_M; + return((GPIO_QualificationMode)qualRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationPeriod +// +//***************************************************************************** +void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask, regVal, shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + ASSERT((divider >= 1U) && (divider <= 510U)); + + shiftAmt = (pin % 32U) & ~((uint32_t)0x7U); + pinMask = (uint32_t)0xFFU << shiftAmt; + + // + // Divide divider by two to get the value that needs to go into the field. + // Then shift it into the right place. + // + regVal = (divider / 2U) << shiftAmt; + + // + // Write the divider parameter into the register. + // + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setControllerCore +// +//***************************************************************************** +void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t cSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U); + cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U); + + // + // Write the core parameter into the register. + // + EALLOW; + gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setAnalogMode +// +//***************************************************************************** +void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT((pin == 42U) || (pin == 43U)); + + pinMask = (uint32_t)1U << (pin % 32U); + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + + // + // Set the analog mode selection. + // + if(mode == GPIO_ANALOG_ENABLED) + { + // + // Enable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask; + } + else + { + // + // Disable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_setPinConfig +// +//***************************************************************************** +void +GPIO_setPinConfig(uint32_t pinConfig) +{ + uint32_t muxRegAddr; + uint32_t pinMask, shiftAmt; + + muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16); + shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU); + pinMask = (uint32_t)0x3U << shiftAmt; + + EALLOW; + + // + // Clear fields in MUX register first to avoid glitches + // + HWREG(muxRegAddr) &= ~pinMask; + + // + // Write value into GMUX register + // + HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) = + (HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) | + (((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt); + + // + // Write value into MUX register + // + HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt); + EDIS; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/gpio.h b/gpio_bitfield_cpu2/device/driverlib/gpio.h new file mode 100644 index 0000000..05ae80a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/gpio.h @@ -0,0 +1,1047 @@ +//########################################################################### +// +// FILE: gpio.h +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef GPIO_H +#define GPIO_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup gpio_api GPIO +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_gpio.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_xint.h" +#include "cpu.h" +#include "xbar.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions to access gpio registers. +// Not intended for use by application code. +// +// Divide by 2 is for C28x which has word access +// +//***************************************************************************** +#define GPIO_CTRL_REGS_STEP ((GPIO_O_GPBCTRL - GPIO_O_GPACTRL) / 2U) +#define GPIO_DATA_REGS_STEP ((GPIO_O_GPBDAT - GPIO_O_GPADAT) / 2U) + +#define GPIO_GPxCTRL_INDEX (GPIO_O_GPACTRL / 2U) +#define GPIO_GPxQSEL_INDEX (GPIO_O_GPAQSEL1 / 2U) +#define GPIO_GPxMUX_INDEX (GPIO_O_GPAMUX1 / 2U) +#define GPIO_GPxDIR_INDEX (GPIO_O_GPADIR / 2U) +#define GPIO_GPxAMSEL_INDEX (0x00000014U / 2U) // Address rsvd for GPAAMSEL +#define GPIO_GPxPUD_INDEX (GPIO_O_GPAPUD / 2U) +#define GPIO_GPxINV_INDEX (GPIO_O_GPAINV / 2U) +#define GPIO_GPxODR_INDEX (GPIO_O_GPAODR / 2U) +#define GPIO_GPxGMUX_INDEX (GPIO_O_GPAGMUX1 / 2U) +#define GPIO_GPxCSEL_INDEX (GPIO_O_GPACSEL1 / 2U) +#define GPIO_GPxLOCK_INDEX (GPIO_O_GPALOCK / 2U) +#define GPIO_GPxCR_INDEX (GPIO_O_GPACR / 2U) + +#define GPIO_GPxDAT_INDEX (GPIO_O_GPADAT / 2U) +#define GPIO_GPxSET_INDEX (GPIO_O_GPASET / 2U) +#define GPIO_GPxCLEAR_INDEX (GPIO_O_GPACLEAR / 2U) +#define GPIO_GPxTOGGLE_INDEX (GPIO_O_GPATOGGLE / 2U) + +#define GPIO_MUX_TO_GMUX (GPIO_O_GPAGMUX1 - GPIO_O_GPAMUX1) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to GPIO_setPadConfig() as the pinType parameter +// and returned by GPIO_getPadConfig(). +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x0000U //!< Push-pull output or floating input +#define GPIO_PIN_TYPE_PULLUP 0x0001U //!< Pull-up enable for input +#define GPIO_PIN_TYPE_INVERT 0x0002U //!< Invert polarity on input +#define GPIO_PIN_TYPE_OD 0x0004U //!< Open-drain on output +#endif + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO +//! parameter and returned from GPIO_getDirectionMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_DIR_MODE_IN, //!< Pin is a GPIO input + GPIO_DIR_MODE_OUT //!< Pin is a GPIO output +} GPIO_Direction; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptType() as the \e intType +//! parameter and returned from GPIO_getInterruptType(). +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge + GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge + GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges +} GPIO_IntType; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setQualificationMode() as the +//! \e qualification parameter and returned by GPIO_getQualificationMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_QUAL_SYNC, //!< Synchronization to SYSCLK + GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples + GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples + GPIO_QUAL_ASYNC //!< No synchronization +} GPIO_QualificationMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_ANALOG_DISABLED, //!< Pin is in digital mode + GPIO_ANALOG_ENABLED //!< Pin is in analog mode +} GPIO_AnalogMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setControllerCore() as the \e core +//! parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_CORE_CPU1, //!< CPU1 selected as controller core + GPIO_CORE_CPU1_CLA1, //!< CPU1's CLA1 selected as controller core + GPIO_CORE_CPU2, //!< CPU2 selected as controller core + GPIO_CORE_CPU2_CLA1 //!< CPU2's CLA1 selected as controller core +} GPIO_CoreSelect; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(), +//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_PORT_A = 0, //!< GPIO port A + GPIO_PORT_B = 1, //!< GPIO port B + GPIO_PORT_C = 2, //!< GPIO port C + GPIO_PORT_D = 3, //!< GPIO port D + GPIO_PORT_E = 4, //!< GPIO port E + GPIO_PORT_F = 5 //!< GPIO port F +} GPIO_Port; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptPin(), +//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(), +//! GPIO_disableInterrupt(), as the \e extIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_XINT1, //!< External Interrupt 1 + GPIO_INT_XINT2, //!< External Interrupt 2 + GPIO_INT_XINT3, //!< External Interrupt 3 + GPIO_INT_XINT4, //!< External Interrupt 4 + GPIO_INT_XINT5 //!< External Interrupt 5 +} GPIO_ExternalIntNum; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks that a pin number is valid for a device. +//! +//! Note that this function reflects the highest possible GPIO number of a +//! device on its biggest package. Check the datasheet to see what the actual +//! range of valid pin numbers is for a specific package. +//! +//! \return None. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +GPIO_isPinValid(uint32_t pin) +{ + return(pin <= 168U); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin. +//! +//! \param extIntNum specifies the external interrupt. +//! \param intType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin on the selected GPIO port. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! One of the following flags can be used to define the \e intType +//! parameter: +//! +//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to +//! falling +//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising +//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType) +{ + // + // Write the selected polarity to the appropriate register. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) = + (HWREGH(XINT_BASE + (uint16_t)extIntNum) & ~XINT_1CR_POLARITY_M) | + (uint16_t)intType; +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function gets the interrupt type for a interrupt. The interrupt can be +//! configured as a falling-edge, rising-edge, or both-edges detected +//! interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return Returns one of the flags described for GPIO_setInterruptType(). +// +//***************************************************************************** +static inline GPIO_IntType +GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum) +{ + // + // Read the selected polarity from the appropriate register. + // + return((GPIO_IntType)((uint16_t)(HWREGH(XINT_BASE + (uint16_t)extIntNum) & + XINT_1CR_POLARITY_M))); +} + +//***************************************************************************** +// +//! Enables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function enables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Set the enable bit for the specified interrupt. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) |= XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Disables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function disables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Clear the enable bit for the specified interrupt + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) &= ~XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Gets the value of the external interrupt counter. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns external interrupt counter value. +// +//***************************************************************************** +static inline uint16_t +GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum) +{ + ASSERT(extIntNum <= GPIO_INT_XINT3); + + // + // Read the counter value from the appropriate register. + // + return((HWREGH(XINT_BASE + XINT_O_1CTR + (uint16_t)extIntNum))); +} + +//***************************************************************************** +// +//! Reads the value present on the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! The value at the specified pin are read, as specified by \e pin. The value +//! is returned for both input and output pins. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return Returns the value in the data register for the specified pin. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + return((gpioDataReg[GPIO_GPxDAT_INDEX] >> (pin % 32U)) & (uint32_t)0x1U); +} + + +//***************************************************************************** +// +//! Writes a value to the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param outVal is the value to write to the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePin(uint32_t pin, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + pinMask = (uint32_t)1U << (pin % 32U); + + if(outVal == 0U) + { + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; + } + else + { + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; + } +} + +//***************************************************************************** +// +//! Toggles the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = (uint32_t)1U << (pin % 32U); +} + +//***************************************************************************** +// +//! Reads the data on the specified port. +//! +//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X +//! where X is the port letter. +//! +//! \return Returns the value available on pin for the specified port. Each +//! bit of the the return value represents a pin on the port, where bit 0 +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPortData(GPIO_Port port) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and return DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + return(gpioDataReg[GPIO_GPxDAT_INDEX]); +} + + +//***************************************************************************** +// +//! Writes a value to the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param outVal is the value to write to the port. +//! +//! This function writes the value \e outVal to the port specified by the +//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X +//! is the port letter. For example, use \b GPIO_PORT_A to affect port A +//! (GPIOs 0-31). +//! +//! The \e outVal is a bit-packed value, where each bit represents a bit on a +//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port +//! pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePortData(GPIO_Port port, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxDAT_INDEX] = outVal; +} + +//***************************************************************************** +// +//! Sets all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function sets all of the pins specified by the \e pinMask parameter on +//! the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO +//! port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to SET. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Clears all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function clears all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is \b set +//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1 +//! represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to CLEAR. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Toggles all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function toggles all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to TOGGLE. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Locks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function locks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that this function is for locking the configuration of a pin such as +//! the pin muxing, direction, open drain mode, and other settings. It does not +//! affect the ability to change the value of the pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function unlocks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] &= ~pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function commits the lock configuration registers of the pins +//! specified by the \e pinMask parameter on the port specified by the \e port +//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the +//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that once this function is called, GPIO_lockPortConfig() and +//! GPIO_unlockPortConfig() will no longer have any effect on the specified +//! pins. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxCR_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinIO is the pin direction mode. +//! +//! This function configures the specified pin on the selected GPIO port as +//! either input or output. +//! +//! The parameter \e pinIO is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input +//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO); + +//***************************************************************************** +// +//! Gets the direction mode of a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function gets the direction mode for a specified pin. The pin can be +//! configured as either an input or output The type of direction is returned +//! as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIO_setDirectionMode(). +// +//***************************************************************************** +extern GPIO_Direction +GPIO_getDirectionMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the pin for the specified external interrupt. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param extIntNum specifies the external interrupt. +//! +//! This function sets which pin triggers the selected external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \sa XBAR_setInputPin() +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum); + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinType specifies the pin type. +//! +//! This function sets the pin type for the specified pin. The parameter +//! \e pinType can be the following values: +//! +//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input +//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input +//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin +//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input +//! +//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or +//! \b GPIO_PIN_TYPE_PULLUP. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType); + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function returns the pin type for the specified pin. The value +//! returned corresponds to the values used in GPIO_setPadConfig(). +//! +//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD, +//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT. +// +//***************************************************************************** +extern uint32_t +GPIO_getPadConfig(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification mode for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param qualification specifies the qualification mode of the pin. +//! +//! This function sets the qualification mode for the specified pin. The +//! parameter \e qualification can be one of the following values: +//! - \b GPIO_QUAL_SYNC +//! - \b GPIO_QUAL_3SAMPLE +//! - \b GPIO_QUAL_6SAMPLE +//! - \b GPIO_QUAL_ASYNC +//! +//! To set the qualification sampling period, use +//! GPIO_setQualificationPeriod(). +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification); + +//***************************************************************************** +// +//! Gets the qualification type for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! \return Returns the qualification mode in the form of one of the values +//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or +//! \b GPIO_QUAL_ASYNC. +// +//***************************************************************************** +extern GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification period for a set of pins +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param divider specifies the output drive strength. +//! +//! This function sets the qualification period for a set of \b 8 \b pins, +//! specified by the \e pin parameter. For instance, passing in 3 as the value +//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a +//! value of 98 will set the qualification period for GPIO96 through GPIO103. +//! This is because the register field that configures the divider is shared. +//! +//! To think of this in terms of an equation, configuring \e pin as \b n will +//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7). +//! +//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It +//! can be 1 or an even value between 2 and 510 inclusive. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider); + +//***************************************************************************** +// +//! Selects the controller core of a specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param core is the core that is controller of the specified pin. +//! +//! This function configures which core owns the specified pin's data registers +//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data +//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's +//! CLA1 controller of the pin. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core); + +//***************************************************************************** +// +//! Sets the analog mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param mode is the selected analog mode. +//! +//! This function configures the specified pin for either analog or digital +//! mode. Not all GPIO pins have the ability to be switched to analog mode, +//! so refer to the technical reference manual for details. This setting should +//! be thought of as another level of muxing. +//! +//! The parameter \e mode is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode +//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \b Note: The pin parameter is applicable for both AIO and GPIO because +//! the GPAxMSEL.GPIOy register configures for both +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode); + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param pinConfig is the pin configuration value, specified as only one +//! of the \b GPIO_#_???? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). +//! +//! The available mappings are supplied in pin_map.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPinConfig(uint32_t pinConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // GPIO_H diff --git a/gpio_bitfield_cpu2/device/driverlib/hrpwm.c b/gpio_bitfield_cpu2/device/driverlib/hrpwm.c new file mode 100644 index 0000000..04aa22c --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/hrpwm.c @@ -0,0 +1,47 @@ +//########################################################################### +// +// FILE: hrpwm.c +// +// TITLE: C28x HRPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "hrpwm.h" + +// +// All the API functions are in-lined in hrpwm.h +// diff --git a/gpio_bitfield_cpu2/device/driverlib/hrpwm.h b/gpio_bitfield_cpu2/device/driverlib/hrpwm.h new file mode 100644 index 0000000..2561d67 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/hrpwm.h @@ -0,0 +1,1657 @@ +//############################################################################# +// +// FILE: hrpwm.h +// +// TITLE: C28x HRPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef HRPWM_H +#define HRPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup hrpwm_api HRPWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_hrpwm.h" +#include "cpu.h" +#include "debug.h" +#include "epwm.h" +#include "hrpwm.h" + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect(), +//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent() +//! as the \e channel parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_CHANNEL_A = 0, //!< HRPWM A + HRPWM_CHANNEL_B = 8 //!< HRPWM B +} HRPWM_Channel; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_MEP_CTRL_DISABLE = 0, + //! MEP controls rising edge + HRPWM_MEP_CTRL_RISING_EDGE = 1, + //! MEP controls falling edge + HRPWM_MEP_CTRL_FALLING_EDGE = 2, + //! MEP controls both rising and falling edge + HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3 +} HRPWM_MEPEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge + HRPWM_MEP_DUTY_PERIOD_CTRL = 0, + //! TBPHSHR controls MEP edge + HRPWM_MEP_PHASE_CTRL = 1 +} HRPWM_MEPCtrlMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(), +//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode +//! as the \e loadEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! load when counter equals zero + HRPWM_LOAD_ON_CNTR_ZERO = 0, + //! load when counter equals period + HRPWM_LOAD_ON_CNTR_PERIOD = 1, + //! load when counter equals zero or period + HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2, +} HRPWM_LoadMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e +//! outputOnB parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal. + HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted + //!< version of ePWMxA signal +} HRPWM_ChannelBOutput; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e +//! syncPulseSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Counter equals Period + HRPWM_PWMSYNC_SOURCE_PERIOD = 0, + //! Counter equals zero + HRPWM_PWMSYNC_SOURCE_ZERO = 1, + //! Counter equals COMPC when counting up + HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4, + //! Counter equals COMPC when counting down + HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5, + //! Counter equals COMPD when counting up + HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6, + //! Counter equals COMPD when counting down + HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7 +} HRPWM_SyncPulseSource; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e +//! compModule parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A + HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B +} HRPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e +//! mepDBEdge. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_DB_MEP_CTRL_DISABLE = 0, + //! MEP controls Rising Edge Delay + HRPWM_DB_MEP_CTRL_RED = 1, + //! MEP controls Falling Edge Delay + HRPWM_DB_MEP_CTRL_FED = 2, + //! MEP controls both Falling and Rising edge delay + HRPWM_DB_MEP_CTRL_RED_FED = 3 +} HRPWM_MEPDeadBandEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup +//! parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group + HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group + HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group + HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group + HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group +} HRPWM_LockRegisterGroup; + +//***************************************************************************** +// +// Functions APIs shared with ePWM module +// +//***************************************************************************** + +// +// Time Base Sub Module related APIs +// +#define HRPWM_setTimeBaseCounter EPWM_setTimeBaseCounter +#define HRPWM_setCountModeAfterSync EPWM_setCountModeAfterSync +#define HRPWM_setClockPrescaler EPWM_setClockPrescaler +#define HRPWM_swForceSyncPulse EPWM_forceSyncPulse +#define HRPWM_setSyncOutPulseMode EPWM_setSyncOutPulseMode +#define HRPWM_setPeriodLoadMode EPWM_setPeriodLoadMode +#define HRPWM_setTimeBaseCounterMode EPWM_setTimeBaseCounterMode +#define HRPWM_selectPeriodLoadEvent EPWM_selectPeriodLoadEvent +#define HRPWM_enableOneShotSync EPWM_enableOneShotSync +#define HRPWM_disableOneShotSync EPWM_disableOneShotSync +#define HRPWM_startOneShotSync EPWM_startOneShotSync +#define HRPWM_getTimeBaseCounterOverflowStatus \ + EPWM_getTimeBaseCounterOverflowStatus +#define HRPWM_clearTimeBaseCounterOverflowEvent \ + EPWM_clearTimeBaseCounterOverflowEvent +#define HRPWM_getSyncStatus EPWM_getSyncStatus +#define HRPWM_clearSyncEvent EPWM_clearSyncEvent +#define HRPWM_getTimeBaseCounterDirection EPWM_getTimeBaseCounterDirection +#define HRPWM_setupEPWMLinks EPWM_setupEPWMLinks +#define HRPWM_setCounterCompareShadowLoadMode \ + EPWM_setCounterCompareShadowLoadMode +#define HRPWM_disableCounterCompareShadowLoadMode \ + EPWM_disableCounterCompareShadowLoadMode +#define HRPWM_getCounterCompareShadowStatus \ + EPWM_getCounterCompareShadowStatus + +// +// Action Qualifier module related APIs +// +#define HRPWM_setActionQualifierShadowLoadMode \ + EPWM_setActionQualifierShadowLoadMode +#define HRPWM_disableActionQualifierShadowLoadMode \ + EPWM_disableActionQualifierShadowLoadMode +#define HRPWM_setActionQualifierT1TriggerSource \ + EPWM_setActionQualifierT1TriggerSource +#define HRPWM_setActionQualifierT2TriggerSource \ + EPWM_setActionQualifierT2TriggerSource +#define HRPWM_setActionQualifierAction EPWM_setActionQualifierAction +#define HRPWM_setActionQualifierContSWForceShadowMode \ + EPWM_setActionQualifierContSWForceShadowMode +#define HRPWM_setActionQualifierContSWForceAction \ + EPWM_setActionQualifierContSWForceAction +/* HRPWM_setActionQualifierSwAction is kept for compatibility, +use HRPWM_setActionQualifierSWAction*/ +#define HRPWM_setActionQualifierSwAction EPWM_setActionQualifierSwAction +#define HRPWM_setActionQualifierSWAction EPWM_setActionQualifierSWAction +/* HRPWM_forceActionQualifierSwAction is kept for compatibility, +use HRPWM_forceActionQualifierSWAction*/ +#define HRPWM_forceActionQualifierSwAction EPWM_forceActionQualifierSwAction +#define HRPWM_forceActionQualifierSWAction EPWM_forceActionQualifierSWAction +// +// Dead Band Module related APIs +// +#define HRPWM_setDeadBandOutputSwapMode EPWM_setDeadBandOutputSwapMode +#define HRPWM_setDeadBandDelayMode EPWM_setDeadBandDelayMode +#define HRPWM_setDeadBandDelayPolarity EPWM_setDeadBandDelayPolarity +#define HRPWM_setRisingEdgeDeadBandDelayInput \ + EPWM_setRisingEdgeDeadBandDelayInput +#define HRPWM_setFallingEdgeDeadBandDelayInput \ + EPWM_setFallingEdgeDeadBandDelayInput +#define HRPWM_setDeadBandControlShadowLoadMode \ + EPWM_setDeadBandControlShadowLoadMode +#define HRPWM_disableDeadBandControlShadowLoadMode \ + EPWM_disableDeadBandControlShadowLoadMode +#define HRPWM_setRisingEdgeDelayCountShadowLoadMode \ + EPWM_setRisingEdgeDelayCountShadowLoadMode +#define HRPWM_disableRisingEdgeDelayCountShadowLoadMode \ + EPWM_disableRisingEdgeDelayCountShadowLoadMode +#define HRPWM_setFallingEdgeDelayCountShadowLoadMode \ + EPWM_setFallingEdgeDelayCountShadowLoadMode +#define HRPWM_disableFallingEdgeDelayCountShadowLoadMode \ + EPWM_disableFallingEdgeDelayCountShadowLoadMode +#define HRPWM_setDeadBandCounterClock EPWM_setDeadBandCounterClock +#define HRPWM_setRisingEdgeDelayCount EPWM_setRisingEdgeDelayCount +#define HRPWM_setFallingEdgeDelayCount EPWM_setFallingEdgeDelayCount + +// +// Chopper module related APIs +// +#define HRPWM_enableChopper EPWM_enableChopper +#define HRPWM_disableChopper EPWM_disableChopper +#define HRPWM_setChopperDutyCycle EPWM_setChopperDutyCycle +#define HRPWM_setChopperFreq EPWM_setChopperFreq +#define HRPWM_setChopperFirstPulseWidt EPWM_setChopperFirstPulseWidth + +// +// Trip Zone module related APIs +// +#define HRPWM_enableTripZoneSignals EPWM_enableTripZoneSignals +#define HRPWM_disableTripZoneSignals EPWM_disableTripZoneSignals +#define HRPWM_setTripZoneDigitalCompareEventCondition \ + EPWM_setTripZoneDigitalCompareEventCondition +#define HRPWM_enableTripZoneAdvAction EPWM_enableTripZoneAdvAction +#define HRPWM_disableTripZoneAdvAction EPWM_disableTripZoneAdvAction +#define HRPWM_setTripZoneAction EPWM_setTripZoneAction +#define HRPWM_setTripZoneAdvAction EPWM_setTripZoneAdvAction +#define HRPWM_setTripZoneAdvDigitalCompareActionA \ + EPWM_setTripZoneAdvDigitalCompareActionA +#define HRPWM_setTripZoneAdvDigitalCompareActionB \ + EPWM_setTripZoneAdvDigitalCompareActionB +#define HRPWM_enableTripZoneInterrupt EPWM_enableTripZoneInterrupt +#define HRPWM_disableTripZoneInterrupt EPWM_disableTripZoneInterrupt + +// +// HRPWM_getTripZoneInterruptStatus API define is obsolete please use +// HRPWM_getTripZoneFlagStatus going forward. +// +#define HRPWM_getTripZoneInterruptStatus EPWM_getTripZoneFlagStatus +#define HRPWM_getTripZoneFlagStatus EPWM_getTripZoneFlagStatus + +// +// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete +// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward. +// +#define HRPWM_getCycleByCycleTripZoneInterruptStatus \ + HRPWM_getCycleByCycleTripZoneFlagStatus +#define HRPWM_getCycleByCycleTripZoneFlagStatus \ + EPWM_getCycleByCycleTripZoneFlagStatus + +// +// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use +// HRPWM_getOneShotTripZoneFlagStatus going forward. +// +#define HRPWM_getOneShotTripZoneInterruptStatus \ + HRPWM_getOneShotTripZoneFlagStatus +#define HRPWM_getOneShotTripZoneFlagStatus \ + EPWM_getOneShotTripZoneFlagStatus +#define HRPWM_selectCycleByCycleTripZoneClearEvent \ + EPWM_selectCycleByCycleTripZoneClearEvent + +// +// HRPWM_clearTripZoneInterruptFlag is obsolete please use +// HRPWM_clearTripZoneFlag going forward. +// +#define HRPWM_clearTripZoneInterruptFlag HRPWM_clearTripZoneFlag +#define HRPWM_clearTripZoneFlag EPWM_clearTripZoneFlag + +// +// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use +// HRPWM_clearCycleByCycleTripZoneFlag going forward. +// +#define HRPWM_clearCycleByCycleTripZoneInterruptFlag \ + HRPWM_clearCycleByCycleTripZoneFlag +#define HRPWM_clearCycleByCycleTripZoneFlag \ + EPWM_clearCycleByCycleTripZoneFlag + +// +// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use +// HRPWM_clearOneShotTripZoneFlag going forward. +// +#define HRPWM_clearOneShotTripZoneInterruptFlag \ + HRPWM_clearOneShotTripZoneFlag +#define HRPWM_clearOneShotTripZoneFlag \ + EPWM_clearOneShotTripZoneFlag +#define HRPWM_forceTripZoneEvent EPWM_forceTripZoneEvent + +// +// Event Trigger related APIs +// +#define HRPWM_enableInterrupt EPWM_enableInterrupt +#define HRPWM_disableInterrupt EPWM_disableInterrupt +#define HRPWM_setInterruptSource EPWM_setInterruptSource +#define HRPWM_setInterruptEventCount EPWM_setInterruptEventCount +#define HRPWM_getEventTriggerInterruptStatus \ + EPWM_getEventTriggerInterruptStatus +#define HRPWM_clearEventTriggerInterruptFlag \ + EPWM_clearEventTriggerInterruptFlag +#define HRPWM_enableInterruptEventCountInit \ + EPWM_enableInterruptEventCountInit +#define HRPWM_disableInterruptEventCountInit \ + EPWM_disableInterruptEventCountInit +#define HRPWM_forceInterruptEventCountInit \ + EPWM_forceInterruptEventCountInit +#define HRPWM_setInterruptEventCountInitValue \ + EPWM_setInterruptEventCountInitValue +#define HRPWM_getInterruptEventCount EPWM_getInterruptEventCount +#define HRPWM_forceEventTriggerInterrupt EPWM_forceEventTriggerInterrupt + +// +// ADC SOC configuration related APIs +// +#define HRPWM_enableADCTrigger EPWM_enableADCTrigger +#define HRPWM_disableADCTrigger EPWM_disableADCTrigger +#define HRPWM_setADCTriggerSource EPWM_setADCTriggerSource +#define HRPWM_setADCTriggerEventPrescale EPWM_setADCTriggerEventPrescale +#define HRPWM_getADCTriggerFlagStatus EPWM_getADCTriggerFlagStatus +#define HRPWM_clearADCTriggerFlag EPWM_clearADCTriggerFlag +#define HRPWM_enableADCTriggerEventCountInit \ + EPWM_enableADCTriggerEventCountInit +#define HRPWM_disableADCTriggerEventCountInit \ + EPWM_disableADCTriggerEventCountInit +#define HRPWM_forceADCTriggerEventCountInit \ + EPWM_forceADCTriggerEventCountInit +#define HRPWM_setADCTriggerEventCountInitValue \ + EPWM_setADCTriggerEventCountInitValue +#define HRPWM_getADCTriggerEventCount EPWM_getADCTriggerEventCount +#define HRPWM_forceADCTrigger EPWM_forceADCTrigger + +// +// Digital Compare Module related APIs +// +#define HRPWM_selectDigitalCompareTripInput \ + EPWM_selectDigitalCompareTripInput +#define HRPWM_enableDigitalCompareBlankingWindow \ + EPWM_enableDigitalCompareBlankingWindow +#define HRPWM_disableDigitalCompareBlankingWindow \ + EPWM_disableDigitalCompareBlankingWindow +#define HRPWM_enableDigitalCompareWindowInverseMode \ + EPWM_enableDigitalCompareWindowInverseMode +#define HRPWM_disableDigitalCompareWindowInverseMode \ + EPWM_disableDigitalCompareWindowInverseMode +#define HRPWM_setDigitalCompareBlankingEvent \ + EPWM_setDigitalCompareBlankingEvent +#define HRPWM_setDigitalCompareFilterInput \ + EPWM_setDigitalCompareFilterInput +#define HRPWM_setDigitalCompareWindowOffset \ + EPWM_setDigitalCompareWindowOffset +#define HRPWM_setDigitalCompareWindowLength \ + EPWM_setDigitalCompareWindowLength +#define HRPWM_getDigitalCompareBlankingWindowOffsetCount \ + EPWM_getDigitalCompareBlankingWindowOffsetCount +#define HRPWM_getDigitalCompareBlankingWindowLengthCount \ + EPWM_getDigitalCompareBlankingWindowLengthCount +#define HRPWM_setDigitalCompareEventSource \ + EPWM_setDigitalCompareEventSource +#define HRPWM_setDigitalCompareEventSyncMode \ + EPWM_setDigitalCompareEventSyncMode +#define HRPWM_enableDigitalCompareADCTrigger \ + EPWM_enableDigitalCompareADCTrigger +#define HRPWM_disableDigitalCompareADCTrigger \ + EPWM_disableDigitalCompareADCTrigger +#define HRPWM_enableDigitalCompareSyncEvent \ + EPWM_enableDigitalCompareSyncEvent +#define HRPWM_disableDigitalCompareSyncEvent \ + EPWM_disableDigitalCompareSyncEvent +#define HRPWM_enableDigitalCompareCounterCapture \ + EPWM_enableDigitalCompareCounterCapture +#define HRPWM_disableDigitalCompareCounterCapture \ + EPWM_disableDigitalCompareCounterCapture +#define HRPWM_setDigitalCompareCounterShadowMode \ + EPWM_setDigitalCompareCounterShadowMode +#define HRPWM_getDigitalCompareCaptureStatus \ + EPWM_getDigitalCompareCaptureStatus +#define HRPWM_getDigitalCompareCaptureCount \ + EPWM_getDigitalCompareCaptureCount +#define HRPWM_enableDigitalCompareTripCombinationInput \ + EPWM_enableDigitalCompareTripCombinationInput +#define HRPWM_disableDigitalCompareTripCombinationInput \ + EPWM_disableDigitalCompareTripCombinationInput + +// +// Valley switching related APIs +// +#define HRPWM_enableValleyCapture EPWM_enableValleyCapture +#define HRPWM_disableValleyCapture EPWM_disableValleyCapture +#define HRPWM_startValleyCapture EPWM_startValleyCapture +#define HRPWM_setValleyTriggerSource EPWM_setValleyTriggerSource +#define HRPWM_setValleyTriggerEdgeCounts EPWM_setValleyTriggerEdgeCounts +#define HRPWM_enableValleyHWDelay EPWM_enableValleyHWDelay +#define HRPWM_disableValleyHWDelay EPWM_disableValleyHWDelay +#define HRPWM_setValleySWDelayValue EPWM_setValleySWDelayValue +#define HRPWM_setValleyDelayDivider EPWM_setValleyDelayDivider +#define HRPWM_getValleyEdgeStatus EPWM_getValleyEdgeStatus +#define HRPWM_getValleyCount EPWM_getValleyCount +#define HRPWM_getValleyHWDelay EPWM_getValleyHWDelay + +// +// Global Load feature related APIs +// +#define HRPWM_enableGlobalLoad EPWM_enableGlobalLoad +#define HRPWM_disableGlobalLoad EPWM_disableGlobalLoad +#define HRPWM_setGlobalLoadTrigger EPWM_setGlobalLoadTrigger +#define HRPWM_setGlobalLoadEventPrescale EPWM_setGlobalLoadEventPrescale +#define HRPWM_getGlobalLoadEventCount EPWM_getGlobalLoadEventCount +#define HRPWM_disableGlobalLoadOneShotMode EPWM_disableGlobalLoadOneShotMode +#define HRPWM_enableGlobalLoadOneShotMode EPWM_enableGlobalLoadOneShotMode +#define HRPWM_setGlobalLoadOneShotLatch EPWM_setGlobalLoadOneShotLatch +#define HRPWM_forceGlobalLoadOneShotEvent EPWM_forceGlobalLoadOneShotEvent +#define HRPWM_enableGlobalLoadRegisters EPWM_enableGlobalLoadRegisters +#define HRPWM_disableGlobalLoadRegisters EPWM_disableGlobalLoadRegisters +#define HRPWM_setEmulationMode EPWM_setEmulationMode + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks HRPWM base address. +//! +//! \param base specifies the HRPWM module base address. +//! +//! This function determines if an HRPWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool HRPWM_isBaseValid(uint32_t base) +{ + return((base == EPWM1_BASE) || (base == EPWM2_BASE) || + (base == EPWM3_BASE) || (base == EPWM4_BASE) || + (base == EPWM5_BASE) || (base == EPWM6_BASE) || + (base == EPWM7_BASE) || (base == EPWM8_BASE)); +} +#endif +//***************************************************************************** +// +//! Sets the consolidated phase shift value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the consolidated phase shift count value. +//! +//! This function sets the consolidated phase shift value, that is, both TBPHS +//! and TBPHSHR values are configured together. +//! +//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions +//! to enable loading of the phaseCount in high resolution mode. +//! +//! \b Note: phaseCount is a 24-bit value. +//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2; +//! phaseCount = 0x3C02 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(phaseCount < 0x1000000U); + + // + // Write to TBPHS:TBPHSHR bits + // + HWREG(base + HRPWM_O_TBPHS) = phaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution phase shift value. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPhaseCount is the high resolution phase shift count value. +//! +//! This function sets only the high resolution phase shift(TBPHSHR) value. +//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of +//! the hrPhaseCount. +//! +//! \b Note: hrPhaseCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPhaseCount < 256U); + + // + // Write to TBPHSHR bits + // + HWREGH(base + HRPWM_O_TBPHS) = hrPhaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets the consolidated period of time base counter used in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is the consolidated period count value. +//! +//! This function sets the consolidated period of time base counter value +//! (TBPRD:TBPRDHR) required in high resolution mode. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct periodCount. +//! +//! \b Note: periodCount is a 24 bit value. +//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA; +//! periodCount = 0x3C0A +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(periodCount < 0x1000000U); + + // + // Write to TBPRD:TBPRDHR bits + // + HWREG(base + HRPWM_O_TBPRDHR) = periodCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution time base counter. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPeriodCount is the high resolution period count value. +//! +//! This function sets only the high resolution time base counter(TBPRDHR) +//! value. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct hrPeriodCount. +//! +//! \b Note: hrPeriodCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPeriodCount < 256U); + + // + // Write to TBPRDHR bits + // + HWREGH(base + HRPWM_O_TBPRDHR) = hrPeriodCount << 8U; +} + +//***************************************************************************** +// +//! Gets the consolidated time base period count used in HR mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value +//! used in high resolution mode. +//! +//! \return The consolidated time base period count value. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRD:TBPRDHR bit + // + return(HWREG(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Gets the only the high resolution time base period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets only the high resolution time base period(TBPRDHR) value. +//! +//! \return The high resolution time base period count value. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResTimeBasePeriodOnly(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRDHR bit + // + return(HWREGH(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner). +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge +//! Positioner). +//! +//! This function sets the edge of the PWM that is controlled by MEP (Micro +//! Edge Positioner). Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepEdgeMode +//! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner) +//! controls rising edge. +//! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls falling edge. +//! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls both edges. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPEdgeMode mepEdgeMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << (uint16_t)channel )) | + ((uint16_t)mepEdgeMode << (uint16_t)channel)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the MEP (Micro Edge Positioner) control mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the mode (register type) the MEP (Micro Edge Positioner) +//! will control. Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepCtrlMode +//! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is +//! controlled by value of CMPAHR/ +//! CMPBHR(depending on the value of +//! channel) or TBPRDHR. +//! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is +//! controlled by TBPHSHR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPCtrlMode mepCtrlMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the MEP control + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x1U << ((uint16_t)channel + 2U))) | + ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution comparator load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param loadEvent is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the shadow load mode of the high resolution comparator. +//! The function sets the COMPA or COMPB register depending on the channel +//! variable. +//! Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - loadEvent +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the CMPAHR or CMPBHR load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << ((uint16_t)channel + 3U))) | + ((uint16_t)loadEvent << ((uint16_t)channel + 3U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableOutputSwap is the output swap flag. +//! +//! This function sets the HRPWM output swap mode. If enableOutputSwap is true, +//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA +//! output. If it is false ePWMxA and ePWMxB outputs are unchanged. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set output swap mode + // + EALLOW; + if(enableOutputSwap) + { + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_SWAPAB; + } + else + { + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_SWAPAB; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output on ePWMxB +//! +//! \param base is the base address of the EPWM module. +//! \param outputOnB is the output signal on ePWMxB. +//! +//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is +//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of +//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is +//! ePWMxB. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the output on ePWM B + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(HRPWM_HRCNFG_SELOUTB)) | + ((uint16_t)outputOnB << 5U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables MEP (Micro Edge Positioner) automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the MEP (Micro Edge Positioner) to automatically +//! scale HRMSTEP. +//! +//! The SFO library will calculate required MEP steps per coarse steps and +//! feed it to HRMSTEP register. The MEP calibration module will use the value +//! in HRMSTEP to determine appropriate number of MEP steps represented by +//! fractional duty cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Enable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Disables MEP automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the MEP (Micro Edge Positioner) from automatically +//! scaling HRMSTEP. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Disable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of high resolution phase shift value which is +//! set by the function HRPWM_setPhaseShift(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of high resolution phase shift value. +//! +//! \return +// +//***************************************************************************** +static inline void +HRPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution PWMSYNC source. +//! +//! \param base is the base address of the EPWM module. +//! \param syncPulseSource is the PWMSYNC source. +//! +//! This function sets the high resolution PWMSYNC pulse source. +//! Valid values for syncPulseSource are: +//! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period. +//! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when +//! counting down. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when +//! counting down. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource) +{ + // + // Set the PWMSYNC source + // + EALLOW; + + // + // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD + // or HRPWM_PWMSYNC_SOURCE_ZERO + // + if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP) + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & + ~(HRPWM_HRPCTL_PWMSYNCSELX_M | HRPWM_HRPCTL_PWMSYNCSEL)) | + ((uint16_t)syncPulseSource << 1U)); + } + else + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & ~HRPWM_HRPCTL_PWMSYNCSELX_M) | + ((uint16_t)syncPulseSource << HRPWM_HRPCTL_PWMSYNCSELX_S)); + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the Translator Remainder value. +//! +//! \param base is the base address of the EPWM module. +//! \param trremVal is the translator remainder value. +//! +//! This function sets the Translator Remainder value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(trremVal < 2048U); + + // + // Set Translator Remainder value + // + EALLOW; + HWREGH(base + HRPWM_O_TRREM) = (trremVal & HRPWM_TRREM_TRREM_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the consolidated counter compare values in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param compCount is the consolidated counter compare count value. +//! +//! This function sets the consolidated counter compare(CMPx:CMPxHR) value +//! required in high resolution mode for counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: compCount is a 24 bit value. +//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of +//! compCount = 0xB464 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint32_t compCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(compCount < 0x1000000U); + + // + // Write to counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPA:CMPAHR + // + HWREG(base + HRPWM_O_CMPA) = compCount << 8U; + } + else + { + // + // Write to CMPB:CMPBHR + // + HWREG(base + HRPWM_O_CMPB) = compCount << 8U; + } +} + +//***************************************************************************** +// +//! Sets only the high resolution counter compare value. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param hrCompCount is the high resolution counter compare count value. +//! +//! This function sets the high resolution counter compare value(CMPxHR) for +//! counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: hrCompCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint16_t hrCompCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrCompCount < 256U); + + // + // Write to the high resolution counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPAHR + // + HWREGH(base + HRPWM_O_CMPA) = hrCompCount << 8U; + } + else + { + // + // Write to CMPBHR + // + HWREGH(base + HRPWM_O_CMPB) = hrCompCount << 8U; + } +} + +//***************************************************************************** +// +//! Gets the consolidated counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets the consolidated counter compare(CMPx:CMPxHR) value +//! used in high resolution for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! +//! \return None. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint32_t compCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + compCount = HWREG(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + compCount = HWREG(base + HRPWM_O_CMPB) >> 8U; + } + return(compCount); +} + +//***************************************************************************** +// +//! Gets only the high resolution counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets only the high resolution counter compare(CMPxHR) value +//! for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint16_t hrCompCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPB) >> 8U; + } + return(hrCompCount); +} + +//***************************************************************************** +// +//! Sets the consolidated RED count in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the high resolution RED count. +//! +//! This function sets the consolidated RED (Rising Edge Delay) count +//! (DBRED:DBREDHR) value used in high resolution mode. The value of +//! redCount should be less than 0x200000. +//! +//! \b Note: redCount is a 21 bit value. +//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of +//! redCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(redCount < 0x200000U); + + // + // Set the consolidated RED (Rising Edge Delay) count + // + HWREG(base + HRPWM_O_DBREDHR) = redCount << 9U; +} + +//***************************************************************************** +// +//! Sets the high resolution RED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrRedCount is the high resolution RED count. +//! +//! This function sets only the high resolution RED (Rising Edge Delay) +//! count(DBREDHR) value. +//! The value of hrRedCount should be less than 128. +//! +//! \b Note: hrRedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrRedCount < 128U); + + // + // Set the High Resolution RED (Rising Edge Delay) count only + // + HWREGH(base + HRPWM_O_DBREDHR) = hrRedCount << 9U; +} + +//***************************************************************************** +// +//! Sets the consolidated FED value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the high resolution FED count. +//! +//! This function sets the consolidated FED (Falling Edge Delay) count +//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount +//! should be less than 0x200000. +//! +//! \b Note: fedCount is a 21 bit value. +//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of +//! fedCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(fedCount < 0x200000U); + + // + // Set the High Resolution FED (Falling Edge Delay) count + // + HWREG(base + HRPWM_O_DBFEDHR) = fedCount << 9U; +} + +//***************************************************************************** +// +//! Sets high resolution FED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrFedCount is the high resolution FED count. +//! +//! This function sets only the high resolution FED (Falling Edge Delay) count +//! (DBFEDHR)value. The value of hrFedCount should be less than 128. +//! +//! \b Note: hrFedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrFedCount < 128U); + + // + // Set the high resolution FED (Falling Edge Delay) count + // + HWREGH(base + HRPWM_O_DBFEDHR) = hrFedCount << 9U; +} + +//***************************************************************************** +// +//! Set high resolution MEP (Micro Edge Positioner) step. +//! +//! \param base is the base address of the EPWM module. +//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step +//! count. +//! +//! This function sets the high resolution MEP (Micro Edge Positioner) step +//! count. The maximum value for the MEP count step is 255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPStep(uint32_t base, uint16_t mepCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(mepCount < 256U); + + // + // Set HRPWM MEP count + // + EALLOW; + HWREGH(base + HRPWM_O_HRMSTEP) = + ((HWREGH(base + HRPWM_O_HRMSTEP) & ~HRPWM_HRMSTEP_HRMSTEP_M) | + mepCount); + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution Dead Band MEP (Micro Edge Positioner) control. +//! +//! \param base is the base address of the EPWM module. +//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control +//! edge. +//! +//! This function sets the high resolution Dead Band edge that the MEP (Micro +//! Edge Positioner) controls Valid values for mepDBEdge are: +//! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls +//! Rising Edge Delay +//! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls +//! Falling Edge Delay +//! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both +//! Falling and Rising edge delays +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, + HRPWM_MEPDeadBandEdgeMode mepDBEdge) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM DB edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_EDGMODEDB_M) | + ((uint16_t)mepDBEdge)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band RED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Rising Edge Delay(RED)Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM RED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBRED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBRED_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band FED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Falling Edge Delay(FED) Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM FED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBFED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBFED_S)); + EDIS; +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // HRPWM_H + diff --git a/gpio_bitfield_cpu2/device/driverlib/hw_reg_inclusive_terminology.h b/gpio_bitfield_cpu2/device/driverlib/hw_reg_inclusive_terminology.h new file mode 100644 index 0000000..d3dc018 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/hw_reg_inclusive_terminology.h @@ -0,0 +1,29 @@ +#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H +#define HW_REG_INCLUSIVE_TERMINOLOGY_H + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE +#define SPI_PRI_PTEINV SPI_PRI_STEINV + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_O_TAR I2C_O_SAR + +#define I2C_TAR_TAR_S I2C_SAR_SAR_S +#define I2C_TAR_TAR_M I2C_SAR_SAR_M + +#define I2C_IER_AAT I2C_IER_AAS + +#define I2C_STR_AAT I2C_STR_AAS +#define I2C_STR_TDIR I2C_STR_SDIR + +#define I2C_MDR_CNT I2C_MDR_MST + + + +#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H diff --git a/gpio_bitfield_cpu2/device/driverlib/i2c.c b/gpio_bitfield_cpu2/device/driverlib/i2c.c new file mode 100644 index 0000000..692f7a2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/i2c.c @@ -0,0 +1,351 @@ +//########################################################################### +// +// FILE: i2c.c +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "i2c.h" + +//***************************************************************************** +// +// I2C_initController +// +//***************************************************************************** +void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((10000000U / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (10000000U / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_initControllerModuleFrequency +// +//***************************************************************************** +void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((moduleFrequency / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (moduleFrequency / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_enableInterrupt +// +//***************************************************************************** +void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the desired basic interrupts + // + HWREGH(base + I2C_O_IER) |= (intFlags & 0xFFFFU); + + // + // Enabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) |= I2C_IER_AAT; + } + + // + // Enable desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// I2C_disableInterrupt +// +//***************************************************************************** +void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the desired basic interrupts. + // + HWREGH(base + I2C_O_IER) &= ~(intFlags & 0xFFFFU); + + // + // Disabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT; + } + + // + // Disable the desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA); + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// I2C_getInterruptStatus +// +//***************************************************************************** +uint32_t +I2C_getInterruptStatus(uint32_t base) +{ + uint32_t temp; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return only the status bits associated with interrupts. + // + temp = (uint32_t)HWREGH(base + I2C_O_STR) & (uint32_t)I2C_STR_INTMASK; + + // + // Read FIFO interrupt flags. + // + if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U) + { + temp |= I2C_INT_TXFF; + } + + if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U) + { + temp |= I2C_INT_RXFF; + } + + return(temp); +} + +//***************************************************************************** +// +// I2C_clearInterruptStatus +// +//***************************************************************************** +void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the interrupt flags that are located in STR. + // + HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK); + + // + // Clear the FIFO interrupt flags if needed. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR; + } +} +//***************************************************************************** +// +// I2C_configureModuleFrequency +// +//***************************************************************************** +void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} +//***************************************************************************** +// +// I2C_configureModuleClockFrequency +// +//***************************************************************************** +void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/i2c.h b/gpio_bitfield_cpu2/device/driverlib/i2c.h new file mode 100644 index 0000000..634c4c8 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/i2c.h @@ -0,0 +1,1386 @@ +//########################################################################### +// +// FILE: i2c.h +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef I2C_H +#define I2C_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup i2c_api I2C +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// I2C Controller commands. +// +//***************************************************************************** +#define I2C_CONTROLLER_SEND_MODE 0x0600U //!< Controller-transmitter mode +#define I2C_CONTROLLER_RECEIVE_MODE 0x0400U //!< Controller-receiver mode +#define I2C_TARGET_SEND_MODE 0x0200U //!< Target-transmitter mode +#define I2C_TARGET_RECEIVE_MODE 0x0000U //!< Target-receiver mode + +#define I2C_REPEAT_MODE 0x0080U //!< Only applies to Controller mode +#define I2C_START_BYTE_MODE 0x0010U //!< Enable start byte mode +#define I2C_FREE_DATA_FORMAT 0x0008U //!< Enable free data (no addr) format + +//***************************************************************************** +// +// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(), +// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by +// I2C_getInterruptStatus(). +// +//***************************************************************************** +#define I2C_INT_ARB_LOST 0x00001U //!< Arbitration-lost interrupt +#define I2C_INT_NO_ACK 0x00002U //!< NACK interrupt +#define I2C_INT_REG_ACCESS_RDY 0x00004U //!< Register-access-ready interrupt +#define I2C_INT_RX_DATA_RDY 0x00008U //!< Receive-data-ready interrupt +#define I2C_INT_TX_DATA_RDY 0x00010U //!< Transmit-data-ready interrupt +#define I2C_INT_STOP_CONDITION 0x00020U //!< Stop condition detected +#define I2C_INT_ADDR_TARGET 0x00200U //!< Addressed as target interrupt +#define I2C_INT_RXFF 0x10000U //!< RX FIFO level interrupt +#define I2C_INT_TXFF 0x20000U //!< TX FIFO level interrupt + + +// +// Helpful define to mask out the bits in the I2CSTR register that aren't +// associated with interrupts. +// +#define I2C_STR_INTMASK ((uint16_t)I2C_INT_ARB_LOST | \ + (uint16_t)I2C_INT_NO_ACK | \ + (uint16_t)I2C_INT_REG_ACCESS_RDY | \ + (uint16_t)I2C_INT_RX_DATA_RDY | \ + (uint16_t)I2C_INT_TX_DATA_RDY | \ + (uint16_t)I2C_INT_STOP_CONDITION | \ + (uint16_t)I2C_INT_ADDR_TARGET) + + + + +//***************************************************************************** +// +// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be +// returned by I2C_getStatus(). +// +//***************************************************************************** +#define I2C_STS_ARB_LOST 0x0001U //!< Arbitration-lost +#define I2C_STS_NO_ACK 0x0002U //!< No-acknowledgment (NACK) +#define I2C_STS_REG_ACCESS_RDY 0x0004U //!< Register-access-ready (ARDY) +#define I2C_STS_RX_DATA_RDY 0x0008U //!< Receive-data-ready +#define I2C_STS_TX_DATA_RDY 0x0010U //!< Transmit-data-ready +#define I2C_STS_STOP_CONDITION 0x0020U //!< Stop condition detected +#define I2C_STS_ADDR_ZERO 0x0100U //!< Address of all zeros detected +#define I2C_STS_ADDR_TARGET 0x0200U //!< Addressed as target +#define I2C_STS_TX_EMPTY 0x0400U //!< Transmit shift register empty +#define I2C_STS_RX_FULL 0x0800U //!< Receive shift register full +#define I2C_STS_BUS_BUSY 0x1000U //!< Bus busy, wait for STOP or reset +#define I2C_STS_NACK_SENT 0x2000U //!< NACK was sent +#define I2C_STS_TARGET_DIR 0x4000U //!< Addressed as target transmitter + +#endif + + +//***************************************************************************** +// +//! I2C interrupts to be returned by I2C_getInterruptSource(). +// +//***************************************************************************** +typedef enum +{ + I2C_INTSRC_NONE, //!< No interrupt pending + I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt + I2C_INTSRC_NO_ACK, //!< NACK interrupt + I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt + I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt + I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt + I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected + I2C_INTSRC_ADDR_TARGET, //!< Addressed as target interrupt +} I2C_InterruptSource; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by I2C_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} I2C_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by I2C_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full +} I2C_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setBitCount() as the \e size parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte + I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte + I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte + I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte + I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte + I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte + I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte + I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte +} I2C_BitCount; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address + I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address +} I2C_AddressMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! If SCL is low, keep it low. If high, stop when it goes low again. + I2C_EMULATION_STOP_SCL_LOW = 0x0000U, + //! Continue I2C operation regardless + I2C_EMULATION_FREE_RUN = 0x4000U +} I2C_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_initController() as the \e dutyCycle +//! parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33% + I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55% +} I2C_DutyCycle; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +I2C_isBaseValid(uint32_t base) +{ + return( + (base == I2CA_BASE) || + (base == I2CB_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) |= I2C_MDR_IRS; +} + +//***************************************************************************** +// +//! Disables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) &= ~(I2C_MDR_IRS); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions enables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST; + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions disables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST); + HWREGH(base + I2C_O_FFRX) &= ~I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or +//! \b I2C_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or +//! \b I2C_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel, + I2C_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + I2C_O_FFTX) = (HWREGH(base + I2C_O_FFTX) & + (~I2C_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + I2C_O_FFRX) = (HWREGH(base + I2C_O_FFRX) & + (~I2C_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, +//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, +//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel, + I2C_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (I2C_TxFIFOLevel)(HWREGH(base + I2C_O_FFTX) & + I2C_FFTX_TXFFIL_M); + *rxLevel = (I2C_RxFIFOLevel)(HWREGH(base + I2C_O_FFRX) & + I2C_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3, +//! ..., or \b I2C_FIFO_TX16 +// +//***************************************************************************** +static inline I2C_TxFIFOLevel +I2C_getTxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFST_M) >> + I2C_FFTX_TXFFST_S); + + return((I2C_TxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3, +//! ..., or \b I2C_FIFO_RX16 +// +//***************************************************************************** +static inline I2C_RxFIFOLevel +I2C_getRxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFST_M) >> + I2C_FFRX_RXFFST_S); + + return((I2C_RxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Reads I2C Module clock prescaler value. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads the I2C prescaler value which configures the I2C module +//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + ) +//! +//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getPreScaler(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the Prescaler register. + // + return(HWREGH(base + I2C_O_PSC)); +} + +//***************************************************************************** +// +//! Sets the address that the I2C Controller places on the bus. +//! +//! \param base is the base address of the I2C instance used. +//! \param targetAddr 7-bit or 10-bit target address +//! +//! This function configures the address that the I2C Controller places on the bus +//! when initiating a transaction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setTargetAddress(uint32_t base, uint16_t targetAddr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(targetAddr <= I2C_TAR_TAR_M); + + HWREGH(base + I2C_O_TAR) = targetAddr; +} + +//***************************************************************************** +// +//! Sets the own address for this I2C module. +//! +//! \param base is the base address of the I2C Target module. +//! \param Addr is the 7-bit or 10-bit address +//! +//! This function writes the specified address. +//! +//! The parameter \e Addr is the value that is compared against the +//! target address sent by an I2C controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setOwnAddress(uint32_t base, uint16_t Addr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(Addr <= I2C_OAR_OAR_M); + + HWREGH(base + I2C_O_OAR) = Addr; +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-controller environment to determine if the +//! bus is free for another data transfer. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +static inline bool +I2C_isBusBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + return((HWREGH(base + I2C_O_STR) & I2C_STR_BB) == I2C_STR_BB); +} + +//***************************************************************************** +// +//! Gets the current I2C module status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the status for the I2C module. +//! +//! \return The current module status, enumerated as a bit field of +//! - \b I2C_STS_ARB_LOST - Arbitration-lost +//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK) +//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY) +//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready +//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready +//! - \b I2C_STS_STOP_CONDITION - Stop condition detected +//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected +//! - \b I2C_STS_ADDR_TARGET - Addressed as Target +//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty +//! - \b I2C_STS_RX_FULL - Receive shift register full +//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset +//! - \b I2C_STS_NACK_SENT - NACK was sent +//! - \b I2C_STS_TARGET_DIR- Addressed as Target transmitter +// +//***************************************************************************** +static inline uint16_t +I2C_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return contents of the status register + // + return(HWREGH(base + I2C_O_STR)); +} + +//***************************************************************************** +// +//! Clears I2C status flags. +//! +//! \param base is the base address of the I2C instance used. +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! +//! This function clears the specified I2C status flags. The \e stsFlags +//! parameter is the logical OR of the following values: +//! - \b I2C_STS_ARB_LOST +//! - \b I2C_STS_NO_ACK, +//! - \b I2C_STS_REG_ACCESS_RDY +//! - \b I2C_STS_RX_DATA_RDY +//! - \b I2C_STS_STOP_CONDITION +//! - \b I2C_STS_NACK_SENT +//! - \b I2C_STS_TARGET_DIR +//! +//! \note Note that some of the status flags returned by I2C_getStatus() cannot +//! be cleared by this function. Some may only be cleared by hardware or a +//! reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_clearStatus(uint32_t base, uint16_t stsFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write to the status registers to clear them. + // + HWREGH(base + I2C_O_STR) = stsFlags; +} + +//***************************************************************************** +// +//! Controls the state of the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param config is the command to be issued to the I2C module. +//! +//! This function is used to control the state of the controller and target send and +//! receive operations. The \e config is a logical OR of the following options. +//! +//! One of the following four options: +//! - \b I2C_CONTROLLER_SEND_MODE - Controller-transmitter mode +//! - \b I2C_CONTROLLER_RECEIVE_MODE - Controller-receiver mode +//! - \b I2C_TARGET_SEND_MODE - Target-transmitter mode +//! - \b I2C_TARGET_RECEIVE_MODE - Target-receiver mode +//! +//! Any of the following: +//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count +//! - \b I2C_START_BYTE_MODE - Use start byte mode +//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & + ~(I2C_MDR_CNT | I2C_MDR_TRX | I2C_MDR_RM | + I2C_MDR_STB | I2C_MDR_FDF)) | config; +} + +//***************************************************************************** +// +//! Sets the data byte bit count the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param size is the number of bits per data byte. +//! +//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of +//! bits per data byte. The default and maximum size is 8 bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setBitCount(uint32_t base, I2C_BitCount size) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_BC_M) | + (uint16_t)size; +} + +//***************************************************************************** +// +//! Issues an I2C START condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a start condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStartCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the START condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STT; +} + +//***************************************************************************** +// +//! Issues an I2C STOP condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a stop condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! To check on the status of the STOP condition, I2C_getStopConditionStatus() +//! can be used. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStopCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the STOP condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STP; +} + +//***************************************************************************** +// +//! Issues a no-acknowledge (NACK) bit. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a NACK bit. This is only +//! applicable when the I2C module is acting as a receiver. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendNACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the NACK mode bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_NACKMOD; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads a byte of data from the I2C Data Receive Register. +//! +//! \return Returns the byte received from by the I2C cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the receive register. + // + return(HWREGH(base + I2C_O_DRR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! \param data is the data to be transmitted from the I2C Controller. +//! +//! This function places the supplied data into I2C Data Transmit Register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_putData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Place the data into the transmit register. + // + HWREGH(base + I2C_O_DXR) = data; +} + +//***************************************************************************** +// +//! Get stop condition status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads and returns the stop condition bit status. +//! +//! \return Returns \b true if the STP bit has been set by the device to +//! generate a stop condition when the internal data counter of the I2C module +//! has reached 0. Returns \b false when the STP bit is zero. This bit is +//! automatically cleared after the stop condition has been generated. +// +//***************************************************************************** +static inline bool +I2C_getStopConditionStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Check the stop condition bit and return appropriately. + // + return((HWREGH(base + I2C_O_MDR) & I2C_MDR_STP) != 0U); +} + +//***************************************************************************** +// +//! Set number of bytes to be to transfer or receive when repeat mode is off. +//! +//! \param base is the base address of the I2C instance used. +//! \param count is the value to be put in the I2C data count register. +//! +//! This function sets the number of bytes to transfer or receive when repeat +//! mode is off. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setDataCount(uint32_t base, uint16_t count) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the count value to the appropriate register. + // + HWREGH(base + I2C_O_CNT) = count; +} + +//***************************************************************************** +// +//! Sets the addressing mode to either 7-bit or 10-bit. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the address mode, 7-bit or 10-bit. +//! +//! This function configures the I2C module for either a 7-bit address +//! (default) or a 10-bit address. The \e mode parameter configures the address +//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when +//! \b I2C_ADDR_MODE_7BITS. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setAddressMode(uint32_t base, I2C_AddressMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the appropriate value to the address expansion bit. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_XA) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Sets I2C emulation mode. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the I2C operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs, +//! the I2C module stops immediately. If SCL is high, the I2C module waits +//! until SCL becomes low and then stops. +//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_FREE) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Enables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables loopback mode. This mode is only valid during controller +//! mode and is helpful during device testing as it causes data transmitted out +//! of the data transmit register to be received in data receive register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Disables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) &= ~I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Returns the current I2C interrupt source. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the event that generated an I2C basic (non-FIFO) +//! interrupt. The possible sources are the following: +//! - \b I2C_INTSRC_NONE +//! - \b I2C_INTSRC_ARB_LOST +//! - \b I2C_INTSRC_NO_ACK +//! - \b I2C_INTSRC_REG_ACCESS_RDY +//! - \b I2C_INTSRC_RX_DATA_RDY +//! - \b I2C_INTSRC_TX_DATA_RDY +//! - \b I2C_INTSRC_STOP_CONDITION +//! - \b I2C_INTSRC_ADDR_TARGET +//! +//! Calling this function will result in hardware automatically clearing the +//! current interrupt code and if ready, loading the next pending enabled +//! interrupt. It will also clear the corresponding interrupt flag if the +//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or +//! \b I2C_INTSRC_STOP_CONDITION. +//! +//! \note Note that this function differs from I2C_getInterruptStatus() in that +//! it returns a single interrupt source. I2C_getInterruptSource() will return +//! the status of all interrupt flags possible, including the flags that aren't +//! necessarily enabled to generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline I2C_InterruptSource +I2C_getInterruptSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the interrupt source value + // + return((I2C_InterruptSource)(HWREGH(base + I2C_O_ISRC) & + I2C_ISRC_INTCODE_M)); +} + + + + + + + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle); + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! \param moduleFrequency is the module clock used by I2C module +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency); + +//***************************************************************************** +// +//! Enables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt +//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt +//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt +//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt +//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt +//! - \b I2C_INT_STOP_CONDITION - Stop condition detected +//! - \b I2C_INT_ADDR_TARGET - Addressed as target interrupt +//! - \b I2C_INT_RXFF - RX FIFO level interrupt +//! - \b I2C_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Target interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current I2C interrupt status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the interrupt status for the I2C module. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! - \b I2C_INT_ARB_LOST +//! - \b I2C_INT_NO_ACK +//! - \b I2C_INT_REG_ACCESS_RDY +//! - \b I2C_INT_RX_DATA_RDY +//! - \b I2C_INT_TX_DATA_RDY +//! - \b I2C_INT_STOP_CONDITION +//! - \b I2C_INT_ADDR_TARGET +//! - \b I2C_INT_RXFF +//! - \b I2C_INT_TXFF +//! +//! \note This function will only return the status flags associated with +//! interrupts. However, a flag may be set even if its corresponding interrupt +//! is disabled. +// +//***************************************************************************** +extern uint32_t +I2C_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \note Also note that some of the status flags returned by +//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only +//! be cleared by hardware or a reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency with a given module clock +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param moduleFrequency is the rate of the module clock used by I2C module +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // I2C_H diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_adc.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_adc.h new file mode 100644 index 0000000..89bd529 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_adc.h @@ -0,0 +1,911 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the ADC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ADC_H +#define HW_ADC_H + +//************************************************************************************************* +// +// The following are defines for the ADC register offsets +// +//************************************************************************************************* +#define ADC_O_CTL1 0x0U // ADC Control 1 Register +#define ADC_O_CTL2 0x1U // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register +#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register +#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register +#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register +#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register +#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register +#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register +#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register +#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register +#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register +#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register +#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register +#define ADC_O_COUNTER 0x39U // ADC Counter Register +#define ADC_O_REV 0x3AU // ADC Revision Register +#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register +#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register +#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register +#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register +#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register +#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register +#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register +#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register +#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register +#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register +#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register +#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register +#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register +#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register +#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register +#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register +#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register +#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register +#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register + +#define ADC_O_RESULT0 0x0U // ADC Result 0 Register +#define ADC_O_RESULT1 0x1U // ADC Result 1 Register +#define ADC_O_RESULT2 0x2U // ADC Result 2 Register +#define ADC_O_RESULT3 0x3U // ADC Result 3 Register +#define ADC_O_RESULT4 0x4U // ADC Result 4 Register +#define ADC_O_RESULT5 0x5U // ADC Result 5 Register +#define ADC_O_RESULT6 0x6U // ADC Result 6 Register +#define ADC_O_RESULT7 0x7U // ADC Result 7 Register +#define ADC_O_RESULT8 0x8U // ADC Result 8 Register +#define ADC_O_RESULT9 0x9U // ADC Result 9 Register +#define ADC_O_RESULT10 0xAU // ADC Result 10 Register +#define ADC_O_RESULT11 0xBU // ADC Result 11 Register +#define ADC_O_RESULT12 0xCU // ADC Result 12 Register +#define ADC_O_RESULT13 0xDU // ADC Result 13 Register +#define ADC_O_RESULT14 0xEU // ADC Result 14 Register +#define ADC_O_RESULT15 0xFU // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register +#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register +#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register +#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//************************************************************************************************* +#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8U +#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//************************************************************************************************* +#define ADC_CTL2_PRESCALE_S 0U +#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//************************************************************************************************* +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8U +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//************************************************************************************************* +#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//************************************************************************************************* +#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//************************************************************************************************* +#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//************************************************************************************************* +#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//************************************************************************************************* +#define ADC_INTSEL1N2_INT1SEL_S 0U +#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode +#define ADC_INTSEL1N2_INT2SEL_S 8U +#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//************************************************************************************************* +#define ADC_INTSEL3N4_INT3SEL_S 0U +#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode +#define ADC_INTSEL3N4_INT4SEL_S 8U +#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//************************************************************************************************* +#define ADC_SOCPRICTL_SOCPRIORITY_S 0U +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5U +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL1_SOC0_S 0U +#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC1_S 2U +#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC2_S 4U +#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC3_S 6U +#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC4_S 8U +#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC5_S 10U +#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC6_S 12U +#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC7_S 14U +#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL2_SOC8_S 0U +#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC9_S 2U +#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC10_S 4U +#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC11_S 6U +#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC12_S 8U +#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC13_S 10U +#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC14_S 12U +#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC15_S 14U +#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//************************************************************************************************* +#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//************************************************************************************************* +#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//************************************************************************************************* +#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//************************************************************************************************* +#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//************************************************************************************************* +#define ADC_SOC0CTL_ACQPS_S 0U +#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15U +#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20U +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//************************************************************************************************* +#define ADC_SOC1CTL_ACQPS_S 0U +#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15U +#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20U +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//************************************************************************************************* +#define ADC_SOC2CTL_ACQPS_S 0U +#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15U +#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20U +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//************************************************************************************************* +#define ADC_SOC3CTL_ACQPS_S 0U +#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15U +#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20U +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//************************************************************************************************* +#define ADC_SOC4CTL_ACQPS_S 0U +#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15U +#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20U +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//************************************************************************************************* +#define ADC_SOC5CTL_ACQPS_S 0U +#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15U +#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20U +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//************************************************************************************************* +#define ADC_SOC6CTL_ACQPS_S 0U +#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15U +#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20U +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//************************************************************************************************* +#define ADC_SOC7CTL_ACQPS_S 0U +#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15U +#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20U +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//************************************************************************************************* +#define ADC_SOC8CTL_ACQPS_S 0U +#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15U +#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20U +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//************************************************************************************************* +#define ADC_SOC9CTL_ACQPS_S 0U +#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15U +#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20U +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//************************************************************************************************* +#define ADC_SOC10CTL_ACQPS_S 0U +#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15U +#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20U +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//************************************************************************************************* +#define ADC_SOC11CTL_ACQPS_S 0U +#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15U +#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20U +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//************************************************************************************************* +#define ADC_SOC12CTL_ACQPS_S 0U +#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15U +#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20U +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//************************************************************************************************* +#define ADC_SOC13CTL_ACQPS_S 0U +#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15U +#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20U +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//************************************************************************************************* +#define ADC_SOC14CTL_ACQPS_S 0U +#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15U +#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20U +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//************************************************************************************************* +#define ADC_SOC15CTL_ACQPS_S 0U +#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15U +#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20U +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//************************************************************************************************* +#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//************************************************************************************************* +#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//************************************************************************************************* +#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//************************************************************************************************* +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOSDETECT register +// +//************************************************************************************************* +#define ADC_OSDETECT_DETECTCFG_S 0U +#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//************************************************************************************************* +#define ADC_COUNTER_FREECOUNT_S 0U +#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCREV register +// +//************************************************************************************************* +#define ADC_REV_TYPE_S 0U +#define ADC_REV_TYPE_M 0xFFU // ADC Type +#define ADC_REV_REV_S 8U +#define ADC_REV_REV_M 0xFF00U // ADC Revision + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//************************************************************************************************* +#define ADC_OFFTRIM_OFFTRIM_S 0U +#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//************************************************************************************************* +#define ADC_PPB1CONFIG_CONFIG_S 0U +#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//************************************************************************************************* +#define ADC_PPB1STAMP_DLYSTAMP_S 0U +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB1OFFCAL_OFFCAL_S 0U +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB1TRIPHI_LIMITHI_S 0U +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB1TRIPLO_LIMITLO_S 0U +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20U +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//************************************************************************************************* +#define ADC_PPB2CONFIG_CONFIG_S 0U +#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//************************************************************************************************* +#define ADC_PPB2STAMP_DLYSTAMP_S 0U +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB2OFFCAL_OFFCAL_S 0U +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB2TRIPHI_LIMITHI_S 0U +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB2TRIPLO_LIMITLO_S 0U +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20U +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//************************************************************************************************* +#define ADC_PPB3CONFIG_CONFIG_S 0U +#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//************************************************************************************************* +#define ADC_PPB3STAMP_DLYSTAMP_S 0U +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB3OFFCAL_OFFCAL_S 0U +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB3TRIPHI_LIMITHI_S 0U +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB3TRIPLO_LIMITLO_S 0U +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20U +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//************************************************************************************************* +#define ADC_PPB4CONFIG_CONFIG_S 0U +#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//************************************************************************************************* +#define ADC_PPB4STAMP_DLYSTAMP_S 0U +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB4OFFCAL_OFFCAL_S 0U +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB4TRIPHI_LIMITHI_S 0U +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB4TRIPLO_LIMITLO_S 0U +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20U +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//************************************************************************************************* +#define ADC_PPB1RESULT_PPBRESULT_S 0U +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB1RESULT_SIGN_S 16U +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//************************************************************************************************* +#define ADC_PPB2RESULT_PPBRESULT_S 0U +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB2RESULT_SIGN_S 16U +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//************************************************************************************************* +#define ADC_PPB3RESULT_PPBRESULT_S 0U +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB3RESULT_SIGN_S 16U +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//************************************************************************************************* +#define ADC_PPB4RESULT_PPBRESULT_S 0U +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB4RESULT_SIGN_S 16U +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_asysctl.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_asysctl.h new file mode 100644 index 0000000..4ee1c62 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_asysctl.h @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: hw_asysctl.h +// +// TITLE: Definitions for the ASYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ASYSCTL_H +#define HW_ASYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the ASYSCTL register offsets +// +//************************************************************************************************* +#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register +#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register +#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register +#define ASYSCTL_O_LOCK 0x2EU // Lock Register +#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register +#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register +#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register +#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC1TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC2TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TSNSCTL register +// +//************************************************************************************************* +#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOCK register +// +//************************************************************************************************* +#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMA register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMB register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMC register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMD register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_can.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_can.h new file mode 100644 index 0000000..05bc58b --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_can.h @@ -0,0 +1,514 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the CAN registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CAN_H +#define HW_CAN_H + +//************************************************************************************************* +// +// The following are defines for the CAN register offsets +// +//************************************************************************************************* +#define CAN_O_CTL 0x0U // CAN Control Register +#define CAN_O_ES 0x4U // Error and Status Register +#define CAN_O_ERRC 0x8U // Error Counter Register +#define CAN_O_BTR 0xCU // Bit Timing Register +#define CAN_O_INT 0x10U // Interrupt Register +#define CAN_O_TEST 0x14U // Test Register +#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register +#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register +#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register +#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register +#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register +#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register +#define CAN_O_NDAT_X 0x98U // CAN New Data Register +#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register +#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register +#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register +#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register +#define CAN_O_IF1CMD 0x100U // IF1 Command Register +#define CAN_O_IF1MSK 0x104U // IF1 Mask Register +#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110U // IF1 Data A Register +#define CAN_O_IF1DATB 0x114U // IF1 Data B Register +#define CAN_O_IF2CMD 0x120U // IF2 Command Register +#define CAN_O_IF2MSK 0x124U // IF2 Mask Register +#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130U // IF2 Data A Register +#define CAN_O_IF2DATB 0x134U // IF2 Data B Register +#define CAN_O_IF3OBS 0x140U // IF3 Observation Register +#define CAN_O_IF3MSK 0x144U // IF3 Mask Register +#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150U // IF3 Data A Register +#define CAN_O_IF3DATB 0x154U // IF3 Data B Register +#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_CTL register +// +//************************************************************************************************* +#define CAN_CTL_INIT 0x1U // Initialization +#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable +#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable +#define CAN_CTL_EIE 0x8U // Error Interrupt Enable +#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission +#define CAN_CTL_CCE 0x40U // Configuration Change Enable +#define CAN_CTL_TEST 0x80U // Test Mode Enable +#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10U +#define CAN_CTL_PMD_M 0x3C00U // Parity on/off +#define CAN_CTL_SWR 0x8000U // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status +#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ES register +// +//************************************************************************************************* +#define CAN_ES_LEC_S 0U +#define CAN_ES_LEC_M 0x7U // Last Error Code +#define CAN_ES_TXOK 0x8U // Transmission status +#define CAN_ES_RXOK 0x10U // Reception status +#define CAN_ES_EPASS 0x20U // Error Passive State +#define CAN_ES_EWARN 0x40U // Warning State +#define CAN_ES_BOFF 0x80U // Bus-Off State +#define CAN_ES_PER 0x100U // Parity Error Detected + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//************************************************************************************************* +#define CAN_ERRC_TEC_S 0U +#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter +#define CAN_ERRC_REC_S 8U +#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter +#define CAN_ERRC_RP 0x8000U // Receive Error Passive + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_BTR register +// +//************************************************************************************************* +#define CAN_BTR_BRP_S 0U +#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6U +#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8U +#define CAN_BTR_TSEG1_M 0xF00U // Time segment +#define CAN_BTR_TSEG2_S 12U +#define CAN_BTR_TSEG2_M 0x7000U // Time segment +#define CAN_BTR_BRPE_S 16U +#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_INT register +// +//************************************************************************************************* +#define CAN_INT_INT0ID_S 0U +#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier +#define CAN_INT_INT1ID_S 16U +#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TEST register +// +//************************************************************************************************* +#define CAN_TEST_SILENT 0x8U // Silent Mode +#define CAN_TEST_LBACK 0x10U // Loopback Mode +#define CAN_TEST_TX_S 5U +#define CAN_TEST_TX_M 0x60U // CANTX Pin Control +#define CAN_TEST_RX 0x80U // CANRX Pin Status +#define CAN_TEST_EXL 0x100U // External Loopback Mode +#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_PERR register +// +//************************************************************************************************* +#define CAN_PERR_MSG_NUM_S 0U +#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number +#define CAN_PERR_WORD_NUM_S 8U +#define CAN_PERR_WORD_NUM_M 0x700U // Word Number + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//************************************************************************************************* +#define CAN_RAM_INIT_KEY0 0x1U // KEY0 +#define CAN_RAM_INIT_KEY1 0x2U // KEY1 +#define CAN_RAM_INIT_KEY2 0x4U // KEY2 +#define CAN_RAM_INIT_KEY3 0x8U // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//************************************************************************************************* +#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0 +#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//************************************************************************************************* +#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//************************************************************************************************* +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//************************************************************************************************* +#define CAN_TXRQ_X_TXRQSTREG1_S 0U +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2U +#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//************************************************************************************************* +#define CAN_NDAT_X_NEWDATREG1_S 0U +#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2U +#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//************************************************************************************************* +#define CAN_IPEN_X_INTPNDREG1_S 0U +#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2U +#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//************************************************************************************************* +#define CAN_MVAL_X_MSGVALREG1_S 0U +#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2U +#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//************************************************************************************************* +#define CAN_IF1CMD_MSG_NUM_S 0U +#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//************************************************************************************************* +#define CAN_IF1MSK_MSK_S 0U +#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//************************************************************************************************* +#define CAN_IF1ARB_ID_S 0U +#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // ` +#define CAN_IF1ARB_DIR 0x20000000U // Message Direction +#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//************************************************************************************************* +#define CAN_IF1MCTL_DLC_S 0U +#define CAN_IF1MCTL_DLC_M 0xFU // Data length code +#define CAN_IF1MCTL_EOB 0x80U // End of Block +#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//************************************************************************************************* +#define CAN_IF1DATA_DATA_0_S 0U +#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8U +#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16U +#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24U +#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//************************************************************************************************* +#define CAN_IF1DATB_DATA_4_S 0U +#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8U +#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16U +#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24U +#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//************************************************************************************************* +#define CAN_IF2CMD_MSG_NUM_S 0U +#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//************************************************************************************************* +#define CAN_IF2MSK_MSK_S 0U +#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//************************************************************************************************* +#define CAN_IF2ARB_ID_S 0U +#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000U // Message Direction +#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//************************************************************************************************* +#define CAN_IF2MCTL_DLC_S 0U +#define CAN_IF2MCTL_DLC_M 0xFU // Data length code +#define CAN_IF2MCTL_EOB 0x80U // End of Block +#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//************************************************************************************************* +#define CAN_IF2DATA_DATA_0_S 0U +#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8U +#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16U +#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24U +#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//************************************************************************************************* +#define CAN_IF2DATB_DATA_4_S 0U +#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8U +#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16U +#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24U +#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//************************************************************************************************* +#define CAN_IF3OBS_MASK 0x1U // Mask data read observation +#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation +#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access +#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access +#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access +#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access +#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access +#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//************************************************************************************************* +#define CAN_IF3MSK_MSK_S 0U +#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask +#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//************************************************************************************************* +#define CAN_IF3ARB_ID_S 0U +#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000U // Message Direction +#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//************************************************************************************************* +#define CAN_IF3MCTL_DLC_S 0U +#define CAN_IF3MCTL_DLC_M 0xFU // Data length code +#define CAN_IF3MCTL_EOB 0x80U // End of Block +#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//************************************************************************************************* +#define CAN_IF3DATA_DATA_0_S 0U +#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8U +#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16U +#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24U +#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//************************************************************************************************* +#define CAN_IF3DATB_DATA_4_S 0U +#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8U +#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16U +#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24U +#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7 + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_cla.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cla.h new file mode 100644 index 0000000..0206de7 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cla.h @@ -0,0 +1,241 @@ +//########################################################################### +// +// FILE: hw_cla.h +// +// TITLE: Definitions for the CLA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLA_H +#define HW_CLA_H + +//************************************************************************************************* +// +// The following are defines for the CLA register offsets +// +//************************************************************************************************* +#ifndef __TMS320C28XX_CLA__ +#define CLA_O_MVECT1 0x0U // Task Interrupt Vector +#define CLA_O_MVECT2 0x1U // Task Interrupt Vector +#define CLA_O_MVECT3 0x2U // Task Interrupt Vector +#define CLA_O_MVECT4 0x3U // Task Interrupt Vector +#define CLA_O_MVECT5 0x4U // Task Interrupt Vector +#define CLA_O_MVECT6 0x5U // Task Interrupt Vector +#define CLA_O_MVECT7 0x6U // Task Interrupt Vector +#define CLA_O_MVECT8 0x7U // Task Interrupt Vector +#define CLA_O_MCTL 0x10U // Control Register +#define CLA_O_MIFR 0x20U // Interrupt Flag Register +#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register +#define CLA_O_MIFRC 0x22U // Interrupt Force Register +#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register +#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register +#define CLA_O_MIER 0x25U // Interrupt Enable Register +#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register +#define CLA_O_MPC 0x28U // CLA Program Counter +#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0 +#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1 +#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register +#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0 +#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1 +#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2 +#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3 +#endif + +#ifdef __TMS320C28XX_CLA__ +#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register +#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register +#endif + + +#ifndef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCTL register +// +//************************************************************************************************* +#define CLA_MCTL_HARDRESET 0x1U // Hard Reset +#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset +#define CLA_MCTL_IACKE 0x4U // IACK enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFR register +// +//************************************************************************************************* +#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag +#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag +#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag +#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag +#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag +#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag +#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag +#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIOVF register +// +//************************************************************************************************* +#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag +#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag +#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag +#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag +#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag +#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag +#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag +#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFRC register +// +//************************************************************************************************* +#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force +#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force +#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force +#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force +#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force +#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force +#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force +#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLR register +// +//************************************************************************************************* +#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear +#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear +#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear +#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear +#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear +#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear +#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear +#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLROVF register +// +//************************************************************************************************* +#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIER register +// +//************************************************************************************************* +#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable +#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable +#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable +#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable +#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable +#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable +#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable +#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIRUN register +// +//************************************************************************************************* +#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status +#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status +#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status +#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status +#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status +#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status +#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status +#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the _MSTF register +// +//************************************************************************************************* +#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag +#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag +#define CLA_MSTF_NF 0x4U // Negative Float Flag +#define CLA_MSTF_ZF 0x8U // Zero Float Flag +#define CLA_MSTF_TF 0x40U // Test Flag +#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode +#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status +#define CLA_MSTF_RPC_S 12U +#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC + +#endif + +#ifdef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTEN register +// +//************************************************************************************************* +#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTFRC register +// +//************************************************************************************************* +#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task. + +#endif + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_clb.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_clb.h new file mode 100644 index 0000000..4390004 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_clb.h @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: hw_clb.h +// +// TITLE: Definitions for the CLB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLB_H +#define HW_CLB_H + +//************************************************************************************************* +// +// The following are defines for the CLB register offsets +// +//************************************************************************************************* +#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET +#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1 +#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0 +#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT +#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1 +#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1 +#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source +#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source +#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source +#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source +#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0 +#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2 +#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0 +#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2 +#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0 +#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1 +#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2 +#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM +#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0 +#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1 +#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2 +#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3 +#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4 +#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5 +#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6 +#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7 +#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller + +#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control +#define CLB_O_LOAD_ADDR 0x2U // Indirect address +#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads +#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and + // synchronizers +#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register +#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux +#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux +#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers +#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs +#define CLB_O_OUT_EN 0x12U // CELL output enable register +#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs +#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs +#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register +#define CLB_O_LOCK 0x22U // Lock control register +#define CLB_O_DBG_R0 0x30U // R0 of High level Controller +#define CLB_O_DBG_R1 0x32U // R1 of High level Controller +#define CLB_O_DBG_R2 0x34U // R2 of High level Controller +#define CLB_O_DBG_R3 0x36U // R3 of High level Controller +#define CLB_O_DBG_C0 0x38U // Count of Unit 0 +#define CLB_O_DBG_C1 0x3AU // Count of Unit 1 +#define CLB_O_DBG_C2 0x3CU // Count of Unit 2 +#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell + +#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from + // HLC) +#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_RESET register +// +//************************************************************************************************* +#define CLB_COUNT_RESET_SEL_0_S 0U +#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0 +#define CLB_COUNT_RESET_SEL_1_S 5U +#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1 +#define CLB_COUNT_RESET_SEL_2_S 10U +#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_1_SEL_0_S 0U +#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0 +#define CLB_COUNT_MODE_1_SEL_1_S 5U +#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1 +#define CLB_COUNT_MODE_1_SEL_2_S 10U +#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_0_SEL_0_S 0U +#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0 +#define CLB_COUNT_MODE_0_SEL_1_S 5U +#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1 +#define CLB_COUNT_MODE_0_SEL_2_S 10U +#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_EVENT register +// +//************************************************************************************************* +#define CLB_COUNT_EVENT_SEL_0_S 0U +#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0 +#define CLB_COUNT_EVENT_SEL_1_S 5U +#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1 +#define CLB_COUNT_EVENT_SEL_2_S 10U +#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN0 register +// +//************************************************************************************************* +#define CLB_LUT4_IN0_SEL_0_S 0U +#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN0_SEL_1_S 5U +#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN0_SEL_2_S 10U +#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN1 register +// +//************************************************************************************************* +#define CLB_LUT4_IN1_SEL_0_S 0U +#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN1_SEL_1_S 5U +#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN1_SEL_2_S 10U +#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN2 register +// +//************************************************************************************************* +#define CLB_LUT4_IN2_SEL_0_S 0U +#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN2_SEL_1_S 5U +#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN2_SEL_2_S 10U +#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN3 register +// +//************************************************************************************************* +#define CLB_LUT4_IN3_SEL_0_S 0U +#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN3_SEL_1_S 5U +#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN3_SEL_2_S 10U +#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN1_0_FN0_S 0U +#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0 +#define CLB_FSM_LUT_FN1_0_FN1_S 16U +#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN2_FN1_S 0U +#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register +// +//************************************************************************************************* +#define CLB_LUT4_FN1_0_FN0_S 0U +#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0 +#define CLB_LUT4_FN1_0_FN1_S 16U +#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN2 register +// +//************************************************************************************************* +#define CLB_LUT4_FN2_FN1_S 0U +#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_0_S0_S 0U +#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_0_S1_S 16U +#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_1_S0_S 0U +#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_1_S1_S 16U +#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_2_S0_S 0U +#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_2_S1_S 16U +#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_MISC_CONTROL register +// +//************************************************************************************************* +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0 +#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1 +#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2 +#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_0_IN0_S 0U +#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_0_IN1_S 5U +#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_0_IN2_S 10U +#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_0_FN_S 15U +#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_1_IN0_S 0U +#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_1_IN1_S 5U +#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_1_IN2_S 10U +#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_1_FN_S 15U +#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_2_IN0_S 0U +#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_2_IN1_S 5U +#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_2_IN2_S 10U +#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_2_FN_S 15U +#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_3_IN0_S 0U +#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_3_IN1_S 5U +#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_3_IN2_S 10U +#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_3_FN_S 15U +#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_4_IN0_S 0U +#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_4_IN1_S 5U +#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_4_IN2_S 10U +#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_4_FN_S 15U +#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_5_IN0_S 0U +#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_5_IN1_S 5U +#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_5_IN2_S 10U +#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_5_FN_S 15U +#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_6_IN0_S 0U +#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_6_IN1_S 5U +#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_6_IN2_S 10U +#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_6_FN_S 15U +#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_7_IN0_S 0U +#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_7_IN1_S 5U +#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_7_IN2_S 10U +#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_7_FN_S 15U +#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register +// +//************************************************************************************************* +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0 +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1 +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2 +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_EN register +// +//************************************************************************************************* +#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable +#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable +#define CLB_LOAD_EN_STOP 0x4U // Debug stop control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_ADDR register +// +//************************************************************************************************* +#define CLB_LOAD_ADDR_ADDR_S 0U +#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INPUT_FILTER register +// +//************************************************************************************************* +#define CLB_INPUT_FILTER_FIN0_S 0U +#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0 +#define CLB_INPUT_FILTER_FIN1_S 2U +#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1 +#define CLB_INPUT_FILTER_FIN2_S 4U +#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2 +#define CLB_INPUT_FILTER_FIN3_S 6U +#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3 +#define CLB_INPUT_FILTER_FIN4_S 8U +#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4 +#define CLB_INPUT_FILTER_FIN5_S 10U +#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5 +#define CLB_INPUT_FILTER_FIN6_S 12U +#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6 +#define CLB_INPUT_FILTER_FIN7_S 14U +#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7 +#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0 +#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1 +#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2 +#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3 +#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4 +#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5 +#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6 +#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register +// +//************************************************************************************************* +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_BUF_PTR register +// +//************************************************************************************************* +#define CLB_BUF_PTR_PULL_S 0U +#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull +#define CLB_BUF_PTR_PUSH_S 16U +#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GP_REG register +// +//************************************************************************************************* +#define CLB_GP_REG_REG_S 0U +#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INTR_TAG_REG register +// +//************************************************************************************************* +#define CLB_INTR_TAG_REG_TAG_S 0U +#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOCK register +// +//************************************************************************************************* +#define CLB_LOCK_LOCK 0x1U // LOCK enable +#define CLB_LOCK_KEY_S 16U +#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_DBG_OUT register +// +//************************************************************************************************* +#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0 +#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0 +#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0 +#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0 +#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0 +#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0 +#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0 +#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1 +#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1 +#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1 +#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1 +#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1 +#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1 +#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1 +#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2 +#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2 +#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2 +#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2 +#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2 +#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2 +#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2 +#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0 +#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1 +#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2 +#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3 +#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4 +#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5 +#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6 +#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7 + + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_clbxbar.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_clbxbar.h new file mode 100644 index 0000000..64072e2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_clbxbar.h @@ -0,0 +1,1272 @@ +//########################################################################### +// +// FILE: hw_clbxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLBXBAR_H +#define HW_CLBXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_AUXSIG0MUX0TO15CFG 0x0U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG0MUX16TO31CFG 0x2U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG1MUX0TO15CFG 0x4U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG1MUX16TO31CFG 0x6U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG2MUX0TO15CFG 0x8U // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG2MUX16TO31CFG 0xAU // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG3MUX0TO15CFG 0xCU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG3MUX16TO31CFG 0xEU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG4MUX0TO15CFG 0x10U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG4MUX16TO31CFG 0x12U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG5MUX0TO15CFG 0x14U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG5MUX16TO31CFG 0x16U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG6MUX0TO15CFG 0x18U // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG6MUX16TO31CFG 0x1AU // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG7MUX0TO15CFG 0x1CU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG7MUX16TO31CFG 0x1EU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG0MUXENABLE 0x20U // CLB XBAR Mux Enable Register for Output-0 +#define XBAR_O_AUXSIG1MUXENABLE 0x22U // CLB XBAR Mux Enable Register for Output-1 +#define XBAR_O_AUXSIG2MUXENABLE 0x24U // CLB XBAR Mux Enable Register for Output-2 +#define XBAR_O_AUXSIG3MUXENABLE 0x26U // CLB XBAR Mux Enable Register for Output-3 +#define XBAR_O_AUXSIG4MUXENABLE 0x28U // CLB XBAR Mux Enable Register for Output-4 +#define XBAR_O_AUXSIG5MUXENABLE 0x2AU // CLB XBAR Mux Enable Register for Output-5 +#define XBAR_O_AUXSIG6MUXENABLE 0x2CU // CLB XBAR Mux Enable Register for Output-6 +#define XBAR_O_AUXSIG7MUXENABLE 0x2EU // CLB XBAR Mux Enable Register for Output-7 +#define XBAR_O_AUXSIGOUTINV 0x38U // CLB XBAR Output Inversion Register +#define XBAR_O_AUXSIGLOCK 0x3EU // ClbXbar Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG0 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG1 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG2 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG3 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG4 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG5 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG6 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGOUTINV register +// +//************************************************************************************************* +#define XBAR_AUXSIGOUTINV_OUT0 0x1U // Selects polarity for AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT1 0x2U // Selects polarity for AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT2 0x4U // Selects polarity for AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT3 0x8U // Selects polarity for AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT4 0x10U // Selects polarity for AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT5 0x20U // Selects polarity for AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT6 0x40U // Selects polarity for AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT7 0x80U // Selects polarity for AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGLOCK register +// +//************************************************************************************************* +#define XBAR_AUXSIGLOCK_LOCK 0x1U // Locks the configuration for CLB-XBAR +#define XBAR_AUXSIGLOCK_KEY_S 16U +#define XBAR_AUXSIGLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_cmpss.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cmpss.h new file mode 100644 index 0000000..67d32e3 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cmpss.h @@ -0,0 +1,235 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the CMPSS registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CMPSS_H +#define HW_CMPSS_H + +//************************************************************************************************* +// +// The following are defines for the CMPSS register offsets +// +//************************************************************************************************* +#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register +#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register +#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register +#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register +#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register +#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register +#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register +#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register +#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register +#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register +#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register +#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register +#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register +#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register +#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register +#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register +#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPCTL register +// +//************************************************************************************************* +#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2U +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10U +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//************************************************************************************************* +#define CMPSS_COMPHYSCTL_COMPHYS_S 0U +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTS register +// +//************************************************************************************************* +#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//************************************************************************************************* +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//************************************************************************************************* +#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14U +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALS register +// +//************************************************************************************************* +#define CMPSS_DACHVALS_DACVAL_S 0U +#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALA register +// +//************************************************************************************************* +#define CMPSS_DACHVALA_DACVAL_S 0U +#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALS register +// +//************************************************************************************************* +#define CMPSS_DACLVALS_DACVAL_S 0U +#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALA register +// +//************************************************************************************************* +#define CMPSS_DACLVALA_DACVAL_S 0U +#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYA_DELAY_S 0U +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYS_DELAY_S 0U +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9U +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9U +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPLOCK register +// +//************************************************************************************************* +#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_cputimer.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cputimer.h new file mode 100644 index 0000000..f7613fb --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_cputimer.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the CPUTIMER registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CPUTIMER_H +#define HW_CPUTIMER_H + +//************************************************************************************************* +// +// The following are defines for the CPUTIMER register offsets +// +//************************************************************************************************* +#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register +#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register +#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TIM register +// +//************************************************************************************************* +#define CPUTIMER_TIM_LSW_S 0U +#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers +#define CPUTIMER_TIM_MSW_S 16U +#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRD register +// +//************************************************************************************************* +#define CPUTIMER_PRD_LSW_S 0U +#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers +#define CPUTIMER_PRD_MSW_S 16U +#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TCR register +// +//************************************************************************************************* +#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20U // Timer reload +#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes +#define CPUTIMER_TCR_FREE 0x800U // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPR register +// +//************************************************************************************************* +#define CPUTIMER_TPR_TDDR_S 0U +#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8U +#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPRH register +// +//************************************************************************************************* +#define CPUTIMER_TPRH_TDDRH_S 0U +#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8U +#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter. + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_dac.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dac.h new file mode 100644 index 0000000..3e3d3a2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dac.h @@ -0,0 +1,122 @@ +//########################################################################### +// +// FILE: hw_dac.h +// +// TITLE: Definitions for the DAC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DAC_H +#define HW_DAC_H + +//************************************************************************************************* +// +// The following are defines for the DAC register offsets +// +//************************************************************************************************* +#define DAC_O_REV 0x0U // DAC Revision Register +#define DAC_O_CTL 0x1U // DAC Control Register +#define DAC_O_VALA 0x2U // DAC Value Register - Active +#define DAC_O_VALS 0x3U // DAC Value Register - Shadow +#define DAC_O_OUTEN 0x4U // DAC Output Enable Register +#define DAC_O_LOCK 0x5U // DAC Lock Register +#define DAC_O_TRIM 0x6U // DAC Trim Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACREV register +// +//************************************************************************************************* +#define DAC_REV_REV_S 0U +#define DAC_REV_REV_M 0xFFU // DAC Revision Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACCTL register +// +//************************************************************************************************* +#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select +#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode +#define DAC_CTL_SYNCSEL_S 4U +#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALA register +// +//************************************************************************************************* +#define DAC_VALA_DACVALA_S 0U +#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALS register +// +//************************************************************************************************* +#define DAC_VALS_DACVALS_S 0U +#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACOUTEN register +// +//************************************************************************************************* +#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLOCK register +// +//************************************************************************************************* +#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock +#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock +#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock +#define DAC_LOCK_KEY_S 12U +#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACTRIM register +// +//************************************************************************************************* +#define DAC_TRIM_OFFSET_TRIM_S 0U +#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_dcsm.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dcsm.h new file mode 100644 index 0000000..c81bcb1 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dcsm.h @@ -0,0 +1,442 @@ +//########################################################################### +// +// FILE: hw_dcsm.h +// +// TITLE: Definitions for the DCSM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DCSM_H +#define HW_DCSM_H + +//************************************************************************************************* +// +// The following are defines for the DCSM register offsets +// +//************************************************************************************************* +#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP +#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP +#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP +#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP + +#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP +#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP +#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP +#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP + +#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer +#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock +#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0 +#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1 +#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2 +#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3 +#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register +#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register +#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register +#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register +#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register + +#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer +#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock +#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0 +#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1 +#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2 +#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3 +#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register +#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register +#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register +#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register +#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register + +#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register +#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register +#define DCSM_O_RAMSTAT 0x4U // RAM Status Register + + + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock. +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z1_BOOTCTRL_KEY_S 0U +#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z1_BOOTCTRL_BMODE_S 8U +#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_CR register +// +//************************************************************************************************* +#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock. +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z2_BOOTCTRL_KEY_S 0U +#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z2_BOOTCTRL_BMODE_S 8U +#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_CR register +// +//************************************************************************************************* +#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FLSEM register +// +//************************************************************************************************* +#define DCSM_FLSEM_SEM_S 0U +#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit +#define DCSM_FLSEM_KEY_S 8U +#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECTSTAT register +// +//************************************************************************************************* +#define DCSM_SECTSTAT_STATUS_SECTA_S 0U +#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A +#define DCSM_SECTSTAT_STATUS_SECTB_S 2U +#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B +#define DCSM_SECTSTAT_STATUS_SECTC_S 4U +#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C +#define DCSM_SECTSTAT_STATUS_SECTD_S 6U +#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D +#define DCSM_SECTSTAT_STATUS_SECTE_S 8U +#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E +#define DCSM_SECTSTAT_STATUS_SECTF_S 10U +#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F +#define DCSM_SECTSTAT_STATUS_SECTG_S 12U +#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G +#define DCSM_SECTSTAT_STATUS_SECTH_S 14U +#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H +#define DCSM_SECTSTAT_STATUS_SECTI_S 16U +#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I +#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U +#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J +#define DCSM_SECTSTAT_STATUS_SECTK_S 20U +#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K +#define DCSM_SECTSTAT_STATUS_SECTL_S 22U +#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L +#define DCSM_SECTSTAT_STATUS_SECTM_S 24U +#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M +#define DCSM_SECTSTAT_STATUS_SECTN_S 26U +#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMSTAT register +// +//************************************************************************************************* +#define DCSM_RAMSTAT_STATUS_RAM0_S 0U +#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0 +#define DCSM_RAMSTAT_STATUS_RAM1_S 2U +#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1 +#define DCSM_RAMSTAT_STATUS_RAM2_S 4U +#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2 +#define DCSM_RAMSTAT_STATUS_RAM3_S 6U +#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3 +#define DCSM_RAMSTAT_STATUS_RAM4_S 8U +#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4 +#define DCSM_RAMSTAT_STATUS_RAM5_S 10U +#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5 +#define DCSM_RAMSTAT_STATUS_RAM6_S 12U +#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0 +#define DCSM_RAMSTAT_STATUS_RAM7_S 14U +#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1 +#define DCSM_RAMSTAT_STATUS_CLA1_S 28U +#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1 + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_dma.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dma.h new file mode 100644 index 0000000..1ecd1d7 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_dma.h @@ -0,0 +1,165 @@ +//########################################################################### +// +// FILE: hw_dma.h +// +// TITLE: Definitions for the DMA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DMA_H +#define HW_DMA_H + +//************************************************************************************************* +// +// The following are defines for the DMA register offsets +// +//************************************************************************************************* +#define DMA_O_CTRL 0x0U // DMA Control Register +#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register +#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register +#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register + +#define DMA_O_MODE 0x0U // Mode Register +#define DMA_O_CONTROL 0x1U // Control Register +#define DMA_O_BURST_SIZE 0x2U // Burst Size Register +#define DMA_O_BURST_COUNT 0x3U // Burst Count Register +#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register +#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register +#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register +#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register +#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register +#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register +#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register +#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register +#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register +#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register +#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register +#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register +#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register +#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register +#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register +#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register +#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register +#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register +#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register +#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACTRL register +// +//************************************************************************************************* +#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit +#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEBUGCTRL register +// +//************************************************************************************************* +#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYCTRL1 register +// +//************************************************************************************************* +#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYSTAT register +// +//************************************************************************************************* +#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U +#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MODE register +// +//************************************************************************************************* +#define DMA_MODE_PERINTSEL_S 0U +#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select +#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable +#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable +#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode +#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit +#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit +#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit +#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CONTROL register +// +//************************************************************************************************* +#define DMA_CONTROL_RUN 0x1U // Run Bit +#define DMA_CONTROL_HALT 0x2U // Halt Bit +#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit +#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit +#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit +#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit +#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit +#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit +#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit +#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit +#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_SIZE register +// +//************************************************************************************************* +#define DMA_BURST_SIZE_BURSTSIZE_S 0U +#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_COUNT register +// +//************************************************************************************************* +#define DMA_BURST_COUNT_BURSTCOUNT_S 0U +#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_ecap.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ecap.h new file mode 100644 index 0000000..48981d6 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ecap.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the ECAP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ECAP_H +#define HW_ECAP_H + +//************************************************************************************************* +// +// The following are defines for the ECAP register offsets +// +//************************************************************************************************* +#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register +#define ECAP_O_CAP1 0x4U // Capture 1 Register +#define ECAP_O_CAP2 0x6U // Capture 2 Register +#define ECAP_O_CAP3 0x8U // Capture 3 Register +#define ECAP_O_CAP4 0xAU // Capture 4 Register +#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register +#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register +#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL1 register +// +//************************************************************************************************* +#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1 +#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2 +#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3 +#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4 +#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9U +#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14U +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL2 register +// +//************************************************************************************************* +#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1U +#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous +#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6U +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECEINT register +// +//************************************************************************************************* +#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable +#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable +#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable +#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable +#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFLG register +// +//************************************************************************************************* +#define ECAP_ECFLG_INT 0x1U // Global Flag +#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCLR register +// +//************************************************************************************************* +#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear +#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear +#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear +#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear +#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear +#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear +#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear +#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFRC register +// +//************************************************************************************************* +#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt +#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt +#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt +#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt +#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt +#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt +#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_emif.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_emif.h new file mode 100644 index 0000000..9f1401e --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_emif.h @@ -0,0 +1,259 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the EMIF registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EMIF_H +#define HW_EMIF_H + +//************************************************************************************************* +// +// The following are defines for the EMIF register offsets +// +//************************************************************************************************* +#define EMIF_O_RCSR 0x0U // Revision Code and Status Register +#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register +#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register +#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register +#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register +#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register +#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register +#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCSR register +// +//************************************************************************************************* +#define EMIF_RCSR_MINOR_REVISION_S 0U +#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8U +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16U +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate. +#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//************************************************************************************************* +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//************************************************************************************************* +#define EMIF_SDRAM_CR_PAGESIGE_S 0U +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size. +#define EMIF_SDRAM_CR_IBANK_S 4U +#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit + // is set. +#define EMIF_SDRAM_CR_CL_S 9U +#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency. +#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode. +#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down. +#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//************************************************************************************************* +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2U +#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2U +#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2U +#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//************************************************************************************************* +#define EMIF_SDRAM_TR_T_RRD_S 4U +#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank. +#define EMIF_SDRAM_TR_T_RC_S 8U +#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12U +#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16U +#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20U +#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24U +#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing. +#define EMIF_SDRAM_TR_T_RFC_S 27U +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//************************************************************************************************* +#define EMIF_SDR_EXT_TMNG_T_XS_S 0U +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_RAW register +// +//************************************************************************************************* +#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2U // Line Trap. +#define EMIF_INT_RAW_WR_S 2U +#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK register +// +//************************************************************************************************* +#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2U +#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//************************************************************************************************* +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//************************************************************************************************* +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise. + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwm.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwm.h new file mode 100644 index 0000000..6f7bf2d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwm.h @@ -0,0 +1,1050 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the EPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWM_H +#define HW_EPWM_H + +//************************************************************************************************* +// +// The following are defines for the EPWM register offsets +// +//************************************************************************************************* +#define EPWM_O_TBCTL 0x0U // Time Base Control Register +#define EPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4U // Time Base Counter Register +#define EPWM_O_TBSTS 0x5U // Time Base Status Register +#define EPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define EPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define EPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define EPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define EPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define EPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define EPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define EPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define EPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define EPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21U // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define EPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define EPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define EPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define EPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define EPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38U // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define EPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define EPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define EPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define EPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define EPWM_O_TBPHS 0x60U // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define EPWM_O_TBPRD 0x63U // Time Base Period Register +#define EPWM_O_CMPA 0x6AU // Counter Compare A Register +#define EPWM_O_CMPB 0x6CU // Compare B Register +#define EPWM_O_CMPC 0x6FU // Counter Compare C Register +#define EPWM_O_CMPD 0x71U // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define EPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define EPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define EPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define EPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define EPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define EPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define EPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define EPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define EPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define EPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define EPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define EPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define EPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define EPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define EPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define EPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define EPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define EPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define EPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define EPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define EPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define EPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define EPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define EPWM_TBCTL_CTRMODE_S 0U +#define EPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4U +#define EPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7U +#define EPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10U +#define EPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14U +#define EPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12U +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14U +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define EPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define EPWM_CMPCTL_LOADAMODE_S 0U +#define EPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2U +#define EPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define EPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define EPWM_CMPCTL_LOADASYNC_S 10U +#define EPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12U +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define EPWM_CMPCTL2_LOADCMODE_S 0U +#define EPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2U +#define EPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10U +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12U +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define EPWM_DBCTL_OUT_MODE_S 0U +#define EPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2U +#define EPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4U +#define EPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define EPWM_DBCTL_LOADREDMODE_S 6U +#define EPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8U +#define EPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12U +#define EPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define EPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define EPWM_AQCTL_LDAQAMODE_S 0U +#define EPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2U +#define EPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define EPWM_AQCTL_LDAQASYNC_S 8U +#define EPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10U +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define EPWM_AQTSRCSEL_T1SEL_S 0U +#define EPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4U +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define EPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1U +#define EPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5U +#define EPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8U +#define EPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define EPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define EPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define EPWM_VCAPCTL_TRIGSEL_S 2U +#define EPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define EPWM_VCAPCTL_VDELAYDIV_S 7U +#define EPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define EPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define EPWM_VCNTCFG_STARTEDGE_S 0U +#define EPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define EPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define EPWM_VCNTCFG_STOPEDGE_S 8U +#define EPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define EPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define EPWM_HRCNFG_EDGMODE_S 0U +#define EPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3U +#define EPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define EPWM_HRCNFG_EDGMODEB_S 8U +#define EPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11U +#define EPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define EPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define EPWM_HRMSTEP_HRMSTEP_S 0U +#define EPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define EPWM_HRCNFG2_EDGMODEDB_S 0U +#define EPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define EPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define EPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define EPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define EPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4U +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define EPWM_TRREM_TRREM_S 0U +#define EPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define EPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define EPWM_GLDCTL_GLDMODE_S 1U +#define EPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7U +#define EPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define EPWM_GLDCTL_GLDCNT_S 10U +#define EPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define EPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define EPWM_XLINK_TBPRDLINK_S 0U +#define EPWM_XLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4U +#define EPWM_XLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8U +#define EPWM_XLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12U +#define EPWM_XLINK_CMPCLINK_M 0xF000U // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16U +#define EPWM_XLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28U +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define EPWM_AQCTLA_ZRO_S 0U +#define EPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2U +#define EPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4U +#define EPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6U +#define EPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8U +#define EPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10U +#define EPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define EPWM_AQCTLA2_T1U_S 0U +#define EPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLA2_T1D_S 2U +#define EPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4U +#define EPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLA2_T2D_S 6U +#define EPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define EPWM_AQCTLB_ZRO_S 0U +#define EPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2U +#define EPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4U +#define EPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6U +#define EPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8U +#define EPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10U +#define EPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define EPWM_AQCTLB2_T1U_S 0U +#define EPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLB2_T1D_S 2U +#define EPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4U +#define EPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLB2_T2D_S 6U +#define EPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define EPWM_AQSFRC_ACTSFA_S 0U +#define EPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define EPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3U +#define EPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define EPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6U +#define EPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define EPWM_AQCSFRC_CSFA_S 0U +#define EPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define EPWM_AQCSFRC_CSFB_S 2U +#define EPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define EPWM_DBREDHR_DBREDHR_S 9U +#define EPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define EPWM_DBRED_DBRED_S 0U +#define EPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define EPWM_DBFEDHR_DBFEDHR_S 9U +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define EPWM_DBFED_DBFED_S 0U +#define EPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define EPWM_TBPHS_TBPHSHR_S 0U +#define EPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16U +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define EPWM_CMPA_CMPAHR_S 0U +#define EPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define EPWM_CMPA_CMPA_S 16U +#define EPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define EPWM_CMPB_CMPBHR_S 0U +#define EPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define EPWM_CMPB_CMPB_S 16U +#define EPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define EPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define EPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define EPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define EPWM_TZDCSEL_DCAEVT1_S 0U +#define EPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3U +#define EPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6U +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9U +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define EPWM_TZCTL_TZA_S 0U +#define EPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define EPWM_TZCTL_TZB_S 2U +#define EPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4U +#define EPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6U +#define EPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8U +#define EPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10U +#define EPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define EPWM_TZCTL2_TZAU_S 0U +#define EPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3U +#define EPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6U +#define EPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9U +#define EPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define EPWM_TZCTLDCA_DCAEVT1U_S 0U +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3U +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6U +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9U +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define EPWM_TZCTLDCB_DCBEVT1U_S 0U +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3U +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6U +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9U +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define EPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define EPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define EPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define EPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define EPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define EPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define EPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define EPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define EPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define EPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14U +#define EPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define EPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define EPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define EPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define EPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define EPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define EPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define EPWM_ETSEL_INTSEL_S 0U +#define EPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8U +#define EPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12U +#define EPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define EPWM_ETPS_INTPRD_S 0U +#define EPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2U +#define EPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define EPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8U +#define EPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10U +#define EPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12U +#define EPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14U +#define EPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define EPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define EPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define EPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define EPWM_ETINTPS_INTPRD2_S 0U +#define EPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4U +#define EPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define EPWM_ETSOCPS_SOCAPRD2_S 0U +#define EPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4U +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8U +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12U +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define EPWM_ETCNTINIT_INTINIT_S 0U +#define EPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4U +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8U +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define EPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define EPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define EPWM_DCFCTL_SRCSEL_S 0U +#define EPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define EPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4U +#define EPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define EPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define EPWM_DCFCTL_EDGEMODE_S 8U +#define EPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define EPWM_DCFCTL_EDGECOUNT_S 10U +#define EPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define EPWM_DCFCTL_EDGESTATUS_S 13U +#define EPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define EPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define EPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define EPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define EPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwmxbar.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwmxbar.h new file mode 100644 index 0000000..5fb6058 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_epwmxbar.h @@ -0,0 +1,1192 @@ +//########################################################################### +// +// FILE: hw_epwmxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWMXBAR_H +#define HW_EPWMXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_TRIP4MUX0TO15CFG 0x0U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP4MUX16TO31CFG 0x2U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP5MUX0TO15CFG 0x4U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP5MUX16TO31CFG 0x6U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP7MUX0TO15CFG 0x8U // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP7MUX16TO31CFG 0xAU // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP8MUX0TO15CFG 0xCU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP8MUX16TO31CFG 0xEU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP9MUX0TO15CFG 0x10U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP9MUX16TO31CFG 0x12U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP10MUX0TO15CFG 0x14U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP10MUX16TO31CFG 0x16U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP11MUX0TO15CFG 0x18U // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP11MUX16TO31CFG 0x1AU // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP12MUX0TO15CFG 0x1CU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP12MUX16TO31CFG 0x1EU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP4MUXENABLE 0x20U // ePWM XBAR Mux Enable for TRIP4 +#define XBAR_O_TRIP5MUXENABLE 0x22U // ePWM XBAR Mux Enable for TRIP5 +#define XBAR_O_TRIP7MUXENABLE 0x24U // ePWM XBAR Mux Enable for TRIP7 +#define XBAR_O_TRIP8MUXENABLE 0x26U // ePWM XBAR Mux Enable for TRIP8 +#define XBAR_O_TRIP9MUXENABLE 0x28U // ePWM XBAR Mux Enable for TRIP9 +#define XBAR_O_TRIP10MUXENABLE 0x2AU // ePWM XBAR Mux Enable for TRIP10 +#define XBAR_O_TRIP11MUXENABLE 0x2CU // ePWM XBAR Mux Enable for TRIP11 +#define XBAR_O_TRIP12MUXENABLE 0x2EU // ePWM XBAR Mux Enable for TRIP12 +#define XBAR_O_TRIPOUTINV 0x38U // ePWM XBAR Output Inversion Register +#define XBAR_O_TRIPLOCK 0x3EU // ePWM XBAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP4 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP5 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP7 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP8 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP9MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP9MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP9MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP9MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP9MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP9MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP9MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP9MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP9MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP9MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP9MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP9MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP9MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP9MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP9MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP9MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP9MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP9MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP9MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP9MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP9MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP9MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP9MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP9MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP9MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP9MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP9MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP9MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP9MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP9MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP9MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP9MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP9 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP10MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP10MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP10MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP10MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP10MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP10MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP10MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP10MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP10MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP10MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP10MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP10MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP10MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP10MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP10MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP10MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP10MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP10MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP10MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP10MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP10MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP10MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP10MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP10MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP10MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP10MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP10MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP10MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP10MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP10MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP10MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP10MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP11MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP11MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP11MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP11MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP11MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP11MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP11MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP11MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP11MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP11MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP11MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP11MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP11MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP11MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP11MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP11MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP11MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP11MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP11MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP11MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP11MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP11MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP11MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP11MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP11MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP11MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP11MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP11MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP11MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP11MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP11MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP11MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP12MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP12MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP12MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP12MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP12MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP12MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP12MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP12MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP12MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP12MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP12MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP12MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP12MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP12MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP12MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP12MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP12MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP12MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP12MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP12MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP12MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP12MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP12MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP12MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP12MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP12MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP12MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP12MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP12MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP12MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP12MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP12MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP4MUXENABLE_MUX0 0x1U // mux0 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP5MUXENABLE_MUX0 0x1U // mux0 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP7MUXENABLE_MUX0 0x1U // mux0 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP8MUXENABLE_MUX0 0x1U // mux0 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP9MUXENABLE_MUX0 0x1U // mux0 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP10MUXENABLE_MUX0 0x1U // mux0 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP10 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP11MUXENABLE_MUX0 0x1U // mux0 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP11 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP12MUXENABLE_MUX0 0x1U // mux0 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPOUTINV register +// +//************************************************************************************************* +#define XBAR_TRIPOUTINV_TRIP4 0x1U // Selects polarity for TRIP4 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP5 0x2U // Selects polarity for TRIP5 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP7 0x4U // Selects polarity for TRIP7 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP8 0x8U // Selects polarity for TRIP8 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP9 0x10U // Selects polarity for TRIP9 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP10 0x20U // Selects polarity for TRIP10 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP11 0x40U // Selects polarity for TRIP11 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP12 0x80U // Selects polarity for TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPLOCK register +// +//************************************************************************************************* +#define XBAR_TRIPLOCK_LOCK 0x1U // Locks the configuration for EPWM-XBAR +#define XBAR_TRIPLOCK_KEY_S 16U +#define XBAR_TRIPLOCK_KEY_M 0xFFFF0000U // Write protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_eqep.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_eqep.h new file mode 100644 index 0000000..7dbb33a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_eqep.h @@ -0,0 +1,225 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the EQEP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EQEP_H +#define HW_EQEP_H + +//************************************************************************************************* +// +// The following are defines for the EQEP register offsets +// +//************************************************************************************************* +#define EQEP_O_QPOSCNT 0x0U // Position Counter +#define EQEP_O_QPOSINIT 0x2U // Position Counter Init +#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6U // Position Compare +#define EQEP_O_QPOSILAT 0x8U // Index Position Latch +#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xCU // Position Latch +#define EQEP_O_QUTMR 0xEU // QEP Unit Timer +#define EQEP_O_QUPRD 0x10U // QEP Unit Period +#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15U // QEP Control +#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17U // Position Compare Control +#define EQEP_O_QEINT 0x18U // QEP Interrupt Control +#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1CU // QEP Status +#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer +#define EQEP_O_QCPRD 0x1EU // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QDECCTL register +// +//************************************************************************************************* +#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter +#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14U +#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPCTL register +// +//************************************************************************************************* +#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable +#define EQEP_QEPCTL_IEL_S 4U +#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch +#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80U // Software init position counter +#define EQEP_QEPCTL_IEI_S 8U +#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count +#define EQEP_QEPCTL_SEI_S 10U +#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12U +#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14U +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCAPCTL register +// +//************************************************************************************************* +#define EQEP_QCAPCTL_UPPS_S 0U +#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4U +#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler +#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QPOSCTL register +// +//************************************************************************************************* +#define EQEP_QPOSCTL_PCSPW_S 0U +#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width +#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEINT register +// +//************************************************************************************************* +#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable +#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable +#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable +#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable +#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable +#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable +#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable +#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable +#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable +#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable +#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFLG register +// +//************************************************************************************************* +#define EQEP_QFLG_INT 0x1U // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag +#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag +#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag +#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag +#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag +#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag +#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag +#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag +#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag +#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCLR register +// +//************************************************************************************************* +#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag +#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag +#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag +#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag +#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag +#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag +#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag +#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag +#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag +#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag +#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFRC register +// +//************************************************************************************************* +#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt +#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt +#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt +#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt +#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt +#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt +#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt +#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt +#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt +#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt +#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPSTS register +// +//************************************************************************************************* +#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40U // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_flash.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_flash.h new file mode 100644 index 0000000..73319f1 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_flash.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_flash.h +// +// TITLE: Definitions for the FLASH registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_FLASH_H +#define HW_FLASH_H + +//************************************************************************************************* +// +// The following are defines for the FLASH register offsets +// +//************************************************************************************************* +#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register +#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register +#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register +#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register +#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1 +#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register +#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register + +#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable +#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low +#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High +#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low +#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High +#define FLASH_O_ERR_STATUS 0xAU // Error Status +#define FLASH_O_ERR_POS 0xCU // Error Position +#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear +#define FLASH_O_ERR_CNT 0x10U // Error Control +#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold +#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag +#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear +#define FLASH_O_FDATAH_TEST 0x18U // Data High Test +#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test +#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address +#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address +#define FLASH_O_FECC_CTRL 0x20U // ECC Control +#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High +#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low +#define FLASH_O_FECC_STATUS 0x26U // ECC Status + +#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRDCNTL register +// +//************************************************************************************************* +#define FLASH_FRDCNTL_RWAIT_S 8U +#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBAC register +// +//************************************************************************************************* +#define FLASH_FBAC_VREADST_S 0U +#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBFALLBACK register +// +//************************************************************************************************* +#define FLASH_FBFALLBACK_BNKPWR0_S 0U +#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBPRDY register +// +//************************************************************************************************* +#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State +#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FPAC1 register +// +//************************************************************************************************* +#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode +#define FLASH_FPAC1_PSLEEP_S 16U +#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FMSTAT register +// +//************************************************************************************************* +#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend. +#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend. +#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status +#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status +#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data +#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status +#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status +#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit +#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status +#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRD_INTF_CTRL register +// +//************************************************************************************************* +#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable +#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECC_ENABLE register +// +//************************************************************************************************* +#define FLASH_ECC_ENABLE_ENABLE_S 0U +#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred +#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_POS register +// +//************************************************************************************************* +#define FLASH_ERR_POS_ERR_POS_L_S 0U +#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits +#define FLASH_ERR_POS_ERR_POS_H_S 16U +#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS_CLR register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error + // occurred Clear +#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error + // occurred Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_CNT register +// +//************************************************************************************************* +#define FLASH_ERR_CNT_ERR_CNT_S 0U +#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_THRESHOLD register +// +//************************************************************************************************* +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTFLG register +// +//************************************************************************************************* +#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag +#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTCLR register +// +//************************************************************************************************* +#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear +#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FADDR_TEST register +// +//************************************************************************************************* +#define FLASH_FADDR_TEST_ADDRL_S 3U +#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low +#define FLASH_FADDR_TEST_ADDRH_S 16U +#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_TEST register +// +//************************************************************************************************* +#define FLASH_FECC_TEST_ECC_S 0U +#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_CTRL register +// +//************************************************************************************************* +#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic +#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select +#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_STATUS register +// +//************************************************************************************************* +#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error +#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error +#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U +#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error +#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PUMPREQUEST register +// +//************************************************************************************************* +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between + // CPU1 and CPU2 +#define FLASH_PUMPREQUEST_KEY_S 16U +#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this + // register + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_gpio.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_gpio.h new file mode 100644 index 0000000..0be426d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_gpio.h @@ -0,0 +1,4018 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the GPIO registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_GPIO_H +#define HW_GPIO_H + +//************************************************************************************************* +// +// The following are defines for the GPIO register offsets +// +//************************************************************************************************* +#define GPIO_O_GPACTRL 0x0U // GPIO A Qualification Sampling Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2U // GPIO A Qualifier Select 1 Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4U // GPIO A Qualifier Select 2 Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6U // GPIO A Mux 1 Register (GPIO0 to 15) +#define GPIO_O_GPAMUX2 0x8U // GPIO A Mux 2 Register (GPIO16 to 31) +#define GPIO_O_GPADIR 0xAU // GPIO A Direction Register (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xCU // GPIO A Pull Up Disable Register (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10U // GPIO A Input Polarity Invert Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12U // GPIO A Open Drain Output Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20U // GPIO A Peripheral Group Mux (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22U // GPIO A Peripheral Group Mux (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28U // GPIO A Core Select Register (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2AU // GPIO A Core Select Register (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2CU // GPIO A Core Select Register (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2EU // GPIO A Core Select Register (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3CU // GPIO A Lock Configuration Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3EU // GPIO A Lock Commit Register (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40U // GPIO B Qualification Sampling Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42U // GPIO B Qualifier Select 1 Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44U // GPIO B Qualifier Select 2 Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46U // GPIO B Mux 1 Register (GPIO32 to 47) +#define GPIO_O_GPBMUX2 0x48U // GPIO B Mux 2 Register (GPIO48 to 63) +#define GPIO_O_GPBDIR 0x4AU // GPIO B Direction Register (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4CU // GPIO B Pull Up Disable Register (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50U // GPIO B Input Polarity Invert Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52U // GPIO B Open Drain Output Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54U // GPIO B Analog Mode Select register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60U // GPIO B Peripheral Group Mux (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62U // GPIO B Peripheral Group Mux (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68U // GPIO B Core Select Register (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6AU // GPIO B Core Select Register (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6CU // GPIO B Core Select Register (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6EU // GPIO B Core Select Register (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7CU // GPIO B Lock Configuration Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7EU // GPIO B Lock Commit Register (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80U // GPIO C Qualification Sampling Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82U // GPIO C Qualifier Select 1 Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84U // GPIO C Qualifier Select 2 Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86U // GPIO C Mux 1 Register (GPIO64 to 79) +#define GPIO_O_GPCMUX2 0x88U // GPIO C Mux 2 Register (GPIO80 to 95) +#define GPIO_O_GPCDIR 0x8AU // GPIO C Direction Register (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8CU // GPIO C Pull Up Disable Register (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90U // GPIO C Input Polarity Invert Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92U // GPIO C Open Drain Output Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0U // GPIO C Peripheral Group Mux (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2U // GPIO C Peripheral Group Mux (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8U // GPIO C Core Select Register (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAAU // GPIO C Core Select Register (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xACU // GPIO C Core Select Register (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAEU // GPIO C Core Select Register (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBCU // GPIO C Lock Configuration Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBEU // GPIO C Lock Commit Register (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0U // GPIO D Qualification Sampling Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2U // GPIO D Qualifier Select 1 Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4U // GPIO D Qualifier Select 2 Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6U // GPIO D Mux 1 Register (GPIO96 to 111) +#define GPIO_O_GPDMUX2 0xC8U // GPIO D Mux 2 Register (GPIO112 to 127) +#define GPIO_O_GPDDIR 0xCAU // GPIO D Direction Register (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCCU // GPIO D Pull Up Disable Register (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0U // GPIO D Input Polarity Invert Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2U // GPIO D Open Drain Output Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0U // GPIO D Peripheral Group Mux (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2U // GPIO D Peripheral Group Mux (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8U // GPIO D Core Select Register (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEAU // GPIO D Core Select Register (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xECU // GPIO D Core Select Register (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEEU // GPIO D Core Select Register (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFCU // GPIO D Lock Configuration Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFEU // GPIO D Lock Commit Register (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100U // GPIO E Qualification Sampling Period Control (GPIO128 to 159) +#define GPIO_O_GPEQSEL1 0x102U // GPIO E Qualifier Select 1 Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104U // GPIO E Qualifier Select 2 Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106U // GPIO E Mux 1 Register (GPIO128 to 143) +#define GPIO_O_GPEMUX2 0x108U // GPIO E Mux 2 Register (GPIO144 to 159) +#define GPIO_O_GPEDIR 0x10AU // GPIO E Direction Register (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10CU // GPIO E Pull Up Disable Register (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110U // GPIO E Input Polarity Invert Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112U // GPIO E Open Drain Output Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120U // GPIO E Peripheral Group Mux (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122U // GPIO E Peripheral Group Mux (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128U // GPIO E Core Select Register (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12AU // GPIO E Core Select Register (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12CU // GPIO E Core Select Register (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12EU // GPIO E Core Select Register (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13CU // GPIO E Lock Configuration Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13EU // GPIO E Lock Commit Register (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140U // GPIO F Qualification Sampling Period Control (GPIO160 to 168) +#define GPIO_O_GPFQSEL1 0x142U // GPIO F Qualifier Select 1 Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146U // GPIO F Mux 1 Register (GPIO160 to 168) +#define GPIO_O_GPFDIR 0x14AU // GPIO F Direction Register (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14CU // GPIO F Pull Up Disable Register (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150U // GPIO F Input Polarity Invert Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152U // GPIO F Open Drain Output Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160U // GPIO F Peripheral Group Mux (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168U // GPIO F Core Select Register (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16AU // GPIO F Core Select Register (GPIO168) +#define GPIO_O_GPFLOCK 0x17CU // GPIO F Lock Configuration Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17EU // GPIO F Lock Commit Register (GPIO160 to 168) + +#define GPIO_O_GPADAT 0x0U // GPIO A Data Register (GPIO0 to 31) +#define GPIO_O_GPASET 0x2U // GPIO A Data Set Register (GPIO0 to 31) +#define GPIO_O_GPACLEAR 0x4U // GPIO A Data Clear Register (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6U // GPIO A Data Toggle Register (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8U // GPIO B Data Register (GPIO32 to 63) +#define GPIO_O_GPBSET 0xAU // GPIO B Data Set Register (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xCU // GPIO B Data Clear Register (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xEU // GPIO B Data Toggle Register (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10U // GPIO C Data Register (GPIO64 to 95) +#define GPIO_O_GPCSET 0x12U // GPIO C Data Set Register (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14U // GPIO C Data Clear Register (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16U // GPIO C Data Toggle Register (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18U // GPIO D Data Register (GPIO96 to 127) +#define GPIO_O_GPDSET 0x1AU // GPIO D Data Set Register (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1CU // GPIO D Data Clear Register (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1EU // GPIO D Data Toggle Register (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20U // GPIO E Data Register (GPIO128 to 159) +#define GPIO_O_GPESET 0x22U // GPIO E Data Set Register (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24U // GPIO E Data Clear Register (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26U // GPIO E Data Toggle Register (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28U // GPIO F Data Register (GPIO160 to 168) +#define GPIO_O_GPFSET 0x2AU // GPIO F Data Set Register (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2CU // GPIO F Data Clear Register (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2EU // GPIO F Data Toggle Register (GPIO160 to 168) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACTRL register +// +//************************************************************************************************* +#define GPIO_GPACTRL_QUALPRD0_S 0U +#define GPIO_GPACTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8U +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO8 to + // GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16U +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO16 to + // GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24U +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO24 to + // GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL1_GPIO0_S 0U +#define GPIO_GPAQSEL1_GPIO0_M 0x3U // Select input qualification type for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2U +#define GPIO_GPAQSEL1_GPIO1_M 0xCU // Select input qualification type for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4U +#define GPIO_GPAQSEL1_GPIO2_M 0x30U // Select input qualification type for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6U +#define GPIO_GPAQSEL1_GPIO3_M 0xC0U // Select input qualification type for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8U +#define GPIO_GPAQSEL1_GPIO4_M 0x300U // Select input qualification type for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10U +#define GPIO_GPAQSEL1_GPIO5_M 0xC00U // Select input qualification type for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12U +#define GPIO_GPAQSEL1_GPIO6_M 0x3000U // Select input qualification type for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14U +#define GPIO_GPAQSEL1_GPIO7_M 0xC000U // Select input qualification type for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16U +#define GPIO_GPAQSEL1_GPIO8_M 0x30000U // Select input qualification type for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18U +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000U // Select input qualification type for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20U +#define GPIO_GPAQSEL1_GPIO10_M 0x300000U // Select input qualification type for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22U +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000U // Select input qualification type for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24U +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000U // Select input qualification type for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26U +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000U // Select input qualification type for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28U +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000U // Select input qualification type for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30U +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000U // Select input qualification type for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL2_GPIO16_S 0U +#define GPIO_GPAQSEL2_GPIO16_M 0x3U // Select input qualification type for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2U +#define GPIO_GPAQSEL2_GPIO17_M 0xCU // Select input qualification type for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4U +#define GPIO_GPAQSEL2_GPIO18_M 0x30U // Select input qualification type for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6U +#define GPIO_GPAQSEL2_GPIO19_M 0xC0U // Select input qualification type for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8U +#define GPIO_GPAQSEL2_GPIO20_M 0x300U // Select input qualification type for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10U +#define GPIO_GPAQSEL2_GPIO21_M 0xC00U // Select input qualification type for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12U +#define GPIO_GPAQSEL2_GPIO22_M 0x3000U // Select input qualification type for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14U +#define GPIO_GPAQSEL2_GPIO23_M 0xC000U // Select input qualification type for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16U +#define GPIO_GPAQSEL2_GPIO24_M 0x30000U // Select input qualification type for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18U +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000U // Select input qualification type for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20U +#define GPIO_GPAQSEL2_GPIO26_M 0x300000U // Select input qualification type for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22U +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000U // Select input qualification type for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24U +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000U // Select input qualification type for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26U +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000U // Select input qualification type for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28U +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000U // Select input qualification type for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30U +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000U // Select input qualification type for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAMUX1_GPIO0_S 0U +#define GPIO_GPAMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2U +#define GPIO_GPAMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4U +#define GPIO_GPAMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6U +#define GPIO_GPAMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8U +#define GPIO_GPAMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10U +#define GPIO_GPAMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12U +#define GPIO_GPAMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14U +#define GPIO_GPAMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16U +#define GPIO_GPAMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18U +#define GPIO_GPAMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20U +#define GPIO_GPAMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22U +#define GPIO_GPAMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24U +#define GPIO_GPAMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26U +#define GPIO_GPAMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28U +#define GPIO_GPAMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30U +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAMUX2_GPIO16_S 0U +#define GPIO_GPAMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2U +#define GPIO_GPAMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4U +#define GPIO_GPAMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6U +#define GPIO_GPAMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8U +#define GPIO_GPAMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10U +#define GPIO_GPAMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12U +#define GPIO_GPAMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14U +#define GPIO_GPAMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16U +#define GPIO_GPAMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18U +#define GPIO_GPAMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20U +#define GPIO_GPAMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22U +#define GPIO_GPAMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24U +#define GPIO_GPAMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26U +#define GPIO_GPAMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28U +#define GPIO_GPAMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30U +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADIR register +// +//************************************************************************************************* +#define GPIO_GPADIR_GPIO0 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAPUD register +// +//************************************************************************************************* +#define GPIO_GPAPUD_GPIO0 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO1 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO2 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO3 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO4 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO5 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO6 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO7 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO8 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO9 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO10 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO11 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO12 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO13 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO14 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO15 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO16 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO17 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO18 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO19 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO20 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO21 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO22 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO23 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO24 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO25 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO26 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO27 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO28 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO29 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO30 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO31 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAINV register +// +//************************************************************************************************* +#define GPIO_GPAINV_GPIO0 0x1U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO1 0x2U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO2 0x4U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO3 0x8U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO4 0x10U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO5 0x20U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO6 0x40U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO7 0x80U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO8 0x100U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO9 0x200U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO10 0x400U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO11 0x800U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO12 0x1000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO13 0x2000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO14 0x4000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO15 0x8000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO16 0x10000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO17 0x20000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO18 0x40000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO19 0x80000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO20 0x100000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO21 0x200000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO22 0x400000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO23 0x800000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO24 0x1000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO25 0x2000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO26 0x4000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO27 0x8000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO28 0x10000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO29 0x20000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO30 0x40000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO31 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAODR register +// +//************************************************************************************************* +#define GPIO_GPAODR_GPIO0 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO1 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO2 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO3 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO4 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO5 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO6 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO7 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO8 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO9 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO10 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO11 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO12 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO13 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO14 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO15 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO16 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO17 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO18 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO19 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO20 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO21 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO22 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO23 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO24 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO25 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO26 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO27 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO28 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO29 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO30 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO31 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX1_GPIO0_S 0U +#define GPIO_GPAGMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2U +#define GPIO_GPAGMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4U +#define GPIO_GPAGMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6U +#define GPIO_GPAGMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8U +#define GPIO_GPAGMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10U +#define GPIO_GPAGMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12U +#define GPIO_GPAGMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14U +#define GPIO_GPAGMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16U +#define GPIO_GPAGMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18U +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20U +#define GPIO_GPAGMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22U +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24U +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26U +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28U +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30U +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX2_GPIO16_S 0U +#define GPIO_GPAGMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2U +#define GPIO_GPAGMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4U +#define GPIO_GPAGMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6U +#define GPIO_GPAGMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8U +#define GPIO_GPAGMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10U +#define GPIO_GPAGMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12U +#define GPIO_GPAGMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14U +#define GPIO_GPAGMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16U +#define GPIO_GPAGMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18U +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20U +#define GPIO_GPAGMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22U +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24U +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26U +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28U +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30U +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//************************************************************************************************* +#define GPIO_GPACSEL1_GPIO0_S 0U +#define GPIO_GPACSEL1_GPIO0_M 0xFU // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4U +#define GPIO_GPACSEL1_GPIO1_M 0xF0U // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8U +#define GPIO_GPACSEL1_GPIO2_M 0xF00U // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12U +#define GPIO_GPACSEL1_GPIO3_M 0xF000U // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16U +#define GPIO_GPACSEL1_GPIO4_M 0xF0000U // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20U +#define GPIO_GPACSEL1_GPIO5_M 0xF00000U // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24U +#define GPIO_GPACSEL1_GPIO6_M 0xF000000U // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28U +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000U // GPIO7 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//************************************************************************************************* +#define GPIO_GPACSEL2_GPIO8_S 0U +#define GPIO_GPACSEL2_GPIO8_M 0xFU // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4U +#define GPIO_GPACSEL2_GPIO9_M 0xF0U // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8U +#define GPIO_GPACSEL2_GPIO10_M 0xF00U // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12U +#define GPIO_GPACSEL2_GPIO11_M 0xF000U // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16U +#define GPIO_GPACSEL2_GPIO12_M 0xF0000U // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20U +#define GPIO_GPACSEL2_GPIO13_M 0xF00000U // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24U +#define GPIO_GPACSEL2_GPIO14_M 0xF000000U // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28U +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000U // GPIO15 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//************************************************************************************************* +#define GPIO_GPACSEL3_GPIO16_S 0U +#define GPIO_GPACSEL3_GPIO16_M 0xFU // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4U +#define GPIO_GPACSEL3_GPIO17_M 0xF0U // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8U +#define GPIO_GPACSEL3_GPIO18_M 0xF00U // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12U +#define GPIO_GPACSEL3_GPIO19_M 0xF000U // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16U +#define GPIO_GPACSEL3_GPIO20_M 0xF0000U // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20U +#define GPIO_GPACSEL3_GPIO21_M 0xF00000U // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24U +#define GPIO_GPACSEL3_GPIO22_M 0xF000000U // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28U +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000U // GPIO23 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//************************************************************************************************* +#define GPIO_GPACSEL4_GPIO24_S 0U +#define GPIO_GPACSEL4_GPIO24_M 0xFU // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4U +#define GPIO_GPACSEL4_GPIO25_M 0xF0U // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8U +#define GPIO_GPACSEL4_GPIO26_M 0xF00U // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12U +#define GPIO_GPACSEL4_GPIO27_M 0xF000U // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16U +#define GPIO_GPACSEL4_GPIO28_M 0xF0000U // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20U +#define GPIO_GPACSEL4_GPIO29_M 0xF00000U // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24U +#define GPIO_GPACSEL4_GPIO30_M 0xF000000U // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28U +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000U // GPIO31 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPALOCK register +// +//************************************************************************************************* +#define GPIO_GPALOCK_GPIO0 0x1U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO1 0x2U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO2 0x4U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO3 0x8U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO4 0x10U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO5 0x20U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO6 0x40U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO7 0x80U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO8 0x100U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO9 0x200U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO10 0x400U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO11 0x800U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO12 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO13 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO14 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO15 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO16 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO17 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO18 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO19 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO20 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO21 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO22 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO23 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO24 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO25 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO26 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO27 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO28 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO29 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO30 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO31 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACR register +// +//************************************************************************************************* +#define GPIO_GPACR_GPIO0 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO1 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO2 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO3 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO4 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO5 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO6 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO7 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO8 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO9 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO10 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO11 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO12 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO13 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO14 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO15 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO16 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO17 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO18 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO19 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO20 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO21 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO22 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO23 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO24 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO25 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO26 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO27 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO28 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO29 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO30 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO31 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCTRL register +// +//************************************************************************************************* +#define GPIO_GPBCTRL_QUALPRD0_S 0U +#define GPIO_GPBCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO32 to + // GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8U +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO40 to + // GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16U +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO48 to + // GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24U +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO56 to + // GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL1_GPIO32_S 0U +#define GPIO_GPBQSEL1_GPIO32_M 0x3U // Select input qualification type for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2U +#define GPIO_GPBQSEL1_GPIO33_M 0xCU // Select input qualification type for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4U +#define GPIO_GPBQSEL1_GPIO34_M 0x30U // Select input qualification type for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6U +#define GPIO_GPBQSEL1_GPIO35_M 0xC0U // Select input qualification type for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8U +#define GPIO_GPBQSEL1_GPIO36_M 0x300U // Select input qualification type for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10U +#define GPIO_GPBQSEL1_GPIO37_M 0xC00U // Select input qualification type for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12U +#define GPIO_GPBQSEL1_GPIO38_M 0x3000U // Select input qualification type for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14U +#define GPIO_GPBQSEL1_GPIO39_M 0xC000U // Select input qualification type for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16U +#define GPIO_GPBQSEL1_GPIO40_M 0x30000U // Select input qualification type for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18U +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000U // Select input qualification type for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20U +#define GPIO_GPBQSEL1_GPIO42_M 0x300000U // Select input qualification type for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22U +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000U // Select input qualification type for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24U +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000U // Select input qualification type for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26U +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000U // Select input qualification type for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28U +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000U // Select input qualification type for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30U +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000U // Select input qualification type for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL2_GPIO48_S 0U +#define GPIO_GPBQSEL2_GPIO48_M 0x3U // Select input qualification type for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2U +#define GPIO_GPBQSEL2_GPIO49_M 0xCU // Select input qualification type for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4U +#define GPIO_GPBQSEL2_GPIO50_M 0x30U // Select input qualification type for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6U +#define GPIO_GPBQSEL2_GPIO51_M 0xC0U // Select input qualification type for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8U +#define GPIO_GPBQSEL2_GPIO52_M 0x300U // Select input qualification type for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10U +#define GPIO_GPBQSEL2_GPIO53_M 0xC00U // Select input qualification type for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12U +#define GPIO_GPBQSEL2_GPIO54_M 0x3000U // Select input qualification type for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14U +#define GPIO_GPBQSEL2_GPIO55_M 0xC000U // Select input qualification type for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16U +#define GPIO_GPBQSEL2_GPIO56_M 0x30000U // Select input qualification type for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18U +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000U // Select input qualification type for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20U +#define GPIO_GPBQSEL2_GPIO58_M 0x300000U // Select input qualification type for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22U +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000U // Select input qualification type for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24U +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000U // Select input qualification type for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26U +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000U // Select input qualification type for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28U +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000U // Select input qualification type for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30U +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000U // Select input qualification type for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBMUX1_GPIO32_S 0U +#define GPIO_GPBMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2U +#define GPIO_GPBMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4U +#define GPIO_GPBMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6U +#define GPIO_GPBMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8U +#define GPIO_GPBMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10U +#define GPIO_GPBMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12U +#define GPIO_GPBMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14U +#define GPIO_GPBMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16U +#define GPIO_GPBMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18U +#define GPIO_GPBMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20U +#define GPIO_GPBMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22U +#define GPIO_GPBMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24U +#define GPIO_GPBMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26U +#define GPIO_GPBMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28U +#define GPIO_GPBMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30U +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBMUX2_GPIO48_S 0U +#define GPIO_GPBMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2U +#define GPIO_GPBMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4U +#define GPIO_GPBMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6U +#define GPIO_GPBMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8U +#define GPIO_GPBMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10U +#define GPIO_GPBMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12U +#define GPIO_GPBMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14U +#define GPIO_GPBMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16U +#define GPIO_GPBMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18U +#define GPIO_GPBMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20U +#define GPIO_GPBMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22U +#define GPIO_GPBMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24U +#define GPIO_GPBMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26U +#define GPIO_GPBMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28U +#define GPIO_GPBMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30U +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDIR register +// +//************************************************************************************************* +#define GPIO_GPBDIR_GPIO32 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBPUD register +// +//************************************************************************************************* +#define GPIO_GPBPUD_GPIO32 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO33 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO34 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO35 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO36 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO37 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO38 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO39 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO40 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO41 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO42 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO43 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO44 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO45 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO46 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO47 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO48 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO49 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO50 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO51 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO52 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO53 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO54 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO55 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO56 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO57 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO58 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO59 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO60 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO61 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO62 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO63 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBINV register +// +//************************************************************************************************* +#define GPIO_GPBINV_GPIO32 0x1U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO33 0x2U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO34 0x4U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO35 0x8U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO36 0x10U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO37 0x20U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO38 0x40U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO39 0x80U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO40 0x100U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO41 0x200U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO42 0x400U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO43 0x800U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO44 0x1000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO45 0x2000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO46 0x4000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO47 0x8000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO48 0x10000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO49 0x20000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO50 0x40000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO51 0x80000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO52 0x100000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO53 0x200000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO54 0x400000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO55 0x800000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO56 0x1000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO57 0x2000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO58 0x4000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO59 0x8000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO60 0x10000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO61 0x20000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO62 0x40000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO63 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBODR register +// +//************************************************************************************************* +#define GPIO_GPBODR_GPIO32 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO33 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO34 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO35 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO36 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO37 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO38 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO39 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO40 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO41 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO42 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO43 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO44 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO45 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO46 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO47 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO48 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO49 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO50 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO51 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO52 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO53 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO54 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO55 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO56 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO57 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO58 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO59 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO60 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO61 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO62 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO63 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//************************************************************************************************* +#define GPIO_GPBAMSEL_GPIO42 0x400U // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800U // Analog Mode select for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX1_GPIO32_S 0U +#define GPIO_GPBGMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2U +#define GPIO_GPBGMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4U +#define GPIO_GPBGMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6U +#define GPIO_GPBGMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8U +#define GPIO_GPBGMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10U +#define GPIO_GPBGMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12U +#define GPIO_GPBGMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14U +#define GPIO_GPBGMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16U +#define GPIO_GPBGMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18U +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20U +#define GPIO_GPBGMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22U +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24U +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26U +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28U +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30U +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX2_GPIO48_S 0U +#define GPIO_GPBGMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2U +#define GPIO_GPBGMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4U +#define GPIO_GPBGMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6U +#define GPIO_GPBGMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8U +#define GPIO_GPBGMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10U +#define GPIO_GPBGMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12U +#define GPIO_GPBGMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14U +#define GPIO_GPBGMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16U +#define GPIO_GPBGMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18U +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20U +#define GPIO_GPBGMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22U +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24U +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26U +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28U +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30U +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL1_GPIO32_S 0U +#define GPIO_GPBCSEL1_GPIO32_M 0xFU // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4U +#define GPIO_GPBCSEL1_GPIO33_M 0xF0U // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8U +#define GPIO_GPBCSEL1_GPIO34_M 0xF00U // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12U +#define GPIO_GPBCSEL1_GPIO35_M 0xF000U // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16U +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000U // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20U +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000U // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24U +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000U // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28U +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000U // GPIO39 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL2_GPIO40_S 0U +#define GPIO_GPBCSEL2_GPIO40_M 0xFU // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4U +#define GPIO_GPBCSEL2_GPIO41_M 0xF0U // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8U +#define GPIO_GPBCSEL2_GPIO42_M 0xF00U // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12U +#define GPIO_GPBCSEL2_GPIO43_M 0xF000U // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16U +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000U // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20U +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000U // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24U +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000U // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28U +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000U // GPIO47 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL3_GPIO48_S 0U +#define GPIO_GPBCSEL3_GPIO48_M 0xFU // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4U +#define GPIO_GPBCSEL3_GPIO49_M 0xF0U // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8U +#define GPIO_GPBCSEL3_GPIO50_M 0xF00U // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12U +#define GPIO_GPBCSEL3_GPIO51_M 0xF000U // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16U +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000U // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20U +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000U // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24U +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000U // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28U +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000U // GPIO55 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL4_GPIO56_S 0U +#define GPIO_GPBCSEL4_GPIO56_M 0xFU // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4U +#define GPIO_GPBCSEL4_GPIO57_M 0xF0U // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8U +#define GPIO_GPBCSEL4_GPIO58_M 0xF00U // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12U +#define GPIO_GPBCSEL4_GPIO59_M 0xF000U // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16U +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000U // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20U +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000U // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24U +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000U // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28U +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000U // GPIO63 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBLOCK register +// +//************************************************************************************************* +#define GPIO_GPBLOCK_GPIO32 0x1U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO33 0x2U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO34 0x4U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO35 0x8U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO36 0x10U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO37 0x20U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO38 0x40U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO39 0x80U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO40 0x100U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO41 0x200U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO42 0x400U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO43 0x800U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO44 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO45 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO46 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO47 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO48 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO49 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO50 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO51 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO52 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO53 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO54 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO55 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO56 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO57 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO58 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO59 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO60 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO61 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO62 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO63 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCR register +// +//************************************************************************************************* +#define GPIO_GPBCR_GPIO32 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO33 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO34 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO35 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO36 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO37 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO38 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO39 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO40 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO41 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO42 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO43 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO44 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO45 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO46 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO47 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO48 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO49 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO50 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO51 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO52 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO53 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO54 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO55 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO56 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO57 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO58 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO59 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO60 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO61 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO62 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO63 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCTRL register +// +//************************************************************************************************* +#define GPIO_GPCCTRL_QUALPRD0_S 0U +#define GPIO_GPCCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO64 to + // GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8U +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO72 to + // GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16U +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO80 to + // GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24U +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO88 to + // GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL1_GPIO64_S 0U +#define GPIO_GPCQSEL1_GPIO64_M 0x3U // Select input qualification type for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2U +#define GPIO_GPCQSEL1_GPIO65_M 0xCU // Select input qualification type for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4U +#define GPIO_GPCQSEL1_GPIO66_M 0x30U // Select input qualification type for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6U +#define GPIO_GPCQSEL1_GPIO67_M 0xC0U // Select input qualification type for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8U +#define GPIO_GPCQSEL1_GPIO68_M 0x300U // Select input qualification type for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10U +#define GPIO_GPCQSEL1_GPIO69_M 0xC00U // Select input qualification type for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12U +#define GPIO_GPCQSEL1_GPIO70_M 0x3000U // Select input qualification type for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14U +#define GPIO_GPCQSEL1_GPIO71_M 0xC000U // Select input qualification type for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16U +#define GPIO_GPCQSEL1_GPIO72_M 0x30000U // Select input qualification type for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18U +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000U // Select input qualification type for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20U +#define GPIO_GPCQSEL1_GPIO74_M 0x300000U // Select input qualification type for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22U +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000U // Select input qualification type for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24U +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000U // Select input qualification type for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26U +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000U // Select input qualification type for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28U +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000U // Select input qualification type for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30U +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000U // Select input qualification type for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL2_GPIO80_S 0U +#define GPIO_GPCQSEL2_GPIO80_M 0x3U // Select input qualification type for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2U +#define GPIO_GPCQSEL2_GPIO81_M 0xCU // Select input qualification type for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4U +#define GPIO_GPCQSEL2_GPIO82_M 0x30U // Select input qualification type for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6U +#define GPIO_GPCQSEL2_GPIO83_M 0xC0U // Select input qualification type for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8U +#define GPIO_GPCQSEL2_GPIO84_M 0x300U // Select input qualification type for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10U +#define GPIO_GPCQSEL2_GPIO85_M 0xC00U // Select input qualification type for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12U +#define GPIO_GPCQSEL2_GPIO86_M 0x3000U // Select input qualification type for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14U +#define GPIO_GPCQSEL2_GPIO87_M 0xC000U // Select input qualification type for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16U +#define GPIO_GPCQSEL2_GPIO88_M 0x30000U // Select input qualification type for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18U +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000U // Select input qualification type for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20U +#define GPIO_GPCQSEL2_GPIO90_M 0x300000U // Select input qualification type for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22U +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000U // Select input qualification type for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24U +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000U // Select input qualification type for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26U +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000U // Select input qualification type for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28U +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000U // Select input qualification type for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30U +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000U // Select input qualification type for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCMUX1_GPIO64_S 0U +#define GPIO_GPCMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2U +#define GPIO_GPCMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4U +#define GPIO_GPCMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6U +#define GPIO_GPCMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8U +#define GPIO_GPCMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10U +#define GPIO_GPCMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12U +#define GPIO_GPCMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14U +#define GPIO_GPCMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16U +#define GPIO_GPCMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18U +#define GPIO_GPCMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20U +#define GPIO_GPCMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22U +#define GPIO_GPCMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24U +#define GPIO_GPCMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26U +#define GPIO_GPCMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28U +#define GPIO_GPCMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30U +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCMUX2_GPIO80_S 0U +#define GPIO_GPCMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2U +#define GPIO_GPCMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4U +#define GPIO_GPCMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6U +#define GPIO_GPCMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8U +#define GPIO_GPCMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10U +#define GPIO_GPCMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12U +#define GPIO_GPCMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14U +#define GPIO_GPCMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16U +#define GPIO_GPCMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18U +#define GPIO_GPCMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20U +#define GPIO_GPCMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22U +#define GPIO_GPCMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24U +#define GPIO_GPCMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26U +#define GPIO_GPCMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28U +#define GPIO_GPCMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30U +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDIR register +// +//************************************************************************************************* +#define GPIO_GPCDIR_GPIO64 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCPUD register +// +//************************************************************************************************* +#define GPIO_GPCPUD_GPIO64 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO65 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO66 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO67 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO68 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO69 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO70 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO71 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO72 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO73 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO74 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO75 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO76 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO77 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO78 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO79 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO80 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO81 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO82 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO83 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO84 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO85 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO86 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO87 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO88 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO89 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO90 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO91 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO92 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO93 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO94 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO95 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCINV register +// +//************************************************************************************************* +#define GPIO_GPCINV_GPIO64 0x1U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO65 0x2U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO66 0x4U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO67 0x8U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO68 0x10U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO69 0x20U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO70 0x40U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO71 0x80U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO72 0x100U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO73 0x200U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO74 0x400U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO75 0x800U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO76 0x1000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO77 0x2000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO78 0x4000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO79 0x8000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO80 0x10000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO81 0x20000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO82 0x40000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO83 0x80000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO84 0x100000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO85 0x200000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO86 0x400000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO87 0x800000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO88 0x1000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO89 0x2000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO90 0x4000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO91 0x8000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO92 0x10000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO93 0x20000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO94 0x40000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO95 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCODR register +// +//************************************************************************************************* +#define GPIO_GPCODR_GPIO64 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO65 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO66 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO67 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO68 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO69 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO70 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO71 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO72 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO73 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO74 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO75 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO76 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO77 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO78 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO79 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO80 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO81 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO82 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO83 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO84 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO85 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO86 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO87 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO88 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO89 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO90 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO91 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO92 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO93 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO94 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO95 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX1_GPIO64_S 0U +#define GPIO_GPCGMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2U +#define GPIO_GPCGMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4U +#define GPIO_GPCGMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6U +#define GPIO_GPCGMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8U +#define GPIO_GPCGMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10U +#define GPIO_GPCGMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12U +#define GPIO_GPCGMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14U +#define GPIO_GPCGMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16U +#define GPIO_GPCGMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18U +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20U +#define GPIO_GPCGMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22U +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24U +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26U +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28U +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30U +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX2_GPIO80_S 0U +#define GPIO_GPCGMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2U +#define GPIO_GPCGMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4U +#define GPIO_GPCGMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6U +#define GPIO_GPCGMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8U +#define GPIO_GPCGMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10U +#define GPIO_GPCGMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12U +#define GPIO_GPCGMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14U +#define GPIO_GPCGMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16U +#define GPIO_GPCGMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18U +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20U +#define GPIO_GPCGMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22U +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24U +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26U +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28U +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30U +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL1_GPIO64_S 0U +#define GPIO_GPCCSEL1_GPIO64_M 0xFU // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4U +#define GPIO_GPCCSEL1_GPIO65_M 0xF0U // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8U +#define GPIO_GPCCSEL1_GPIO66_M 0xF00U // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12U +#define GPIO_GPCCSEL1_GPIO67_M 0xF000U // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16U +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000U // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20U +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000U // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24U +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000U // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28U +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000U // GPIO71 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL2_GPIO72_S 0U +#define GPIO_GPCCSEL2_GPIO72_M 0xFU // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4U +#define GPIO_GPCCSEL2_GPIO73_M 0xF0U // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8U +#define GPIO_GPCCSEL2_GPIO74_M 0xF00U // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12U +#define GPIO_GPCCSEL2_GPIO75_M 0xF000U // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16U +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000U // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20U +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000U // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24U +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000U // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28U +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000U // GPIO79 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL3_GPIO80_S 0U +#define GPIO_GPCCSEL3_GPIO80_M 0xFU // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4U +#define GPIO_GPCCSEL3_GPIO81_M 0xF0U // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8U +#define GPIO_GPCCSEL3_GPIO82_M 0xF00U // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12U +#define GPIO_GPCCSEL3_GPIO83_M 0xF000U // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16U +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000U // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20U +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000U // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24U +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000U // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28U +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000U // GPIO87 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL4_GPIO88_S 0U +#define GPIO_GPCCSEL4_GPIO88_M 0xFU // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4U +#define GPIO_GPCCSEL4_GPIO89_M 0xF0U // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8U +#define GPIO_GPCCSEL4_GPIO90_M 0xF00U // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12U +#define GPIO_GPCCSEL4_GPIO91_M 0xF000U // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16U +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000U // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20U +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000U // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24U +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000U // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28U +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000U // GPIO95 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCLOCK register +// +//************************************************************************************************* +#define GPIO_GPCLOCK_GPIO64 0x1U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO65 0x2U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO66 0x4U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO67 0x8U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO68 0x10U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO69 0x20U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO70 0x40U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO71 0x80U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO72 0x100U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO73 0x200U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO74 0x400U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO75 0x800U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO76 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO77 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO78 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO79 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO80 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO81 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO82 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO83 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO84 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO85 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO86 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO87 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO88 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO89 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO90 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO91 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO92 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO93 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO94 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO95 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCR register +// +//************************************************************************************************* +#define GPIO_GPCCR_GPIO64 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO65 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO66 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO67 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO68 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO69 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO70 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO71 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO72 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO73 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO74 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO75 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO76 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO77 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO78 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO79 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO80 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO81 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO82 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO83 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO84 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO85 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO86 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO87 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO88 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO89 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO90 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO91 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO92 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO93 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO94 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO95 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCTRL register +// +//************************************************************************************************* +#define GPIO_GPDCTRL_QUALPRD0_S 0U +#define GPIO_GPDCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO96 to + // GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8U +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO104 to + // GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16U +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO112 to + // GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24U +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO120 to + // GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL1_GPIO96_S 0U +#define GPIO_GPDQSEL1_GPIO96_M 0x3U // Select input qualification type for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2U +#define GPIO_GPDQSEL1_GPIO97_M 0xCU // Select input qualification type for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4U +#define GPIO_GPDQSEL1_GPIO98_M 0x30U // Select input qualification type for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6U +#define GPIO_GPDQSEL1_GPIO99_M 0xC0U // Select input qualification type for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8U +#define GPIO_GPDQSEL1_GPIO100_M 0x300U // Select input qualification type for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10U +#define GPIO_GPDQSEL1_GPIO101_M 0xC00U // Select input qualification type for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12U +#define GPIO_GPDQSEL1_GPIO102_M 0x3000U // Select input qualification type for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14U +#define GPIO_GPDQSEL1_GPIO103_M 0xC000U // Select input qualification type for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16U +#define GPIO_GPDQSEL1_GPIO104_M 0x30000U // Select input qualification type for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18U +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000U // Select input qualification type for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20U +#define GPIO_GPDQSEL1_GPIO106_M 0x300000U // Select input qualification type for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22U +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000U // Select input qualification type for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24U +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000U // Select input qualification type for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26U +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000U // Select input qualification type for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28U +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000U // Select input qualification type for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30U +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000U // Select input qualification type for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL2_GPIO112_S 0U +#define GPIO_GPDQSEL2_GPIO112_M 0x3U // Select input qualification type for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2U +#define GPIO_GPDQSEL2_GPIO113_M 0xCU // Select input qualification type for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4U +#define GPIO_GPDQSEL2_GPIO114_M 0x30U // Select input qualification type for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6U +#define GPIO_GPDQSEL2_GPIO115_M 0xC0U // Select input qualification type for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8U +#define GPIO_GPDQSEL2_GPIO116_M 0x300U // Select input qualification type for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10U +#define GPIO_GPDQSEL2_GPIO117_M 0xC00U // Select input qualification type for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12U +#define GPIO_GPDQSEL2_GPIO118_M 0x3000U // Select input qualification type for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14U +#define GPIO_GPDQSEL2_GPIO119_M 0xC000U // Select input qualification type for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16U +#define GPIO_GPDQSEL2_GPIO120_M 0x30000U // Select input qualification type for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18U +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000U // Select input qualification type for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20U +#define GPIO_GPDQSEL2_GPIO122_M 0x300000U // Select input qualification type for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22U +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000U // Select input qualification type for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24U +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000U // Select input qualification type for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26U +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000U // Select input qualification type for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28U +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000U // Select input qualification type for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30U +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000U // Select input qualification type for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDMUX1_GPIO96_S 0U +#define GPIO_GPDMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2U +#define GPIO_GPDMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4U +#define GPIO_GPDMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6U +#define GPIO_GPDMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8U +#define GPIO_GPDMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10U +#define GPIO_GPDMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12U +#define GPIO_GPDMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14U +#define GPIO_GPDMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16U +#define GPIO_GPDMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18U +#define GPIO_GPDMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20U +#define GPIO_GPDMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22U +#define GPIO_GPDMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24U +#define GPIO_GPDMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26U +#define GPIO_GPDMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28U +#define GPIO_GPDMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30U +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDMUX2_GPIO112_S 0U +#define GPIO_GPDMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2U +#define GPIO_GPDMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4U +#define GPIO_GPDMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6U +#define GPIO_GPDMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8U +#define GPIO_GPDMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10U +#define GPIO_GPDMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12U +#define GPIO_GPDMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14U +#define GPIO_GPDMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16U +#define GPIO_GPDMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18U +#define GPIO_GPDMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20U +#define GPIO_GPDMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22U +#define GPIO_GPDMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24U +#define GPIO_GPDMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26U +#define GPIO_GPDMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28U +#define GPIO_GPDMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30U +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDIR register +// +//************************************************************************************************* +#define GPIO_GPDDIR_GPIO96 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDPUD register +// +//************************************************************************************************* +#define GPIO_GPDPUD_GPIO96 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO97 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO98 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO99 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO100 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO101 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO102 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO103 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO104 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO105 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO106 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO107 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO108 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO109 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO110 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO111 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO112 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO113 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO114 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO115 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO116 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO117 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO118 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO119 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO120 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO121 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO122 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO123 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO124 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO125 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO126 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO127 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDINV register +// +//************************************************************************************************* +#define GPIO_GPDINV_GPIO96 0x1U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO97 0x2U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO98 0x4U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO99 0x8U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO100 0x10U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO101 0x20U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO102 0x40U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO103 0x80U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO104 0x100U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO105 0x200U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO106 0x400U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO107 0x800U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO108 0x1000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO109 0x2000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO110 0x4000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO111 0x8000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO112 0x10000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO113 0x20000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO114 0x40000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO115 0x80000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO116 0x100000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO117 0x200000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO118 0x400000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO119 0x800000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO120 0x1000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO121 0x2000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO122 0x4000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO123 0x8000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO124 0x10000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO125 0x20000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO126 0x40000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO127 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDODR register +// +//************************************************************************************************* +#define GPIO_GPDODR_GPIO96 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO97 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO98 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO99 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO100 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO101 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO102 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO103 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO104 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO105 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO106 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO107 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO108 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO109 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO110 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO111 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO112 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO113 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO114 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO115 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO116 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO117 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO118 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO119 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO120 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO121 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO122 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO123 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO124 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO125 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO126 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO127 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX1_GPIO96_S 0U +#define GPIO_GPDGMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2U +#define GPIO_GPDGMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4U +#define GPIO_GPDGMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6U +#define GPIO_GPDGMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8U +#define GPIO_GPDGMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10U +#define GPIO_GPDGMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12U +#define GPIO_GPDGMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14U +#define GPIO_GPDGMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16U +#define GPIO_GPDGMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18U +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20U +#define GPIO_GPDGMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22U +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24U +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26U +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28U +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30U +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX2_GPIO112_S 0U +#define GPIO_GPDGMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2U +#define GPIO_GPDGMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4U +#define GPIO_GPDGMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6U +#define GPIO_GPDGMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8U +#define GPIO_GPDGMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10U +#define GPIO_GPDGMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12U +#define GPIO_GPDGMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14U +#define GPIO_GPDGMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16U +#define GPIO_GPDGMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18U +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20U +#define GPIO_GPDGMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22U +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24U +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26U +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28U +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30U +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL1_GPIO96_S 0U +#define GPIO_GPDCSEL1_GPIO96_M 0xFU // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4U +#define GPIO_GPDCSEL1_GPIO97_M 0xF0U // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8U +#define GPIO_GPDCSEL1_GPIO98_M 0xF00U // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12U +#define GPIO_GPDCSEL1_GPIO99_M 0xF000U // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16U +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000U // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20U +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000U // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24U +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000U // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28U +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000U // GPIO103 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL2_GPIO104_S 0U +#define GPIO_GPDCSEL2_GPIO104_M 0xFU // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4U +#define GPIO_GPDCSEL2_GPIO105_M 0xF0U // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8U +#define GPIO_GPDCSEL2_GPIO106_M 0xF00U // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12U +#define GPIO_GPDCSEL2_GPIO107_M 0xF000U // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16U +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000U // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20U +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000U // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24U +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000U // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28U +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000U // GPIO111 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL3_GPIO112_S 0U +#define GPIO_GPDCSEL3_GPIO112_M 0xFU // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4U +#define GPIO_GPDCSEL3_GPIO113_M 0xF0U // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8U +#define GPIO_GPDCSEL3_GPIO114_M 0xF00U // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12U +#define GPIO_GPDCSEL3_GPIO115_M 0xF000U // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16U +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000U // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20U +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000U // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24U +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000U // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28U +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000U // GPIO119 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL4_GPIO120_S 0U +#define GPIO_GPDCSEL4_GPIO120_M 0xFU // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4U +#define GPIO_GPDCSEL4_GPIO121_M 0xF0U // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8U +#define GPIO_GPDCSEL4_GPIO122_M 0xF00U // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12U +#define GPIO_GPDCSEL4_GPIO123_M 0xF000U // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16U +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000U // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20U +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000U // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24U +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000U // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28U +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000U // GPIO127 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDLOCK register +// +//************************************************************************************************* +#define GPIO_GPDLOCK_GPIO96 0x1U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO97 0x2U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO98 0x4U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO99 0x8U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO100 0x10U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO101 0x20U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO102 0x40U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO103 0x80U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO104 0x100U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO105 0x200U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO106 0x400U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO107 0x800U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO108 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO109 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO110 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO111 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO112 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO113 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO114 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO115 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO116 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO117 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO118 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO119 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO120 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO121 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO122 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO123 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO124 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO125 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO126 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO127 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCR register +// +//************************************************************************************************* +#define GPIO_GPDCR_GPIO96 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO97 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO98 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO99 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO100 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO101 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO102 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO103 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO104 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO105 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO106 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO107 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO108 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO109 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO110 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO111 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO112 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO113 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO114 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO115 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO116 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO117 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO118 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO119 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO120 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO121 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO122 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO123 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO124 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO125 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO126 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO127 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECTRL register +// +//************************************************************************************************* +#define GPIO_GPECTRL_QUALPRD0_S 0U +#define GPIO_GPECTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO128 to + // GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8U +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO136 to + // GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16U +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO144 to + // GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24U +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO152 to + // GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL1_GPIO128_S 0U +#define GPIO_GPEQSEL1_GPIO128_M 0x3U // Select input qualification type for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2U +#define GPIO_GPEQSEL1_GPIO129_M 0xCU // Select input qualification type for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4U +#define GPIO_GPEQSEL1_GPIO130_M 0x30U // Select input qualification type for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6U +#define GPIO_GPEQSEL1_GPIO131_M 0xC0U // Select input qualification type for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8U +#define GPIO_GPEQSEL1_GPIO132_M 0x300U // Select input qualification type for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10U +#define GPIO_GPEQSEL1_GPIO133_M 0xC00U // Select input qualification type for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12U +#define GPIO_GPEQSEL1_GPIO134_M 0x3000U // Select input qualification type for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14U +#define GPIO_GPEQSEL1_GPIO135_M 0xC000U // Select input qualification type for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16U +#define GPIO_GPEQSEL1_GPIO136_M 0x30000U // Select input qualification type for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18U +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000U // Select input qualification type for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20U +#define GPIO_GPEQSEL1_GPIO138_M 0x300000U // Select input qualification type for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22U +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000U // Select input qualification type for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24U +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000U // Select input qualification type for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26U +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000U // Select input qualification type for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28U +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000U // Select input qualification type for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30U +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000U // Select input qualification type for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL2_GPIO144_S 0U +#define GPIO_GPEQSEL2_GPIO144_M 0x3U // Select input qualification type for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2U +#define GPIO_GPEQSEL2_GPIO145_M 0xCU // Select input qualification type for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4U +#define GPIO_GPEQSEL2_GPIO146_M 0x30U // Select input qualification type for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6U +#define GPIO_GPEQSEL2_GPIO147_M 0xC0U // Select input qualification type for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8U +#define GPIO_GPEQSEL2_GPIO148_M 0x300U // Select input qualification type for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10U +#define GPIO_GPEQSEL2_GPIO149_M 0xC00U // Select input qualification type for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12U +#define GPIO_GPEQSEL2_GPIO150_M 0x3000U // Select input qualification type for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14U +#define GPIO_GPEQSEL2_GPIO151_M 0xC000U // Select input qualification type for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16U +#define GPIO_GPEQSEL2_GPIO152_M 0x30000U // Select input qualification type for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18U +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000U // Select input qualification type for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20U +#define GPIO_GPEQSEL2_GPIO154_M 0x300000U // Select input qualification type for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22U +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000U // Select input qualification type for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24U +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000U // Select input qualification type for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26U +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000U // Select input qualification type for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28U +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000U // Select input qualification type for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30U +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000U // Select input qualification type for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEMUX1_GPIO128_S 0U +#define GPIO_GPEMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2U +#define GPIO_GPEMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4U +#define GPIO_GPEMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6U +#define GPIO_GPEMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8U +#define GPIO_GPEMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10U +#define GPIO_GPEMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12U +#define GPIO_GPEMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14U +#define GPIO_GPEMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16U +#define GPIO_GPEMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18U +#define GPIO_GPEMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20U +#define GPIO_GPEMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22U +#define GPIO_GPEMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24U +#define GPIO_GPEMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26U +#define GPIO_GPEMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28U +#define GPIO_GPEMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30U +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEMUX2_GPIO144_S 0U +#define GPIO_GPEMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2U +#define GPIO_GPEMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4U +#define GPIO_GPEMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6U +#define GPIO_GPEMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8U +#define GPIO_GPEMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10U +#define GPIO_GPEMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12U +#define GPIO_GPEMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14U +#define GPIO_GPEMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16U +#define GPIO_GPEMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18U +#define GPIO_GPEMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20U +#define GPIO_GPEMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22U +#define GPIO_GPEMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24U +#define GPIO_GPEMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26U +#define GPIO_GPEMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28U +#define GPIO_GPEMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30U +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDIR register +// +//************************************************************************************************* +#define GPIO_GPEDIR_GPIO128 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEPUD register +// +//************************************************************************************************* +#define GPIO_GPEPUD_GPIO128 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO129 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO130 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO131 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO132 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO133 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO134 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO135 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO136 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO137 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO138 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO139 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO140 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO141 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO142 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO143 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO144 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO145 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO146 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO147 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO148 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO149 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO150 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO151 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO152 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO153 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO154 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO155 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO156 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO157 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO158 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO159 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEINV register +// +//************************************************************************************************* +#define GPIO_GPEINV_GPIO128 0x1U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO129 0x2U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO130 0x4U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO131 0x8U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO132 0x10U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO133 0x20U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO134 0x40U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO135 0x80U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO136 0x100U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO137 0x200U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO138 0x400U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO139 0x800U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO140 0x1000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO141 0x2000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO142 0x4000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO143 0x8000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO144 0x10000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO145 0x20000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO146 0x40000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO147 0x80000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO148 0x100000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO149 0x200000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO150 0x400000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO151 0x800000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO152 0x1000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO153 0x2000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO154 0x4000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO155 0x8000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO156 0x10000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO157 0x20000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO158 0x40000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO159 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEODR register +// +//************************************************************************************************* +#define GPIO_GPEODR_GPIO128 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO129 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO130 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO131 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO132 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO133 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO134 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO135 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO136 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO137 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO138 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO139 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO140 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO141 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO142 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO143 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO144 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO145 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO146 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO147 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO148 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO149 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO150 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO151 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO152 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO153 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO154 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO155 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO156 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO157 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO158 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO159 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX1_GPIO128_S 0U +#define GPIO_GPEGMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2U +#define GPIO_GPEGMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4U +#define GPIO_GPEGMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6U +#define GPIO_GPEGMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8U +#define GPIO_GPEGMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10U +#define GPIO_GPEGMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12U +#define GPIO_GPEGMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14U +#define GPIO_GPEGMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16U +#define GPIO_GPEGMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18U +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20U +#define GPIO_GPEGMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22U +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24U +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26U +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28U +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30U +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX2_GPIO144_S 0U +#define GPIO_GPEGMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2U +#define GPIO_GPEGMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4U +#define GPIO_GPEGMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6U +#define GPIO_GPEGMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8U +#define GPIO_GPEGMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10U +#define GPIO_GPEGMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12U +#define GPIO_GPEGMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14U +#define GPIO_GPEGMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16U +#define GPIO_GPEGMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18U +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20U +#define GPIO_GPEGMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22U +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24U +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26U +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28U +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30U +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//************************************************************************************************* +#define GPIO_GPECSEL1_GPIO128_S 0U +#define GPIO_GPECSEL1_GPIO128_M 0xFU // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4U +#define GPIO_GPECSEL1_GPIO129_M 0xF0U // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8U +#define GPIO_GPECSEL1_GPIO130_M 0xF00U // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12U +#define GPIO_GPECSEL1_GPIO131_M 0xF000U // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16U +#define GPIO_GPECSEL1_GPIO132_M 0xF0000U // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20U +#define GPIO_GPECSEL1_GPIO133_M 0xF00000U // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24U +#define GPIO_GPECSEL1_GPIO134_M 0xF000000U // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28U +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000U // GPIO135 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//************************************************************************************************* +#define GPIO_GPECSEL2_GPIO136_S 0U +#define GPIO_GPECSEL2_GPIO136_M 0xFU // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4U +#define GPIO_GPECSEL2_GPIO137_M 0xF0U // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8U +#define GPIO_GPECSEL2_GPIO138_M 0xF00U // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12U +#define GPIO_GPECSEL2_GPIO139_M 0xF000U // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16U +#define GPIO_GPECSEL2_GPIO140_M 0xF0000U // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20U +#define GPIO_GPECSEL2_GPIO141_M 0xF00000U // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24U +#define GPIO_GPECSEL2_GPIO142_M 0xF000000U // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28U +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000U // GPIO143 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//************************************************************************************************* +#define GPIO_GPECSEL3_GPIO144_S 0U +#define GPIO_GPECSEL3_GPIO144_M 0xFU // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4U +#define GPIO_GPECSEL3_GPIO145_M 0xF0U // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8U +#define GPIO_GPECSEL3_GPIO146_M 0xF00U // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12U +#define GPIO_GPECSEL3_GPIO147_M 0xF000U // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16U +#define GPIO_GPECSEL3_GPIO148_M 0xF0000U // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20U +#define GPIO_GPECSEL3_GPIO149_M 0xF00000U // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24U +#define GPIO_GPECSEL3_GPIO150_M 0xF000000U // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28U +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000U // GPIO151 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//************************************************************************************************* +#define GPIO_GPECSEL4_GPIO152_S 0U +#define GPIO_GPECSEL4_GPIO152_M 0xFU // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4U +#define GPIO_GPECSEL4_GPIO153_M 0xF0U // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8U +#define GPIO_GPECSEL4_GPIO154_M 0xF00U // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12U +#define GPIO_GPECSEL4_GPIO155_M 0xF000U // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16U +#define GPIO_GPECSEL4_GPIO156_M 0xF0000U // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20U +#define GPIO_GPECSEL4_GPIO157_M 0xF00000U // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24U +#define GPIO_GPECSEL4_GPIO158_M 0xF000000U // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28U +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000U // GPIO159 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPELOCK register +// +//************************************************************************************************* +#define GPIO_GPELOCK_GPIO128 0x1U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO129 0x2U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO130 0x4U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO131 0x8U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO132 0x10U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO133 0x20U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO134 0x40U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO135 0x80U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO136 0x100U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO137 0x200U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO138 0x400U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO139 0x800U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO140 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO141 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO142 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO143 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO144 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO145 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO146 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO147 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO148 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO149 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO150 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO151 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO152 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO153 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO154 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO155 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO156 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO157 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO158 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO159 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECR register +// +//************************************************************************************************* +#define GPIO_GPECR_GPIO128 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO129 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO130 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO131 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO132 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO133 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO134 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO135 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO136 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO137 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO138 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO139 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO140 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO141 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO142 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO143 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO144 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO145 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO146 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO147 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO148 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO149 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO150 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO151 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO152 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO153 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO154 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO155 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO156 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO157 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO158 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO159 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCTRL register +// +//************************************************************************************************* +#define GPIO_GPFCTRL_QUALPRD0_S 0U +#define GPIO_GPFCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8U +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFQSEL1_GPIO160_S 0U +#define GPIO_GPFQSEL1_GPIO160_M 0x3U // Select input qualification type for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2U +#define GPIO_GPFQSEL1_GPIO161_M 0xCU // Select input qualification type for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4U +#define GPIO_GPFQSEL1_GPIO162_M 0x30U // Select input qualification type for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6U +#define GPIO_GPFQSEL1_GPIO163_M 0xC0U // Select input qualification type for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8U +#define GPIO_GPFQSEL1_GPIO164_M 0x300U // Select input qualification type for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10U +#define GPIO_GPFQSEL1_GPIO165_M 0xC00U // Select input qualification type for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12U +#define GPIO_GPFQSEL1_GPIO166_M 0x3000U // Select input qualification type for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14U +#define GPIO_GPFQSEL1_GPIO167_M 0xC000U // Select input qualification type for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16U +#define GPIO_GPFQSEL1_GPIO168_M 0x30000U // Select input qualification type for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFMUX1_GPIO160_S 0U +#define GPIO_GPFMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2U +#define GPIO_GPFMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4U +#define GPIO_GPFMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6U +#define GPIO_GPFMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8U +#define GPIO_GPFMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10U +#define GPIO_GPFMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12U +#define GPIO_GPFMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14U +#define GPIO_GPFMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16U +#define GPIO_GPFMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDIR register +// +//************************************************************************************************* +#define GPIO_GPFDIR_GPIO160 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFPUD register +// +//************************************************************************************************* +#define GPIO_GPFPUD_GPIO160 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO161 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO162 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO163 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO164 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO165 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO166 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO167 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO168 0x100U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFINV register +// +//************************************************************************************************* +#define GPIO_GPFINV_GPIO160 0x1U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO161 0x2U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO162 0x4U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO163 0x8U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO164 0x10U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO165 0x20U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO166 0x40U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO167 0x80U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO168 0x100U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFODR register +// +//************************************************************************************************* +#define GPIO_GPFODR_GPIO160 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO161 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO162 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO163 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO164 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO165 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO166 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO167 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO168 0x100U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFGMUX1_GPIO160_S 0U +#define GPIO_GPFGMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2U +#define GPIO_GPFGMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4U +#define GPIO_GPFGMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6U +#define GPIO_GPFGMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8U +#define GPIO_GPFGMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10U +#define GPIO_GPFGMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12U +#define GPIO_GPFGMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14U +#define GPIO_GPFGMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16U +#define GPIO_GPFGMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL1_GPIO160_S 0U +#define GPIO_GPFCSEL1_GPIO160_M 0xFU // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4U +#define GPIO_GPFCSEL1_GPIO161_M 0xF0U // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8U +#define GPIO_GPFCSEL1_GPIO162_M 0xF00U // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12U +#define GPIO_GPFCSEL1_GPIO163_M 0xF000U // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16U +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000U // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20U +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000U // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24U +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000U // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28U +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000U // GPIO167 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL2_GPIO168_S 0U +#define GPIO_GPFCSEL2_GPIO168_M 0xFU // GPIO168 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFLOCK register +// +//************************************************************************************************* +#define GPIO_GPFLOCK_GPIO160 0x1U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO161 0x2U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO162 0x4U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO163 0x8U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO164 0x10U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO165 0x20U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO166 0x40U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO167 0x80U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO168 0x100U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCR register +// +//************************************************************************************************* +#define GPIO_GPFCR_GPIO160 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO161 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO162 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO163 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO164 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO165 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO166 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO167 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO168 0x100U // Configuration lock commit bit for this pin + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADAT register +// +//************************************************************************************************* +#define GPIO_GPADAT_GPIO0 0x1U // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2U // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4U // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8U // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10U // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20U // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40U // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80U // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100U // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200U // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400U // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800U // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000U // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000U // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000U // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000U // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000U // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000U // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000U // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000U // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000U // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000U // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000U // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000U // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPASET register +// +//************************************************************************************************* +#define GPIO_GPASET_GPIO0 0x1U // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2U // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4U // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8U // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10U // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20U // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40U // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80U // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100U // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200U // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400U // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800U // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACLEAR register +// +//************************************************************************************************* +#define GPIO_GPACLEAR_GPIO0 0x1U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//************************************************************************************************* +#define GPIO_GPATOGGLE_GPIO0 0x1U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDAT register +// +//************************************************************************************************* +#define GPIO_GPBDAT_GPIO32 0x1U // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2U // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4U // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8U // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10U // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20U // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40U // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80U // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100U // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200U // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400U // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800U // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBSET register +// +//************************************************************************************************* +#define GPIO_GPBSET_GPIO32 0x1U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//************************************************************************************************* +#define GPIO_GPBCLEAR_GPIO32 0x1U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPBTOGGLE_GPIO32 0x1U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDAT register +// +//************************************************************************************************* +#define GPIO_GPCDAT_GPIO64 0x1U // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2U // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4U // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8U // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10U // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20U // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40U // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80U // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100U // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200U // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400U // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800U // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCSET register +// +//************************************************************************************************* +#define GPIO_GPCSET_GPIO64 0x1U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//************************************************************************************************* +#define GPIO_GPCCLEAR_GPIO64 0x1U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPCTOGGLE_GPIO64 0x1U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDAT register +// +//************************************************************************************************* +#define GPIO_GPDDAT_GPIO96 0x1U // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2U // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4U // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8U // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10U // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20U // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40U // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80U // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100U // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200U // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400U // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800U // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDSET register +// +//************************************************************************************************* +#define GPIO_GPDSET_GPIO96 0x1U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//************************************************************************************************* +#define GPIO_GPDCLEAR_GPIO96 0x1U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPDTOGGLE_GPIO96 0x1U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDAT register +// +//************************************************************************************************* +#define GPIO_GPEDAT_GPIO128 0x1U // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2U // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4U // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8U // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10U // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20U // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40U // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80U // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100U // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200U // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400U // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800U // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPESET register +// +//************************************************************************************************* +#define GPIO_GPESET_GPIO128 0x1U // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2U // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4U // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8U // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10U // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20U // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40U // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80U // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100U // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200U // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400U // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800U // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECLEAR register +// +//************************************************************************************************* +#define GPIO_GPECLEAR_GPIO128 0x1U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//************************************************************************************************* +#define GPIO_GPETOGGLE_GPIO128 0x1U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDAT register +// +//************************************************************************************************* +#define GPIO_GPFDAT_GPIO160 0x1U // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2U // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4U // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8U // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10U // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20U // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40U // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80U // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFSET register +// +//************************************************************************************************* +#define GPIO_GPFSET_GPIO160 0x1U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//************************************************************************************************* +#define GPIO_GPFCLEAR_GPIO160 0x1U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPFTOGGLE_GPIO160 0x1U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100U // Output Toggle bit for this pin + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_hic.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_hic.h new file mode 100644 index 0000000..07d544f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_hic.h @@ -0,0 +1,344 @@ +//########################################################################### +// +// FILE: hw_hic.h +// +// TITLE: Definitions for the HIC registers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HIC_H +#define HW_HIC_H + +//************************************************************************************************* +// +// The following are defines for the HIC register offsets +// +//************************************************************************************************* +#define HIC_O_REV 0x0U // Module Revision Register +#define HIC_O_GCR 0x2U // Global Control Register +#define HIC_O_LOCK 0x4U // Lock Register +#define HIC_O_MODECR 0x6U // Mode Control Register +#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register +#define HIC_O_BASESEL 0xAU // Base Select Register +#define HIC_O_HOSTCR 0xCU // Host Control Register +#define HIC_O_ERRADDR 0xEU // Host Error Address register +#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register +#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register +#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0 +#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1 +#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2 +#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3 +#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4 +#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5 +#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6 +#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7 +#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable +#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag +#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear +#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force +#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable +#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag +#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear +#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force +#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address +#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0 +#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1 +#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2 +#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3 +#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4 +#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5 +#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6 +#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7 +#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8 +#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9 +#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10 +#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11 +#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12 +#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13 +#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14 +#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15 +#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0 +#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1 +#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2 +#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3 +#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4 +#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5 +#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6 +#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7 +#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8 +#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9 +#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10 +#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11 +#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12 +#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13 +#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14 +#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICREV register +// +//************************************************************************************************* +#define HIC_REV_MINOR_S 0U +#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number +#define HIC_REV_CUSTOM_S 6U +#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number +#define HIC_REV_MAJOR_S 8U +#define HIC_REV_MAJOR_M 0x700U // Major Revision Number +#define HIC_REV_RTL_S 11U +#define HIC_REV_RTL_M 0xF800U // Design Release Number +#define HIC_REV_FUNC_S 16U +#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number +#define HIC_REV_SCHEME_S 30U +#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICGCR register +// +//************************************************************************************************* +#define HIC_GCR_HICEN_S 0U +#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICLOCK register +// +//************************************************************************************************* +#define HIC_LOCK_LOCK 0x1U // LOCK enable +#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U +#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICMODECR register +// +//************************************************************************************************* +#define HIC_MODECR_DW_MODE_S 0U +#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode +#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode +#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present +#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present +#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer +#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer +#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region +#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICPINPOLCR register +// +//************************************************************************************************* +#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity +#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity +#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity +#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity +#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICBASESEL register +// +//************************************************************************************************* +#define HIC_BASESEL_BASE_SELECT_S 0U +#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICHOSTCR register +// +//************************************************************************************************* +#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable +#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size +#define HIC_HOSTCR_PAGESEL 0x4U // Page Select +#define HIC_HOSTCR_HKEY_S 8U +#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICERRADDR register +// +//************************************************************************************************* +#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U +#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an + // error for Device +#define HIC_ERRADDR_H2D_BASE_SEL_S 12U +#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event +#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U +#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an + // error for Host +#define HIC_ERRADDR_D2H_BASE_SEL_S 28U +#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR0 register +// +//************************************************************************************************* +#define HIC_DBADDR0_BASE_ADDR_S 7U +#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR1 register +// +//************************************************************************************************* +#define HIC_DBADDR1_BASE_ADDR_S 7U +#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR2 register +// +//************************************************************************************************* +#define HIC_DBADDR2_BASE_ADDR_S 7U +#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR3 register +// +//************************************************************************************************* +#define HIC_DBADDR3_BASE_ADDR_S 7U +#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR4 register +// +//************************************************************************************************* +#define HIC_DBADDR4_BASE_ADDR_S 7U +#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR5 register +// +//************************************************************************************************* +#define HIC_DBADDR5_BASE_ADDR_S 7U +#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR6 register +// +//************************************************************************************************* +#define HIC_DBADDR6_BASE_ADDR_S 7U +#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR7 register +// +//************************************************************************************************* +#define HIC_DBADDR7_BASE_ADDR_S 7U +#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTEN register +// +//************************************************************************************************* +#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable +#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable +#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFLG register +// +//************************************************************************************************* +#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag +#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag +#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag +#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTCLR register +// +//************************************************************************************************* +#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear +#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFRC register +// +//************************************************************************************************* +#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set +#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTEN register +// +//************************************************************************************************* +#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable +#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable +#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable +#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable +#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U +#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFLG register +// +//************************************************************************************************* +#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag +#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag +#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag +#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag +#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag +#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U +#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTCLR register +// +//************************************************************************************************* +#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear +#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear +#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U +#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFRC register +// +//************************************************************************************************* +#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set +#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set +#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U +#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_hrpwm.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_hrpwm.h new file mode 100644 index 0000000..a6c899f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_hrpwm.h @@ -0,0 +1,1058 @@ +//########################################################################### +// +// FILE: hw_hrpwm.h +// +// TITLE: Definitions for the HRPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HRPWM_H +#define HW_HRPWM_H + +//************************************************************************************************* +// +// The following are defines for the HRPWM register offsets +// +//************************************************************************************************* +#define HRPWM_O_TBCTL 0x0U // Time Base Control Register +#define HRPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define HRPWM_O_TBCTR 0x4U // Time Base Counter Register +#define HRPWM_O_TBSTS 0x5U // Time Base Status Register +#define HRPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define HRPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define HRPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define HRPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define HRPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define HRPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define HRPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define HRPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define HRPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define HRPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define HRPWM_O_HRPWR 0x21U // HRPWM Power Register +#define HRPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define HRPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define HRPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define HRPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define HRPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define HRPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define HRPWM_O_EPWMXLINK 0x38U // EPWMx Link Register +#define HRPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define HRPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define HRPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define HRPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define HRPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define HRPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define HRPWM_O_TBPHS 0x60U // Time Base Phase High +#define HRPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define HRPWM_O_TBPRD 0x63U // Time Base Period Register +#define HRPWM_O_CMPA 0x6AU // Counter Compare A Register +#define HRPWM_O_CMPB 0x6CU // Compare B Register +#define HRPWM_O_CMPC 0x6FU // Counter Compare C Register +#define HRPWM_O_CMPD 0x71U // Counter Compare D Register +#define HRPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define HRPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define HRPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define HRPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define HRPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define HRPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define HRPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define HRPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define HRPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define HRPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define HRPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define HRPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define HRPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define HRPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define HRPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define HRPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define HRPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define HRPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define HRPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define HRPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define HRPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define HRPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define HRPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define HRPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define HRPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define HRPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define HRPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define HRPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define HRPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define HRPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define HRPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define HRPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define HRPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define HRPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define HRPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define HRPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define HRPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define HRPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define HRPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define HRPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define HRPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define HRPWM_TBCTL_CTRMODE_S 0U +#define HRPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define HRPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define HRPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define HRPWM_TBCTL_SYNCOSEL_S 4U +#define HRPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define HRPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define HRPWM_TBCTL_HSPCLKDIV_S 7U +#define HRPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define HRPWM_TBCTL_CLKDIV_S 10U +#define HRPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define HRPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define HRPWM_TBCTL_FREE_SOFT_S 14U +#define HRPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define HRPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define HRPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define HRPWM_TBCTL2_SYNCOSELX_S 12U +#define HRPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define HRPWM_TBCTL2_PRDLDSYNC_S 14U +#define HRPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define HRPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define HRPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define HRPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define HRPWM_CMPCTL_LOADAMODE_S 0U +#define HRPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define HRPWM_CMPCTL_LOADBMODE_S 2U +#define HRPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define HRPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define HRPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define HRPWM_CMPCTL_LOADASYNC_S 10U +#define HRPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define HRPWM_CMPCTL_LOADBSYNC_S 12U +#define HRPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define HRPWM_CMPCTL2_LOADCMODE_S 0U +#define HRPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define HRPWM_CMPCTL2_LOADDMODE_S 2U +#define HRPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define HRPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define HRPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define HRPWM_CMPCTL2_LOADCSYNC_S 10U +#define HRPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define HRPWM_CMPCTL2_LOADDSYNC_S 12U +#define HRPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define HRPWM_DBCTL_OUT_MODE_S 0U +#define HRPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define HRPWM_DBCTL_POLSEL_S 2U +#define HRPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define HRPWM_DBCTL_IN_MODE_S 4U +#define HRPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define HRPWM_DBCTL_LOADREDMODE_S 6U +#define HRPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define HRPWM_DBCTL_LOADFEDMODE_S 8U +#define HRPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define HRPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define HRPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define HRPWM_DBCTL_OUTSWAP_S 12U +#define HRPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define HRPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define HRPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define HRPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define HRPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define HRPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define HRPWM_AQCTL_LDAQAMODE_S 0U +#define HRPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define HRPWM_AQCTL_LDAQBMODE_S 2U +#define HRPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define HRPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define HRPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define HRPWM_AQCTL_LDAQASYNC_S 8U +#define HRPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define HRPWM_AQCTL_LDAQBSYNC_S 10U +#define HRPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define HRPWM_AQTSRCSEL_T1SEL_S 0U +#define HRPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define HRPWM_AQTSRCSEL_T2SEL_S 4U +#define HRPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define HRPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define HRPWM_PCCTL_OSHTWTH_S 1U +#define HRPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define HRPWM_PCCTL_CHPFREQ_S 5U +#define HRPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define HRPWM_PCCTL_CHPDUTY_S 8U +#define HRPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define HRPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define HRPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define HRPWM_VCAPCTL_TRIGSEL_S 2U +#define HRPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define HRPWM_VCAPCTL_VDELAYDIV_S 7U +#define HRPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define HRPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define HRPWM_VCNTCFG_STARTEDGE_S 0U +#define HRPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define HRPWM_VCNTCFG_STOPEDGE_S 8U +#define HRPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define HRPWM_HRCNFG_EDGMODE_S 0U +#define HRPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOAD_S 3U +#define HRPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define HRPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define HRPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define HRPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define HRPWM_HRCNFG_EDGMODEB_S 8U +#define HRPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOADB_S 11U +#define HRPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define HRPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define HRPWM_HRMSTEP_HRMSTEP_S 0U +#define HRPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define HRPWM_HRCNFG2_EDGMODEDB_S 0U +#define HRPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define HRPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define HRPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define HRPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define HRPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define HRPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define HRPWM_HRPCTL_PWMSYNCSELX_S 4U +#define HRPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define HRPWM_TRREM_TRREM_S 0U +#define HRPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define HRPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define HRPWM_GLDCTL_GLDMODE_S 1U +#define HRPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define HRPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define HRPWM_GLDCTL_GLDPRD_S 7U +#define HRPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define HRPWM_GLDCTL_GLDCNT_S 10U +#define HRPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define HRPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define HRPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define HRPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define HRPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define HRPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define HRPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define HRPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define HRPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define HRPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define HRPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define HRPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define HRPWM_EPWMXLINK_TBPRDLINK_S 0U +#define HRPWM_EPWMXLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define HRPWM_EPWMXLINK_CMPALINK_S 4U +#define HRPWM_EPWMXLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define HRPWM_EPWMXLINK_CMPBLINK_S 8U +#define HRPWM_EPWMXLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define HRPWM_EPWMXLINK_CMPCLINK_S 12U +#define HRPWM_EPWMXLINK_CMPCLINK_M 0xF000U // CMPC Link +#define HRPWM_EPWMXLINK_CMPDLINK_S 16U +#define HRPWM_EPWMXLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define HRPWM_EPWMXLINK_GLDCTL2LINK_S 28U +#define HRPWM_EPWMXLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define HRPWM_AQCTLA_ZRO_S 0U +#define HRPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLA_PRD_S 2U +#define HRPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLA_CAU_S 4U +#define HRPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLA_CAD_S 6U +#define HRPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLA_CBU_S 8U +#define HRPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLA_CBD_S 10U +#define HRPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLA2_T1U_S 0U +#define HRPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLA2_T1D_S 2U +#define HRPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLA2_T2U_S 4U +#define HRPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLA2_T2D_S 6U +#define HRPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define HRPWM_AQCTLB_ZRO_S 0U +#define HRPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLB_PRD_S 2U +#define HRPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLB_CAU_S 4U +#define HRPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLB_CAD_S 6U +#define HRPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLB_CBU_S 8U +#define HRPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLB_CBD_S 10U +#define HRPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLB2_T1U_S 0U +#define HRPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLB2_T1D_S 2U +#define HRPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLB2_T2U_S 4U +#define HRPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLB2_T2D_S 6U +#define HRPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define HRPWM_AQSFRC_ACTSFA_S 0U +#define HRPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define HRPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define HRPWM_AQSFRC_ACTSFB_S 3U +#define HRPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define HRPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define HRPWM_AQSFRC_RLDCSF_S 6U +#define HRPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define HRPWM_AQCSFRC_CSFA_S 0U +#define HRPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define HRPWM_AQCSFRC_CSFB_S 2U +#define HRPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define HRPWM_DBREDHR_DBREDHR_S 9U +#define HRPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define HRPWM_DBRED_DBRED_S 0U +#define HRPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define HRPWM_DBFEDHR_DBFEDHR_S 9U +#define HRPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define HRPWM_DBFED_DBFED_S 0U +#define HRPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define HRPWM_TBPHS_TBPHSHR_S 0U +#define HRPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define HRPWM_TBPHS_TBPHS_S 16U +#define HRPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define HRPWM_CMPA_CMPAHR_S 0U +#define HRPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define HRPWM_CMPA_CMPA_S 16U +#define HRPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define HRPWM_CMPB_CMPBHR_S 0U +#define HRPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define HRPWM_CMPB_CMPB_S 16U +#define HRPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define HRPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define HRPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define HRPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define HRPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define HRPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define HRPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define HRPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define HRPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define HRPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define HRPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define HRPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define HRPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define HRPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define HRPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define HRPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define HRPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define HRPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define HRPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define HRPWM_TZDCSEL_DCAEVT1_S 0U +#define HRPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define HRPWM_TZDCSEL_DCAEVT2_S 3U +#define HRPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define HRPWM_TZDCSEL_DCBEVT1_S 6U +#define HRPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define HRPWM_TZDCSEL_DCBEVT2_S 9U +#define HRPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define HRPWM_TZCTL_TZA_S 0U +#define HRPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define HRPWM_TZCTL_TZB_S 2U +#define HRPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define HRPWM_TZCTL_DCAEVT1_S 4U +#define HRPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define HRPWM_TZCTL_DCAEVT2_S 6U +#define HRPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define HRPWM_TZCTL_DCBEVT1_S 8U +#define HRPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define HRPWM_TZCTL_DCBEVT2_S 10U +#define HRPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define HRPWM_TZCTL2_TZAU_S 0U +#define HRPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define HRPWM_TZCTL2_TZAD_S 3U +#define HRPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define HRPWM_TZCTL2_TZBU_S 6U +#define HRPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define HRPWM_TZCTL2_TZBD_S 9U +#define HRPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define HRPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCA_DCAEVT1U_S 0U +#define HRPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT1D_S 3U +#define HRPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCA_DCAEVT2U_S 6U +#define HRPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT2D_S 9U +#define HRPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCB_DCBEVT1U_S 0U +#define HRPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT1D_S 3U +#define HRPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCB_DCBEVT2U_S 6U +#define HRPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT2D_S 9U +#define HRPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define HRPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define HRPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define HRPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define HRPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define HRPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define HRPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define HRPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define HRPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define HRPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define HRPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define HRPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define HRPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define HRPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define HRPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define HRPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define HRPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define HRPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define HRPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define HRPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define HRPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event + // 2 +#define HRPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event + // 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define HRPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define HRPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define HRPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define HRPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define HRPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define HRPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define HRPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event + // 1 +#define HRPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event + // 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define HRPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define HRPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define HRPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define HRPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define HRPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define HRPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define HRPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define HRPWM_TZCLR_CBCPULSE_S 14U +#define HRPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define HRPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define HRPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define HRPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define HRPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define HRPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define HRPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define HRPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define HRPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define HRPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define HRPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define HRPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define HRPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define HRPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define HRPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define HRPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define HRPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define HRPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define HRPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define HRPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define HRPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define HRPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define HRPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define HRPWM_ETSEL_INTSEL_S 0U +#define HRPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define HRPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define HRPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define HRPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define HRPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define HRPWM_ETSEL_SOCASEL_S 8U +#define HRPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define HRPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define HRPWM_ETSEL_SOCBSEL_S 12U +#define HRPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define HRPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define HRPWM_ETPS_INTPRD_S 0U +#define HRPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define HRPWM_ETPS_INTCNT_S 2U +#define HRPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define HRPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCAPRD_S 8U +#define HRPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define HRPWM_ETPS_SOCACNT_S 10U +#define HRPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define HRPWM_ETPS_SOCBPRD_S 12U +#define HRPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define HRPWM_ETPS_SOCBCNT_S 14U +#define HRPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define HRPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define HRPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define HRPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define HRPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define HRPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define HRPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define HRPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define HRPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define HRPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define HRPWM_ETINTPS_INTPRD2_S 0U +#define HRPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define HRPWM_ETINTPS_INTCNT2_S 4U +#define HRPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define HRPWM_ETSOCPS_SOCAPRD2_S 0U +#define HRPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define HRPWM_ETSOCPS_SOCACNT2_S 4U +#define HRPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define HRPWM_ETSOCPS_SOCBPRD2_S 8U +#define HRPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define HRPWM_ETSOCPS_SOCBCNT2_S 12U +#define HRPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define HRPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define HRPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define HRPWM_ETCNTINIT_INTINIT_S 0U +#define HRPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCAINIT_S 4U +#define HRPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCBINIT_S 8U +#define HRPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define HRPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define HRPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define HRPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define HRPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define HRPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define HRPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define HRPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define HRPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define HRPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define HRPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define HRPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define HRPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define HRPWM_DCFCTL_SRCSEL_S 0U +#define HRPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define HRPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define HRPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define HRPWM_DCFCTL_PULSESEL_S 4U +#define HRPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define HRPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define HRPWM_DCFCTL_EDGEMODE_S 8U +#define HRPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define HRPWM_DCFCTL_EDGECOUNT_S 10U +#define HRPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define HRPWM_DCFCTL_EDGESTATUS_S 13U +#define HRPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define HRPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define HRPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define HRPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define HRPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define HRPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_i2c.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_i2c.h new file mode 100644 index 0000000..e37ef50 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_i2c.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the I2C registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_I2C_H +#define HW_I2C_H + +//************************************************************************************************* +// +// The following are defines for the I2C register offsets +// +//************************************************************************************************* +#define I2C_O_OAR 0x0U // I2C Own address +#define I2C_O_IER 0x1U // I2C Interrupt Enable +#define I2C_O_STR 0x2U // I2C Status +#define I2C_O_CLKL 0x3U // I2C Clock low-time divider +#define I2C_O_CLKH 0x4U // I2C Clock high-time divider +#define I2C_O_CNT 0x5U // I2C Data count +#define I2C_O_DRR 0x6U // I2C Data receive +#define I2C_O_SAR 0x7U // I2C Slave address +#define I2C_O_DXR 0x8U // I2C Data Transmit +#define I2C_O_MDR 0x9U // I2C Mode +#define I2C_O_ISRC 0xAU // I2C Interrupt Source +#define I2C_O_EMDR 0xBU // I2C Extended Mode +#define I2C_O_PSC 0xCU // I2C Prescaler +#define I2C_O_FFTX 0x20U // I2C FIFO Transmit +#define I2C_O_FFRX 0x21U // I2C FIFO Receive + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2COAR register +// +//************************************************************************************************* +#define I2C_OAR_OAR_S 0U +#define I2C_OAR_OAR_M 0x3FFU // I2C Own address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CIER register +// +//************************************************************************************************* +#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable +#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable +#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable +#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable +#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable +#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable +#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSTR register +// +//************************************************************************************************* +#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit +#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit. +#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit +#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit. +#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit. +#define I2C_STR_SCD 0x20U // Stop condition detected bit. +#define I2C_STR_AD0 0x100U // Address 0 bits +#define I2C_STR_AAS 0x200U // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit. +#define I2C_STR_RSFULL 0x800U // Receive shift register full bit. +#define I2C_STR_BB 0x1000U // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000U // NACK sent bit. +#define I2C_STR_SDIR 0x4000U // Slave direction bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDRR register +// +//************************************************************************************************* +#define I2C_DRR_DATA_S 0U +#define I2C_DRR_DATA_M 0xFFU // Receive data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSAR register +// +//************************************************************************************************* +#define I2C_SAR_SAR_S 0U +#define I2C_SAR_SAR_M 0x3FFU // Slave Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDXR register +// +//************************************************************************************************* +#define I2C_DXR_DATA_S 0U +#define I2C_DXR_DATA_M 0xFFU // Transmit data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CMDR register +// +//************************************************************************************************* +#define I2C_MDR_BC_S 0U +#define I2C_MDR_BC_M 0x7U // Bit count bits. +#define I2C_MDR_FDF 0x8U // Free Data Format +#define I2C_MDR_STB 0x10U // START Byte Mode +#define I2C_MDR_IRS 0x20U // I2C Module Reset +#define I2C_MDR_DLB 0x40U // Digital Loopback Mode +#define I2C_MDR_RM 0x80U // Repeat Mode +#define I2C_MDR_XA 0x100U // Expanded Address Mode +#define I2C_MDR_TRX 0x200U // Transmitter Mode +#define I2C_MDR_MST 0x400U // Master Mode +#define I2C_MDR_STP 0x800U // STOP Condition +#define I2C_MDR_STT 0x2000U // START condition bit +#define I2C_MDR_FREE 0x4000U // Debug Action +#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CISRC register +// +//************************************************************************************************* +#define I2C_ISRC_INTCODE_S 0U +#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits. +#define I2C_ISRC_WRITE_ZEROS_S 8U +#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CEMDR register +// +//************************************************************************************************* +#define I2C_EMDR_BC 0x1U // Backwards compatibility mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CPSC register +// +//************************************************************************************************* +#define I2C_PSC_IPSC_S 0U +#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFTX register +// +//************************************************************************************************* +#define I2C_FFTX_TXFFIL_S 0U +#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear +#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8U +#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFRX register +// +//************************************************************************************************* +#define I2C_FFRX_RXFFIL_S 0U +#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear +#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8U +#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_inputxbar.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_inputxbar.h new file mode 100644 index 0000000..a2567f2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_inputxbar.h @@ -0,0 +1,92 @@ +//########################################################################### +// +// FILE: hw_inputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_INPUTXBAR_H +#define HW_INPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INPUTSELECTLOCK register +// +//************************************************************************************************* +#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_ints.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ints.h new file mode 100644 index 0000000..d49c58d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ints.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// +// +//########################################################################### + +#ifndef HW_INTS_H +#define HW_INTS_H + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1 +#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1 +#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1 +#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt +#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt +#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1 +#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt +#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt +#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt +#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt +#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt +#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt +#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt +#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt +#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt + +// Lower PIE Group 3 +#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt +#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt +#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt +#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt +#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt +#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt +#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt +#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt + +// Lower PIE Group 4 +#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt +#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt +#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt +#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt +#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt +#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt +// Lower PIE Group 5 +#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt +#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt +#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt +#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt +#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt +#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt +#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + +// Lower PIE Group 6 +#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt +#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt +#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt +#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt +#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt +#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt +#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt +#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt +#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt +#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt +#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt +#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt +#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1 +#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2 +#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1 +#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2 +#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt +#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt +#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt +#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt +#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt +#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt +#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt +#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0 +#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1 +#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0 +#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1 + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt +#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2 +#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3 +#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4 +#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt +#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2 +#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3 +#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1 +#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2 +#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3 +#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4 +#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5 +#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6 +#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7 +#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt +#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt +#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt +#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt +#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt +#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt +#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt +#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt + +// Upper PIE Group 1 +#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1 +#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2 +#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3 +#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt +#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt +#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt +#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt + +// Upper PIE Group 3 +#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt +#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt +#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt +#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt + +// Upper PIE Group 5 +#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt +#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt + +// Upper PIE Group 6 +#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt +#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt + +// Upper PIE Group 9 +#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt +#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2 +#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3 +#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4 +#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt +#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2 +#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3 +#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt +#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt +#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt +#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt + +// Other interrupts +#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt +#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt +#define INT_DATALOG 0x000F0000U // Datalogging Interrupt +#define INT_RTOS 0x00100000U // RTOS Interrupt +#define INT_EMU 0x00110000U // Emulation Interrupt +#define INT_NMI 0x00120000U // Non-Maskable Interrupt +#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap +#define INT_USER1 0x00140000U // User Defined Trap 1 +#define INT_USER2 0x00150000U // User Defined Trap 2 +#define INT_USER3 0x00160000U // User Defined Trap 3 +#define INT_USER4 0x00170000U // User Defined Trap 4 +#define INT_USER5 0x00180000U // User Defined Trap 5 +#define INT_USER6 0x00190000U // User Defined Trap 6 +#define INT_USER7 0x001A0000U // User Defined Trap 7 +#define INT_USER8 0x001B0000U // User Defined Trap 8 +#define INT_USER9 0x001C0000U // User Defined Trap 9 +#define INT_USER10 0x001D0000U // User Defined Trap 10 +#define INT_USER11 0x001E0000U // User Defined Trap 11 +#define INT_USER12 0x001F0000U // User Defined Trap 12 + +#endif // HW_INTS_H diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_ipc.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ipc.h new file mode 100644 index 0000000..e99715f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_ipc.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: hw_ipc.h +// +// TITLE: Definitions for the IPC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_IPC_H +#define HW_IPC_H + +//***************************************************************************** +// +// The following are defines for the IPC register offsets +// +//***************************************************************************** +#define IPC_O_ACK 0x0U // IPC incoming flag clear + // (acknowledge) register +#define IPC_O_STS 0x2U // IPC incoming flag status + // register +#define IPC_O_SET 0x4U // IPC remote flag set register +#define IPC_O_CLR 0x6U // IPC remote flag clear + // register +#define IPC_O_FLG 0x8U // IPC remote flag status + // register +#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register +#define IPC_O_COUNTERH 0xEU // IPC Counter High Register +#ifndef CPU2 +#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply + // Data Register +#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply + // Data Register +#else +#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply + // Data Register +#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply + // Data Register +#endif +#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status + // Register +#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCACK register +// +//***************************************************************************** +#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0 + // Acknowledgement +#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1 + // Acknowledgement +#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2 + // Acknowledgement +#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3 + // Acknowledgement +#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4 + // Acknowledgement +#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5 + // Acknowledgement +#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6 + // Acknowledgement +#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7 + // Acknowledgement +#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8 + // Acknowledgement +#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9 + // Acknowledgement +#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10 + // Acknowledgement +#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11 + // Acknowledgement +#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12 + // Acknowledgement +#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13 + // Acknowledgement +#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14 + // Acknowledgement +#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15 + // Acknowledgement +#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16 + // Acknowledgement +#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17 + // Acknowledgement +#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18 + // Acknowledgement +#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19 + // Acknowledgement +#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20 + // Acknowledgement +#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21 + // Acknowledgement +#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22 + // Acknowledgement +#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23 + // Acknowledgement +#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24 + // Acknowledgement +#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25 + // Acknowledgement +#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26 + // Acknowledgement +#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27 + // Acknowledgement +#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28 + // Acknowledgement +#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29 + // Acknowledgement +#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30 + // Acknowledgement +#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31 + // Acknowledgement + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSTS register +// +//***************************************************************************** +#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status +#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status +#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status +#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status +#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status +#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status +#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status +#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status +#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status +#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status +#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status +#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status +#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status +#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status +#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status +#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status +#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status +#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status +#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status +#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status +#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status +#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status +#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status +#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status +#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status +#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status +#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status +#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status +#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status +#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status +#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status +#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSET register +// +//***************************************************************************** +#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag +#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag +#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag +#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag +#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag +#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag +#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag +#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag +#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag +#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag +#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag +#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag +#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag +#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag +#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag +#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag +#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag +#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag +#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag +#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag +#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag +#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag +#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag +#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag +#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag +#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag +#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag +#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag +#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag +#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag +#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag +#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCCLR register +// +//***************************************************************************** +#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag +#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag +#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag +#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag +#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag +#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag +#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag +#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag +#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag +#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag +#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag +#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag +#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag +#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag +#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag +#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag +#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag +#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag +#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag +#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag +#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag +#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag +#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag +#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag +#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag +#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag +#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag +#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag +#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag +#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag +#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag +#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCFLG register +// +//***************************************************************************** +#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status +#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status +#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status +#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status +#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status +#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status +#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status +#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status +#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status +#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status +#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status +#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status +#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status +#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status +#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status +#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status +#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status +#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status +#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status +#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status +#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status +#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status +#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status +#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status +#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status +#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status +#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status +#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status +#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status +#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status +#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status +#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_mcbsp.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_mcbsp.h new file mode 100644 index 0000000..814055f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_mcbsp.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_mcbsp.h +// +// TITLE: Definitions for the MCBSP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MCBSP_H +#define HW_MCBSP_H + +//************************************************************************************************* +// +// The following are defines for the MCBSP register offsets +// +//************************************************************************************************* +#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16 +#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0 +#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16 +#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0 +#define MCBSP_O_SPCR2 0x4U // Serial port control register 2 +#define MCBSP_O_SPCR1 0x5U // Serial port control register 1 +#define MCBSP_O_RCR2 0x6U // Receive Control register 2 +#define MCBSP_O_RCR1 0x7U // Receive Control register 1 +#define MCBSP_O_XCR2 0x8U // Transmit Control register 2 +#define MCBSP_O_XCR1 0x9U // Transmit Control register 1 +#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2 +#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1 +#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2 +#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1 +#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A +#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B +#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A +#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B +#define MCBSP_O_PCR 0x12U // Pin Control register +#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C +#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D +#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C +#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D +#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E +#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F +#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E +#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F +#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G +#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H +#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G +#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H +#define MCBSP_O_MFFINT 0x23U // Interrupt enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR2 register +// +//************************************************************************************************* +#define MCBSP_DRR2_HWLB_S 0U +#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DRR2_HWHB_S 8U +#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR1 register +// +//************************************************************************************************* +#define MCBSP_DRR1_LWLB_S 0U +#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DRR1_LWHB_S 8U +#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR2 register +// +//************************************************************************************************* +#define MCBSP_DXR2_HWLB_S 0U +#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DXR2_HWHB_S 8U +#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR1 register +// +//************************************************************************************************* +#define MCBSP_DXR1_LWLB_S 0U +#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DXR1_LWHB_S 8U +#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR2 register +// +//************************************************************************************************* +#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset +#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready +#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty +#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag +#define MCBSP_SPCR2_XINTM_S 4U +#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits +#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset +#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset +#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit +#define MCBSP_SPCR2_FREE 0x200U // FREE bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR1 register +// +//************************************************************************************************* +#define MCBSP_SPCR1_RRST 0x1U // Receiver reset +#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready +#define MCBSP_SPCR1_RFULL 0x4U // Receiver full +#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag +#define MCBSP_SPCR1_RINTM_S 4U +#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits +#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable +#define MCBSP_SPCR1_CLKSTP_S 11U +#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode +#define MCBSP_SPCR1_RJUST_S 13U +#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode +#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR2 register +// +//************************************************************************************************* +#define MCBSP_RCR2_RDATDLY_S 0U +#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay +#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore +#define MCBSP_RCR2_RCOMPAND_S 3U +#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects +#define MCBSP_RCR2_RWDLEN2_S 5U +#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2 +#define MCBSP_RCR2_RFRLEN2_S 8U +#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2 +#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR1 register +// +//************************************************************************************************* +#define MCBSP_RCR1_RWDLEN1_S 5U +#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1 +#define MCBSP_RCR1_RFRLEN1_S 8U +#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR2 register +// +//************************************************************************************************* +#define MCBSP_XCR2_XDATDLY_S 0U +#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay +#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore +#define MCBSP_XCR2_XCOMPAND_S 3U +#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects +#define MCBSP_XCR2_XWDLEN2_S 5U +#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2 +#define MCBSP_XCR2_XFRLEN2_S 8U +#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2 +#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR1 register +// +//************************************************************************************************* +#define MCBSP_XCR1_XWDLEN1_S 5U +#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1 +#define MCBSP_XCR1_XFRLEN1_S 8U +#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR2 register +// +//************************************************************************************************* +#define MCBSP_SRGR2_FPER_S 0U +#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period +#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode +#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode +#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR1 register +// +//************************************************************************************************* +#define MCBSP_SRGR1_CLKGDV_S 0U +#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider +#define MCBSP_SRGR1_FWID_S 8U +#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR2 register +// +//************************************************************************************************* +#define MCBSP_MCR2_XMCM_S 0U +#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay +#define MCBSP_MCR2_XCBLK_S 2U +#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore +#define MCBSP_MCR2_XPABLK_S 5U +#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects +#define MCBSP_MCR2_XPBBLK_S 7U +#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2 +#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR1 register +// +//************************************************************************************************* +#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode +#define MCBSP_MCR1_RCBLK_S 2U +#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block +#define MCBSP_MCR1_RPABLK_S 5U +#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block +#define MCBSP_MCR1_RPBBLK_S 7U +#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block +#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCR register +// +//************************************************************************************************* +#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity +#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity +#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity +#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity +#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection +#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode +#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode. +#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode +#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MFFINT register +// +//************************************************************************************************* +#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt +#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_memcfg.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_memcfg.h new file mode 100644 index 0000000..d5d7e8c --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_memcfg.h @@ -0,0 +1,870 @@ +//########################################################################### +// +// FILE: hw_memcfg.h +// +// TITLE: Definitions for the MEMCFG registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMCFG_H +#define HW_MEMCFG_H + +//************************************************************************************************* +// +// The following are defines for the MEMCFG register offsets +// +//************************************************************************************************* +#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register +#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register +#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register +#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register +#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register +#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register +#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register +#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register +#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register +#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register +#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0 +#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1 +#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register +#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register +#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register +#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register +#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register +#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register +#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0 +#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1 +#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2 +#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3 +#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register +#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register +#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register +#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register +#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register +#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register + +#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register +#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register +#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register +#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0 + +#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register +#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register +#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0 + +#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register +#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register +#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register +#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register +#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address +#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address +#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address +#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address +#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address +#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address +#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address +#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register +#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register +#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register +#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register +#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address +#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address +#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address + +#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register +#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register +#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register +#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address +#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address +#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address +#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register +#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register +#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register +#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address +#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register +#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register +#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register +#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register +#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register +#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register + +#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register + +#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxLOCK register +// +//************************************************************************************************* +#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock + // bit +#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock + // bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent + // lock +#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM +#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxTEST register +// +//************************************************************************************************* +#define MEMCFG_DXTEST_TEST_M0_S 0U +#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM +#define MEMCFG_DXTEST_TEST_M1_S 2U +#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM +#define MEMCFG_DXTEST_TEST_D0_S 4U +#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM +#define MEMCFG_DXTEST_TEST_D1_S 6U +#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINIT register +// +//************************************************************************************************* +#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM. +#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM. +#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM. +#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U +#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM +#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U +#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM +#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U +#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM +#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U +#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM +#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U +#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM +#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U +#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCLAPGM register +// +//************************************************************************************************* +#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxTEST register +// +//************************************************************************************************* +#define MEMCFG_LSXTEST_TEST_LS0_S 0U +#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM +#define MEMCFG_LSXTEST_TEST_LS1_S 2U +#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM +#define MEMCFG_LSXTEST_TEST_LS2_S 4U +#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM +#define MEMCFG_LSXTEST_TEST_LS3_S 6U +#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM +#define MEMCFG_LSXTEST_TEST_LS4_S 8U +#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM +#define MEMCFG_LSXTEST_TEST_LS5_S 10U +#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINIT register +// +//************************************************************************************************* +#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM. +#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM. +#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM. +#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM. +#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM. +#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM +#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM +#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM +#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM +#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM +#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM +#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM +#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM +#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM +#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM +#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM +#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM +#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM +#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM +#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM +#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT2 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT3 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxTEST register +// +//************************************************************************************************* +#define MEMCFG_GSXTEST_TEST_GS0_S 0U +#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM +#define MEMCFG_GSXTEST_TEST_GS1_S 2U +#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM +#define MEMCFG_GSXTEST_TEST_GS2_S 4U +#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM +#define MEMCFG_GSXTEST_TEST_GS3_S 6U +#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM +#define MEMCFG_GSXTEST_TEST_GS4_S 8U +#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM +#define MEMCFG_GSXTEST_TEST_GS5_S 10U +#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM +#define MEMCFG_GSXTEST_TEST_GS6_S 12U +#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM +#define MEMCFG_GSXTEST_TEST_GS7_S 14U +#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM +#define MEMCFG_GSXTEST_TEST_GS8_S 16U +#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM +#define MEMCFG_GSXTEST_TEST_GS9_S 18U +#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM +#define MEMCFG_GSXTEST_TEST_GS10_S 20U +#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM +#define MEMCFG_GSXTEST_TEST_GS11_S 22U +#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM +#define MEMCFG_GSXTEST_TEST_GS12_S 24U +#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM +#define MEMCFG_GSXTEST_TEST_GS13_S 26U +#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM +#define MEMCFG_GSXTEST_TEST_GS14_S 28U +#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM +#define MEMCFG_GSXTEST_TEST_GS15_S 30U +#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINIT register +// +//************************************************************************************************* +#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM. +#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM. +#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM. +#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM. +#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM. +#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM. +#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM. +#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM. +#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM. +#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM. +#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM. +#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM. +#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM. +#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM. +#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM. +#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxTEST register +// +//************************************************************************************************* +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINIT register +// +//************************************************************************************************* +#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM +#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM +#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG + // RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1 + // MSG RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU + // MSG RAM + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1MSEL register +// +//************************************************************************************************* +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1. +#define MEMCFG_EMIF1MSEL_KEY_S 4U +#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1 + // bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2 +#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVFLG register +// +//************************************************************************************************* +#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag +#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag +#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag +#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVSET register +// +//************************************************************************************************* +#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set +#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVCLR register +// +//************************************************************************************************* +#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVFLG register +// +//************************************************************************************************* +#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag +#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag +#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVSET register +// +//************************************************************************************************* +#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set +#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set +#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVCLR register +// +//************************************************************************************************* +#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear +#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRFLG register +// +//************************************************************************************************* +#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRSET register +// +//************************************************************************************************* +#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRCLR register +// +//************************************************************************************************* +#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRFLG register +// +//************************************************************************************************* +#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag +#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag +#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRSET register +// +//************************************************************************************************* +#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set +#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set +#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRCLR register +// +//************************************************************************************************* +#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTFLG register +// +//************************************************************************************************* +#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTCLR register +// +//************************************************************************************************* +#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTSET register +// +//************************************************************************************************* +#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTEN register +// +//************************************************************************************************* +#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMWAITSTATE register +// +//************************************************************************************************* +#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMPREFETCH register +// +//************************************************************************************************* +#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_memmap.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_memmap.h new file mode 100644 index 0000000..ba0b5e5 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_memmap.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMMAP_H +#define HW_MEMMAP_H + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define M0_RAM_BASE 0x00000000U +#define M1_RAM_BASE 0x00000400U +#define ADCARESULT_BASE 0x00000B00U +#define ADCBRESULT_BASE 0x00000B20U +#define ADCCRESULT_BASE 0x00000B40U +#define ADCDRESULT_BASE 0x00000B60U +#define CPUTIMER0_BASE 0x00000C00U +#define CPUTIMER1_BASE 0x00000C08U +#define CPUTIMER2_BASE 0x00000C10U +#define CLA1_SOFTINT_BASE 0x00000CE0U +#define PIECTRL_BASE 0x00000CE0U +#define PIEVECTTABLE_BASE 0x00000D00U +#define DMA_BASE 0x00001000U +#define DMA_CH1_BASE 0x00001020U +#define DMA_CH2_BASE 0x00001040U +#define DMA_CH3_BASE 0x00001060U +#define DMA_CH4_BASE 0x00001080U +#define DMA_CH5_BASE 0x000010A0U +#define DMA_CH6_BASE 0x000010C0U +#define CLA1_BASE 0x00001400U +#define CLATOCPU_RAM_BASE 0x00001480U +#define CPUTOCLA_RAM_BASE 0x00001500U +#define CLB1_BASE 0x00003000U +#define CLB1_LOGICCFG_BASE 0x00003000U +#define CLB1_LOGICCTL_BASE 0x00003100U +#define CLB1_DATAEXCH_BASE 0x00003200U +#define CLB2_BASE 0x00003400U +#define CLB2_LOGICCFG_BASE 0x00003400U +#define CLB2_LOGICCTL_BASE 0x00003500U +#define CLB2_DATAEXCH_BASE 0x00003600U +#define CLB3_BASE 0x00003800U +#define CLB3_LOGICCFG_BASE 0x00003800U +#define CLB3_LOGICCTL_BASE 0x00003900U +#define CLB3_DATAEXCH_BASE 0x00003A00U +#define CLB4_BASE 0x00003C00U +#define CLB4_LOGICCFG_BASE 0x00003C00U +#define CLB4_LOGICCTL_BASE 0x00003D00U +#define CLB4_DATAEXCH_BASE 0x00003E00U +#define EPWM1_BASE 0x00004000U +#define EPWM2_BASE 0x00004100U +#define EPWM3_BASE 0x00004200U +#define EPWM4_BASE 0x00004300U +#define EPWM5_BASE 0x00004400U +#define EPWM6_BASE 0x00004500U +#define EPWM7_BASE 0x00004600U +#define EPWM8_BASE 0x00004700U +#define EPWM9_BASE 0x00004800U +#define EPWM10_BASE 0x00004900U +#define EPWM11_BASE 0x00004A00U +#define EPWM12_BASE 0x00004B00U +#define ECAP1_BASE 0x00005000U +#define ECAP2_BASE 0x00005020U +#define ECAP3_BASE 0x00005040U +#define ECAP4_BASE 0x00005060U +#define ECAP5_BASE 0x00005080U +#define ECAP6_BASE 0x000050A0U +#define EQEP1_BASE 0x00005100U +#define EQEP2_BASE 0x00005140U +#define EQEP3_BASE 0x00005180U +#define DACA_BASE 0x00005C00U +#define DACB_BASE 0x00005C10U +#define DACC_BASE 0x00005C20U +#define CMPSS1_BASE 0x00005C80U +#define CMPSS2_BASE 0x00005CA0U +#define CMPSS3_BASE 0x00005CC0U +#define CMPSS4_BASE 0x00005CE0U +#define CMPSS5_BASE 0x00005D00U +#define CMPSS6_BASE 0x00005D20U +#define CMPSS7_BASE 0x00005D40U +#define CMPSS8_BASE 0x00005D60U +#define SDFM1_BASE 0x00005E00U +#define SDFM2_BASE 0x00005E80U +#define MCBSPA_BASE 0x00006000U +#define MCBSPB_BASE 0x00006040U +#define SPIA_BASE 0x00006100U +#define SPIB_BASE 0x00006110U +#define SPIC_BASE 0x00006120U +#define UPP_BASE 0x00006200U +#define UPP_TX_MSG_RAM_BASE 0x00006C00U +#define UPP_RX_MSG_RAM_BASE 0x00006E00U +#define WD_BASE 0x00007000U +#define NMI_BASE 0x00007060U +#define XINT_BASE 0x00007070U +#define SCIA_BASE 0x00007200U +#define SCIB_BASE 0x00007210U +#define SCIC_BASE 0x00007220U +#define SCID_BASE 0x00007230U +#define I2CA_BASE 0x00007300U +#define I2CB_BASE 0x00007340U +#define ADCA_BASE 0x00007400U +#define ADCB_BASE 0x00007480U +#define ADCC_BASE 0x00007500U +#define ADCD_BASE 0x00007580U +#define INPUTXBAR_BASE 0x00007900U +#define XBAR_BASE 0x00007920U +#define SYNCSOC_BASE 0x00007940U +#define DMACLASRCSEL_BASE 0x00007980U +#define EPWMXBAR_BASE 0x00007A00U +#define CLBXBAR_BASE 0x00007A40U +#define OUTPUTXBAR_BASE 0x00007A80U +#define GPIOCTRL_BASE 0x00007C00U +#define GPIODATA_BASE 0x00007F00U +#define LS0_RAM_BASE 0x00008000U +#define LS1_RAM_BASE 0x00008800U +#define LS2_RAM_BASE 0x00009000U +#define LS3_RAM_BASE 0x00009800U +#define LS4_RAM_BASE 0x0000A000U +#define LS5_RAM_BASE 0x0000A800U +#define D0_RAM_BASE 0x0000B000U +#define D1_RAM_BASE 0x0000B800U +#define GS0_RAM_BASE 0x0000C000U +#define GS1_RAM_BASE 0x0000D000U +#define GS2_RAM_BASE 0x0000E000U +#define GS3_RAM_BASE 0x0000F000U +#define GS4_RAM_BASE 0x00010000U +#define GS5_RAM_BASE 0x00011000U +#define GS6_RAM_BASE 0x00012000U +#define GS7_RAM_BASE 0x00013000U +#define GS8_RAM_BASE 0x00014000U +#define GS9_RAM_BASE 0x00015000U +#define GS10_RAM_BASE 0x00016000U +#define GS11_RAM_BASE 0x00017000U +#define GS12_RAM_BASE 0x00018000U +#define GS13_RAM_BASE 0x00019000U +#define GS14_RAM_BASE 0x0001A000U +#define GS15_RAM_BASE 0x0001B000U +#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U +#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U +#define USBA_BASE 0x00040000U +#define EMIF1_BASE 0x00047000U +#define EMIF2_BASE 0x00047800U +#define CANA_BASE 0x00048000U +#define CANA_MSG_RAM_BASE 0x00049000U +#define CANB_BASE 0x0004A000U +#define CANB_MSG_RAM_BASE 0x0004B000U +#define IPC_BASE 0x00050000U +#define FLASHPUMPSEMAPHORE_BASE 0x00050024U +#define DEVCFG_BASE 0x0005D000U +#define ANALOGSUBSYS_BASE 0x0005D180U +#define CLKCFG_BASE 0x0005D200U +#define CPUSYS_BASE 0x0005D300U +#define ROMPREFETCH_BASE 0x0005E608U +#define DCSM_Z1_BASE 0x0005F000U +#define DCSM_Z2_BASE 0x0005F040U +#define DCSMCOMMON_BASE 0x0005F070U +#define MEMCFG_BASE 0x0005F400U +#define EMIF1CONFIG_BASE 0x0005F480U +#define EMIF2CONFIG_BASE 0x0005F4A0U +#define ACCESSPROTECTION_BASE 0x0005F4C0U +#define MEMORYERROR_BASE 0x0005F500U +#define ROMWAITSTATE_BASE 0x0005F540U +#define FLASH0CTRL_BASE 0x0005F800U +#define FLASH0ECC_BASE 0x0005FB00U +#define DCSM_Z1OTP_BASE 0x00078000U +#define DCSM_Z2OTP_BASE 0x00078200U +#define UID_BASE 0x000703C0U +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_nmi.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_nmi.h new file mode 100644 index 0000000..efd8157 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_nmi.h @@ -0,0 +1,134 @@ +//########################################################################### +// +// FILE: hw_nmi.h +// +// TITLE: Definitions for the NMI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_NMI_H +#define HW_NMI_H + +//************************************************************************************************* +// +// The following are defines for the NMI register offsets +// +//************************************************************************************************* +#define NMI_O_CFG 0x0U // NMI Configuration Register +#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear) +#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register +#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register +#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register +#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register +#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMICFG register +// +//************************************************************************************************* +#define NMI_CFG_NMIE 0x1U // Global NMI Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLG register +// +//************************************************************************************************* +#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag +#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag +#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag +#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag +#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag +#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag +#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag +#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag +#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag +#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGCLR register +// +//************************************************************************************************* +#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear +#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear +#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear +#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear +#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear +#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear +#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear +#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear +#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear +#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear +#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGFRC register +// +//************************************************************************************************* +#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force +#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force +#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force +#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force +#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force +#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force +#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force +#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force +#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force +#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMISHDFLG register +// +//************************************************************************************************* +#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag +#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag +#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag +#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag +#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag +#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag +#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag +#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag +#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag +#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_otp.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_otp.h new file mode 100644 index 0000000..d074499 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_otp.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: hw_otp.h +// +// TITLE: Definitions for the OTP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OTP_H +#define HW_OTP_H + +//************************************************************************************************* +// +// The following are defines for the OTP register offsets +// +//************************************************************************************************* +#define OTP_O_UID_PSRAND0 0x0U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND1 0x2U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND2 0x4U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND3 0x6U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND4 0x8U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND5 0xAU // UID Psuedo-random 160 bit number +#define OTP_O_UID_UNIQUE 0xCU // UID UID Unique 32 bit number +#define OTP_O_UID_CHECKSUM 0xEU // UID Checksum + + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_outputxbar.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_outputxbar.h new file mode 100644 index 0000000..30a10e9 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_outputxbar.h @@ -0,0 +1,1340 @@ +//########################################################################### +// +// FILE: hw_outputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OUTPUTXBAR_H +#define HW_OUTPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_OUTPUT1MUX0TO15CFG 0x0U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT1MUX16TO31CFG 0x2U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT2MUX0TO15CFG 0x4U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT2MUX16TO31CFG 0x6U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT3MUX0TO15CFG 0x8U // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT3MUX16TO31CFG 0xAU // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT4MUX0TO15CFG 0xCU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT4MUX16TO31CFG 0xEU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT5MUX0TO15CFG 0x10U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT5MUX16TO31CFG 0x12U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT6MUX0TO15CFG 0x14U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT6MUX16TO31CFG 0x16U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT7MUX0TO15CFG 0x18U // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT7MUX16TO31CFG 0x1AU // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT8MUX0TO15CFG 0x1CU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT8MUX16TO31CFG 0x1EU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT1MUXENABLE 0x20U // Output X-BAR Mux Enable for Output 1 +#define XBAR_O_OUTPUT2MUXENABLE 0x22U // Output X-BAR Mux Enable for Output 2 +#define XBAR_O_OUTPUT3MUXENABLE 0x24U // Output X-BAR Mux Enable for Output 3 +#define XBAR_O_OUTPUT4MUXENABLE 0x26U // Output X-BAR Mux Enable for Output 4 +#define XBAR_O_OUTPUT5MUXENABLE 0x28U // Output X-BAR Mux Enable for Output 5 +#define XBAR_O_OUTPUT6MUXENABLE 0x2AU // Output X-BAR Mux Enable for Output 6 +#define XBAR_O_OUTPUT7MUXENABLE 0x2CU // Output X-BAR Mux Enable for Output 7 +#define XBAR_O_OUTPUT8MUXENABLE 0x2EU // Output X-BAR Mux Enable for Output 8 +#define XBAR_O_OUTPUTLATCH 0x30U // Output X-BAR Output Latch +#define XBAR_O_OUTPUTLATCHCLR 0x32U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHFRC 0x34U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHENABLE 0x36U // Output X-BAR Output Latch Enable +#define XBAR_O_OUTPUTINV 0x38U // Output X-BAR Output Inversion +#define XBAR_O_OUTPUTLOCK 0x3EU // Output X-BAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT1 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT2 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT3 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT4 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT5 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT6 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT7 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCH register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCH_OUTPUT1 0x1U // Records the OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT2 0x2U // Records the OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT3 0x4U // Records the OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT4 0x8U // Records the OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT5 0x10U // Records the OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT6 0x20U // Records the OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT7 0x40U // Records the OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT8 0x80U // Records the OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHCLR register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHCLR_OUTPUT1 0x1U // Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT2 0x2U // Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT3 0x4U // Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT4 0x8U // Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT5 0x10U // Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT6 0x20U // Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT7 0x40U // Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT8 0x80U // Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHFRC register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHFRC_OUTPUT1 0x1U // Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT2 0x2U // Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT3 0x4U // Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT4 0x8U // Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT5 0x10U // Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT6 0x20U // Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT7 0x40U // Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT8 0x80U // Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHENABLE_OUTPUT1 0x1U // Selects the output latch to drive OUTPUT1 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT2 0x2U // Selects the output latch to drive OUTPUT2 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT3 0x4U // Selects the output latch to drive OUTPUT3 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT4 0x8U // Selects the output latch to drive OUTPUT4 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT5 0x10U // Selects the output latch to drive OUTPUT5 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT6 0x20U // Selects the output latch to drive OUTPUT6 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT7 0x40U // Selects the output latch to drive OUTPUT7 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT8 0x80U // Selects the output latch to drive OUTPUT8 for + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTINV register +// +//************************************************************************************************* +#define XBAR_OUTPUTINV_OUTPUT1 0x1U // Selects polarity for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT2 0x2U // Selects polarity for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT3 0x4U // Selects polarity for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT4 0x8U // Selects polarity for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT5 0x10U // Selects polarity for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT6 0x20U // Selects polarity for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT7 0x40U // Selects polarity for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT8 0x80U // Selects polarity for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLOCK register +// +//************************************************************************************************* +#define XBAR_OUTPUTLOCK_LOCK 0x1U // Locks the configuration for OUTPUT-XBAR +#define XBAR_OUTPUTLOCK_KEY_S 16U +#define XBAR_OUTPUTLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_pie.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_pie.h new file mode 100644 index 0000000..9a4f09f --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_pie.h @@ -0,0 +1,636 @@ +//########################################################################### +// +// FILE: hw_pie.h +// +// TITLE: Definitions for the PIE registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_PIE_H +#define HW_PIE_H + +//************************************************************************************************* +// +// The following are defines for the PIE register offsets +// +//************************************************************************************************* +#define PIE_O_CTRL 0x0U // ePIE Control Register +#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register +#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register +#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register +#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register +#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register +#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register +#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register +#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register +#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register +#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register +#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register +#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register +#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register +#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register +#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register +#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register +#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register +#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register +#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register +#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register +#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register +#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register +#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register +#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register +#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIECTRL register +// +//************************************************************************************************* +#define PIE_CTRL_ENPIE 0x1U // PIE Enable +#define PIE_CTRL_PIEVECT_S 1U +#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEACK register +// +//************************************************************************************************* +#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1 +#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2 +#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3 +#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4 +#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5 +#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6 +#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7 +#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8 +#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9 +#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10 +#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11 +#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER1 register +// +//************************************************************************************************* +#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1 +#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2 +#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3 +#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4 +#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5 +#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6 +#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7 +#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8 +#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9 +#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10 +#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11 +#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12 +#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13 +#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14 +#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15 +#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR1 register +// +//************************************************************************************************* +#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1 +#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2 +#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3 +#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4 +#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5 +#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6 +#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7 +#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8 +#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9 +#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10 +#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11 +#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12 +#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13 +#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14 +#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15 +#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER2 register +// +//************************************************************************************************* +#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1 +#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2 +#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3 +#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4 +#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5 +#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6 +#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7 +#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8 +#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9 +#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10 +#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11 +#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12 +#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13 +#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14 +#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15 +#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR2 register +// +//************************************************************************************************* +#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1 +#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2 +#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3 +#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4 +#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5 +#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6 +#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7 +#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8 +#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9 +#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10 +#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11 +#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12 +#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13 +#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14 +#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15 +#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER3 register +// +//************************************************************************************************* +#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1 +#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2 +#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3 +#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4 +#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5 +#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6 +#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7 +#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8 +#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9 +#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10 +#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11 +#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12 +#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13 +#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14 +#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15 +#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR3 register +// +//************************************************************************************************* +#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1 +#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2 +#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3 +#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4 +#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5 +#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6 +#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7 +#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8 +#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9 +#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10 +#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11 +#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12 +#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13 +#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14 +#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15 +#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER4 register +// +//************************************************************************************************* +#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1 +#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2 +#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3 +#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4 +#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5 +#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6 +#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7 +#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8 +#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9 +#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10 +#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11 +#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12 +#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13 +#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14 +#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15 +#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR4 register +// +//************************************************************************************************* +#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1 +#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2 +#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3 +#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4 +#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5 +#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6 +#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7 +#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8 +#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9 +#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10 +#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11 +#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12 +#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13 +#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14 +#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15 +#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER5 register +// +//************************************************************************************************* +#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1 +#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2 +#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3 +#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4 +#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5 +#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6 +#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7 +#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8 +#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9 +#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10 +#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11 +#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12 +#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13 +#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14 +#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15 +#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR5 register +// +//************************************************************************************************* +#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1 +#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2 +#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3 +#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4 +#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5 +#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6 +#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7 +#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8 +#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9 +#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10 +#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11 +#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12 +#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13 +#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14 +#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15 +#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER6 register +// +//************************************************************************************************* +#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1 +#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2 +#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3 +#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4 +#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5 +#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6 +#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7 +#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8 +#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9 +#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10 +#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11 +#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12 +#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13 +#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14 +#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15 +#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR6 register +// +//************************************************************************************************* +#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1 +#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2 +#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3 +#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4 +#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5 +#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6 +#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7 +#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8 +#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9 +#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10 +#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11 +#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12 +#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13 +#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14 +#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15 +#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER7 register +// +//************************************************************************************************* +#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1 +#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2 +#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3 +#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4 +#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5 +#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6 +#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7 +#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8 +#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9 +#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10 +#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11 +#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12 +#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13 +#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14 +#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15 +#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR7 register +// +//************************************************************************************************* +#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1 +#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2 +#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3 +#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4 +#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5 +#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6 +#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7 +#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8 +#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9 +#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10 +#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11 +#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12 +#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13 +#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14 +#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15 +#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER8 register +// +//************************************************************************************************* +#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1 +#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2 +#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3 +#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4 +#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5 +#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6 +#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7 +#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8 +#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9 +#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10 +#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11 +#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12 +#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13 +#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14 +#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15 +#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR8 register +// +//************************************************************************************************* +#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1 +#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2 +#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3 +#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4 +#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5 +#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6 +#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7 +#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8 +#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9 +#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10 +#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11 +#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12 +#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13 +#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14 +#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15 +#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER9 register +// +//************************************************************************************************* +#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1 +#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2 +#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3 +#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4 +#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5 +#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6 +#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7 +#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8 +#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9 +#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10 +#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11 +#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12 +#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13 +#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14 +#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15 +#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR9 register +// +//************************************************************************************************* +#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1 +#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2 +#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3 +#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4 +#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5 +#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6 +#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7 +#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8 +#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9 +#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10 +#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11 +#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12 +#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13 +#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14 +#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15 +#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER10 register +// +//************************************************************************************************* +#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1 +#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2 +#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3 +#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4 +#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5 +#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6 +#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7 +#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8 +#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9 +#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10 +#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11 +#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12 +#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13 +#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14 +#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15 +#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR10 register +// +//************************************************************************************************* +#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1 +#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2 +#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3 +#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4 +#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5 +#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6 +#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7 +#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8 +#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9 +#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10 +#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11 +#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12 +#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13 +#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14 +#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15 +#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER11 register +// +//************************************************************************************************* +#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1 +#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2 +#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3 +#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4 +#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5 +#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6 +#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7 +#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8 +#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9 +#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10 +#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11 +#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12 +#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13 +#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14 +#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15 +#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR11 register +// +//************************************************************************************************* +#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1 +#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2 +#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3 +#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4 +#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5 +#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6 +#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7 +#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8 +#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9 +#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10 +#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11 +#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12 +#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13 +#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14 +#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15 +#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER12 register +// +//************************************************************************************************* +#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1 +#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2 +#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3 +#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4 +#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5 +#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6 +#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7 +#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8 +#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9 +#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10 +#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11 +#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12 +#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13 +#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14 +#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15 +#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR12 register +// +//************************************************************************************************* +#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1 +#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2 +#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3 +#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4 +#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5 +#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6 +#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7 +#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8 +#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9 +#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10 +#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11 +#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12 +#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13 +#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14 +#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15 +#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16 + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_sci.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sci.h new file mode 100644 index 0000000..2fc9680 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sci.h @@ -0,0 +1,209 @@ +//########################################################################### +// +// FILE: hw_sci.h +// +// TITLE: Definitions for the SCI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SCI_H +#define HW_SCI_H + +//************************************************************************************************* +// +// The following are defines for the SCI register offsets +// +//************************************************************************************************* +#define SCI_O_CCR 0x0U // Communications control register +#define SCI_O_CTL1 0x1U // Control register 1 +#define SCI_O_HBAUD 0x2U // Baud rate (high) register +#define SCI_O_LBAUD 0x3U // Baud rate (low) register +#define SCI_O_CTL2 0x4U // Control register 2 +#define SCI_O_RXST 0x5U // Receive status register +#define SCI_O_RXEMU 0x6U // Receive emulation buffer register +#define SCI_O_RXBUF 0x7U // Receive data buffer +#define SCI_O_TXBUF 0x9U // Transmit data buffer +#define SCI_O_FFTX 0xAU // FIFO transmit register +#define SCI_O_FFRX 0xBU // FIFO receive register +#define SCI_O_FFCT 0xCU // FIFO control register +#define SCI_O_PRI 0xFU // SCI priority control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICCR register +// +//************************************************************************************************* +#define SCI_CCR_SCICHAR_S 0U +#define SCI_CCR_SCICHAR_M 0x7U // Character length control +#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control +#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable +#define SCI_CCR_PARITYENA 0x20U // Parity enable +#define SCI_CCR_PARITY 0x40U // Even or Odd Parity +#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL1 register +// +//************************************************************************************************* +#define SCI_CTL1_RXENA 0x1U // SCI receiver enable +#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable +#define SCI_CTL1_SLEEP 0x4U // SCI sleep +#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method +#define SCI_CTL1_SWRESET 0x20U // Software reset +#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//************************************************************************************************* +#define SCI_HBAUD_BAUD_S 0U +#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCILBAUD register +// +//************************************************************************************************* +#define SCI_LBAUD_BAUD_S 0U +#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL2 register +// +//************************************************************************************************* +#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable +#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable +#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag +#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXST register +// +//************************************************************************************************* +#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag +#define SCI_RXST_PE 0x4U // Parity error flag +#define SCI_RXST_OE 0x8U // Overrun error flag +#define SCI_RXST_FE 0x10U // Framing error flag +#define SCI_RXST_BRKDT 0x20U // Break-detect flag +#define SCI_RXST_RXRDY 0x40U // Receiver ready flag +#define SCI_RXST_RXERROR 0x80U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//************************************************************************************************* +#define SCI_RXEMU_ERXDT_S 0U +#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//************************************************************************************************* +#define SCI_RXBUF_SAR_S 0U +#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits +#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag +#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCITXBUF register +// +//************************************************************************************************* +#define SCI_TXBUF_TXDT_S 0U +#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFTX register +// +//************************************************************************************************* +#define SCI_FFTX_TXFFIL_S 0U +#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level +#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable +#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFTX_TXFFINT 0x80U // INT flag +#define SCI_FFTX_TXFFST_S 8U +#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status +#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset +#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable +#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFRX register +// +//************************************************************************************************* +#define SCI_FFRX_RXFFIL_S 0U +#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level +#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable +#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFRX_RXFFINT 0x80U // INT flag +#define SCI_FFRX_RXFFST_S 8U +#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status +#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset +#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow +#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFCT register +// +//************************************************************************************************* +#define SCI_FFCT_FFTXDLY_S 0U +#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay +#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable +#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear +#define SCI_FFCT_ABD 0x8000U // Auto baud detect + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIPRI register +// +//************************************************************************************************* +#define SCI_PRI_FREESOFT_S 3U +#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_sdfm.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sdfm.h new file mode 100644 index 0000000..d2ba146 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sdfm.h @@ -0,0 +1,431 @@ +//########################################################################### +// +// FILE: hw_sdfm.h +// +// TITLE: Definitions for the SDFM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SDFM_H +#define HW_SDFM_H + +//************************************************************************************************* +// +// The following are defines for the SDFM register offsets +// +//************************************************************************************************* +#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register +#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register +#define SDFM_O_SDCTL 0x4U // SD Control Register +#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable +#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1 +#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1 +#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1 +#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1 +#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1 +#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1 +#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1 +#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2 +#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2 +#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2 +#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2 +#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2 +#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2 +#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2 +#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3 +#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3 +#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3 +#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3 +#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3 +#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3 +#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3 +#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4 +#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4 +#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4 +#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4 +#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4 +#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4 +#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLG register +// +//************************************************************************************************* +#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLGCLR register +// +//************************************************************************************************* +#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTL register +// +//************************************************************************************************* +#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDMFILEN register +// +//************************************************************************************************* +#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM1_MOD_S 0U +#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM1_DOSR_S 0U +#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM1_SST_S 10U +#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3) +#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM1_SH_S 11U +#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH1 register +// +//************************************************************************************************* +#define SDFM_SDCMPH1_HLT_S 0U +#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL1 register +// +//************************************************************************************************* +#define SDFM_SDCMPL1_LLT_S 0U +#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCPARM1_COSR_S 0U +#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM1_CS1_CS0_S 7U +#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA1 register +// +//************************************************************************************************* +#define SDFM_SDDATA1_DATA16_S 0U +#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA1_DATA32HI_S 16U +#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM2_MOD_S 0U +#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM2_DOSR_S 0U +#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM2_SST_S 10U +#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3) +#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM2_SH_S 11U +#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH2 register +// +//************************************************************************************************* +#define SDFM_SDCMPH2_HLT_S 0U +#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL2 register +// +//************************************************************************************************* +#define SDFM_SDCMPL2_LLT_S 0U +#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCPARM2_COSR_S 0U +#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM2_CS1_CS0_S 7U +#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA2 register +// +//************************************************************************************************* +#define SDFM_SDDATA2_DATA16_S 0U +#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA2_DATA32HI_S 16U +#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM3_MOD_S 0U +#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM3_DOSR_S 0U +#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM3_SST_S 10U +#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM3_SH_S 11U +#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH3 register +// +//************************************************************************************************* +#define SDFM_SDCMPH3_HLT_S 0U +#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL3 register +// +//************************************************************************************************* +#define SDFM_SDCMPL3_LLT_S 0U +#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCPARM3_COSR_S 0U +#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM3_CS1_CS0_S 7U +#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA3 register +// +//************************************************************************************************* +#define SDFM_SDDATA3_DATA16_S 0U +#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA3_DATA32HI_S 16U +#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM4_MOD_S 0U +#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM4_DOSR_S 0U +#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM4_SST_S 10U +#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM4_SH_S 11U +#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH4 register +// +//************************************************************************************************* +#define SDFM_SDCMPH4_HLT_S 0U +#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL4 register +// +//************************************************************************************************* +#define SDFM_SDCMPL4_LLT_S 0U +#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCPARM4_COSR_S 0U +#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM4_CS1_CS0_S 7U +#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA4 register +// +//************************************************************************************************* +#define SDFM_SDDATA4_DATA16_S 0U +#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA4_DATA32HI_S 16U +#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_spi.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_spi.h new file mode 100644 index 0000000..c4907aa --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_spi.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_spi.h +// +// TITLE: Definitions for the SPI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SPI_H +#define HW_SPI_H + +//************************************************************************************************* +// +// The following are defines for the SPI register offsets +// +//************************************************************************************************* +#define SPI_O_CCR 0x0U // SPI Configuration Control Register +#define SPI_O_CTL 0x1U // SPI Operation Control Register +#define SPI_O_STS 0x2U // SPI Status Register +#define SPI_O_BRR 0x4U // SPI Baud Rate Register +#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register +#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register +#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register +#define SPI_O_DAT 0x9U // SPI Serial Data Register +#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register +#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register +#define SPI_O_FFCT 0xCU // SPI FIFO Control Register +#define SPI_O_PRI 0xFU // SPI Priority Control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICCR register +// +//************************************************************************************************* +#define SPI_CCR_SPICHAR_S 0U +#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control +#define SPI_CCR_SPILBK 0x10U // SPI Loopback +#define SPI_CCR_HS_MODE 0x20U // High Speed mode control +#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity +#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICTL register +// +//************************************************************************************************* +#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable +#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable +#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control +#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase +#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPISTS register +// +//************************************************************************************************* +#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag +#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag +#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIBRR register +// +//************************************************************************************************* +#define SPI_BRR_SPI_BIT_RATE_S 0U +#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFTX register +// +//************************************************************************************************* +#define SPI_FFTX_TXFFIL_S 0U +#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level +#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable +#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear +#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag +#define SPI_FFTX_TXFFST_S 8U +#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset +#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable +#define SPI_FFTX_SPIRST 0x8000U // SPI Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFRX register +// +//************************************************************************************************* +#define SPI_FFRX_RXFFIL_S 0U +#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level +#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable +#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear +#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag +#define SPI_FFRX_RXFFST_S 8U +#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset +#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear +#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFCT register +// +//************************************************************************************************* +#define SPI_FFCT_TXDLY_S 0U +#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIPRI register +// +//************************************************************************************************* +#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit +#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit +#define SPI_PRI_FREE 0x10U // Free emulation mode +#define SPI_PRI_SOFT 0x20U // Soft emulation mode + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_sysctl.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sysctl.h new file mode 100644 index 0000000..11df8d3 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_sysctl.h @@ -0,0 +1,1428 @@ +//########################################################################### +// +// FILE: hw_sysctl.h +// +// TITLE: Definitions for the SYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SYSCTL_H +#define HW_SYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the SYSCTL register offsets +// +//************************************************************************************************* +#define SYSCTL_O_DEVCFGLOCK1 0x0U // Lock bit for CPUSELx registers +#define SYSCTL_O_PARTIDL 0x8U // Lower 32-bit of Device PART Identification Number +#define SYSCTL_O_PARTIDH 0xAU // Upper 32-bit of Device PART Identification Number +#define SYSCTL_O_REVID 0xCU // Device Revision Number +#define SYSCTL_O_DC0 0x10U // Device Capability: Device Information +#define SYSCTL_O_DC1 0x12U // Device Capability: Processing Block Customization +#define SYSCTL_O_DC2 0x14U // Device Capability: EMIF Customization +#define SYSCTL_O_DC3 0x16U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC4 0x18U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC5 0x1AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC6 0x1CU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC7 0x1EU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC8 0x20U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC9 0x22U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC10 0x24U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC11 0x26U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC12 0x28U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC13 0x2AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC14 0x2CU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC15 0x2EU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC17 0x32U // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC18 0x34U // Device Capability: CPU1 Lx SRAM Customization +#define SYSCTL_O_DC19 0x36U // Device Capability: CPU2 Lx SRAM Customization +#define SYSCTL_O_DC20 0x38U // Device Capability: GSx SRAM Customization +#define SYSCTL_O_PERCNF1 0x60U // Peripheral Configuration register +#define SYSCTL_O_FUSEERR 0x74U // e-Fuse error Status register +#define SYSCTL_O_SOFTPRES0 0x82U // Processing Block Software Reset register +#define SYSCTL_O_SOFTPRES1 0x84U // EMIF Software Reset register +#define SYSCTL_O_SOFTPRES2 0x86U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES3 0x88U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES4 0x8AU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES6 0x8EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES7 0x90U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES8 0x92U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES9 0x94U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES11 0x98U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES13 0x9CU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES14 0x9EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES16 0xA2U // Peripheral Software Reset register +#define SYSCTL_O_CPUSEL0 0xD6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL1 0xD8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL2 0xDAU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL4 0xDEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL5 0xE0U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL6 0xE2U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL7 0xE4U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL8 0xE6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL9 0xE8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL11 0xECU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL12 0xEEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL14 0xF2U // CPU Select register for common peripherals +#define SYSCTL_O_CPU2RESCTL 0x122U // CPU2 Reset Control Register +#define SYSCTL_O_RSTSTAT 0x124U // Reset Status register for secondary C28x CPUs +#define SYSCTL_O_LPMSTAT 0x125U // LPM Status Register for secondary C28x CPUs +#define SYSCTL_O_SYSDBGCTL 0x12CU // System Debug Control register + +#define SYSCTL_O_CLKSEM 0x0U // Clock Control Semaphore Register +#define SYSCTL_O_CLKCFGLOCK1 0x2U // Lock bit for CLKCFG registers +#define SYSCTL_O_CLKSRCCTL1 0x8U // Clock Source Control register-1 +#define SYSCTL_O_CLKSRCCTL2 0xAU // Clock Source Control register-2 +#define SYSCTL_O_CLKSRCCTL3 0xCU // Clock Source Control register-3 +#define SYSCTL_O_SYSPLLCTL1 0xEU // SYSPLL Control register-1 +#define SYSCTL_O_SYSPLLMULT 0x14U // SYSPLL Multiplier register +#define SYSCTL_O_SYSPLLSTS 0x16U // SYSPLL Status register +#define SYSCTL_O_AUXPLLCTL1 0x18U // AUXPLL Control register-1 +#define SYSCTL_O_AUXPLLMULT 0x1EU // AUXPLL Multiplier register +#define SYSCTL_O_AUXPLLSTS 0x20U // AUXPLL Status register +#define SYSCTL_O_SYSCLKDIVSEL 0x22U // System Clock Divider Select register +#define SYSCTL_O_AUXCLKDIVSEL 0x24U // Auxillary Clock Divider Select register +#define SYSCTL_O_PERCLKDIVSEL 0x26U // Peripheral Clock Divider Selet register +#define SYSCTL_O_XCLKOUTDIVSEL 0x28U // XCLKOUT Divider Select register +#define SYSCTL_O_LOSPCP 0x2CU // Low Speed Clock Source Prescalar +#define SYSCTL_O_MCDCR 0x2EU // Missing Clock Detect Control Register +#define SYSCTL_O_X1CNT 0x30U // 10-bit Counter on X1 Clock + +#define SYSCTL_O_CPUSYSLOCK1 0x0U // Lock bit for CPUSYS registers +#define SYSCTL_O_HIBBOOTMODE 0x6U // HIB Boot Mode Register +#define SYSCTL_O_IORESTOREADDR 0x8U // IORestore() routine Address Register +#define SYSCTL_O_PIEVERRADDR 0xAU // PIE Vector Fetch Error Address register +#define SYSCTL_O_PCLKCR0 0x22U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR1 0x24U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR2 0x26U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR3 0x28U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR4 0x2AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR6 0x2EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR7 0x30U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR8 0x32U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR9 0x34U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR10 0x36U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR11 0x38U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR12 0x3AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR13 0x3CU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR14 0x3EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR16 0x42U // Peripheral Clock Gating Registers +#define SYSCTL_O_SECMSEL 0x74U // Secondary Master Select register for common + // peripherals: Selects between CLA & DMA +#define SYSCTL_O_LPMCR 0x76U // LPM Control Register +#define SYSCTL_O_GPIOLPMSEL0 0x78U // GPIO LPM Wakeup select registers +#define SYSCTL_O_GPIOLPMSEL1 0x7AU // GPIO LPM Wakeup select registers +#define SYSCTL_O_TMR2CLKCTL 0x7CU // Timer2 Clock Measurement functionality control register +#define SYSCTL_O_RESC 0x80U // Reset Cause register + +#define SYSCTL_O_SCSR 0x22U // System Control & Status Register +#define SYSCTL_O_WDCNTR 0x23U // Watchdog Counter Register +#define SYSCTL_O_WDKEY 0x25U // Watchdog Reset Key Register +#define SYSCTL_O_WDCR 0x29U // Watchdog Control Register +#define SYSCTL_O_WDWCR 0x2AU // Watchdog Windowed Control Register + +#define SYSCTL_O_CLA1TASKSRCSELLOCK 0x0U // CLA1 Task Trigger Source Select Lock Register +#define SYSCTL_O_DMACHSRCSELLOCK 0x4U // DMA Channel Triger Source Select Lock Register +#define SYSCTL_O_CLA1TASKSRCSEL1 0x6U // CLA1 Task Trigger Source Select Register-1 +#define SYSCTL_O_CLA1TASKSRCSEL2 0x8U // CLA1 Task Trigger Source Select Register-2 +#define SYSCTL_O_DMACHSRCSEL1 0x16U // DMA Channel Trigger Source Select Register-1 +#define SYSCTL_O_DMACHSRCSEL2 0x18U // DMA Channel Trigger Source Select Register-2 + +#define SYSCTL_O_SYNCSELECT 0x0U // Sync Input and Output Select Register +#define SYSCTL_O_ADCSOCOUTSELECT 0x2U // External ADC (Off Chip) SOC Select Register +#define SYSCTL_O_SYNCSOCLOCK 0x4U // SYNCSEL and EXTADCSOC Select Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEVCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_DEVCFGLOCK1_CPUSEL0 0x1U // Lock bit for CPUSEL0 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL1 0x2U // Lock bit for CPUSEL1 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL2 0x4U // Lock bit for CPUSEL2 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL3 0x8U // Lock bit for CPUSEL3 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL4 0x10U // Lock bit for CPUSEL4 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL5 0x20U // Lock bit for CPUSEL5 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL6 0x40U // Lock bit for CPUSEL6 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL7 0x80U // Lock bit for CPUSEL7 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL8 0x100U // Lock bit for CPUSEL8 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL9 0x200U // Lock bit for CPUSEL9 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL10 0x400U // Lock bit for CPUSEL10 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL11 0x800U // Lock bit for CPUSEL11 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL12 0x1000U // Lock bit for CPUSEL12 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL13 0x2000U // Lock bit for CPUSEL13 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL14 0x4000U // Lock bit for CPUSEL14 register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDL register +// +//************************************************************************************************* +#define SYSCTL_PARTIDL_QUAL_S 6U +#define SYSCTL_PARTIDL_QUAL_M 0xC0U // Qualification Status +#define SYSCTL_PARTIDL_PIN_COUNT_S 8U +#define SYSCTL_PARTIDL_PIN_COUNT_M 0x700U // Device Pin Count +#define SYSCTL_PARTIDL_INSTASPIN_S 13U +#define SYSCTL_PARTIDL_INSTASPIN_M 0x6000U // Motorware feature set +#define SYSCTL_PARTIDL_FLASH_SIZE_S 16U +#define SYSCTL_PARTIDL_FLASH_SIZE_M 0xFF0000U // Flash size in KB +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S 28U +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M 0xF0000000U // Revision of the PARTID format + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDH register +// +//************************************************************************************************* +#define SYSCTL_PARTIDH_FAMILY_S 8U +#define SYSCTL_PARTIDH_FAMILY_M 0xFF00U // Device family +#define SYSCTL_PARTIDH_PARTNO_S 16U +#define SYSCTL_PARTIDH_PARTNO_M 0xFF0000U // Device part number +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_S 24U +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_M 0xFF000000U // Device class ID + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC0 register +// +//************************************************************************************************* +#define SYSCTL_DC0_SINGLE_CORE 0x1U // Single Core vs Dual Core + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC1 register +// +//************************************************************************************************* +#define SYSCTL_DC1_CPU1_FPU_TMU 0x1U // CPU1's FPU1+TMU1 +#define SYSCTL_DC1_CPU2_FPU_TMU 0x2U // CPU2's FPU2+TMU2 +#define SYSCTL_DC1_CPU1_VCU 0x4U // CPU1's VCU +#define SYSCTL_DC1_CPU2_VCU 0x8U // CPU2's VCU +#define SYSCTL_DC1_CPU1_CLA1 0x40U // CPU1.CLA1 +#define SYSCTL_DC1_CPU2_CLA1 0x100U // CPU2.CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC2 register +// +//************************************************************************************************* +#define SYSCTL_DC2_EMIF1 0x1U // EMIF1 +#define SYSCTL_DC2_EMIF2 0x2U // EMIF2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC3 register +// +//************************************************************************************************* +#define SYSCTL_DC3_EPWM1 0x1U // EPWM1 +#define SYSCTL_DC3_EPWM2 0x2U // EPWM2 +#define SYSCTL_DC3_EPWM3 0x4U // EPWM3 +#define SYSCTL_DC3_EPWM4 0x8U // EPWM4 +#define SYSCTL_DC3_EPWM5 0x10U // EPWM5 +#define SYSCTL_DC3_EPWM6 0x20U // EPWM6 +#define SYSCTL_DC3_EPWM7 0x40U // EPWM7 +#define SYSCTL_DC3_EPWM8 0x80U // EPWM8 +#define SYSCTL_DC3_EPWM9 0x100U // EPWM9 +#define SYSCTL_DC3_EPWM10 0x200U // EPWM10 +#define SYSCTL_DC3_EPWM11 0x400U // EPWM11 +#define SYSCTL_DC3_EPWM12 0x800U // EPWM12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC4 register +// +//************************************************************************************************* +#define SYSCTL_DC4_ECAP1 0x1U // ECAP1 +#define SYSCTL_DC4_ECAP2 0x2U // ECAP2 +#define SYSCTL_DC4_ECAP3 0x4U // ECAP3 +#define SYSCTL_DC4_ECAP4 0x8U // ECAP4 +#define SYSCTL_DC4_ECAP5 0x10U // ECAP5 +#define SYSCTL_DC4_ECAP6 0x20U // ECAP6 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC5 register +// +//************************************************************************************************* +#define SYSCTL_DC5_EQEP1 0x1U // EQEP1 +#define SYSCTL_DC5_EQEP2 0x2U // EQEP2 +#define SYSCTL_DC5_EQEP3 0x4U // EQEP3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC6 register +// +//************************************************************************************************* +#define SYSCTL_DC6_CLB1 0x1U // CLB1 +#define SYSCTL_DC6_CLB2 0x2U // CLB2 +#define SYSCTL_DC6_CLB3 0x4U // CLB3 +#define SYSCTL_DC6_CLB4 0x8U // CLB4 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC7 register +// +//************************************************************************************************* +#define SYSCTL_DC7_SD1 0x1U // SD1 +#define SYSCTL_DC7_SD2 0x2U // SD2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC8 register +// +//************************************************************************************************* +#define SYSCTL_DC8_SCI_A 0x1U // SCI_A +#define SYSCTL_DC8_SCI_B 0x2U // SCI_B +#define SYSCTL_DC8_SCI_C 0x4U // SCI_C +#define SYSCTL_DC8_SCI_D 0x8U // SCI_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC9 register +// +//************************************************************************************************* +#define SYSCTL_DC9_SPI_A 0x1U // SPI_A +#define SYSCTL_DC9_SPI_B 0x2U // SPI_B +#define SYSCTL_DC9_SPI_C 0x4U // SPI_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC10 register +// +//************************************************************************************************* +#define SYSCTL_DC10_I2C_A 0x1U // I2C_A +#define SYSCTL_DC10_I2C_B 0x2U // I2C_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC11 register +// +//************************************************************************************************* +#define SYSCTL_DC11_CAN_A 0x1U // CAN_A +#define SYSCTL_DC11_CAN_B 0x2U // CAN_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC12 register +// +//************************************************************************************************* +#define SYSCTL_DC12_MCBSP_A 0x1U // McBSP_A +#define SYSCTL_DC12_MCBSP_B 0x2U // McBSP_B +#define SYSCTL_DC12_USB_A_S 16U +#define SYSCTL_DC12_USB_A_M 0x30000U // Decides the capability of the USB_A Module + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC13 register +// +//************************************************************************************************* +#define SYSCTL_DC13_UPP_A 0x1U // uPP_A + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC14 register +// +//************************************************************************************************* +#define SYSCTL_DC14_ADC_A 0x1U // ADC_A +#define SYSCTL_DC14_ADC_B 0x2U // ADC_B +#define SYSCTL_DC14_ADC_C 0x4U // ADC_C +#define SYSCTL_DC14_ADC_D 0x8U // ADC_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC15 register +// +//************************************************************************************************* +#define SYSCTL_DC15_CMPSS1 0x1U // CMPSS1 +#define SYSCTL_DC15_CMPSS2 0x2U // CMPSS2 +#define SYSCTL_DC15_CMPSS3 0x4U // CMPSS3 +#define SYSCTL_DC15_CMPSS4 0x8U // CMPSS4 +#define SYSCTL_DC15_CMPSS5 0x10U // CMPSS5 +#define SYSCTL_DC15_CMPSS6 0x20U // CMPSS6 +#define SYSCTL_DC15_CMPSS7 0x40U // CMPSS7 +#define SYSCTL_DC15_CMPSS8 0x80U // CMPSS8 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC17 register +// +//************************************************************************************************* +#define SYSCTL_DC17_DAC_A 0x10000U // Buffered-DAC_A +#define SYSCTL_DC17_DAC_B 0x20000U // Buffered-DAC_B +#define SYSCTL_DC17_DAC_C 0x40000U // Buffered-DAC_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC18 register +// +//************************************************************************************************* +#define SYSCTL_DC18_LS0_1 0x1U // LS0_1 +#define SYSCTL_DC18_LS1_1 0x2U // LS1_1 +#define SYSCTL_DC18_LS2_1 0x4U // LS2_1 +#define SYSCTL_DC18_LS3_1 0x8U // LS3_1 +#define SYSCTL_DC18_LS4_1 0x10U // LS4_1 +#define SYSCTL_DC18_LS5_1 0x20U // LS5_1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC19 register +// +//************************************************************************************************* +#define SYSCTL_DC19_LS0_2 0x1U // LS0_2 +#define SYSCTL_DC19_LS1_2 0x2U // LS1_2 +#define SYSCTL_DC19_LS2_2 0x4U // LS2_2 +#define SYSCTL_DC19_LS3_2 0x8U // LS3_2 +#define SYSCTL_DC19_LS4_2 0x10U // LS4_2 +#define SYSCTL_DC19_LS5_2 0x20U // LS5_2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC20 register +// +//************************************************************************************************* +#define SYSCTL_DC20_GS0 0x1U // GS0 +#define SYSCTL_DC20_GS1 0x2U // GS1 +#define SYSCTL_DC20_GS2 0x4U // GS2 +#define SYSCTL_DC20_GS3 0x8U // GS3 +#define SYSCTL_DC20_GS4 0x10U // GS4 +#define SYSCTL_DC20_GS5 0x20U // GS5 +#define SYSCTL_DC20_GS6 0x40U // GS6 +#define SYSCTL_DC20_GS7 0x80U // GS7 +#define SYSCTL_DC20_GS8 0x100U // GS8 +#define SYSCTL_DC20_GS9 0x200U // GS9 +#define SYSCTL_DC20_GS10 0x400U // GS10 +#define SYSCTL_DC20_GS11 0x800U // GS11 +#define SYSCTL_DC20_GS12 0x1000U // GS12 +#define SYSCTL_DC20_GS13 0x2000U // GS13 +#define SYSCTL_DC20_GS14 0x4000U // GS14 +#define SYSCTL_DC20_GS15 0x8000U // GS15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCNF1 register +// +//************************************************************************************************* +#define SYSCTL_PERCNF1_ADC_A_MODE 0x1U // ADC_A mode setting bit +#define SYSCTL_PERCNF1_ADC_B_MODE 0x2U // ADC_B mode setting bit +#define SYSCTL_PERCNF1_ADC_C_MODE 0x4U // ADC_C mode setting bit +#define SYSCTL_PERCNF1_ADC_D_MODE 0x8U // ADC_D mode setting bit +#define SYSCTL_PERCNF1_USB_A_PHY 0x10000U // USB_A_PHY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FUSEERR register +// +//************************************************************************************************* +#define SYSCTL_FUSEERR_ALERR_S 0U +#define SYSCTL_FUSEERR_ALERR_M 0x1FU // Efuse Autoload Error Status +#define SYSCTL_FUSEERR_ERR 0x20U // Efuse Self Test Error Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES0 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES0_CPU1_CLA1 0x1U // CPU1_CLA1 software reset bit +#define SYSCTL_SOFTPRES0_CPU2_CLA1 0x4U // CPU2_CLA1 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES1 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES1_EMIF1 0x1U // EMIF1 software reset bit +#define SYSCTL_SOFTPRES1_EMIF2 0x2U // EMIF2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES2 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES2_EPWM1 0x1U // EPWM1 software reset bit +#define SYSCTL_SOFTPRES2_EPWM2 0x2U // EPWM2 software reset bit +#define SYSCTL_SOFTPRES2_EPWM3 0x4U // EPWM3 software reset bit +#define SYSCTL_SOFTPRES2_EPWM4 0x8U // EPWM4 software reset bit +#define SYSCTL_SOFTPRES2_EPWM5 0x10U // EPWM5 software reset bit +#define SYSCTL_SOFTPRES2_EPWM6 0x20U // EPWM6 software reset bit +#define SYSCTL_SOFTPRES2_EPWM7 0x40U // EPWM7 software reset bit +#define SYSCTL_SOFTPRES2_EPWM8 0x80U // EPWM8 software reset bit +#define SYSCTL_SOFTPRES2_EPWM9 0x100U // EPWM9 software reset bit +#define SYSCTL_SOFTPRES2_EPWM10 0x200U // EPWM10 software reset bit +#define SYSCTL_SOFTPRES2_EPWM11 0x400U // EPWM11 software reset bit +#define SYSCTL_SOFTPRES2_EPWM12 0x800U // EPWM12 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES3 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES3_ECAP1 0x1U // ECAP1 software reset bit +#define SYSCTL_SOFTPRES3_ECAP2 0x2U // ECAP2 software reset bit +#define SYSCTL_SOFTPRES3_ECAP3 0x4U // ECAP3 software reset bit +#define SYSCTL_SOFTPRES3_ECAP4 0x8U // ECAP4 software reset bit +#define SYSCTL_SOFTPRES3_ECAP5 0x10U // ECAP5 software reset bit +#define SYSCTL_SOFTPRES3_ECAP6 0x20U // ECAP6 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES4 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES4_EQEP1 0x1U // EQEP1 software reset bit +#define SYSCTL_SOFTPRES4_EQEP2 0x2U // EQEP2 software reset bit +#define SYSCTL_SOFTPRES4_EQEP3 0x4U // EQEP3 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES6 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES6_SD1 0x1U // SD1 software reset bit +#define SYSCTL_SOFTPRES6_SD2 0x2U // SD2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES7 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES7_SCI_A 0x1U // SCI_A software reset bit +#define SYSCTL_SOFTPRES7_SCI_B 0x2U // SCI_B software reset bit +#define SYSCTL_SOFTPRES7_SCI_C 0x4U // SCI_C software reset bit +#define SYSCTL_SOFTPRES7_SCI_D 0x8U // SCI_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES8 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES8_SPI_A 0x1U // SPI_A software reset bit +#define SYSCTL_SOFTPRES8_SPI_B 0x2U // SPI_B software reset bit +#define SYSCTL_SOFTPRES8_SPI_C 0x4U // SPI_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES9 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES9_I2C_A 0x1U // I2C_A software reset bit +#define SYSCTL_SOFTPRES9_I2C_B 0x2U // I2C_B software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES11 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES11_MCBSP_A 0x1U // McBSP_A software reset bit +#define SYSCTL_SOFTPRES11_MCBSP_B 0x2U // McBSP_B software reset bit +#define SYSCTL_SOFTPRES11_USB_A 0x10000U // USB_A software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES13 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES13_ADC_A 0x1U // ADC_A software reset bit +#define SYSCTL_SOFTPRES13_ADC_B 0x2U // ADC_B software reset bit +#define SYSCTL_SOFTPRES13_ADC_C 0x4U // ADC_C software reset bit +#define SYSCTL_SOFTPRES13_ADC_D 0x8U // ADC_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES14 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES14_CMPSS1 0x1U // CMPSS1 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS2 0x2U // CMPSS2 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS3 0x4U // CMPSS3 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS4 0x8U // CMPSS4 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS5 0x10U // CMPSS5 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS6 0x20U // CMPSS6 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS7 0x40U // CMPSS7 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS8 0x80U // CMPSS8 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES16 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES16_DAC_A 0x10000U // Buffered_DAC_A software reset bit +#define SYSCTL_SOFTPRES16_DAC_B 0x20000U // Buffered_DAC_B software reset bit +#define SYSCTL_SOFTPRES16_DAC_C 0x40000U // Buffered_DAC_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL0 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL0_EPWM1 0x1U // EPWM1 CPU select bit +#define SYSCTL_CPUSEL0_EPWM2 0x2U // EPWM2 CPU select bit +#define SYSCTL_CPUSEL0_EPWM3 0x4U // EPWM3 CPU select bit +#define SYSCTL_CPUSEL0_EPWM4 0x8U // EPWM4 CPU select bit +#define SYSCTL_CPUSEL0_EPWM5 0x10U // EPWM5 CPU select bit +#define SYSCTL_CPUSEL0_EPWM6 0x20U // EPWM6 CPU select bit +#define SYSCTL_CPUSEL0_EPWM7 0x40U // EPWM7 CPU select bit +#define SYSCTL_CPUSEL0_EPWM8 0x80U // EPWM8 CPU select bit +#define SYSCTL_CPUSEL0_EPWM9 0x100U // EPWM9 CPU select bit +#define SYSCTL_CPUSEL0_EPWM10 0x200U // EPWM10 CPU select bit +#define SYSCTL_CPUSEL0_EPWM11 0x400U // EPWM11 CPU select bit +#define SYSCTL_CPUSEL0_EPWM12 0x800U // EPWM12 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL1_ECAP1 0x1U // ECAP1 CPU select bit +#define SYSCTL_CPUSEL1_ECAP2 0x2U // ECAP2 CPU select bit +#define SYSCTL_CPUSEL1_ECAP3 0x4U // ECAP3 CPU select bit +#define SYSCTL_CPUSEL1_ECAP4 0x8U // ECAP4 CPU select bit +#define SYSCTL_CPUSEL1_ECAP5 0x10U // ECAP5 CPU select bit +#define SYSCTL_CPUSEL1_ECAP6 0x20U // ECAP6 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL2_EQEP1 0x1U // EQEP1 CPU select bit +#define SYSCTL_CPUSEL2_EQEP2 0x2U // EQEP2 CPU select bit +#define SYSCTL_CPUSEL2_EQEP3 0x4U // EQEP3 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL4 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL4_SD1 0x1U // SD1 CPU select bit +#define SYSCTL_CPUSEL4_SD2 0x2U // SD2 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL5 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL5_SCI_A 0x1U // SCI_A CPU select bit +#define SYSCTL_CPUSEL5_SCI_B 0x2U // SCI_B CPU select bit +#define SYSCTL_CPUSEL5_SCI_C 0x4U // SCI_C CPU select bit +#define SYSCTL_CPUSEL5_SCI_D 0x8U // SCI_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL6 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL6_SPI_A 0x1U // SPI_A CPU select bit +#define SYSCTL_CPUSEL6_SPI_B 0x2U // SPI_B CPU select bit +#define SYSCTL_CPUSEL6_SPI_C 0x4U // SPI_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL7 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL7_I2C_A 0x1U // I2C_A CPU select bit +#define SYSCTL_CPUSEL7_I2C_B 0x2U // I2C_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL8 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL8_CAN_A 0x1U // CAN_A CPU select bit +#define SYSCTL_CPUSEL8_CAN_B 0x2U // CAN_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL9 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL9_MCBSP_A 0x1U // McBSP_A CPU select bit +#define SYSCTL_CPUSEL9_MCBSP_B 0x2U // McBSP_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL11 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL11_ADC_A 0x1U // ADC_A CPU select bit +#define SYSCTL_CPUSEL11_ADC_B 0x2U // ADC_B CPU select bit +#define SYSCTL_CPUSEL11_ADC_C 0x4U // ADC_C CPU select bit +#define SYSCTL_CPUSEL11_ADC_D 0x8U // ADC_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL12 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL12_CMPSS1 0x1U // CMPSS1 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS2 0x2U // CMPSS2 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS3 0x4U // CMPSS3 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS4 0x8U // CMPSS4 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS5 0x10U // CMPSS5 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS6 0x20U // CMPSS6 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS7 0x40U // CMPSS7 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS8 0x80U // CMPSS8 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL14 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL14_DAC_A 0x10000U // Buffered_DAC_A CPU select bit +#define SYSCTL_CPUSEL14_DAC_B 0x20000U // Buffered_DAC_B CPU select bit +#define SYSCTL_CPUSEL14_DAC_C 0x40000U // Buffered_DAC_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPU2RESCTL register +// +//************************************************************************************************* +#define SYSCTL_CPU2RESCTL_RESET 0x1U // CPU2 Reset Control bit +#define SYSCTL_CPU2RESCTL_KEY_S 16U +#define SYSCTL_CPU2RESCTL_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RSTSTAT register +// +//************************************************************************************************* +#define SYSCTL_RSTSTAT_CPU2RES 0x1U // CPU2 Reset Status bit +#define SYSCTL_RSTSTAT_CPU2NMIWDRST 0x2U // Indicates whether a CPU2.NMIWD reset was issued + // to CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST0 0x4U // Indicates whether a HWBIST reset was issued to + // CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST1 0x8U // Indicates whether a HWBIST reset was issued to + // CPU2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMSTAT register +// +//************************************************************************************************* +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_S 0U +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_M 0x3U // CPU2 LPM Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSDBGCTL register +// +//************************************************************************************************* +#define SYSCTL_SYSDBGCTL_BIT_0 0x1U // Used in PLL startup. Only reset by POR. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSEM register +// +//************************************************************************************************* +#define SYSCTL_CLKSEM_SEM_S 0U +#define SYSCTL_CLKSEM_SEM_M 0x3U // Semaphore for CLKCFG Ownership by CPU1 or CPU2 +#define SYSCTL_CLKSEM_KEY_S 16U +#define SYSCTL_CLKSEM_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL1 0x1U // Lock bit for CLKSRCCTL1 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL2 0x2U // Lock bit for CLKSRCCTL2 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL3 0x4U // Lock bit for CLKSRCCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL1 0x8U // Lock bit for SYSPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL2 0x10U // Lock bit for SYSPLLCTL2 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL3 0x20U // Lock bit for SYSPLLCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLMULT 0x40U // Lock bit for SYSPLLMULT register +#define SYSCTL_CLKCFGLOCK1_AUXPLLCTL1 0x80U // Lock bit for AUXPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_AUXPLLMULT 0x400U // Lock bit for AUXPLLMULT register +#define SYSCTL_CLKCFGLOCK1_SYSCLKDIVSEL 0x800U // Lock bit for SYSCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_AUXCLKDIVSEL 0x1000U // Lock bit for AUXCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_PERCLKDIVSEL 0x2000U // Lock bit for PERCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_LOSPCP 0x8000U // Lock bit for LOSPCP register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL1 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M 0x3U // OSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL1_INTOSC2OFF 0x8U // Internal Oscillator 2 Off Bit +#define SYSCTL_CLKSRCCTL1_XTALOFF 0x10U // Crystal (External) Oscillator Off Bit +#define SYSCTL_CLKSRCCTL1_WDHALTI 0x20U // Watchdog HALT Mode Ignore Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL2 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M 0x3U // AUXOSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_S 2U +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_M 0xCU // CANA Bit Clock Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S 4U +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M 0x30U // CANB Bit Clock Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL3 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_S 0U +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M 0x7U // XCLKOUT Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLCTL1_PLLEN 0x1U // SYSPLL enable/disable bit +#define SYSCTL_SYSPLLCTL1_PLLCLKEN 0x2U // SYSPLL bypassed or included in the PLLSYSCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLMULT_IMULT_S 0U +#define SYSCTL_SYSPLLMULT_IMULT_M 0x7FU // SYSPLL Integer Multiplier +#define SYSCTL_SYSPLLMULT_FMULT_S 8U +#define SYSCTL_SYSPLLMULT_FMULT_M 0x300U // SYSPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLSTS_LOCKS 0x1U // SYSPLL Lock Status Bit +#define SYSCTL_SYSPLLSTS_SLIPS 0x2U // SYSPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLCTL1_PLLEN 0x1U // AUXPLL enable/disable bit +#define SYSCTL_AUXPLLCTL1_PLLCLKEN 0x2U // AUXPLL bypassed or included in the AUXPLLCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLMULT_IMULT_S 0U +#define SYSCTL_AUXPLLMULT_IMULT_M 0x7FU // AUXPLL Integer Multiplier +#define SYSCTL_AUXPLLMULT_FMULT_S 8U +#define SYSCTL_AUXPLLMULT_FMULT_M 0x300U // AUXPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLSTS_LOCKS 0x1U // AUXPLL Lock Status Bit +#define SYSCTL_AUXPLLSTS_SLIPS 0x2U // AUXPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_S 0U +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M 0x3FU // PLLSYSCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_S 0U +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M 0x3U // AUXPLLCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_S 0U +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M 0x3U // EPWM Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV 0x10U // EMIF1 Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV 0x40U // EMIF2 Clock Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCLKOUTDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_S 0U +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M 0x3U // XCLKOUT Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOSPCP register +// +//************************************************************************************************* +#define SYSCTL_LOSPCP_LSPCLKDIV_S 0U +#define SYSCTL_LOSPCP_LSPCLKDIV_M 0x7U // LSPCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCDCR register +// +//************************************************************************************************* +#define SYSCTL_MCDCR_MCLKSTS 0x1U // Missing Clock Status Bit +#define SYSCTL_MCDCR_MCLKCLR 0x2U // Missing Clock Clear Bit +#define SYSCTL_MCDCR_MCLKOFF 0x4U // Missing Clock Detect Off Bit +#define SYSCTL_MCDCR_OSCOFF 0x8U // Oscillator Clock Off Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the X1CNT register +// +//************************************************************************************************* +#define SYSCTL_X1CNT_X1CNT_S 0U +#define SYSCTL_X1CNT_X1CNT_M 0x3FFU // X1 Counter + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSYSLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSYSLOCK1_HIBBOOTMODE 0x1U // Lock bit for HIBBOOTMODE register +#define SYSCTL_CPUSYSLOCK1_IORESTOREADDR 0x2U // Lock bit for IORESTOREADDR Register +#define SYSCTL_CPUSYSLOCK1_PIEVERRADDR 0x4U // Lock bit for PIEVERRADDR Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR0 0x8U // Lock bit for PCLKCR0 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR1 0x10U // Lock bit for PCLKCR1 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR2 0x20U // Lock bit for PCLKCR2 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR3 0x40U // Lock bit for PCLKCR3 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR4 0x80U // Lock bit for PCLKCR4 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR5 0x100U // Lock bit for PCLKCR5 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR6 0x200U // Lock bit for PCLKCR6 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR7 0x400U // Lock bit for PCLKCR7 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR8 0x800U // Lock bit for PCLKCR8 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR9 0x1000U // Lock bit for PCLKCR9 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR10 0x2000U // Lock bit for PCLKCR10 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR11 0x4000U // Lock bit for PCLKCR11 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR12 0x8000U // Lock bit for PCLKCR12 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR13 0x10000U // Lock bit for PCLKCR13 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR14 0x20000U // Lock bit for PCLKCR14 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR15 0x40000U // Lock bit for PCLKCR15 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR16 0x80000U // Lock bit for PCLKCR16 Register +#define SYSCTL_CPUSYSLOCK1_SECMSEL 0x100000U // Lock bit for SECMSEL Register +#define SYSCTL_CPUSYSLOCK1_LPMCR 0x200000U // Lock bit for LPMCR Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL0 0x400000U // Lock bit for GPIOLPMSEL0 Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL1 0x800000U // Lock bit for GPIOLPMSEL1 Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IORESTOREADDR register +// +//************************************************************************************************* +#define SYSCTL_IORESTOREADDR_ADDR_S 0U +#define SYSCTL_IORESTOREADDR_ADDR_M 0x3FFFFFU // restoreIO() routine address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEVERRADDR register +// +//************************************************************************************************* +#define SYSCTL_PIEVERRADDR_ADDR_S 0U +#define SYSCTL_PIEVERRADDR_ADDR_M 0x3FFFFFU // PIE Vector Fetch Error Handler Routine Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR0 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR0_CLA1 0x1U // CLA1 Clock Enable Bit +#define SYSCTL_PCLKCR0_DMA 0x4U // DMA Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER0 0x8U // CPUTIMER0 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER1 0x10U // CPUTIMER1 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER2 0x20U // CPUTIMER2 Clock Enable bit +#define SYSCTL_PCLKCR0_HRPWM 0x10000U // HRPWM Clock Enable Bit +#define SYSCTL_PCLKCR0_TBCLKSYNC 0x40000U // EPWM Time Base Clock sync +#define SYSCTL_PCLKCR0_GTBCLKSYNC 0x80000U // EPWM Time Base Clock Global sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR1 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR1_EMIF1 0x1U // EMIF1 Clock Enable bit +#define SYSCTL_PCLKCR1_EMIF2 0x2U // EMIF2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR2 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR2_EPWM1 0x1U // EPWM1 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM2 0x2U // EPWM2 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM3 0x4U // EPWM3 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM4 0x8U // EPWM4 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM5 0x10U // EPWM5 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM6 0x20U // EPWM6 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM7 0x40U // EPWM7 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM8 0x80U // EPWM8 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM9 0x100U // EPWM9 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM10 0x200U // EPWM10 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM11 0x400U // EPWM11 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM12 0x800U // EPWM12 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR3 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR3_ECAP1 0x1U // ECAP1 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP2 0x2U // ECAP2 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP3 0x4U // ECAP3 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP4 0x8U // ECAP4 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP5 0x10U // ECAP5 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP6 0x20U // ECAP6 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR4 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR4_EQEP1 0x1U // EQEP1 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP2 0x2U // EQEP2 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP3 0x4U // EQEP3 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR6 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR6_SD1 0x1U // SD1 Clock Enable bit +#define SYSCTL_PCLKCR6_SD2 0x2U // SD2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR7 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR7_SCI_A 0x1U // SCI_A Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_B 0x2U // SCI_B Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_C 0x4U // SCI_C Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_D 0x8U // SCI_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR8 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR8_SPI_A 0x1U // SPI_A Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_B 0x2U // SPI_B Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_C 0x4U // SPI_C Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR9 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR9_I2C_A 0x1U // I2C_A Clock Enable bit +#define SYSCTL_PCLKCR9_I2C_B 0x2U // I2C_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR10 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR10_CAN_A 0x1U // CAN_A Clock Enable bit +#define SYSCTL_PCLKCR10_CAN_B 0x2U // CAN_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR11 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR11_MCBSP_A 0x1U // McBSP_A Clock Enable bit +#define SYSCTL_PCLKCR11_MCBSP_B 0x2U // McBSP_B Clock Enable bit +#define SYSCTL_PCLKCR11_USB_A 0x10000U // USB_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR12 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR12_UPP_A 0x1U // uPP_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR13 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR13_ADC_A 0x1U // ADC_A Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_B 0x2U // ADC_B Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_C 0x4U // ADC_C Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_D 0x8U // ADC_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR14 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR14_CMPSS1 0x1U // CMPSS1 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS2 0x2U // CMPSS2 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS3 0x4U // CMPSS3 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS4 0x8U // CMPSS4 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS5 0x10U // CMPSS5 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS6 0x20U // CMPSS6 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS7 0x40U // CMPSS7 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS8 0x80U // CMPSS8 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR16 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR16_DAC_A 0x10000U // Buffered_DAC_A Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_B 0x20000U // Buffered_DAC_B Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_C 0x40000U // Buffered_DAC_C Clock Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECMSEL register +// +//************************************************************************************************* +#define SYSCTL_SECMSEL_PF1SEL_S 0U +#define SYSCTL_SECMSEL_PF1SEL_M 0x3U // Secondary Master Select for VBUS32_1 Bridge +#define SYSCTL_SECMSEL_PF2SEL_S 2U +#define SYSCTL_SECMSEL_PF2SEL_M 0xCU // Secondary Master Select for VBUS32_2 Bridge + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMCR register +// +//************************************************************************************************* +#define SYSCTL_LPMCR_LPM_S 0U +#define SYSCTL_LPMCR_LPM_M 0x3U // Low Power Mode setting +#define SYSCTL_LPMCR_QUALSTDBY_S 2U +#define SYSCTL_LPMCR_QUALSTDBY_M 0xFCU // STANDBY Wakeup Pin Qualification Setting +#define SYSCTL_LPMCR_WDINTE 0x8000U // Enable for WDINT wakeup from STANDBY +#define SYSCTL_LPMCR_M0M1MODE_S 16U +#define SYSCTL_LPMCR_M0M1MODE_M 0x30000U // Configuration for M0 and M1 mode during HIB +#define SYSCTL_LPMCR_IOISODIS 0x80000000U // IO Isolation Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL0 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL0_GPIO0 0x1U // GPIO0 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO1 0x2U // GPIO1 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO2 0x4U // GPIO2 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO3 0x8U // GPIO3 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO4 0x10U // GPIO4 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO5 0x20U // GPIO5 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO6 0x40U // GPIO6 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO7 0x80U // GPIO7 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO8 0x100U // GPIO8 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO9 0x200U // GPIO9 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO10 0x400U // GPIO10 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO11 0x800U // GPIO11 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO12 0x1000U // GPIO12 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO13 0x2000U // GPIO13 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO14 0x4000U // GPIO14 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO15 0x8000U // GPIO15 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO16 0x10000U // GPIO16 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO17 0x20000U // GPIO17 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO18 0x40000U // GPIO18 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO19 0x80000U // GPIO19 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO20 0x100000U // GPIO20 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO21 0x200000U // GPIO21 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO22 0x400000U // GPIO22 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO23 0x800000U // GPIO23 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO24 0x1000000U // GPIO24 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO25 0x2000000U // GPIO25 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO26 0x4000000U // GPIO26 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO27 0x8000000U // GPIO27 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO28 0x10000000U // GPIO28 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO29 0x20000000U // GPIO29 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO30 0x40000000U // GPIO30 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO31 0x80000000U // GPIO31 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL1 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL1_GPIO32 0x1U // GPIO32 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO33 0x2U // GPIO33 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO34 0x4U // GPIO34 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO35 0x8U // GPIO35 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO36 0x10U // GPIO36 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO37 0x20U // GPIO37 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO38 0x40U // GPIO38 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO39 0x80U // GPIO39 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO40 0x100U // GPIO40 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO41 0x200U // GPIO41 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO42 0x400U // GPIO42 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO43 0x800U // GPIO43 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO44 0x1000U // GPIO44 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO45 0x2000U // GPIO45 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO46 0x4000U // GPIO46 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO47 0x8000U // GPIO47 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO48 0x10000U // GPIO48 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO49 0x20000U // GPIO49 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO50 0x40000U // GPIO50 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO51 0x80000U // GPIO51 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO52 0x100000U // GPIO52 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO53 0x200000U // GPIO53 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO54 0x400000U // GPIO54 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO55 0x800000U // GPIO55 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO56 0x1000000U // GPIO56 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO57 0x2000000U // GPIO57 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO58 0x4000000U // GPIO58 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO59 0x8000000U // GPIO59 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO60 0x10000000U // GPIO60 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO61 0x20000000U // GPIO61 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO62 0x40000000U // GPIO62 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO63 0x80000000U // GPIO63 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TMR2CLKCTL register +// +//************************************************************************************************* +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S 0U +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M 0x7U // CPU Timer 2 Clock Source Select Bit +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S 3U +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M 0x38U // CPU Timer 2 Clock Pre-Scale Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RESC register +// +//************************************************************************************************* +#define SYSCTL_RESC_POR 0x1U // POR Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN 0x2U // XRSn Reset Cause Indication Bit +#define SYSCTL_RESC_WDRSN 0x4U // WDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_NMIWDRSN 0x8U // NMIWDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_HWBISTN 0x20U // HWBISTn Reset Cause Indication Bit +#define SYSCTL_RESC_HIBRESETN 0x40U // HIBRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_SCCRESETN 0x100U // SCCRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN_PIN_STATUS 0x40000000U // XRSN Pin Status +#define SYSCTL_RESC_TRSTN_PIN_STATUS 0x80000000U // TRSTn Status + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCSR register +// +//************************************************************************************************* +#define SYSCTL_SCSR_WDOVERRIDE 0x1U // WD Override for WDDIS bit +#define SYSCTL_SCSR_WDENINT 0x2U // WD Interrupt Enable +#define SYSCTL_SCSR_WDINTS 0x4U // WD Interrupt Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCNTR register +// +//************************************************************************************************* +#define SYSCTL_WDCNTR_WDCNTR_S 0U +#define SYSCTL_WDCNTR_WDCNTR_M 0xFFU // WD Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDKEY register +// +//************************************************************************************************* +#define SYSCTL_WDKEY_WDKEY_S 0U +#define SYSCTL_WDKEY_WDKEY_M 0xFFU // WD KEY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCR register +// +//************************************************************************************************* +#define SYSCTL_WDCR_WDPS_S 0U +#define SYSCTL_WDCR_WDPS_M 0x7U // WD Clock Prescalar +#define SYSCTL_WDCR_WDCHK_S 3U +#define SYSCTL_WDCR_WDCHK_M 0x38U // WD Check Bits +#define SYSCTL_WDCR_WDDIS 0x40U // WD Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDWCR register +// +//************************************************************************************************* +#define SYSCTL_WDWCR_MIN_S 0U +#define SYSCTL_WDWCR_MIN_M 0xFFU // WD Min Threshold setting for Windowed Watchdog + // functionality +#define SYSCTL_WDWCR_FIRSTKEY 0x100U // First Key Detect Flag + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL1 0x1U // CLA1TASKSRCSEL1 Register Lock bit +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL2 0x2U // CLA1TASKSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL1 0x1U // DMACHSRCSEL1 Register Lock bit +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL2 0x2U // DMACHSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_S 0U +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_M 0xFFU // Selects the Trigger Source for TASK1 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_S 8U +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_M 0xFF00U // Selects the Trigger Source for TASK2 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_S 16U +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_M 0xFF0000U // Selects the Trigger Source for TASK3 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_S 24U +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_M 0xFF000000U // Selects the Trigger Source for TASK4 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_S 0U +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_M 0xFFU // Selects the Trigger Source for TASK5 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_S 8U +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_M 0xFF00U // Selects the Trigger Source for TASK6 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_S 16U +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_M 0xFF0000U // Selects the Trigger Source for TASK7 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_S 24U +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_M 0xFF000000U // Selects the Trigger Source for TASK8 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL1_CH1_S 0U +#define SYSCTL_DMACHSRCSEL1_CH1_M 0xFFU // Selects the Trigger and Sync Source CH1 of DMA +#define SYSCTL_DMACHSRCSEL1_CH2_S 8U +#define SYSCTL_DMACHSRCSEL1_CH2_M 0xFF00U // Selects the Trigger and Sync Source CH2 of DMA +#define SYSCTL_DMACHSRCSEL1_CH3_S 16U +#define SYSCTL_DMACHSRCSEL1_CH3_M 0xFF0000U // Selects the Trigger and Sync Source CH3 of DMA +#define SYSCTL_DMACHSRCSEL1_CH4_S 24U +#define SYSCTL_DMACHSRCSEL1_CH4_M 0xFF000000U // Selects the Trigger and Sync Source CH4 of DMA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL2_CH5_S 0U +#define SYSCTL_DMACHSRCSEL2_CH5_M 0xFFU // Selects the Trigger and Sync Source CH5 of DMA +#define SYSCTL_DMACHSRCSEL2_CH6_S 8U +#define SYSCTL_DMACHSRCSEL2_CH6_M 0xFF00U // Selects the Trigger and Sync Source CH6 of DMA + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSELECT register +// +//************************************************************************************************* +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_S 0U +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_M 0x7U // Selects Sync Input Source for EPWM4 +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_S 3U +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_M 0x38U // Selects Sync Input Source for EPWM7 +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_S 6U +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_M 0x1C0U // Selects Sync Input Source for EPWM10 +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_S 9U +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_M 0xE00U // Selects Sync Input Source for ECAP1 +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_S 12U +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_M 0x7000U // Selects Sync Input Source for ECAP4 +#define SYSCTL_SYNCSELECT_SYNCOUT_S 27U +#define SYSCTL_SYNCSELECT_SYNCOUT_M 0x18000000U // Select Syncout Source + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOUTSELECT register +// +//************************************************************************************************* +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCAEN 0x1U // PWM1SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCAEN 0x2U // PWM2SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCAEN 0x4U // PWM3SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCAEN 0x8U // PWM4SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCAEN 0x10U // PWM5SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCAEN 0x20U // PWM6SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCAEN 0x40U // PWM7SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCAEN 0x80U // PWM8SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCAEN 0x100U // PWM9SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCAEN 0x200U // PWM10SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCAEN 0x400U // PWM11SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCAEN 0x800U // PWM12SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCBEN 0x10000U // PWM1SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCBEN 0x20000U // PWM2SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCBEN 0x40000U // PWM3SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCBEN 0x80000U // PWM4SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCBEN 0x100000U // PWM5SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCBEN 0x200000U // PWM6SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCBEN 0x400000U // PWM7SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCBEN 0x800000U // PWM8SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCBEN 0x1000000U // PWM9SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCBEN 0x2000000U // PWM10SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCBEN 0x4000000U // PWM11SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCBEN 0x8000000U // PWM12SOCBEN Enable for ADCSOCBO + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSOCLOCK register +// +//************************************************************************************************* +#define SYSCTL_SYNCSOCLOCK_SYNCSELECT 0x1U // SYNCSEL Register Lock bit +#define SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT 0x2U // ADCSOCOUTSELECT Register Lock bit + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_types.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_types.h new file mode 100644 index 0000000..8c1b32d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_types.h @@ -0,0 +1,166 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in driverlib functions. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_TYPES_H +#define HW_TYPES_H + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#if defined(__TMS320C28XX_CLA__) + #define HWREG(x) \ + (*((volatile uint32_t *)((uintptr_t)(x)))) + #define HWREGH(x) \ + (*((volatile uint16_t *)((uintptr_t)(x)))) +#else + #define HWREG(x) \ + (*((volatile uint32_t *)(x))) + #define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#endif + +#define HWREG_BP(x) \ + __byte_peripheral_32((uint32_t *)(x)) +#define HWREGB(x) \ + __byte((int *)(x),0) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_S_SUCCESS (0) +#define STATUS_E_FAILURE (-1) + +//***************************************************************************** +// +// Definition of 8 bit types for USB Driver code to maintain portability +// between byte and word addressable cores of C2000 Devices. +// +//***************************************************************************** +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//**************************************************************************** +// +// For checking NULL pointers +// +//**************************************************************************** +#ifndef NULL +#define NULL ((void *)0x0) +#endif + +//***************************************************************************** +// +// 32-bit & 64-bit float type +// +//***************************************************************************** +#ifndef C2000_IEEE754_TYPES +#define C2000_IEEE754_TYPES +#ifdef __TI_EABI__ +typedef float float32_t; +typedef double float64_t; +#else // TI COFF +typedef float float32_t; +typedef long double float64_t; +#endif // __TI_EABI__ +#endif // C2000_IEEE754_TYPES + + +//***************************************************************************** +// +// Emulated Bitbanded write +// +//***************************************************************************** +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) + +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) + +//***************************************************************************** +// +// Emulated Bitbanded read +// +//***************************************************************************** +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// These are provided to satisfy static analysis tools. The #ifndef is required +// because the '&' is for a C++-style reference, and although it is the correct +// prototype, it will not build in C code. +// +//***************************************************************************** +#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__)) +#else +extern int16_t &__byte(int16_t *array, uint16_t byte_index); +extern uint32_t &__byte_peripheral_32(uint32_t *x); +#endif + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +/* To fix Misra-C errors */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif // HW_TYPES_H diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_upp.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_upp.h new file mode 100644 index 0000000..9f73e9b --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_upp.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: hw_upp.h +// +// TITLE: Definitions for the UPP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_UPP_H +#define HW_UPP_H + +//************************************************************************************************* +// +// The following are defines for the UPP register offsets +// +//************************************************************************************************* +#define UPP_O_PID 0x0U // Peripheral ID Register +#define UPP_O_PERCTL 0x2U // Peripheral Control Register +#define UPP_O_CHCTL 0x8U // General Control Register +#define UPP_O_IFCFG 0xAU // Interface Configuration Register +#define UPP_O_IFIVAL 0xCU // Interface Idle Value Register +#define UPP_O_THCFG 0xEU // Threshold Configuration Register +#define UPP_O_RAWINTST 0x10U // Raw Interrupt Status Register +#define UPP_O_ENINTST 0x12U // Enable Interrupt Status Register +#define UPP_O_INTENSET 0x14U // Interrupt Enable Set Register +#define UPP_O_INTENCLR 0x16U // Interrupt Enable Clear Register +#define UPP_O_CHIDESC0 0x20U // DMA Channel I Descriptor 0 Register +#define UPP_O_CHIDESC1 0x22U // DMA Channel I Descriptor 1 Register +#define UPP_O_CHIDESC2 0x24U // DMA Channel I Descriptor 2 Register +#define UPP_O_CHIST0 0x28U // DMA Channel I Status 0 Register +#define UPP_O_CHIST1 0x2AU // DMA Channel I Status 1 Register +#define UPP_O_CHIST2 0x2CU // DMA Channel I Status 2 Register +#define UPP_O_CHQDESC0 0x30U // DMA Channel Q Descriptor 0 Register +#define UPP_O_CHQDESC1 0x32U // DMA Channel Q Descriptor 1 Register +#define UPP_O_CHQDESC2 0x34U // DMA Channel Q Descriptor 2 Register +#define UPP_O_CHQST0 0x38U // DMA Channel Q Status 0 Register +#define UPP_O_CHQST1 0x3AU // DMA Channel Q Status 1 Register +#define UPP_O_CHQST2 0x3CU // DMA Channel Q Status 2 Register +#define UPP_O_GINTEN 0x40U // Global Peripheral Interrupt Enable Register +#define UPP_O_GINTFLG 0x42U // Global Peripheral Interrupt Flag Register +#define UPP_O_GINTCLR 0x44U // Global Peripheral Interrupt Clear Register +#define UPP_O_DLYCTL 0x46U // IO clock data skew control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCTL register +// +//************************************************************************************************* +#define UPP_PERCTL_FREE 0x1U // Emulation control. +#define UPP_PERCTL_SOFT 0x2U // Emulation control. +#define UPP_PERCTL_RTEMU 0x4U // Realtime emulation control. +#define UPP_PERCTL_PEREN 0x8U // Peripheral Enable +#define UPP_PERCTL_SOFTRST 0x10U // Software Reset +#define UPP_PERCTL_DMAST 0x80U // DMA Burst transaction status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHCTL register +// +//************************************************************************************************* +#define UPP_CHCTL_MODE_S 0U +#define UPP_CHCTL_MODE_M 0x3U // Operating mode +#define UPP_CHCTL_SDRTXILA 0x8U // SDR TX Interleve mode +#define UPP_CHCTL_DEMUXA 0x10U // DDR de-multiplexing mode +#define UPP_CHCTL_DRA 0x10000U // Data rate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFCFG register +// +//************************************************************************************************* +#define UPP_IFCFG_STARTPOLA 0x1U // Polarity of START(SELECT) signal +#define UPP_IFCFG_ENAPOLA 0x2U // Polarity of ENABLE(WRITE) signal +#define UPP_IFCFG_WAITPOLA 0x4U // Polarity of WAIT signal. +#define UPP_IFCFG_STARTA 0x8U // Enable Usage of START (SELECT) signal +#define UPP_IFCFG_ENAA 0x10U // Enable Usage of ENABLE (WRITE) signal +#define UPP_IFCFG_WAITA 0x20U // Enable Usage of WAIT signal +#define UPP_IFCFG_CLKDIVA_S 8U +#define UPP_IFCFG_CLKDIVA_M 0xF00U // Clock divider for tx mode +#define UPP_IFCFG_CLKINVA 0x1000U // Clock inversion +#define UPP_IFCFG_TRISENA 0x2000U // Pin Tri-state Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFIVAL register +// +//************************************************************************************************* +#define UPP_IFIVAL_VALA_S 0U +#define UPP_IFIVAL_VALA_M 0x1FFU // Idle Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the THCFG register +// +//************************************************************************************************* +#define UPP_THCFG_RDSIZEI_S 0U +#define UPP_THCFG_RDSIZEI_M 0x3U // DMA Read Threshold for DMA Channel I +#define UPP_THCFG_RDSIZEQ_S 8U +#define UPP_THCFG_RDSIZEQ_M 0x300U // DMA Read Threshold for DMA Channel Q +#define UPP_THCFG_TXSIZEA_S 16U +#define UPP_THCFG_TXSIZEA_M 0x30000U // I/O Transmit Threshold Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAWINTST register +// +//************************************************************************************************* +#define UPP_RAWINTST_DPEI 0x1U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEI 0x2U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWI 0x8U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLI 0x10U // Interrupt raw status for end-of-line condition +#define UPP_RAWINTST_DPEQ 0x100U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEQ 0x200U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWQ 0x800U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLQ 0x1000U // Interrupt raw status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ENINTST register +// +//************************************************************************************************* +#define UPP_ENINTST_DPEI 0x1U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEI 0x2U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWI 0x8U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLI 0x10U // Interrupt enable status for end-of-line condition +#define UPP_ENINTST_DPEQ 0x100U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEQ 0x200U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWQ 0x800U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLQ 0x1000U // Interrupt enable status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENSET register +// +//************************************************************************************************* +#define UPP_INTENSET_DPEI 0x1U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEI 0x2U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWI 0x8U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLI 0x10U // Interrupt enable for end-of-line condition +#define UPP_INTENSET_DPEQ 0x100U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEQ 0x200U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWQ 0x800U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLQ 0x1000U // Interrupt enable for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENCLR register +// +//************************************************************************************************* +#define UPP_INTENCLR_DPEI 0x1U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEI 0x2U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWI 0x8U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLI 0x10U // Interrupt clear for end-of-line condition +#define UPP_INTENCLR_DPEQ 0x100U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEQ 0x200U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWQ 0x800U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLQ 0x1000U // Interrupt clear for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC1 register +// +//************************************************************************************************* +#define UPP_CHIDESC1_BCNT_S 0U +#define UPP_CHIDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel I + // transfer. +#define UPP_CHIDESC1_LCNT_S 16U +#define UPP_CHIDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel I + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC2 register +// +//************************************************************************************************* +#define UPP_CHIDESC2_LOFFSET_S 0U +#define UPP_CHIDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST1 register +// +//************************************************************************************************* +#define UPP_CHIST1_BCNT_S 0U +#define UPP_CHIST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHIST1_LCNT_S 16U +#define UPP_CHIST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST2 register +// +//************************************************************************************************* +#define UPP_CHIST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHIST2_PEND 0x2U // Status of DMA. +#define UPP_CHIST2_WM_S 4U +#define UPP_CHIST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel I tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC1 register +// +//************************************************************************************************* +#define UPP_CHQDESC1_BCNT_S 0U +#define UPP_CHQDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel Q + // transfer. +#define UPP_CHQDESC1_LCNT_S 16U +#define UPP_CHQDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel Q + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC2 register +// +//************************************************************************************************* +#define UPP_CHQDESC2_LOFFSET_S 0U +#define UPP_CHQDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST1 register +// +//************************************************************************************************* +#define UPP_CHQST1_BCNT_S 0U +#define UPP_CHQST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHQST1_LCNT_S 16U +#define UPP_CHQST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST2 register +// +//************************************************************************************************* +#define UPP_CHQST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHQST2_PEND 0x2U // Status of DMA. +#define UPP_CHQST2_WM_S 4U +#define UPP_CHQST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel Q tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTEN register +// +//************************************************************************************************* +#define UPP_GINTEN_GINTEN 0x1U // Global Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTFLG register +// +//************************************************************************************************* +#define UPP_GINTFLG_GINTFLG 0x1U // Global Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTCLR register +// +//************************************************************************************************* +#define UPP_GINTCLR_GINTCLR 0x1U // Global Interrupt Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DLYCTL register +// +//************************************************************************************************* +#define UPP_DLYCTL_DLYDIS 0x1U // IO dealy control disable. +#define UPP_DLYCTL_DLYCTL_S 1U +#define UPP_DLYCTL_DLYCTL_M 0x6U // IO delay control. + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_usb.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_usb.h new file mode 100644 index 0000000..27907eb --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_usb.h @@ -0,0 +1,4614 @@ +//########################################################################### +// +// FILE: hw_usb.h +// +// TITLE: Definitions for the USB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_USB_H +#define HW_USB_H + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif + +#endif // __HW_USB_H__ diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_xbar.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_xbar.h new file mode 100644 index 0000000..7869257 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_xbar.h @@ -0,0 +1,271 @@ +//########################################################################### +// +// FILE: hw_xbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XBAR_H +#define HW_XBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_FLG1 0x0U // X-Bar Input Flag Register 1 +#define XBAR_O_FLG2 0x2U // X-Bar Input Flag Register 2 +#define XBAR_O_FLG3 0x4U // X-Bar Input Flag Register 3 +#define XBAR_O_CLR1 0x8U // X-Bar Input Flag Clear Register 1 +#define XBAR_O_CLR2 0xAU // X-Bar Input Flag Clear Register 2 +#define XBAR_O_CLR3 0xCU // X-Bar Input Flag Clear Register 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG1 register +// +//************************************************************************************************* +#define XBAR_FLG1_CMPSS1_CTRIPL 0x1U // Input Flag for CMPSS1.CTRIPL Signal +#define XBAR_FLG1_CMPSS1_CTRIPH 0x2U // Input Flag for CMPSS1.CTRIPH Signal +#define XBAR_FLG1_CMPSS2_CTRIPL 0x4U // Input Flag for CMPSS2.CTRIPL Signal +#define XBAR_FLG1_CMPSS2_CTRIPH 0x8U // Input Flag for CMPSS2.CTRIPH Signal +#define XBAR_FLG1_CMPSS3_CTRIPL 0x10U // Input Flag for CMPSS3.CTRIPL Signal +#define XBAR_FLG1_CMPSS3_CTRIPH 0x20U // Input Flag for CMPSS3.CTRIPH Signal +#define XBAR_FLG1_CMPSS4_CTRIPL 0x40U // Input Flag for CMPSS4.CTRIPL Signal +#define XBAR_FLG1_CMPSS4_CTRIPH 0x80U // Input Flag for CMPSS4.CTRIPH Signal +#define XBAR_FLG1_CMPSS5_CTRIPL 0x100U // Input Flag for CMPSS5.CTRIPL Signal +#define XBAR_FLG1_CMPSS5_CTRIPH 0x200U // Input Flag for CMPSS5.CTRIPH Signal +#define XBAR_FLG1_CMPSS6_CTRIPL 0x400U // Input Flag for CMPSS6.CTRIPL Signal +#define XBAR_FLG1_CMPSS6_CTRIPH 0x800U // Input Flag for CMPSS6.CTRIPH Signal +#define XBAR_FLG1_CMPSS7_CTRIPL 0x1000U // Input Flag for CMPSS7.CTRIPL Signal +#define XBAR_FLG1_CMPSS7_CTRIPH 0x2000U // Input Flag for CMPSS7.CTRIPH Signal +#define XBAR_FLG1_CMPSS8_CTRIPL 0x4000U // Input Flag for CMPSS8.CTRIPL Signal +#define XBAR_FLG1_CMPSS8_CTRIPH 0x8000U // Input Flag for CMPSS8.CTRIPH Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag for CMPSS1.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag for CMPSS1.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag for CMPSS2.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag for CMPSS2.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag for CMPSS3.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag for CMPSS3.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag for CMPSS4.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag for CMPSS4.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag for CMPSS5.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag for CMPSS5.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag for CMPSS6.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag for CMPSS6.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag for CMPSS7.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag for CMPSS7.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag for CMPSS8.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG2 register +// +//************************************************************************************************* +#define XBAR_FLG2_INPUT1 0x1U // Input Flag for INPUT1 Signal +#define XBAR_FLG2_INPUT2 0x2U // Input Flag for INPUT2 Signal +#define XBAR_FLG2_INPUT3 0x4U // Input Flag for INPUT3 Signal +#define XBAR_FLG2_INPUT4 0x8U // Input Flag for INPUT4 Signal +#define XBAR_FLG2_INPUT5 0x10U // Input Flag for INPUT5 Signal +#define XBAR_FLG2_INPUT6 0x20U // Input Flag for INPUT6 Signal +#define XBAR_FLG2_ADCSOCAO 0x40U // Input Flag for ADCSOCAO Signal +#define XBAR_FLG2_ADCSOCBO 0x80U // Input Flag for ADCSOCBO Signal +#define XBAR_FLG2_CLB1_OUT4 0x100U // Input Flag for CLB1_OUT4 Signal +#define XBAR_FLG2_CLB1_OUT5 0x200U // Input Flag for CLB1_OUT5 Signal +#define XBAR_FLG2_CLB2_OUT4 0x400U // Input Flag for CLB2_OUT4 Signal +#define XBAR_FLG2_CLB2_OUT5 0x800U // Input Flag for CLB2_OUT5 Signal +#define XBAR_FLG2_CLB3_OUT4 0x1000U // Input Flag for CLB3_OUT4 Signal +#define XBAR_FLG2_CLB3_OUT5 0x2000U // Input Flag for CLB3_OUT5 Signal +#define XBAR_FLG2_CLB4_OUT4 0x4000U // Input Flag for CLB4_OUT4 Signal +#define XBAR_FLG2_CLB4_OUT5 0x8000U // Input Flag for CLB4_OUT5 Signal +#define XBAR_FLG2_ECAP1_OUT 0x10000U // Input Flag for ECAP1.OUT Signal +#define XBAR_FLG2_ECAP2_OUT 0x20000U // Input Flag for ECAP2.OUT Signal +#define XBAR_FLG2_ECAP3_OUT 0x40000U // Input Flag for ECAP3.OUT Signal +#define XBAR_FLG2_ECAP4_OUT 0x80000U // Input Flag for ECAP4.OUT Signal +#define XBAR_FLG2_ECAP5_OUT 0x100000U // Input Flag for ECAP5.OUT Signal +#define XBAR_FLG2_ECAP6_OUT 0x200000U // Input Flag for ECAP6.OUT Signal +#define XBAR_FLG2_EXTSYNCOUT 0x400000U // Input Flag for EXTSYNCOUT Signal +#define XBAR_FLG2_ADCAEVT1 0x800000U // Input Flag for ADCAEVT1 Signal +#define XBAR_FLG2_ADCAEVT2 0x1000000U // Input Flag for ADCAEVT2 Signal +#define XBAR_FLG2_ADCAEVT3 0x2000000U // Input Flag for ADCAEVT3 Signal +#define XBAR_FLG2_ADCAEVT4 0x4000000U // Input Flag for ADCAEVT4 Signal +#define XBAR_FLG2_ADCBEVT1 0x8000000U // Input Flag for ADCBEVT1 Signal +#define XBAR_FLG2_ADCBEVT2 0x10000000U // Input Flag for ADCBEVT2 Signal +#define XBAR_FLG2_ADCBEVT3 0x20000000U // Input Flag for ADCBEVT3 Signal +#define XBAR_FLG2_ADCBEVT4 0x40000000U // Input Flag for ADCBEVT4 Signal +#define XBAR_FLG2_ADCCEVT1 0x80000000U // Input Flag for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG3 register +// +//************************************************************************************************* +#define XBAR_FLG3_ADCCEVT2 0x1U // Input Flag for ADCCEVT2 Signal +#define XBAR_FLG3_ADCCEVT3 0x2U // Input Flag for ADCCEVT3 Signal +#define XBAR_FLG3_ADCCEVT4 0x4U // Input Flag for ADCCEVT4 Signal +#define XBAR_FLG3_ADCDEVT1 0x8U // Input Flag for ADCDEVT1 Signal +#define XBAR_FLG3_ADCDEVT2 0x10U // Input Flag for ADCDEVT2 Signal +#define XBAR_FLG3_ADCDEVT3 0x20U // Input Flag for ADCDEVT3 Signal +#define XBAR_FLG3_ADCDEVT4 0x40U // Input Flag for ADCDEVT4 Signal +#define XBAR_FLG3_SD1FLT1_COMPL 0x80U // Input Flag for SD1FLT1.COMPL Signal +#define XBAR_FLG3_SD1FLT1_COMPH 0x100U // Input Flag for SD1FLT1.COMPH Signal +#define XBAR_FLG3_SD1FLT2_COMPL 0x200U // Input Flag for SD1FLT2.COMPL Signal +#define XBAR_FLG3_SD1FLT2_COMPH 0x400U // Input Flag for SD1FLT2.COMPH Signal +#define XBAR_FLG3_SD1FLT3_COMPL 0x800U // Input Flag for SD1FLT3.COMPL Signal +#define XBAR_FLG3_SD1FLT3_COMPH 0x1000U // Input Flag for SD1FLT3.COMPH Signal +#define XBAR_FLG3_SD1FLT4_COMPL 0x2000U // Input Flag for SD1FLT4.COMPL Signal +#define XBAR_FLG3_SD1FLT4_COMPH 0x4000U // Input Flag for SD1FLT4.COMPH Signal +#define XBAR_FLG3_SD2FLT1_COMPL 0x8000U // Input Flag for SD2FLT1.COMPL Signal +#define XBAR_FLG3_SD2FLT1_COMPH 0x10000U // Input Flag for SD2FLT1.COMPH Signal +#define XBAR_FLG3_SD2FLT2_COMPL 0x20000U // Input Flag for SD2FLT2.COMPL Signal +#define XBAR_FLG3_SD2FLT2_COMPH 0x40000U // Input Flag for SD2FLT2.COMPH Signal +#define XBAR_FLG3_SD2FLT3_COMPL 0x80000U // Input Flag for SD2FLT3.COMPL Signal +#define XBAR_FLG3_SD2FLT3_COMPH 0x100000U // Input Flag for SD2FLT3.COMPH Signal +#define XBAR_FLG3_SD2FLT4_COMPL 0x200000U // Input Flag for SD2FLT4.COMPL Signal +#define XBAR_FLG3_SD2FLT4_COMPH 0x400000U // Input Flag for SD2FLT4.COMPH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR1 register +// +//************************************************************************************************* +#define XBAR_CLR1_CMPSS1_CTRIPL 0x1U // Input Flag Clear for CMPSS1.CTRIPL Signal +#define XBAR_CLR1_CMPSS1_CTRIPH 0x2U // Input Flag Clear for CMPSS1.CTRIPH Signal +#define XBAR_CLR1_CMPSS2_CTRIPL 0x4U // Input Flag Clear for CMPSS2.CTRIPL Signal +#define XBAR_CLR1_CMPSS2_CTRIPH 0x8U // Input Flag Clear for CMPSS2.CTRIPH Signal +#define XBAR_CLR1_CMPSS3_CTRIPL 0x10U // Input Flag Clear for CMPSS3.CTRIPL Signal +#define XBAR_CLR1_CMPSS3_CTRIPH 0x20U // Input Flag Clear for CMPSS3.CTRIPH Signal +#define XBAR_CLR1_CMPSS4_CTRIPL 0x40U // Input Flag Clear for CMPSS4.CTRIPL Signal +#define XBAR_CLR1_CMPSS4_CTRIPH 0x80U // Input Flag Clear for CMPSS4.CTRIPH Signal +#define XBAR_CLR1_CMPSS5_CTRIPL 0x100U // Input Flag Clear for CMPSS5.CTRIPL Signal +#define XBAR_CLR1_CMPSS5_CTRIPH 0x200U // Input Flag Clear for CMPSS5.CTRIPH Signal +#define XBAR_CLR1_CMPSS6_CTRIPL 0x400U // Input Flag Clear for CMPSS6.CTRIPL Signal +#define XBAR_CLR1_CMPSS6_CTRIPH 0x800U // Input Flag Clear for CMPSS6.CTRIPH Signal +#define XBAR_CLR1_CMPSS7_CTRIPL 0x1000U // Input Flag Clear for CMPSS7.CTRIPL Signal +#define XBAR_CLR1_CMPSS7_CTRIPH 0x2000U // Input Flag Clear for CMPSS7.CTRIPH Signal +#define XBAR_CLR1_CMPSS8_CTRIPL 0x4000U // Input Flag Clear for CMPSS8.CTRIPL Signal +#define XBAR_CLR1_CMPSS8_CTRIPH 0x8000U // Input Flag Clear for CMPSS8.CTRIPH Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag Clear for CMPSS1.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag Clear for CMPSS1.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag Clear for CMPSS2.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag Clear for CMPSS2.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag Clear for CMPSS3.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag Clear for CMPSS3.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag Clear for CMPSS4.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag Clear for CMPSS4.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag Clear for CMPSS5.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag Clear for CMPSS5.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag Clear for CMPSS6.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag Clear for CMPSS6.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag Clear for CMPSS7.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag Clear for CMPSS7.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag Clear for CMPSS8.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag Clear for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR2 register +// +//************************************************************************************************* +#define XBAR_CLR2_INPUT1 0x1U // Input Flag Clear for INPUT1 Signal +#define XBAR_CLR2_INPUT2 0x2U // Input Flag Clear for INPUT2 Signal +#define XBAR_CLR2_INPUT3 0x4U // Input Flag Clear for INPUT3 Signal +#define XBAR_CLR2_INPUT4 0x8U // Input Flag Clear for INPUT4 Signal +#define XBAR_CLR2_INPUT5 0x10U // Input Flag Clear for INPUT5 Signal +#define XBAR_CLR2_INPUT7 0x20U // Input Flag Clear for INPUT7 Signal +#define XBAR_CLR2_ADCSOCAO 0x40U // Input Flag Clear for ADCSOCAO Signal +#define XBAR_CLR2_ADCSOCBO 0x80U // Input Flag Clear for ADCSOCBO Signal +#define XBAR_CLR2_CLB1_OUT4 0x100U // Input Flag Clear for CLB1_OUT4 Signal +#define XBAR_CLR2_CLB1_OUT5 0x200U // Input Flag Clear for CLB1_OUT5 Signal +#define XBAR_CLR2_CLB2_OUT4 0x400U // Input Flag Clear for CLB2_OUT4 Signal +#define XBAR_CLR2_CLB2_OUT5 0x800U // Input Flag Clear for CLB2_OUT5 Signal +#define XBAR_CLR2_CLB3_OUT4 0x1000U // Input Flag Clear for CLB3_OUT4 Signal +#define XBAR_CLR2_CLB3_OUT5 0x2000U // Input Flag Clear for CLB3_OUT5 Signal +#define XBAR_CLR2_CLB4_OUT4 0x4000U // Input Flag Clear for CLB4_OUT4 Signal +#define XBAR_CLR2_CLB4_OUT5 0x8000U // Input Flag Clear for CLB4_OUT5 Signal +#define XBAR_CLR2_ECAP1_OUT 0x10000U // Input Flag Clear for ECAP1.OUT Signal +#define XBAR_CLR2_ECAP2_OUT 0x20000U // Input Flag Clear for ECAP2.OUT Signal +#define XBAR_CLR2_ECAP3_OUT 0x40000U // Input Flag Clear for ECAP3.OUT Signal +#define XBAR_CLR2_ECAP4_OUT 0x80000U // Input Flag Clear for ECAP4.OUT Signal +#define XBAR_CLR2_ECAP5_OUT 0x100000U // Input Flag Clear for ECAP5.OUT Signal +#define XBAR_CLR2_ECAP6_OUT 0x200000U // Input Flag Clear for ECAP6.OUT Signal +#define XBAR_CLR2_EXTSYNCOUT 0x400000U // Input Flag Clear for EXTSYNCOUT Signal +#define XBAR_CLR2_ADCAEVT1 0x800000U // Input Flag Clear for ADCAEVT1 Signal +#define XBAR_CLR2_ADCAEVT2 0x1000000U // Input Flag Clear for ADCAEVT2 Signal +#define XBAR_CLR2_ADCAEVT3 0x2000000U // Input Flag Clear for ADCAEVT3 Signal +#define XBAR_CLR2_ADCAEVT4 0x4000000U // Input Flag Clear for ADCAEVT4 Signal +#define XBAR_CLR2_ADCBEVT1 0x8000000U // Input Flag Clear for ADCBEVT1 Signal +#define XBAR_CLR2_ADCBEVT2 0x10000000U // Input Flag Clear for ADCBEVT2 Signal +#define XBAR_CLR2_ADCBEVT3 0x20000000U // Input Flag Clear for ADCBEVT3 Signal +#define XBAR_CLR2_ADCBEVT4 0x40000000U // Input Flag Clear for ADCBEVT4 Signal +#define XBAR_CLR2_ADCCEVT1 0x80000000U // Input Flag Clear for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR3 register +// +//************************************************************************************************* +#define XBAR_CLR3_ADCCEVT2 0x1U // Input Flag Clear for ADCCEVT2 Signal +#define XBAR_CLR3_ADCCEVT3 0x2U // Input Flag Clear for ADCCEVT3 Signal +#define XBAR_CLR3_ADCCEVT4 0x4U // Input Flag Clear for ADCCEVT4 Signal +#define XBAR_CLR3_ADCDEVT1 0x8U // Input Flag Clear for ADCDEVT1 Signal +#define XBAR_CLR3_ADCDEVT2 0x10U // Input Flag Clear for ADCDEVT2 Signal +#define XBAR_CLR3_ADCDEVT3 0x20U // Input Flag Clear for ADCDEVT3 Signal +#define XBAR_CLR3_ADCDEVT4 0x40U // Input Flag Clear for ADCDEVT4 Signal +#define XBAR_CLR3_SD1FLT1_COMPL 0x80U // Input Flag Clear for SD1FLT1.COMPL Signal +#define XBAR_CLR3_SD1FLT1_COMPH 0x100U // Input Flag Clear for SD1FLT1.COMPH Signal +#define XBAR_CLR3_SD1FLT2_COMPL 0x200U // Input Flag Clear for SD1FLT2.COMPL Signal +#define XBAR_CLR3_SD1FLT2_COMPH 0x400U // Input Flag Clear for SD1FLT2.COMPH Signal +#define XBAR_CLR3_SD1FLT3_COMPL 0x800U // Input Flag Clear for SD1FLT3.COMPL Signal +#define XBAR_CLR3_SD1FLT3_COMPH 0x1000U // Input Flag Clear for SD1FLT3.COMPH Signal +#define XBAR_CLR3_SD1FLT4_COMPL 0x2000U // Input Flag Clear for SD1FLT4.COMPL Signal +#define XBAR_CLR3_SD1FLT4_COMPH 0x4000U // Input Flag Clear for SD1FLT4.COMPH Signal +#define XBAR_CLR3_SD2FLT1_COMPL 0x8000U // Input Flag Clear for SD2FLT1.COMPL Signal +#define XBAR_CLR3_SD2FLT1_COMPH 0x10000U // Input Flag Clear for SD2FLT1.COMPH Signal +#define XBAR_CLR3_SD2FLT2_COMPL 0x20000U // Input Flag Clear for SD2FLT2.COMPL Signal +#define XBAR_CLR3_SD2FLT2_COMPH 0x40000U // Input Flag Clear for SD2FLT2.COMPH Signal +#define XBAR_CLR3_SD2FLT3_COMPL 0x80000U // Input Flag Clear for SD2FLT3.COMPL Signal +#define XBAR_CLR3_SD2FLT3_COMPH 0x100000U // Input Flag Clear for SD2FLT3.COMPH Signal +#define XBAR_CLR3_SD2FLT4_COMPL 0x200000U // Input Flag Clear for SD2FLT4.COMPL Signal +#define XBAR_CLR3_SD2FLT4_COMPH 0x400000U // Input Flag Clear for SD2FLT4.COMPH Signal + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/inc/hw_xint.h b/gpio_bitfield_cpu2/device/driverlib/inc/hw_xint.h new file mode 100644 index 0000000..677c2f9 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/inc/hw_xint.h @@ -0,0 +1,108 @@ +//########################################################################### +// +// FILE: hw_xint.h +// +// TITLE: Definitions for the XINT registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XINT_H +#define HW_XINT_H + +//************************************************************************************************* +// +// The following are defines for the XINT register offsets +// +//************************************************************************************************* +#define XINT_O_1CR 0x0U // XINT1 configuration register +#define XINT_O_2CR 0x1U // XINT2 configuration register +#define XINT_O_3CR 0x2U // XINT3 configuration register +#define XINT_O_4CR 0x3U // XINT4 configuration register +#define XINT_O_5CR 0x4U // XINT5 configuration register +#define XINT_O_1CTR 0x8U // XINT1 counter register +#define XINT_O_2CTR 0x9U // XINT2 counter register +#define XINT_O_3CTR 0xAU // XINT3 counter register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT1CR register +// +//************************************************************************************************* +#define XINT_1CR_ENABLE 0x1U // XINT1 Enable +#define XINT_1CR_POLARITY_S 2U +#define XINT_1CR_POLARITY_M 0xCU // XINT1 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT2CR register +// +//************************************************************************************************* +#define XINT_2CR_ENABLE 0x1U // XINT2 Enable +#define XINT_2CR_POLARITY_S 2U +#define XINT_2CR_POLARITY_M 0xCU // XINT2 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT3CR register +// +//************************************************************************************************* +#define XINT_3CR_ENABLE 0x1U // XINT3 Enable +#define XINT_3CR_POLARITY_S 2U +#define XINT_3CR_POLARITY_M 0xCU // XINT3 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT4CR register +// +//************************************************************************************************* +#define XINT_4CR_ENABLE 0x1U // XINT4 Enable +#define XINT_4CR_POLARITY_S 2U +#define XINT_4CR_POLARITY_M 0xCU // XINT4 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT5CR register +// +//************************************************************************************************* +#define XINT_5CR_ENABLE 0x1U // XINT5 Enable +#define XINT_5CR_POLARITY_S 2U +#define XINT_5CR_POLARITY_M 0xCU // XINT5 Polarity + + + +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/interrupt.c b/gpio_bitfield_cpu2/device/driverlib/interrupt.c new file mode 100644 index 0000000..4d628ce --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/interrupt.c @@ -0,0 +1,425 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Clears the IFR flag in the CPU. +//! +//! \param group specifies the interrupt group to be cleared. +//! +//! This function clears the IFR flag. This switch is needed because the +//! clearing of the IFR can only be done with a constant. +// +//***************************************************************************** +static void Interrupt_clearIFR(uint16_t group) +{ + switch(group) + { + case 0x0001U: + IFR &= ~(uint16_t)0x0001U; + break; + case 0x0002U: + IFR &= ~(uint16_t)0x0002U; + break; + case 0x0004U: + IFR &= ~(uint16_t)0x0004U; + break; + case 0x0008U: + IFR &= ~(uint16_t)0x0008U; + break; + case 0x0010U: + IFR &= ~(uint16_t)0x0010U; + break; + case 0x0020U: + IFR &= ~(uint16_t)0x0020U; + break; + case 0x0040U: + IFR &= ~(uint16_t)0x0040U; + break; + case 0x0080U: + IFR &= ~(uint16_t)0x0080U; + break; + case 0x0100U: + IFR &= ~(uint16_t)0x0100U; + break; + case 0x0200U: + IFR &= ~(uint16_t)0x0200U; + break; + case 0x0400U: + IFR &= ~(uint16_t)0x0400U; + break; + case 0x0800U: + IFR &= ~(uint16_t)0x0800U; + break; + case 0x1000U: + IFR &= ~(uint16_t)0x1000U; + break; + case 0x2000U: + IFR &= ~(uint16_t)0x2000U; + break; + case 0x4000U: + IFR &= ~(uint16_t)0x4000U; + break; + case 0x8000U: + IFR &= ~(uint16_t)0x8000U; + break; + default: + // + // Invalid group mask. + // + ASSERT((bool)false); + break; + } +} + +//***************************************************************************** +// +// Interrupt_initModule +// +//***************************************************************************** +void +Interrupt_initModule(void) +{ + // + // Disable and clear all interrupts at the CPU + // + (void)Interrupt_disableGlobal(); + IER = 0x0000U; + IFR = 0x0000U; + + // + // Clear all PIEIER registers + // + HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U; + + // + // Clear all PIEIFR registers + // + HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U; + + // + // Enable vector fetching from PIE block + // + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; + +} + +//***************************************************************************** +// +//! The default interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_defaultHandler(void) +{ + uint16_t pieVect; + uint16_t vectID; + + // + // Calculate the vector ID. If the vector is in the lower PIE, it's the + // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT) + // divided by two. + // + pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL); + vectID = (pieVect & 0xFEU) >> 1U; + + // + // If the vector is in the upper PIE, the vector ID is 128 or higher. + // + if(pieVect >= 0x0E00U) + { + vectID += 128U; + } + + // + // Something has gone wrong. An interrupt without a proper registered + // handler function has occurred. To help you debug the issue, local + // variable vectID contains the vector ID of the interrupt that occurred. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default illegal instruction trap interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_illegalOperationHandler(void) +{ + // + // Something has gone wrong. The CPU has tried to execute an illegal + // instruction, generating an illegal instruction trap (ITRAP). + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default non-maskable interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_nmiHandler(void) +{ + // + // A non-maskable interrupt has occurred, indicating that a hardware error + // has occurred in the system. You can use SysCtl_getNMIFlagStatus() to + // to read the NMIFLG register and determine what caused the NMI. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +// Interrupt_initVectorTable +// +//***************************************************************************** +void +Interrupt_initVectorTable(void) +{ + uint16_t i; + + EALLOW; + + // + // We skip the first three locations because they are initialized by Boot + // ROM with boot variables. + // + for(i = 3U; i < 224U; i++) + { + HWREG(PIEVECTTABLE_BASE + (2U * i)) = + (uint32_t)Interrupt_defaultHandler; + } + + // + // NMI and ITRAP get their own handlers. + // + HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) = + (uint32_t)Interrupt_nmiHandler; + HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) = + (uint32_t)Interrupt_illegalOperationHandler; + + EDIS; +} + +//***************************************************************************** +// +//Interrupt_enable +// +//***************************************************************************** +void +Interrupt_enable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + // + // Globally disable interrupts but save status + // + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |= + (uint16_t)1U << ((interruptNumber & 0xFFU) - 1U); + + // + // Enable PIE Group Interrupt + // + IER |= groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER |= (uint16_t)1U << (vectID - 1U); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} + +//***************************************************************************** +// +// Interrupt_disable +// +//***************************************************************************** +void +Interrupt_disable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + // + // Disable individual PIE interrupt + // + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &= + ~(1U << ((interruptNumber & 0xFFUL) - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR(groupMask); + + // + // Acknowledge any interrupts + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER &= ~((uint16_t)1U << (vectID - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR((uint16_t)1U << (vectID - 1U)); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} diff --git a/gpio_bitfield_cpu2/device/driverlib/interrupt.h b/gpio_bitfield_cpu2/device/driverlib/interrupt.h new file mode 100644 index 0000000..05a555a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/interrupt.h @@ -0,0 +1,497 @@ +//########################################################################### +// +// FILE: interrupt.h +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef INTERRUPT_H +#define INTERRUPT_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup interrupt_api Interrupt +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pie.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_enableInCPU() +// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter. +// +//***************************************************************************** +#define INTERRUPT_CPU_INT1 0x1U //!< CPU Interrupt Number 1 +#define INTERRUPT_CPU_INT2 0x2U //!< CPU Interrupt Number 2 +#define INTERRUPT_CPU_INT3 0x4U //!< CPU Interrupt Number 3 +#define INTERRUPT_CPU_INT4 0x8U //!< CPU Interrupt Number 4 +#define INTERRUPT_CPU_INT5 0x10U //!< CPU Interrupt Number 5 +#define INTERRUPT_CPU_INT6 0x20U //!< CPU Interrupt Number 6 +#define INTERRUPT_CPU_INT7 0x40U //!< CPU Interrupt Number 7 +#define INTERRUPT_CPU_INT8 0x80U //!< CPU Interrupt Number 8 +#define INTERRUPT_CPU_INT9 0x100U //!< CPU Interrupt Number 9 +#define INTERRUPT_CPU_INT10 0x200U //!< CPU Interrupt Number 10 +#define INTERRUPT_CPU_INT11 0x400U //!< CPU Interrupt Number 11 +#define INTERRUPT_CPU_INT12 0x800U //!< CPU Interrupt Number 12 +#define INTERRUPT_CPU_INT13 0x1000U //!< CPU Interrupt Number 13 +#define INTERRUPT_CPU_INT14 0x2000U //!< CPU Interrupt Number 14 +#define INTERRUPT_CPU_DLOGINT 0x4000U //!< CPU Data Log Interrupt +#define INTERRUPT_CPU_RTOSINT 0x8000U //!< CPU RTOS Interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_clearACKGroup() +// function as the group parameter. +// +//***************************************************************************** +#define INTERRUPT_ACK_GROUP1 0x1U //!< Acknowledge PIE Interrupt Group 1 +#define INTERRUPT_ACK_GROUP2 0x2U //!< Acknowledge PIE Interrupt Group 2 +#define INTERRUPT_ACK_GROUP3 0x4U //!< Acknowledge PIE Interrupt Group 3 +#define INTERRUPT_ACK_GROUP4 0x8U //!< Acknowledge PIE Interrupt Group 4 +#define INTERRUPT_ACK_GROUP5 0x10U //!< Acknowledge PIE Interrupt Group 5 +#define INTERRUPT_ACK_GROUP6 0x20U //!< Acknowledge PIE Interrupt Group 6 +#define INTERRUPT_ACK_GROUP7 0x40U //!< Acknowledge PIE Interrupt Group 7 +#define INTERRUPT_ACK_GROUP8 0x80U //!< Acknowledge PIE Interrupt Group 8 +#define INTERRUPT_ACK_GROUP9 0x100U //!< Acknowledge PIE Interrupt Group 9 +#define INTERRUPT_ACK_GROUP10 0x200U //!< Acknowledge PIE Interrupt Group 10 +#define INTERRUPT_ACK_GROUP11 0x400U //!< Acknowledge PIE Interrupt Group 11 +#define INTERRUPT_ACK_GROUP12 0x800U //!< Acknowledge PIE Interrupt Group 12 +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. The Interrupt_initVectorTable() +//! function sets all vectors to this function. Also, when an interrupt is +//! unregistered using the Interrupt_unregister() function, this handler takes +//! its place. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_defaultHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default illegal instruction trap interrupt handler. +//! +//! This is the default interrupt handler for an illegal instruction trap +//! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate +//! vector to this function. This should never be called during normal +//! operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with +//! an appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_illegalOperationHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default non-maskable interrupt handler. +//! +//! This is the default interrupt handler for a non-maskable interrupt (NMI). +//! The Interrupt_initVectorTable() function sets the appropriate vector to +//! this function. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_nmiHandler(void); + +//***************************************************************************** +// +//! Allows the CPU to process interrupts. +//! +//! This function clears the global interrupt mask bit (INTM) in the CPU, +//! allowing the processor to respond to interrupts. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_enableGlobal(void) +{ + // + // Enable processor interrupts. + // + return(((__enable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Stops the CPU from processing interrupts. +//! +//! This function sets the global interrupt mask bit (INTM) in the CPU, +//! preventing the processor from receiving maskable interrupts. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_disableGlobal(void) +{ + // + // Disable processor interrupts. + // + return(((__disable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! \param handler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via Interrupt_enable()), the handler function will be +//! called in interrupt context. Since the handler function can preempt other +//! code, care must be taken to protect memory or peripherals that are accessed +//! by the handler and other non-handler code. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \note This function assumes that the PIE has been enabled. See +//! Interrupt_initModule(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_register(uint32_t interruptNumber, void (*handler)(void)) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)handler; + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! +//! This function is used to indicate that a default handler +//! Interrupt_defaultHandler() should be called when the given interrupt is +//! asserted to the processor. Call Interrupt_disable() to disable +//! the interrupt before calling this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \sa Interrupt_register() for important information about registering +//! interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_unregister(uint32_t interruptNumber) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy default ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)Interrupt_defaultHandler; + EDIS; +} + +//***************************************************************************** +// +//! Enables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be enabled. +//! +//! This function enables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enableInCPU(uint16_t cpuInterrupt) +{ + // + // Set the interrupt bits in the CPU. + // + IER |= cpuInterrupt; +} + +//***************************************************************************** +// +//! Disables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be disabled. +//! +//! This function disables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disableInCPU(uint16_t cpuInterrupt) +{ + // + // Clear the interrupt bits in the CPU. + // + IER &= ~cpuInterrupt; +} + +//***************************************************************************** +// +//! Acknowledges PIE Interrupt Group +//! +//! \param group specifies the interrupt group to be acknowledged. +//! +//! The specified interrupt group is acknowledged and clears any interrupt +//! flag within that respective group. +//! +//! The \e group parameter must be a logical OR of the following: +//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3 +//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6 +//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9 +//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11, +//! \b INTERRUPT_ACK_GROUP12. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_clearACKGroup(uint16_t group) +{ + // + // Set interrupt group acknowledge bits + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = group; +} + +//***************************************************************************** +// +//! Enables the PIE block. +//! +//! This function enables the vector fetching for the peripheral interrupts by +//! enabling the PIE block. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Disables the PIE block. +//! +//! This function disables the vector fetching for the peripheral interrupts by +//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be +//! accessed even when the PIE block is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) &= ~PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Initializes the PIE control registers by setting them to a known state. +//! +//! This function initializes the PIE control registers. After globally +//! disabling interrupts and enabling the PIE, it clears all of the PIE +//! interrupt enable bits and interrupt flags. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initModule(void); + +//***************************************************************************** +// +//! Initializes the PIE vector table by setting all vectors to a default +//! handler function. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initVectorTable(void); + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_enable(uint32_t interruptNumber); + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_disable(uint32_t interruptNumber); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // INTERRUPT_H diff --git a/gpio_bitfield_cpu2/device/driverlib/ipc.c b/gpio_bitfield_cpu2/device/driverlib/ipc.c new file mode 100644 index 0000000..8d6982e --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/ipc.c @@ -0,0 +1,445 @@ +//########################################################################### +// +// FILE: ipc.c +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ipc.h" + +// +// Macros internal to the IPC driver +// + +#define IPC_ADDR_OFFSET_NOCHANGE 2U +#define IPC_ADDR_OFFSET_MUL2 4U +#define IPC_ADDR_OFFSET_DIV2 1U + +#define IPC_ADDR_OFFSET_CORR(addr, corr) (((addr) * (corr)) / 2U) + +#if IPC_MSGQ_SUPPORT == 1U + +// +// Global Circular Buffer Definitions +// + + +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_PutBuffer, "MSGRAM_CPU1_TO_CPU2") +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_GetBuffer, "MSGRAM_CPU2_TO_CPU1") + +// +// IPC_CPU1_To_CPU2_PutBuffer acts as IPC_CPU2_To_CPU1_GetBuffer and +// IPC_CPU1_To_CPU2_GetBuffer acts as IPC_CPU2_To_CPU1_PutBuffer +// +IPC_PutBuffer_t IPC_CPU1_To_CPU2_PutBuffer; +IPC_GetBuffer_t IPC_CPU1_To_CPU2_GetBuffer; +#endif + +const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM] = { + + /* IPC_CPU1_L_CPU2_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = &IPC_CPU1_To_CPU2_PutBuffer, + .IPC_GetBuffer = &IPC_CPU1_To_CPU2_GetBuffer +#endif + }, + + /* IPC_CPU2_L_CPU1_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = (IPC_PutBuffer_t *)&IPC_CPU1_To_CPU2_GetBuffer, + .IPC_GetBuffer = (IPC_GetBuffer_t *)&IPC_CPU1_To_CPU2_PutBuffer +#endif + } +}; + +//***************************************************************************** +// +// IPC_sendCommand +// +//***************************************************************************** +bool IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data) +{ + bool ret; + + // + // Check whether the flags are not busy + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) == 0U) + { + ret = true; + + if(addrCorrEnable) + { + // + // Update the command registers. ADDR register holds the offset + // from the base address of the MSG RAM + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = + addr - IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + else + { + // + // Update the command registers. addr param remains as is. + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = addr; + } + + // + // Set the flags to indicate the remote core + // + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; + } + else + { + ret = false; + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readCommand +// +//***************************************************************************** +bool IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data) +{ + bool ret; + uint32_t addrReg; + + // + // Check whether the flags are not empty + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U) + { + ret = true; + + // + // Read the command registers + // + *command = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVCOM; + addrReg = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVADDR; + *data = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVDATA; + + if(addrCorrEnable) + { + // + // Calculate the address form the offset + // + *addr = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(addrReg, + IPC_Instance[ipcType].IPC_Offset_Corr); + + } + else + { + *addr = addrReg; + } + + } + else + { + ret = false; + } + + return(ret); +} + + +//***************************************************************************** +// +// IPC_registerInterrupt +// +//***************************************************************************** +void IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Register the interrupt handler + // + + Interrupt_register(intNum, pfnHandler); + + // + // Enable the interrupt + // + Interrupt_enable(intNum); +} + +//***************************************************************************** +// +// IPC_unregisterInterrupt +// +//***************************************************************************** +void IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Disable the interrupt. + // + Interrupt_disable(intNum); + + // + // Unregister the interrupt handler. + // + + Interrupt_unregister(intNum); +} + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// IPCinitMessageQueue +// +//***************************************************************************** +void IPC_initMessageQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(ipcInt_L < IPC_NUM_OF_INTERRUPTS); + ASSERT(ipcInt_R < IPC_NUM_OF_INTERRUPTS); + + IPC_PutBuffer_t *putBuffer = IPC_Instance[ipcType].IPC_PutBuffer; + IPC_GetBuffer_t *getBuffer = IPC_Instance[ipcType].IPC_GetBuffer; + + // + // L->R Put Buffer and Index Initialization + // + msgQueue->PutBuffer = putBuffer->Buffer[ipcInt_R]; + msgQueue->PutWriteIndex = &(putBuffer->PutWriteIndex[ipcInt_R]); + msgQueue->GetReadIndex = &(putBuffer->GetReadIndex[ipcInt_L]); + msgQueue->PutFlag = (uint32_t)1U << ipcInt_R; + + // + // L->R Get Buffer and Index Initialization + // + msgQueue->GetBuffer = getBuffer->Buffer[ipcInt_L]; + msgQueue->GetWriteIndex = &(getBuffer->GetWriteIndex[ipcInt_L]); + msgQueue->PutReadIndex = &(getBuffer->PutReadIndex[ipcInt_R]); + + // + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + // + *(msgQueue->PutWriteIndex) = 0U; + *(msgQueue->GetReadIndex) = 0U; +} + +//***************************************************************************** +// +// IPC_sendMessageToQueue +// +//***************************************************************************** +bool IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->PutWriteIndex); + readIndex = *(msgQueue->PutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while(((writeIndex + 1U) & IPC_MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + readIndex = *(msgQueue->PutReadIndex); + } + + if(ret != false) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + msgQueue->PutBuffer[writeIndex] = *msg; + + if(addrCorrEnable) + { + msgQueue->PutBuffer[writeIndex].address -= + IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + + writeIndex = (writeIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->PutWriteIndex) = writeIndex; + + IPC_setFlagLtoR(ipcType, msgQueue->PutFlag); + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readMessageFromQueue +// +//***************************************************************************** +bool IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->GetWriteIndex); + readIndex = *(msgQueue->GetReadIndex); + + // + // Loop while GetBuffer is empty + // + while(writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + writeIndex = *(msgQueue->GetWriteIndex); + } + + if(ret != false) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *msg = msgQueue->GetBuffer[readIndex]; + if(addrCorrEnable) + { + msg->address = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(msg->address, + IPC_Instance[ipcType].IPC_Offset_Corr); + } + + readIndex = (readIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->GetReadIndex) = readIndex; + } + + return(ret); +} +#endif diff --git a/gpio_bitfield_cpu2/device/driverlib/ipc.h b/gpio_bitfield_cpu2/device/driverlib/ipc.h new file mode 100644 index 0000000..8da7688 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/ipc.h @@ -0,0 +1,880 @@ +//########################################################################### +// +// FILE: ipc.h +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef IPC_H +#define IPC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ipc_api IPC +//! \brief This module is used for inter-processor communications. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "debug.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ipc.h" +#include "inc/hw_ints.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the APIs +// +//***************************************************************************** +//***************************************************************************** +// +// Driver configuration macros +// +//***************************************************************************** +#define IPC_MSGQ_SUPPORT 1U + +// +// Number of IPC messages in circular buffer (must be interval of 2) +// +#define IPC_BUFFER_SIZE 4U + +// +// Number of IPC interrupts using circular buffer (must be same number on both +// CPUs) +// +#define IPC_NUM_OF_INTERRUPTS 4U + +//***************************************************************************** +// +// Values that can be passed as parameter flags in all the IPC API functions. +// +//***************************************************************************** +#ifndef IPC_FLAGS_DEFINED +#define IPC_FLAGS_DEFINED +#define IPC_NO_FLAG 0x00000000U //!< NO FLAG +#define IPC_FLAG0 0x00000001U //!< IPC FLAG 0 +#define IPC_FLAG1 0x00000002U //!< IPC FLAG 1 +#define IPC_FLAG2 0x00000004U //!< IPC FLAG 2 +#define IPC_FLAG3 0x00000008U //!< IPC FLAG 3 +#define IPC_FLAG4 0x00000010U //!< IPC FLAG 4 +#define IPC_FLAG5 0x00000020U //!< IPC FLAG 5 +#define IPC_FLAG6 0x00000040U //!< IPC FLAG 6 +#define IPC_FLAG7 0x00000080U //!< IPC FLAG 7 +#define IPC_FLAG8 0x00000100U //!< IPC FLAG 8 +#define IPC_FLAG9 0x00000200U //!< IPC FLAG 9 +#define IPC_FLAG10 0x00000400U //!< IPC FLAG 10 +#define IPC_FLAG11 0x00000800U //!< IPC FLAG 11 +#define IPC_FLAG12 0x00001000U //!< IPC FLAG 12 +#define IPC_FLAG13 0x00002000U //!< IPC FLAG 13 +#define IPC_FLAG14 0x00004000U //!< IPC FLAG 14 +#define IPC_FLAG15 0x00008000U //!< IPC FLAG 15 +#define IPC_FLAG16 0x00010000U //!< IPC FLAG 16 +#define IPC_FLAG17 0x00020000U //!< IPC FLAG 17 +#define IPC_FLAG18 0x00040000U //!< IPC FLAG 18 +#define IPC_FLAG19 0x00080000U //!< IPC FLAG 19 +#define IPC_FLAG20 0x00100000U //!< IPC FLAG 20 +#define IPC_FLAG21 0x00200000U //!< IPC FLAG 21 +#define IPC_FLAG22 0x00400000U //!< IPC FLAG 22 +#define IPC_FLAG23 0x00800000U //!< IPC FLAG 23 +#define IPC_FLAG24 0x01000000U //!< IPC FLAG 24 +#define IPC_FLAG25 0x02000000U //!< IPC FLAG 25 +#define IPC_FLAG26 0x04000000U //!< IPC FLAG 26 +#define IPC_FLAG27 0x08000000U //!< IPC FLAG 27 +#define IPC_FLAG28 0x10000000U //!< IPC FLAG 28 +#define IPC_FLAG29 0x20000000U //!< IPC FLAG 29 +#define IPC_FLAG30 0x40000000U //!< IPC FLAG 30 +#define IPC_FLAG31 0x80000000U //!< IPC FLAG 31 +#define IPC_FLAG_ALL 0xFFFFFFFFU //!< All IPC flags +#endif + +//***************************************************************************** +// +// Values that can be passed as parameter ipcInt in +// IPC_registerInterrupt and IPC_unregisterInterrupt functions. +// Please refer to the datasheet for the actual number of interrupts available +// for each IPC instance +// +//***************************************************************************** +#define IPC_INT0 0x0U //!< IPC Interrupt 0 +#define IPC_INT1 0x1U //!< IPC Interrupt 1 +#define IPC_INT2 0x2U //!< IPC Interrupt 2 +#define IPC_INT3 0x3U //!< IPC Interrupt 3 +#define IPC_INT4 0x4U //!< IPC Interrupt 4 +#define IPC_INT5 0x5U //!< IPC Interrupt 5 +#define IPC_INT6 0x6U //!< IPC Interrupt 6 +#define IPC_INT7 0x7U //!< IPC Interrupt 7 + +//***************************************************************************** +// +// Values that can be passed as parameter addrCorrEnable in +// IPC_sendCommand, IPC_readCommand, IPC_sendMessageToQueue and +// IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_ADDR_CORRECTION_ENABLE true +#define IPC_ADDR_CORRECTION_DISABLE false + +//***************************************************************************** +// +// Values that can be passed as parameter block in +// IPC_sendMessageToQueue and IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_BLOCKING_CALL true +#define IPC_NONBLOCKING_CALL false + + + +//***************************************************************************** +// +// Internal macros used for message queue implementation +// +//***************************************************************************** +#define IPC_MAX_BUFFER_INDEX (IPC_BUFFER_SIZE - 1U) + +//***************************************************************************** +// +// Enums for the APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! Values that can be passed as parameter \e ipcType in all the driver +//! functions +// +//***************************************************************************** +typedef enum +{ + IPC_CPU1_L_CPU2_R, //!< CPU1 - Local core, CPU2 - Remote core + IPC_CPU2_L_CPU1_R, //!< CPU2 - Local core, CPU1 - Remote core + IPC_TOTAL_NUM +}IPC_Type_t; + +//***************************************************************************** +// +// Internal structs for register and messaage queue accesses +// +//***************************************************************************** +typedef struct +{ + uint32_t IPC_ACK; + uint32_t IPC_STS; + uint32_t IPC_SET; + uint32_t IPC_CLR; + uint32_t IPC_FLG; + uint32_t IPC_RSVDREG; + uint32_t IPC_COUNTERL; + uint32_t IPC_COUNTERH; +}IPC_Flag_Ctr_Reg_t; + +typedef struct +{ + uint32_t IPC_SENDCOM; + uint32_t IPC_SENDADDR; + uint32_t IPC_SENDDATA; + uint32_t IPC_REMOTEREPLY; +}IPC_SendCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_RECVCOM; + uint32_t IPC_RECVADDR; + uint32_t IPC_RECVDATA; + uint32_t IPC_LOCALREPLY; +}IPC_RecvCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_BOOTSTS; + uint32_t IPC_BOOTMODE; +}IPC_Boot_Pump_Reg_t; + +#if IPC_MSGQ_SUPPORT == 1U +typedef struct +{ + uint32_t command; + uint32_t address; + uint32_t dataw1; + uint32_t dataw2; +}IPC_Message_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t PutWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t GetReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_PutBuffer_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t GetWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t PutReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_GetBuffer_t; +#endif + +//***************************************************************************** +// +// Internal struct used to store the required information regarding an IPC +// instance +// +//***************************************************************************** +typedef struct +{ + volatile IPC_Flag_Ctr_Reg_t *IPC_Flag_Ctr_Reg; + volatile IPC_SendCmd_Reg_t *IPC_SendCmd_Reg; + volatile IPC_RecvCmd_Reg_t *IPC_RecvCmd_Reg; + volatile IPC_Boot_Pump_Reg_t *IPC_Boot_Pump_Reg; + uint32_t IPC_IntNum[8U]; + uint32_t IPC_MsgRam_LtoR; + uint32_t IPC_MsgRam_RtoL; + uint32_t IPC_Offset_Corr; +#if IPC_MSGQ_SUPPORT == 1U + IPC_PutBuffer_t *IPC_PutBuffer; + IPC_GetBuffer_t *IPC_GetBuffer; +#endif +}IPC_Instance_t; + +extern const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM]; + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// A structure that defines an IPC message queue. These +// fields are used by the IPC drivers, and normally it is not necessary for +// user software to directly read or write fields in the table. +// +//***************************************************************************** + +typedef struct +{ + IPC_Message_t * PutBuffer; + uint32_t PutFlag; + uint16_t * PutWriteIndex; + uint16_t * PutReadIndex; + IPC_Message_t * GetBuffer; + uint16_t * GetWriteIndex; + uint16_t * GetReadIndex; +} IPC_MessageQueue_t; +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! Local core sets Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being set +//! +//! This function will allow the Local core system to set the designated IPC +//! flags to send to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; +} + +//***************************************************************************** +// +//! Local core clears Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being cleared +//! +//! This function will allow the Local core system to clear the designated IPC +//! flags sent to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_clearFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_CLR = flags; +} + +//***************************************************************************** +// +//! Local core acknowledges Remote to Local IPC Flag. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being acknowledged. +//! +//! This function will allow the Local core system to acknowledge/clear the IPC +//! flag set by the Remote core system. The \e flags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_ackFlagRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_ACK = flags; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Local to Remote IPC flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Local to Remote +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) != 0U); +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Remote to Local IPC Flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Remote to Local +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U); +} + +//***************************************************************************** +// +//! Wait for the remote core to send a flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the Remote to Local IPC flag mask to wait for +//! +//! Allows the caller to wait for the Remote to Local flag to be send by +//! the remote core. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForFlag(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flag) == 0U) + { + } +} + +//***************************************************************************** +// +//! Wait for the IPC flag to be acknowledged +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask for which ack is pending +//! +//! Allows the caller to wait for the IPC flag to be acknowledged by the +//! remote core. The \e flagsparameter can be any of the IPC flag values: +//! \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForAck(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flag) != 0U) + { + } +} + +//***************************************************************************** +// +//! Synchronises the two cores +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask with which synchronisation is done +//! +//! Allows the local and remote cores to synchronise. Neither core will return +//! from this function call before the other core enters it. +//! +//! \note Must be called with same flag mask on both the cores +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_sync(IPC_Type_t ipcType, uint32_t flag) +{ + IPC_setFlagLtoR(ipcType, flag); + IPC_waitForFlag(ipcType, flag); + IPC_ackFlagRtoL(ipcType, flag); + IPC_waitForAck(ipcType, flag); +} + +//***************************************************************************** +// +//! Initialize IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +// +//! This function initializes IPC by clearing all the flags +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_init(IPC_Type_t ipcType) +{ + IPC_clearFlagLtoR(ipcType, IPC_FLAG_ALL); +} + +//***************************************************************************** +// +//! Sends a command to the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags to be set +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit command value +//! \param addr is the 32-bit address to be sent as part of command +//! \param data is the 32-bit data to be sent as part of command +//! +//! Allows the caller to send a command to the remote core. A command consists +//! of a unique command value, a 32-bit address and a 32-bit data. The function +//! also sends the designated flags to the remote core. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! The application shall use the function IPC_getResponse to read the response +//! sent by the remote core. +//! +//! \note The application is expected to wait until the the response is +//! received before sending another command. +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is sent properly and \b false if +//! the designated flags were busy and hence command was not sent. +// +//***************************************************************************** +extern bool +IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data); + +//***************************************************************************** +// +//! Reads a command sent by the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags sent by the remote core +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit pointer at which the command value is read to +//! \param addr is the 32-bit pointer at which address value is read to +//! \param data is the 32-bit pointer at which the data is read to +//! +//! Allows the caller to read a command sent by the remote core. A command +//! consists of a unique command value, a 32-bit address and a 32-bit data. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! \note The application is expected to acknowledge the flag and send a +//! response (if needed) after reading the command +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is read properly and \b false if +//! the designated flags were empty and hence command was not read. +// +//***************************************************************************** +extern bool +IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data); + +//***************************************************************************** +// +//! Sends the response to the command sent by remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param data is the 32-bit value of the response to be sent +//! +//! Allows the caller to send a response to the command previously sent by the +//! remote core +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_sendResponse(IPC_Type_t ipcType, uint32_t data) +{ + IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_LOCALREPLY = data; +} + +//***************************************************************************** +// +//! Reads the response from the remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the response sent by the remote core to the +//! command previously sent by the local core +//! +//! \return the 32-bit value of the response. +// +//***************************************************************************** +static inline uint32_t +IPC_getResponse(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_REMOTEREPLY); +} + +//***************************************************************************** +// +//! Sets the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param mode is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! \note This function shall be called by CPU1 only. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_setBootMode(IPC_Type_t ipcType, uint32_t mode) +{ + ASSERT(ipcType == IPC_CPU1_L_CPU2_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE = mode; +} + +//***************************************************************************** +// +//! Reads the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTMODE register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootMode(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE); +} + +//***************************************************************************** +// +//! Sets the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param status is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTSTS register. +//! +//! \note This function shall be called by CPU2 and CM only +//! +//! \note This function shall be called by CPU2 only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setBootStatus(IPC_Type_t ipcType, uint32_t status) +{ + ASSERT(ipcType == IPC_CPU2_L_CPU1_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS = status; +} + +//***************************************************************************** +// +//! Reads the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTSTS register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootStatus(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS); +} + +//***************************************************************************** +// +//! Reads the timestamp counter value. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the IPC timestamp counter value. +//! +//! \return 64-bit counter value. +// +//***************************************************************************** +static inline uint64_t +IPC_getCounter(IPC_Type_t ipcType) +{ + // + // Get the Counter High and Low values. Read to the Counter low register + // saves the value of Counter High register. + // + uint32_t ctrL = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERL; + uint32_t ctrH = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERH; + + // + // Return the 64-bit value of the counter + // + return(((uint64_t)ctrH << 32) | ((uint64_t)ctrL)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being registered +//! \param pfnHandler is the pointer to ISR function +//! +//! This function registers the handler to be called when an IPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! Unregisters an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being unregistered +//! +//! This function clears the handler to be called when an IPC interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt); + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +//! Initializes the IPC message queue +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param ipcInt_L specifies the interrupt number on the local core used by +//! the message queue . +//! \param ipcInt_R specifies the interrupt number on the remote core used by +//! the message queue. +//! +//! This function initializes the IPC message queue with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e ipcInt_L and \e ipcInt_R parameters can be one of the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e IPC_MessageQueue_t +//! instance, that particular interrupt should not be tied to a second +//! \e IPC_MessageQueue_t instance. +//! +//! \note For a particular ipcInt_L - ipcInt_R pair, there must be an instance +//! of IPC_MessageQueue_t defined and initialized on both the locakl and remote +//! systems. +//! +//! \return None. +// +//***************************************************************************** +extern void +IPC_initMessageQueue(IPC_Type_t ipcType, volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R); + +//***************************************************************************** +// +//! Sends a message into the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to be +//! sent to message queue. +//! \param block specifies whether to allow function to block until the buffer +//! has a free slot +//! +//! This function checks if there is a free slot in the message queue. If so, it +//! puts the message pointed to by \e msg into the free and sets the +//! appropriate IPC interrupt flag +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is full. \b true if the message is +//! successfully sent. +// +//***************************************************************************** +extern bool +IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); + +//***************************************************************************** +// +//! Reads a message from the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to which +//! the message needs to be read +//! \param block specifies whether to allow function to block until a message +//! is available in the message queue +//! +//! This function checks if there is a message in the message queue. If so, it +//! reads the message and writes to the address pointed to by \e msg into. +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is empty. \b true if the message successfully +//! read. +// +//***************************************************************************** +extern bool +IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); +#endif +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // IPC_H diff --git a/gpio_bitfield_cpu2/device/driverlib/mcbsp.c b/gpio_bitfield_cpu2/device/driverlib/mcbsp.c new file mode 100644 index 0000000..4b23940 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/mcbsp.c @@ -0,0 +1,1621 @@ +//########################################################################### +// +// FILE: mcbsp.c +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "mcbsp.h" + +//***************************************************************************** +// +// McBSP_transmit16BitdataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit16BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_setRxDataSize +// +//***************************************************************************** +void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word , write to RWDLEN1 and words per frame , write to + // RFRLEN1. + // + HWREGH(base + MCBSP_O_RCR1) = + ((HWREGH(base + MCBSP_O_RCR1) & ~MCBSP_RCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR1_RFRLEN1_S))); + } + else + { + // + // Set bits per word , write to RWDLEN2 and words per frame, write to + // RFRLEN2. + // + HWREGH(base + MCBSP_O_RCR2) = + ((HWREGH(base + MCBSP_O_RCR2) & ~MCBSP_RCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR2_RFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_setTxDataSize +// +//***************************************************************************** +void +McBSP_setTxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word XWDLEN1 and words per frame XFRLEN1. + // + HWREGH(base + MCBSP_O_XCR1) = + ((HWREGH(base + MCBSP_O_XCR1) & ~MCBSP_XCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR1_XFRLEN1_S))); + } + else + { + // + // Set bits per word XWDLEN2 and words per frame XFRLEN2. + // + HWREGH(base + MCBSP_O_XCR2) = + ((HWREGH(base + MCBSP_O_XCR2) & ~MCBSP_XCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR2_XFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_disableRxChannel +// +//***************************************************************************** +void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableRxChannel +// +//***************************************************************************** +void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_disableTxChannel +// +//***************************************************************************** +void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableTxChannel +// +//***************************************************************************** +void McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine wheter it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_configureTxClock +// +//***************************************************************************** +void +McBSP_configureTxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select TX clock source as SRG or External. + // + McBSP_setTxClockSource(base, + (McBSP_TxClockSource)ptrClockParams->clockSourceTx); + + // + // Check if using SRG to drive Transmitter clock. + // + if((McBSP_TxClockSource)ptrClockParams->clockSourceTx == + MCBSP_INTERNAL_TX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setTxSRGClockSource(base, + (McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource); + + // + // Check if SRG is clocked from MCLKR pin. GSYNC feature can be enabled + // in this case as SRG input clock source is MCLKR pin. + // + if((McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource == + MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); + + // + // Check if SRG is to be synced with FSR that is GSYNC is to be + // enabled or not. + // + if(ptrClockParams->clockSRGSyncFlag) + { + McBSP_enableSRGSyncFSR(base); + } + else + { + McBSP_disableSRGSyncFSR(base); + } + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKX. + // Output polarity if using SRG as clock source. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); +} + +//***************************************************************************** +// +// McBSP_configureRxClock +// +//***************************************************************************** +void +McBSP_configureRxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select RX clock source as SRG or External. + // + McBSP_setRxClockSource(base, + (McBSP_RxClockSource)ptrClockParams->clockSourceRx); + + // + // Check if using SRG to drive Receiver clock. + // + if((McBSP_RxClockSource)ptrClockParams->clockSourceRx == + MCBSP_INTERNAL_RX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setRxSRGClockSource(base, + (McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource); + + // + // Check if SRG is clocked from MCLKX pin. GSYNC cannot be enabled in + // this case as GSYNC feature can be used only when SRG clock source is + // MCLKR pin. + // + if((McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource == + MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKR. + // Output polarity if using SRG as clock source. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); +} + +//***************************************************************************** +// +// McBSP_configureTxFrameSync +// +//***************************************************************************** +void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setTxFrameSyncSource(base, + (McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx); + + // + // Check if using internal frame-sync source. + // + if((McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx == + MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Select the internal frame-sync trigger source. + // + McBSP_setTxInternalFrameSyncSource(base, + (McBSP_TxInternalFrameSyncSource)ptrFsyncParams->syncIntSource); + + // + // Check if using SRG FSG to trigger frame-sync pulse and GSYNC feature + // is disabled that is FSG is not derived from external MCLKR pin. + // + if((ptrFsyncParams->syncIntSource == + MCBSP_TX_INTERNAL_FRAME_SYNC_SRG) && + (ptrFsyncParams->syncSRGSyncFSRFlag == false)) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setTxFrameSyncPolarity(base, + (McBSP_TxFrameSyncPolarity)ptrFsyncParams->syncFSXPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableTxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureRxFrameSync +// +//***************************************************************************** +void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setRxFrameSyncSource(base, + (McBSP_RxFrameSyncSource)ptrFsyncParams->syncSourceRx); + + // + // If using internal frame-sync source. + // + if(ptrFsyncParams->syncSourceRx == MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Check if GSYNC feature is disabled that is FSG is not derived + // from external MCLKR pin. + // + if(ptrFsyncParams->syncSRGSyncFSRFlag == false) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setRxFrameSyncPolarity(base, + (McBSP_RxFrameSyncPolarity)ptrFsyncParams->syncFSRPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableRxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureTxDataFormat +// +//***************************************************************************** +void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - a TX must at least has a single phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseTx(base); + + // + // Check if second phase is being used. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseTx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the Tx companding mode. + // + McBSP_setTxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set Tx data delay in bits. + // + McBSP_setTxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set DX pin delay. + // + if(ptrDataParams->pinDelayEnableFlag) + { + McBSP_enableDxPinDelay(base); + } + else + { + McBSP_disableDxPinDelay(base); + } + + // + // Set the transmitter interrupt source. + // + McBSP_setTxInterruptSource(base, + (McBSP_TxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureRxDataFormat +// +//***************************************************************************** +void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP mode. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - an RX must at least have a single phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseRx(base); + + // + // Check if second phase is to be enabled. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseRx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the receiver companding mode. + // + McBSP_setRxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set receiver data delay in bits. + // + McBSP_setRxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set receiver sign-extension and justification mode. + // + McBSP_setRxSignExtension(base, + (McBSP_RxSignExtensionMode)ptrDataParams->signExtMode); + + // + // Set the receiver interrupt source. + // + McBSP_setRxInterruptSource(base, + (McBSP_RxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureTxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorTx; + + errorTx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setTxChannelMode(base, + (McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx); + + // + // Configuration for multichannel selections that is for + // MCBSP_TX_CHANNEL_SELECTION_ENABLED, + // MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or + // MCBSP_SYMMERTIC_RX_TX_SELECTION. + // + if(((McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx) != + MCBSP_ALL_TX_CHANNELS_ENABLED) + { + // + // Select 2 partition or 8 partition. + // + McBSP_setTxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionTx); + + // + // Disable dual phase transmission mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionTx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if(((uint16_t)ptrMchnParams->channelCountTx) > 32U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*(ptrMchnParams->ptrChannelsListTx) + + index)); + } + else + { + errorTx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition B. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + else + { + errorTx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if((uint16_t)ptrMchnParams->channelCountTx > 128U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Enable the Tx channels. + // + McBSP_enableTxChannel(base, MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + } + } + return(errorTx); +} + +//***************************************************************************** +// +// McBSP_configureRxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorRx; + + errorRx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setRxChannelMode(base, + (McBSP_RxChannelMode)ptrMchnParams->multichannelModeRx); + + // + // Select 2 partition or 8 partition. + // + McBSP_setRxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionRx); + + // + // Configuration for multichannel selections that is for + // MCBSP_RX_CHANNEL_SELECTION_ENABLED. + // + if((ptrMchnParams->multichannelModeRx) == + MCBSP_RX_CHANNEL_SELECTION_ENABLED) + { + // + // Disable dual phase reception mode. + // + McBSP_disableTwoPhaseRx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionRx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if((uint16_t)ptrMchnParams->channelCountRx > 32U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (*((ptrMchnParams->ptrChannelsListRx) + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the Rx channel belonging to the block + // assigned to partition B. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if(ptrMchnParams->channelCountRx > 128U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Enable the Rx channels. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + index))); + } + } + } + return(errorRx); +} + +//***************************************************************************** +// +// McBSP_configureSPIMasterMode +// +//***************************************************************************** +void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams *ptrSPIMasterMode) +{ + // + // Configure clock stop mode. + // + if(((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPIMasterMode->clockStopMode); + + // + // Set loop back mode. + // + if(ptrSPIMasterMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as master. Use SRG as clock source for driving + // master clock. MCLKX pin will be the master clock out pin. + // + McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE); + + // + // Set internal clock (LSPCLK) as SRG clock source. + // + McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK); + + // + // Set SRG clock divider for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrSPIMasterMode->clockSRGDivider); + + // + // Set the output master clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPIMasterMode->spiMode); + + // + // Set FSX as an output driven by SRG. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE); + + // + // FSX is triggered when data is written to DXR registers. + // + McBSP_setTxInternalFrameSyncSource(base, + MCBSP_TX_INTERNAL_FRAME_SYNC_DATA); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + + // + // Set one bit data delay for transmission & reception to set correct + // setup time on FSX signal. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + } +} + +//***************************************************************************** +// +// McBSP_configureSPISlaveMode +// +//***************************************************************************** +void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams *ptrSPISlaveMode) +{ + + // + // Configure clock stop mode. + // + if(((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPISlaveMode->clockStopMode); + // + // Set loop back mode. + // + if(ptrSPISlaveMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as Slave. MCLKX pin acts as input slave + // clock and is driven externally by SPI master. + // + McBSP_setTxClockSource(base, MCBSP_EXTERNAL_TX_CLOCK_SOURCE); + + // + // Set the input slave clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPISlaveMode->spiMode); + + // + // Set internal clock (LSPCLK) as SRG clock source. SRG is used to + // synchronize McBSP logic with externally generated master clock. + // + McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK); + + // + // Assign a clock divider value of 1 for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, 1U); + + // + // Set FSX as an input which is driven by slave-enable signal + // from SPI master. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception.. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + + // + // Set zero bit data delay for transmission & reception. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + } +} diff --git a/gpio_bitfield_cpu2/device/driverlib/mcbsp.h b/gpio_bitfield_cpu2/device/driverlib/mcbsp.h new file mode 100644 index 0000000..949987d --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/mcbsp.h @@ -0,0 +1,3340 @@ +//########################################################################### +// +// FILE: mcbsp.h +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MCBSP_H +#define MCBSP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup mcbsp_api McBSP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_mcbsp.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Define to specify mask for setting the word and frame length in +// McBSP_setTxDataSize() anf McBSP_setRxDataSize(). +// +//***************************************************************************** +#define MCBSP_XCR1_M (MCBSP_XCR1_XWDLEN1_M | \ + MCBSP_XCR1_XFRLEN1_M) +#define MCBSP_RCR1_M (MCBSP_RCR1_RWDLEN1_M | \ + MCBSP_RCR1_RFRLEN1_M) +#define MCBSP_XCR2_M (MCBSP_XCR2_XWDLEN2_M | \ + MCBSP_XCR2_XFRLEN2_M) +#define MCBSP_RCR2_M (MCBSP_RCR2_RWDLEN2_M | \ + MCBSP_RCR2_RFRLEN2_M) + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getRxErrorStatus() when +// there is an error in Rx. +// +//***************************************************************************** +#define MCBSP_RX_NO_ERROR 0x0U //!< No error. +#define MCBSP_RX_BUFFER_ERROR 0x4U //!< Buffer Full. +#define MCBSP_RX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_RX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getTxErrorStatus() when +// there is an error in Tx. +// +//***************************************************************************** +#define MCBSP_TX_NO_ERROR 0x0U //!< No error. +#define MCBSP_TX_BUFFER_ERROR 0x4U //!< Buffer overrun. +#define MCBSP_TX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_TX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Values that can be returned by McBSP_configureTxMultichannel() and +// McBSP_configureRxMultichannel(). +// +//***************************************************************************** +#define MCBSP_ERROR_EXCEEDED_CHANNELS 0x1U //!< Exceeded number of channels. +#define MCBSP_ERROR_2_PARTITION_A 0x2U //!< Error in 2 partition A setup. +#define MCBSP_ERROR_2_PARTITION_B 0x4U //!< Error in 2 partition B setup. +#define MCBSP_ERROR_INVALID_MODE 0x8U //!< Invalid mode. + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxSignExtension() as the \e +//! mode parameters. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RIGHT_JUSTIFY_FILL_ZERO = 0x0000U, //!< Right justify and + //!< zero fill MSB. + MCBSP_RIGHT_JUSTIFY_FILL_SIGN = 0x2000U, //!< Right justified sign + //!< extended into MSBs. + MCBSP_LEFT_JUSTIFY_FILL_ZER0 = 0x4000U //!< Left justifies LBS + //!< filled with zero. +}McBSP_RxSignExtensionMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setClockStopMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_CLOCK_MCBSP_MODE = 0x0000U, //!< Disables clock stop mode. + MCBSP_CLOCK_SPI_MODE_NO_DELAY = 0x1000U, //!< Enables clock stop mode. + MCBSP_CLOCK_SPI_MODE_DELAY = 0x1800U //!< Enables clock stop mode + //!< with half cycle delay. +}McBSP_ClockStopMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxInterruptSource() as the +//! \e interruptSource parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RX_ISR_SOURCE_SERIAL_WORD = 0x0000U, //!> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Configures transmitter input clock source for sample generator. +//! +//! \param base is the base address of the McBSP module. +//! \param srgClockSource is clock source for the sample generator. +//! +//! This functions sets the clock source for the sample rate generator. +//! Valid values for \e clockSource are +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK for LSPCLK. +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN for external clock at MCLKR pin. +//! MCLKX pin will be an output driven by sample rate generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxSRGClockSource(uint32_t base, + const McBSP_SRGTxClockSource srgClockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKSM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_CLKSM) | + ((uint16_t)((uint16_t)srgClockSource & 0x1U) << 13U)); + // + // Set or clear SCLKME bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_SCLKME) | + (uint16_t)(((uint16_t)srgClockSource >> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Sets the mode for transmitter internal frame sync signal. +//! +//! \param base is the base address of the McBSP module. +//! \param syncMode is the frame sync mode. +//! +//! This function sets the frame sync signal generation mode. The signal can be +//! generated based on clock divider as set in McBSP_setFrameSyncPulsePeriod() +//! function or when data is transferred from DXR registers to XSR registers. +//! Valid input for syncMode are: +//! +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_DATA - frame sync signal is +//! generated when data is transferred from +//! DXR registers to XSR registers. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SRG - frame sync signal is +//! generated based on the clock counter +//! value as defined in +//! McBSP_setFrameSyncPulsePeriod() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxInternalFrameSyncSource(uint32_t base, + const McBSP_TxInternalFrameSyncSource syncMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSGM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_FSGM) | (uint16_t)syncMode); +} + +//***************************************************************************** +// +//! Set Multichannel receiver partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel receiver. Valid values +//! for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or Clear RMCME bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to receiver in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! receiver partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Check the block value if it is 0,2,4,6 or 1,3,5,7. + // + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to RPABLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPABLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to RPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPBBLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active receiver block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active receiver block involved in McBSP +//! reception. +//! +//! \return Active block in McBSP reception. Returned values range from 0 to 7 +//! representing the respective active block number . +// +//***************************************************************************** +static inline uint16_t +McBSP_getRxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return RCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR1) & MCBSP_MCR1_RCBLK_M) >> + MCBSP_MCR1_RCBLK_S); +} + +//***************************************************************************** +// +//! Configure channel selection mode for receiver. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_RX_CHANNELS_ENABLED - enables all channels. +//! - \b MCBSP_RX_CHANNEL_SELECTION_ENABLED - lets the user enable desired +//! channels by using McBSP_enableRxChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxChannelMode(uint32_t base, const McBSP_RxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear RMCM bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCM) | (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Set Multichannel transmitter partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel transmitter. Valid +//! values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear XMCME bit. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to transmitter in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! transmitter partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to XPABLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPABLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to XPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPBBLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active transmitter block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active transmitter block involved in +//! McBSP transmission. +//! +//! \return Active block in McBSP transmission. Returned values range from +//! 0 to 7 representing the respective active block number. +// +//***************************************************************************** +static inline uint16_t +McBSP_getTxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return XCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR2) & MCBSP_MCR2_XCBLK_M) >> + MCBSP_MCR2_XCBLK_S); + +} + +//***************************************************************************** +// +//! Configure channel selection mode for transmitter. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_TX_CHANNELS_ENABLED - enables and unmasks all channels +//! - \b MCBSP_TX_CHANNEL_SELECTION_ENABLED - lets the user enable and unmask +//! desired channels by using McBSP_enableTxChannel() +//! - \b MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION - All channels enables but +//! until enabled by McBSP_enableTxChannel() +//! - \b MCBSP_SYMMERTIC_RX_TX_SELECTION - Symmetric transmission and +//! reception. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxChannelMode(uint32_t base, const McBSP_TxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set values to the XMCM bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCM_M) | + (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Select the transmitter frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the transmitter frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSX. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! internally. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncSource(uint32_t base, + const McBSP_TxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Set or Clear the FSXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Select receiver frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the receiver frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSR. +//! - \b MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! by SRG. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncSource(uint32_t base, + const McBSP_RxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Configures the Transmit clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the transmission pin. +//! +//! This function configures the clock source for the transmitter. Valid input +//! for rxClockSource are: +//! - \b MCBSP_INTERNAL_TX_CLOCK_SOURCE - internal clock source. SRG is the +//! source. +//! - \b MCBSP_EXTERNAL_TX_CLOCK_SOURCE - external clock source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockSource(uint32_t base, const McBSP_TxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXM ) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Configures the Receive clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the reception pin. +//! +//! This function configures the clock source for the receiver. Valid input +//! for base are: +//! - \b MCBSP_INTERNAL_RX_CLOCK_SOURCE - internal clock source. Sample Rate +//! Generator will be used. +//! - \b MCBSP_EXTERNAL_RX_CLOCK_SOURCE - external clock will drive the data. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockSource(uint32_t base, const McBSP_RxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRM) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Sets transmitter frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSX pin. Use \b MCBSP_TX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_TX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncPolarity(uint32_t base, + const McBSP_TxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets receiver frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSR pin. Use \b MCBSP_RX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_RX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncPolarity(uint32_t base, + const McBSP_RxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets transmitter clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the transmitter +//! clock on MCLKX pin. +//! Valid values for clockPolarity are: +//! - \b MCBSP_TX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_TX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockPolarity(uint32_t base, + const McBSP_TxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKXP bit first , then set or clear CLKXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +//! Sets receiver clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the receiver +//! clock on MCLKR pin. If external clock is used, the polarity will affect +//! CLKG signal. +//! Valid values for clockPolarity are: +//! - \b MCBSP_RX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_RX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockPolarity(uint32_t base, + const McBSP_RxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKRP bit first , then set or clear CLKRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data value in data receive register. +//! +//! \return received data. +// +//***************************************************************************** +static inline +uint16_t McBSP_read16bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DRR1 register. + // + return(HWREGH(base + MCBSP_O_DRR1)); +} + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data values in data receive registers. +//! +//! \return received data. +// +//***************************************************************************** +static inline uint32_t +McBSP_read32bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DDR1 register and return DDR2:DDR1. + // + return((((uint32_t)HWREGH(base + MCBSP_O_DRR2) << 16U) | + HWREGH(base + MCBSP_O_DRR1))); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 8,12 or 16 bit data to data transmit register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write16bitData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data; +} + +//***************************************************************************** +// +//! Write 20, 24 or 32 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 20, 24 or 32 bit data to data transmit registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write32bitData(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR2 register first. + // + HWREGH(base + MCBSP_O_DXR2) = data >> 16U; + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data & 0xFFFFU; +} + +//***************************************************************************** +// +//! Return left justified for data for U Law or A Law companding. +//! +//! \param data is the 14 bit word. +//! \param compandingType specifies the type comapnding desired. +//! +//! This functions returns U law or A law adjusted word. +//! +//! \return U law or A law left justified word. +// +//***************************************************************************** +static inline uint16_t +McBSP_getLeftJustifyData(uint16_t data, + const McBSP_CompandingType compandingType) +{ + return(data << (uint16_t)compandingType); +} + + +//***************************************************************************** +// +//! Enable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_RINT; +} + +//***************************************************************************** +// +//! Disable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_RINT); +} + +//***************************************************************************** +// +//! Enable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_XINT; +} + +//***************************************************************************** +// +//! Disable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_XINT); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. +//! +//! \return None. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written to +//! the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! the transmitter buffer is empty the data will be written to the data +//! registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written +//! to the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData); + + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Reception. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing the first or second frame phase +//! respectively. Valid value for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Transmission. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing single or dual phase respectively. +//! Valid values for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setTxDataSize(uint32_t base, + const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Disables a channel in an eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function disables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function enables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Disables a channel in an eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function disables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function enables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Configures transmitter clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the transmitter clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFSR - true to sync with signal on FSR pin, +//! false to ignore signal on FSR pin. +//! the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_TX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_TX_CLOCK_SOURCE +//! - \b clockTxSRGSource - MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN +//! - \b clockMCLKXPolarity - Output polarity on MCLKX pin. +//! - MCBSP_TX_POLARITY_RISING_EDGE +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockMCLKRPolarity - Input polarity on MCLKR pin (if SRG is +//! sourced from MCLKR pin). +//! - MCBSP_RX_POLARITY_FALLING_EDGE +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures receiver clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the receiver clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_RX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_RX_CLOCK_SOURCE +//! - \b clockRxSRGSource - MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN +//! - \b clockMCLKRPolarity- output polarity on MCLKR pin. +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! - \b clockMCLKXPolarity- Input polarity on MCLKX pin (if SRG is sourced +//! from MCLKX pin). +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures transmitter frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSPTxFsyncParams. +//! This function sets up the transmitter frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin.This value has to +//! be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. false +//! to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceTx - MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncIntSource - MCBSP_TX_INTERNAL_FRAME_SYNC_DATA or +//! MCBSP_TX_INTERNAL_FRAME_SYNC_SRG +//! - \b syncFSXPolarity - MCBSP_TX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_TX_FRAME_SYNC_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures receiver frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSP_RxFsyncParams. +//! This function sets up the receiver frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, +//! false to ignore the pulse on FSR pin. +//! This value has to be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. +//! false to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceRx - MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncFSRPolarity - MCBSP_RX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_RX_FRAME_SYNC_POLARITY_HIGH +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures transmitter data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing \e data format +//! parameters McBSPTxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSPTxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for no loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b pinDelayEnableFlag - true to enable DX pin delay. +//! false to disable DX pin delay. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b interruptMode - MCBSP_TX_ISR_SOURCE_TX_READY, +//! MCBSP_TX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_TX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_TX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures receiver data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing data format +//! parameters McBSP_RxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSP_RxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for non loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b signExtMode - MCBSP_RIGHT_JUSTIFY_FILL_ZERO, +//! MCBSP_RIGHT_JUSTIFY_FILL_SIGN or +//! MCBSP_LEFT_JUSTIFY_FILL_ZER0 +//! - \b interruptMode - MCBSP_RX_ISR_SOURCE_SERIAL_WORD, +//! MCBSP_RX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_RX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_RX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures transmitter multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_TxMultichannelParams. +//! +//! This function sets up the transmitter multichannel mode. The following are +//! valid values and ranges for the parameters of the +//! McBSP_TxMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_TX_CHANNELS_ENABLED, +//! MCBSP_TX_CHANNEL_SELECTION_ENABLED, +//! MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or +//! MCBSP_SYMMERTIC_RX_TX_SELECTION +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even and +//! odd channels. For example you can have channels [48 -63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63] and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures receiver multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_RxMultiChannelParams. +//! +//! This function sets up the receiver multichannel mode. The following are +//! valid values and ranges for the parameters of the McBSPMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_RX_CHANNELS_ENABLED, +//! MCBSP_RX_CHANNEL_SELECTION_ENABLED, +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even +//! and odd channels. For example you can have channels [48 - 63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63]and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures McBSP in SPI master mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPIMasterMode is a pointer to a structure containing SPI +//! parameters McBSP_SPIMasterModeParams. +//! This function sets up the McBSP module in SPI master mode.The following are +//! valid values and ranges for the parameters of the +//! McBSP_SPIMasterModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity can take values: +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockSRGDivider - Maximum valid value is 255. +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams * ptrSPIMasterMode); + +//***************************************************************************** +// +//! Configures McBSP in SPI slave mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPISlaveMode is a pointer to a structure containing SPI +//! parameters McBSP_SPISlaveModeParams. +//! This function sets up the McBSP module in SPI slave mode.The following are +//! valid values and ranges for the parameters of the McBSP_SPISlaveModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity and can take +//! values: +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams * ptrSPISlaveMode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MCBSP_H diff --git a/gpio_bitfield_cpu2/device/driverlib/memcfg.c b/gpio_bitfield_cpu2/device/driverlib/memcfg.c new file mode 100644 index 0000000..c9a4dc7 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/memcfg.c @@ -0,0 +1,701 @@ +//########################################################################### +// +// FILE: memcfg.c +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "memcfg.h" + + +//***************************************************************************** +// +// MemCfg_lockConfig +// +//***************************************************************************** +void +MemCfg_lockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that blocks writes to the sections' configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Lock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_unlockConfig +// +//***************************************************************************** +void +MemCfg_unlockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Clear the bit that blocks writes to the sections' configuration + // registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Unlock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL)); + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_commitConfig +// +//***************************************************************************** +void +MemCfg_commitConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that permanently blocks writes to the sections' + // configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Commit configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setProtection +// +//***************************************************************************** +void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + uint32_t regOffset; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 8 bits in the corresponding ACCPROT register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 8U; + } + + // + // Calculate register offset. Also, make sure the shift value is no greater + // than 31. + // + regOffset = (shiftVal & ~(0x1FU)) >> 4U; + shiftVal &= 0x0001FU; + maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal; + regVal = protectMode << shiftVal; + + // + // Write the access protection mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal; + break; + + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setLSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel) +{ + uint32_t shiftVal; + uint32_t temp; + + // + // Check the arguments. + // + ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Calculate how far the controller select value needs to be shifted. Each + // section number is represented by a bit in the lower word of ramSection + // and 2 bits in the corresponding MSEL register. + // + shiftVal = 0U; + temp = MEMCFG_SECT_NUM_MASK & ramSection; + + while(temp != 1U) + { + temp = temp >> 1U; + shiftVal += 2U; + } + + // + // Write the controller select setting into the appropriate field + // + EALLOW; + + HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) = + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) & + ~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) | + ((uint32_t)controllerSel << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setGSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel) +{ + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS); + + // + // We only need the section number bits for this function. + // + sectionNum = ramSections & MEMCFG_SECT_NUM_MASK; + + // + // Write the controller select setting into the appropriate field. + // + EALLOW; + if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1) + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum; + } + else + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum; + } + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setTestMode +// +//***************************************************************************** +void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 2 bits in the corresponding TEST register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 2U; + } + + maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal; + regVal = (uint32_t)testMode << shiftVal; + + // + // Write the test mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal; + break; + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_initSections +// +//***************************************************************************** +void +MemCfg_initSections(uint32_t ramSections) +{ + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Set the bit in the various initialization registers that starts + // initialization. + // + EALLOW; + + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Initialize all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_MSGX_ALL; + break; + + default: + // + // Do nothing. Invalid ramSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_getInitStatus +// +//***************************************************************************** +bool +MemCfg_getInitStatus(uint32_t ramSections) +{ + uint32_t status; + + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Read registers containing the initialization complete status. + // + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE); + break; + + case MEMCFG_SECT_TYPE_LS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_GS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MSG: + status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Return the overall status. + // + if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) == + (MEMCFG_SECT_DX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) == + (MEMCFG_SECT_LSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) == + (MEMCFG_SECT_GSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) == + (MEMCFG_SECT_MSGX_ALL & MEMCFG_SECT_NUM_MASK))) + { + status = MEMCFG_SECT_NUM_MASK; + } + else + { + status = 0U; + } + break; + + default: + // + // Invalid ramSections. Make sure you aren't OR-ing values for two + // different types of RAM. + // + status = 0U; + break; + } + + return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK)); +} + +//***************************************************************************** +// +// MemCfg_getViolationAddress +// +//***************************************************************************** +uint32_t +MemCfg_getViolationAddress(uint32_t intFlag) +{ + uint32_t address; + uint32_t stsNumber; + + // + // Calculate the the address of the desired violation address register. + // + if((intFlag & MEMCFG_MVIOL_MASK) != 0U) + { + stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT; + address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR; + } + else + { + stsNumber = intFlag; + address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR; + } + + while(stsNumber > 1U) + { + stsNumber = stsNumber >> 1U; + address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR); + } + + // + // Read and return the access violation address at the calculated location. + // + return(HWREG(address)); +} + +//***************************************************************************** +// +// MemCfg_getCorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag) +{ + // + // Check the arguments. + // + if(stsFlag != MEMCFG_CERR_CPUREAD) + { + // + // Currently, the only correctable error address that can be read + // from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD). + // For the sake of keeping this function portable to possible future + // devices with other error types, it still takes a stsFlag parameter. + // + ASSERT((bool)false); + } + + // + // Read and return the error address. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR)); +} + +//***************************************************************************** +// +// MemCfg_getUncorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag) +{ + uint32_t address; + uint32_t temp; + + // + // Calculate the the address of the desired error address register. + // + address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR; + + temp = stsFlag; + + while(temp > 1U) + { + temp = temp >> 1U; + address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR); + } + + // + // Read and return the error address at the calculated location. + // + return(HWREG(address)); +} + + diff --git a/gpio_bitfield_cpu2/device/driverlib/memcfg.h b/gpio_bitfield_cpu2/device/driverlib/memcfg.h new file mode 100644 index 0000000..8a9b6fc --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/memcfg.h @@ -0,0 +1,1266 @@ +//########################################################################### +// +// FILE: memcfg.h +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MEMCFG_H +#define MEMCFG_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup memcfg_api MemCfg +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +// +// Masks to decode memory section defines. +// +#define MEMCFG_SECT_TYPE_MASK 0xFF000000U +#define MEMCFG_SECT_TYPE_D 0x00000000U +#define MEMCFG_SECT_TYPE_LS 0x01000000U +#define MEMCFG_SECT_TYPE_GS 0x02000000U +#define MEMCFG_SECT_TYPE_MSG 0x03000000U +#define MEMCFG_SECT_NUM_MASK 0x00FFFFFFU +#define MEMCFG_XACCPROTX_M ((uint32_t)MEMCFG_GSXACCPROT0_FETCHPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_DMAWRPROT_GS0) +#define MEMCFG_XTEST_M MEMCFG_DXTEST_TEST_M0_M + +// +// Used for access violation functions. +// +#define MEMCFG_NMVIOL_MASK 0x0000FFFFU +#define MEMCFG_MVIOL_MASK 0x000F0000U +#define MEMCFG_MVIOL_SHIFT 16U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(), +// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(), +// MemCfg_setCLAMemType(), MemCfg_setLSRAMControllerSel(), +// MemCfg_getInitStatus() as the memSection(s) or ramSection(s) parameter. +// +//***************************************************************************** +// +// DxRAM - Dedicated RAM config +// +#define MEMCFG_SECT_M0 0x00000001U //!< M0 RAM +#define MEMCFG_SECT_M1 0x00000002U //!< M1 RAM +#define MEMCFG_SECT_D0 0x00000004U //!< D0 RAM +#define MEMCFG_SECT_D1 0x00000008U //!< D1 RAM +#define MEMCFG_SECT_DX_ALL 0x0000000FU //!< All M and D RAM + +// +// LSxRAM - Local shared RAM config +// +#define MEMCFG_SECT_LS0 0x01000001U //!< LS0 RAM +#define MEMCFG_SECT_LS1 0x01000002U //!< LS1 RAM +#define MEMCFG_SECT_LS2 0x01000004U //!< LS2 RAM +#define MEMCFG_SECT_LS3 0x01000008U //!< LS3 RAM +#define MEMCFG_SECT_LS4 0x01000010U //!< LS4 RAM +#define MEMCFG_SECT_LS5 0x01000020U //!< LS5 RAM +#define MEMCFG_SECT_LSX_ALL 0x0100003FU //!< All LS RAM + +// +// GSxRAM - Global shared RAM config +// +#define MEMCFG_SECT_GS0 0x02000001U //!< GS0 RAM +#define MEMCFG_SECT_GS1 0x02000002U //!< GS1 RAM +#define MEMCFG_SECT_GS2 0x02000004U //!< GS2 RAM +#define MEMCFG_SECT_GS3 0x02000008U //!< GS3 RAM +#define MEMCFG_SECT_GS4 0x02000010U //!< GS4 RAM +#define MEMCFG_SECT_GS5 0x02000020U //!< GS5 RAM +#define MEMCFG_SECT_GS6 0x02000040U //!< GS6 RAM +#define MEMCFG_SECT_GS7 0x02000080U //!< GS7 RAM +#define MEMCFG_SECT_GS8 0x02000100U //!< GS8 RAM +#define MEMCFG_SECT_GS9 0x02000200U //!< GS9 RAM +#define MEMCFG_SECT_GS10 0x02000400U //!< GS10 RAM +#define MEMCFG_SECT_GS11 0x02000800U //!< GS11 RAM +#define MEMCFG_SECT_GS12 0x02001000U //!< GS12 RAM +#define MEMCFG_SECT_GS13 0x02002000U //!< GS13 RAM +#define MEMCFG_SECT_GS14 0x02004000U //!< GS14 RAM +#define MEMCFG_SECT_GS15 0x02008000U //!< GS15 RAM +#define MEMCFG_SECT_GSX_ALL 0x0200FFFFU //!< All GS RAM + +// +// MSGxRAM - Message RAM config +// +#define MEMCFG_SECT_MSGCPUTOCPU 0x03000001U //!< CPU-to-CPU message RAM +#define MEMCFG_SECT_MSGCPUTOCLA1 0x03000002U //!< CPU-to-CLA1 message RAM +#define MEMCFG_SECT_MSGCLA1TOCPU 0x03000004U //!< CLA1-to-CPU message RAM +#define MEMCFG_SECT_MSGX_ALL 0x03000007U //!< All message RAM + + +// +// All sections +// +#define MEMCFG_SECT_ALL 0xFFFFFFFFU //!< All configurable RAM + +//***************************************************************************** +// +// Values that can be passed to MemCfg_setProtection() as the protectMode +// parameter. +// +//***************************************************************************** +#define MEMCFG_PROT_ALLOWCPUFETCH 0x00000000U //!< CPU fetch allowed +#define MEMCFG_PROT_BLOCKCPUFETCH 0x00000001U //!< CPU fetch blocked + +#define MEMCFG_PROT_ALLOWCPUWRITE 0x00000000U //!< CPU write allowed +#define MEMCFG_PROT_BLOCKCPUWRITE 0x00000002U //!< CPU write blocked + +#define MEMCFG_PROT_ALLOWDMAWRITE 0x00000000U //!< DMA write allowed (GSxRAM) +#define MEMCFG_PROT_BLOCKDMAWRITE 0x00000004U //!< DMA write blocked (GSxRAM) + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_NMVIOL_CPUREAD 0x00000001U //!< Non-controller CPU read access +#define MEMCFG_NMVIOL_CPUWRITE 0x00000002U //!< Non-controller CPU write access +#define MEMCFG_NMVIOL_CPUFETCH 0x00000004U //!< Non-controller CPU fetch access +#define MEMCFG_NMVIOL_DMAWRITE 0x00000008U //!< Non-controller DMA write access +#define MEMCFG_NMVIOL_CLA1READ 0x00000010U //!< Non-controller CLA1 read access +#define MEMCFG_NMVIOL_CLA1WRITE 0x00000020U //!< Non-controller CLA1 write access +#define MEMCFG_NMVIOL_CLA1FETCH 0x00000040U //!< Non-controller CLA1 fetch access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_MVIOL_CPUFETCH 0x00010000U //!< Controller CPU fetch access +#define MEMCFG_MVIOL_CPUWRITE 0x00020000U //!< Controller CPU write access +#define MEMCFG_MVIOL_DMAWRITE 0x00040000U //!< Controller DMA write access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceCorrErrorStatus(), +// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus(). +// +// Note that MEMCFG_CERR_CPUREAD is the only value below that has a +// corresponding interrupt and may be used with the error functions that take +// an intFlag(s) parameter. +// +//***************************************************************************** +#define MEMCFG_CERR_CPUREAD 0x0001U //!< Correctable CPU read error +#define MEMCFG_CERR_DMAREAD 0x0002U //!< Correctable DMA read error +#define MEMCFG_CERR_CLA1READ 0x0004U //!< Correctable CLA1 read error +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceUncorrErrorStatus(), +// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus(). +// +//***************************************************************************** +#define MEMCFG_UCERR_CPUREAD 0x0001U //!< Uncorrectable CPU read error +#define MEMCFG_UCERR_DMAREAD 0x0002U //!< Uncorrectable DMA read error +#define MEMCFG_UCERR_CLA1READ 0x0004U //!< Uncorrectable CLA1 read error + +#endif + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory + MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory +} MemCfg_CLAMemoryType; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setLSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_LSRAMCONTROLLER_CPU_ONLY, //!< CPU is the owner of the section + MEMCFG_LSRAMCONTROLLER_CPU_CLA1 //!< CPU and CLA1 share this section +} MemCfg_LSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setGSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_GSRAMCONTROLLER_CPU1, //!< CPU1 is controller of the section + MEMCFG_GSRAMCONTROLLER_CPU2 //!< CPU2 is controller of the section +} MemCfg_GSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setTestMode() as the \e testMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Functional mode. Test mode is disabled. + MEMCFG_TEST_FUNCTIONAL = 0, + //! Writes allowed to data only + MEMCFG_TEST_WRITE_DATA = 1, + //! Writes allowed to ECC only (for DxRAM/MxRAM) + MEMCFG_TEST_WRITE_ECC = 2, + //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM) + MEMCFG_TEST_WRITE_PARITY = 2 +} MemCfg_TestMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the CLA memory type of the specified RAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param claMemType indicates data memory or program memory. +//! +//! This function sets the CLA memory type configuration of the RAM section. If +//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will +//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM +//! section will be configured as CLA program memory. +//! +//! The \e ramSections parameter is an OR of the following indicators: +//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx. +//! +//! \note This API only applies to LSx RAM and has no effect if the CLA isn't +//! controller of the memory section. +//! +//! \sa MemCfg_setLSRAControllerSel() +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType) +{ + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Write the CLA memory configuration to the appropriate register. Either + // set or clear the bit that determines the function of the RAM section as + // it relates to the CLA. + // + EALLOW; + + if(claMemType == MEMCFG_CLA_MEM_PROGRAM) + { + // + // Program memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) |= ramSections; + } + else + { + // + // Data memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) &= ~ramSections; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! This function enables the indicated RAM access violation interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableViolationInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function disables the indicated RAM access violation interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only non-controller violations may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableViolationInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) &= + ~(intFlags & MEMCFG_NMVIOL_MASK); + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) &= + ~((intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM access violation status. +//! +//! This function returns the RAM access violation status. This function will +//! return flags for both controller and non-controller access violations +//! although only the non-controller flags have the ability to cause the +//! generation of an interrupt. +//! +//! \return Returns the current violation status, enumerated as a bit field of +//! the values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//***************************************************************************** +static inline uint32_t +MemCfg_getViolationInterruptStatus(void) +{ + uint32_t status; + + // + // Read and return RAM access status flags. + // + status = (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVFLG)) | + (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) << + MEMCFG_MVIOL_SHIFT); + + return(status); +} + +//***************************************************************************** +// +//! Sets the RAM access violation status. +//! +//! \param intFlags is a bit mask of the access violation flags to be set. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function sets the RAM access violation status. This function will +//! set flags for both controller and non-controller access violations, and an +//! interrupt will be generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceViolationInterrupt(uint32_t intFlags) +{ + // + // Shift and mask the flags appropriately and write them to the + // corresponding SET register. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVSET) = + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVSET) = + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Clears RAM access violation flags. +//! +//! \param intFlags is a bit mask of the access violation flags to be cleared. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearViolationInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested access violation flags. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVCLR) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVCLR) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the correctable error threshold value. +//! +//! \param threshold is the correctable error threshold. +//! +//! This value sets the error-count threshold at which a correctable error +//! interrupt is generated. That is when the error count register reaches the +//! value specified by the \e threshold parameter, an interrupt is +//! generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCorrErrorThreshold(uint32_t threshold) +{ + // + // Write the threshold value to the appropriate register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRTHRES) = threshold; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the correctable error count. +//! +//! \return Returns the number of correctable error have occurred. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorCount(void) +{ + // + // Read and return the number of errors that have occurred. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCNT)); +} + +//***************************************************************************** +// +//! Enables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function enables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function disables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) &= ~(intFlags); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM correctable error interrupt status. +//! +//! \return Returns the current error interrupt status. Will return a value of +//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the +//! function will return 0. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorInterruptStatus(void) +{ + // + // Read and return correctable error interrupt flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTFLG)); +} + +//***************************************************************************** +// +//! Sets the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be set. Can take +//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function sets the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTSET) = intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function clears the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTCLR) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current correctable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRFLG)); +} + +//***************************************************************************** +// +//! Gets the current uncorrectable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getUncorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRFLG)); +} + +//***************************************************************************** +// +//! Sets the specified correctable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function sets the specified correctable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the specified uncorrectable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function sets the specified uncorrectable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears correctable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function clears the specified correctable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears uncorrectable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function clears the specified uncorrectable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 1-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMWaitState(void) +{ + // + // Clear the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) &= + ~((uint32_t)MEMCFG_ROMWAITSTATE_WSDISABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 0-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMWaitState(void) +{ + // + // Set the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) |= + MEMCFG_ROMWAITSTATE_WSDISABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMPrefetch(void) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) |= + MEMCFG_ROMPREFETCH_PFENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMPrefetch(void) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) &= + ~((uint32_t)MEMCFG_ROMPREFETCH_PFENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the writes to the configuration of specified memory sections. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function locks writes to the access protection and controller select +//! configuration of a memory section.That means calling MemCfg_setProtection() +//! or MemCfg_setLSRAMControllerSel() for a locked memory section will have no +//! effect until MemCfg_unlockConfig() is called. +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_lockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Unlocks the writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function unlocks writes to the access protection and controller select +//! configuration of a memory section that has been locked using +//! MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_unlockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Permanently locks writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function permanently locks writes to the access protection and +//! controller select configuration of a memory section. That means calling +//! MemCfg_setProtection() or MemCfg_setLSRAMControllerSel() for a locked memory +//! section will have no effect. To lock the configuration in a nonpermanent +//! way, use MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_commitConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Sets the access protection mode of a single memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param protectMode is the logical OR of the settings to be applied. +//! +//! This function sets the access protection mode of a specified memory section. +//! The mode is passed into the \e protectMode parameter as the logical OR of +//! the following values: +//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch +//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write +//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_D0 or \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory +//! is configured as CLA program memory. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode); + +//***************************************************************************** +// +//! Sets the controller of the specified LSxRAM section. +//! +//! \param ramSection is the LSxRAM section to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the LSxRAM +//! section. +//! If the \e controllerSel parameter is \b MEMCFG_LSRAMCONTROLLER_CPU_ONLY, +//! the LSxRAM section passed into the \e ramSection parameter will be dedicated +//! to the CPU. If \b MEMCFG_LSRAMCONTROLLER_CPU_CLA1, the memory section will +//! be shared between the CPU and the CLA. +//! +//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0 +//! through \b MEMCFG_SECT_LSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to LSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the controller of the specified GSxRAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the GSxRAM +//! section.If the \e controllerSel parameter is \b MEMCFG_GSRAMCONTROLLER_CPU1, +//! the GSRAM sections passed into the \e ramSections parameter will be +//! dedicated to CPU1. If \b MEMCFG_GSRAMCONTROLLER_CPU2, the memory section +//! will be dedicated to CPU2. +//! +//! The \e ramSections parameter should be a logical OR of values from +//! \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to GSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the test mode of the specified memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param testMode is the test mode selected. +//! +//! This function sets the test mode configuration of the RAM section. The +//! \e testMode parameter can take one of the following values: +//! - \b MEMCFG_TEST_FUNCTIONAL +//! - \b MEMCFG_TEST_WRITE_DATA +//! - \b MEMCFG_TEST_WRITE_ECC +//! - \b MEMCFG_TEST_WRITE_PARITY +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1 +//! - \b MEMCFG_SECT_D0, \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode); + +//***************************************************************************** +// +//! Starts the initialization the specified RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be initialized. +//! +//! This function starts the initialization of the specified RAM sections. Use +//! MemCfg_getInitStatus() to check if the initialization is done. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_initSections(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the status of initialized RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be checked. +//! +//! This function gets the initialization status of the RAM sections specified +//! by the \e ramSections parameter. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections. +//! +//! \note Use MemCfg_initSections() to start the initialization. +//! +//! \return Returns \b true if all the sections specified by \e ramSections +//! have been initialized and \b false if not. +// +//***************************************************************************** +extern bool +MemCfg_getInitStatus(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the violation address associated with a intFlag. +//! +//! \param intFlag is the type of access violation as indicated by ONE of +//! these values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return Returns the violation address associated with the \e intFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getViolationAddress(uint32_t intFlag); + +//***************************************************************************** +// +//! Get the correctable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. Can currently take the value \b MEMCFG_CERR_CPUREAD only. +//! Other values are reserved. +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag); + +//***************************************************************************** +// +//! Get the uncorrectable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. It may be passed one of these values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or +//! \b MEMCFG_UCERR_CLA1READ values +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MEMCFG_H diff --git a/gpio_bitfield_cpu2/device/driverlib/pin_map.h b/gpio_bitfield_cpu2/device/driverlib/pin_map.h new file mode 100644 index 0000000..95c6fa3 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/pin_map.h @@ -0,0 +1,894 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// 0x00000003 = MUX register value +// 0x0000000C = GMUX register value +// 0x0000FF00 = Shift amount within mux registers +// 0xFFFF0000 = Offset of MUX register +//***************************************************************************** + + +#define GPIO_0_GPIO0 0x00060000U +#define GPIO_0_EPWM1A 0x00060001U +#define GPIO_0_SDAA 0x00060006U + +#define GPIO_1_GPIO1 0x00060200U +#define GPIO_1_EPWM1B 0x00060201U +#define GPIO_1_MFSRB 0x00060203U +#define GPIO_1_SCLA 0x00060206U + +#define GPIO_2_GPIO2 0x00060400U +#define GPIO_2_EPWM2A 0x00060401U +#define GPIO_2_OUTPUTXBAR1 0x00060405U +#define GPIO_2_SDAB 0x00060406U + +#define GPIO_3_GPIO3 0x00060600U +#define GPIO_3_EPWM2B 0x00060601U +#define GPIO_3_OUTPUTXBAR2 0x00060602U +#define GPIO_3_MCLKRB 0x00060603U +#define GPIO_3_SCLB 0x00060606U + +#define GPIO_4_GPIO4 0x00060800U +#define GPIO_4_EPWM3A 0x00060801U +#define GPIO_4_OUTPUTXBAR3 0x00060805U +#define GPIO_4_CANTXA 0x00060806U + +#define GPIO_5_GPIO5 0x00060A00U +#define GPIO_5_EPWM3B 0x00060A01U +#define GPIO_5_MFSRA 0x00060A02U +#define GPIO_5_OUTPUTXBAR3 0x00060A03U +#define GPIO_5_CANRXA 0x00060A06U + +#define GPIO_6_GPIO6 0x00060C00U +#define GPIO_6_EPWM4A 0x00060C01U +#define GPIO_6_OUTPUTXBAR4 0x00060C02U +#define GPIO_6_EPWMSYNCO 0x00060C03U +#define GPIO_6_EQEP3A 0x00060C05U +#define GPIO_6_CANTXB 0x00060C06U + +#define GPIO_7_GPIO7 0x00060E00U +#define GPIO_7_EPWM4B 0x00060E01U +#define GPIO_7_MCLKRA 0x00060E02U +#define GPIO_7_OUTPUTXBAR5 0x00060E03U +#define GPIO_7_EQEP3B 0x00060E05U +#define GPIO_7_CANRXB 0x00060E06U + +#define GPIO_8_GPIO8 0x00061000U +#define GPIO_8_EPWM5A 0x00061001U +#define GPIO_8_CANTXB 0x00061002U +#define GPIO_8_ADCSOCAO 0x00061003U +#define GPIO_8_EQEP3S 0x00061005U +#define GPIO_8_SCITXDA 0x00061006U + +#define GPIO_9_GPIO9 0x00061200U +#define GPIO_9_EPWM5B 0x00061201U +#define GPIO_9_SCITXDB 0x00061202U +#define GPIO_9_OUTPUTXBAR6 0x00061203U +#define GPIO_9_EQEP3I 0x00061205U +#define GPIO_9_SCIRXDA 0x00061206U + +#define GPIO_10_GPIO10 0x00061400U +#define GPIO_10_EPWM6A 0x00061401U +#define GPIO_10_CANRXB 0x00061402U +#define GPIO_10_ADCSOCBO 0x00061403U +#define GPIO_10_EQEP1A 0x00061405U +#define GPIO_10_SCITXDB 0x00061406U +#define GPIO_10_UPP_WAIT 0x0006140FU + +#define GPIO_11_GPIO11 0x00061600U +#define GPIO_11_EPWM6B 0x00061601U +#define GPIO_11_SCIRXDB 0x00061602U +#define GPIO_11_OUTPUTXBAR7 0x00061603U +#define GPIO_11_EQEP1B 0x00061605U +#define GPIO_11_UPP_STRT 0x0006160FU + +#define GPIO_12_GPIO12 0x00061800U +#define GPIO_12_EPWM7A 0x00061801U +#define GPIO_12_CANTXB 0x00061802U +#define GPIO_12_MDXB 0x00061803U +#define GPIO_12_EQEP1S 0x00061805U +#define GPIO_12_SCITXDC 0x00061806U +#define GPIO_12_UPP_ENA 0x0006180FU + +#define GPIO_13_GPIO13 0x00061A00U +#define GPIO_13_EPWM7B 0x00061A01U +#define GPIO_13_CANRXB 0x00061A02U +#define GPIO_13_MDRB 0x00061A03U +#define GPIO_13_EQEP1I 0x00061A05U +#define GPIO_13_SCIRXDC 0x00061A06U +#define GPIO_13_UPP_D7 0x00061A0FU + +#define GPIO_14_GPIO14 0x00061C00U +#define GPIO_14_EPWM8A 0x00061C01U +#define GPIO_14_SCITXDB 0x00061C02U +#define GPIO_14_MCLKXB 0x00061C03U +#define GPIO_14_OUTPUTXBAR3 0x00061C06U +#define GPIO_14_UPP_D6 0x00061C0FU + +#define GPIO_15_GPIO15 0x00061E00U +#define GPIO_15_EPWM8B 0x00061E01U +#define GPIO_15_SCIRXDB 0x00061E02U +#define GPIO_15_MFSXB 0x00061E03U +#define GPIO_15_OUTPUTXBAR4 0x00061E06U +#define GPIO_15_UPP_D5 0x00061E0FU + +#define GPIO_16_GPIO16 0x00080000U +#define GPIO_16_SPISIMOA 0x00080001U +#define GPIO_16_CANTXB 0x00080002U +#define GPIO_16_OUTPUTXBAR7 0x00080003U +#define GPIO_16_EPWM9A 0x00080005U +#define GPIO_16_SD1_D1 0x00080007U +#define GPIO_16_UPP_D4 0x0008000FU + +#define GPIO_17_GPIO17 0x00080200U +#define GPIO_17_SPISOMIA 0x00080201U +#define GPIO_17_CANRXB 0x00080202U +#define GPIO_17_OUTPUTXBAR8 0x00080203U +#define GPIO_17_EPWM9B 0x00080205U +#define GPIO_17_SD1_C1 0x00080207U +#define GPIO_17_UPP_D3 0x0008020FU + +#define GPIO_18_GPIO18 0x00080400U +#define GPIO_18_SPICLKA 0x00080401U +#define GPIO_18_SCITXDB 0x00080402U +#define GPIO_18_CANRXA 0x00080403U +#define GPIO_18_EPWM10A 0x00080405U +#define GPIO_18_SD1_D2 0x00080407U +#define GPIO_18_UPP_D2 0x0008040FU + +#define GPIO_19_GPIO19 0x00080600U +#define GPIO_19_SPISTEA 0x00080601U +#define GPIO_19_SCIRXDB 0x00080602U +#define GPIO_19_CANTXA 0x00080603U +#define GPIO_19_EPWM10B 0x00080605U +#define GPIO_19_SD1_C2 0x00080607U +#define GPIO_19_UPP_D1 0x0008060FU + +#define GPIO_20_GPIO20 0x00080800U +#define GPIO_20_EQEP1A 0x00080801U +#define GPIO_20_MDXA 0x00080802U +#define GPIO_20_CANTXB 0x00080803U +#define GPIO_20_EPWM11A 0x00080805U +#define GPIO_20_SD1_D3 0x00080807U +#define GPIO_20_UPP_D0 0x0008080FU + +#define GPIO_21_GPIO21 0x00080A00U +#define GPIO_21_EQEP1B 0x00080A01U +#define GPIO_21_MDRA 0x00080A02U +#define GPIO_21_CANRXB 0x00080A03U +#define GPIO_21_EPWM11B 0x00080A05U +#define GPIO_21_SD1_C3 0x00080A07U +#define GPIO_21_UPP_CLK 0x00080A0FU + +#define GPIO_22_GPIO22 0x00080C00U +#define GPIO_22_EQEP1S 0x00080C01U +#define GPIO_22_MCLKXA 0x00080C02U +#define GPIO_22_SCITXDB 0x00080C03U +#define GPIO_22_EPWM12A 0x00080C05U +#define GPIO_22_SPICLKB 0x00080C06U +#define GPIO_22_SD1_D4 0x00080C07U + +#define GPIO_23_GPIO23 0x00080E00U +#define GPIO_23_EQEP1I 0x00080E01U +#define GPIO_23_MFSXA 0x00080E02U +#define GPIO_23_SCIRXDB 0x00080E03U +#define GPIO_23_EPWM12B 0x00080E05U +#define GPIO_23_SPISTEB 0x00080E06U +#define GPIO_23_SD1_C4 0x00080E07U + +#define GPIO_24_GPIO24 0x00081000U +#define GPIO_24_OUTPUTXBAR1 0x00081001U +#define GPIO_24_EQEP2A 0x00081002U +#define GPIO_24_MDXB 0x00081003U +#define GPIO_24_SPISIMOB 0x00081006U +#define GPIO_24_SD2_D1 0x00081007U + +#define GPIO_25_GPIO25 0x00081200U +#define GPIO_25_OUTPUTXBAR2 0x00081201U +#define GPIO_25_EQEP2B 0x00081202U +#define GPIO_25_MDRB 0x00081203U +#define GPIO_25_SPISOMIB 0x00081206U +#define GPIO_25_SD2_C1 0x00081207U + +#define GPIO_26_GPIO26 0x00081400U +#define GPIO_26_OUTPUTXBAR3 0x00081401U +#define GPIO_26_EQEP2I 0x00081402U +#define GPIO_26_MCLKXB 0x00081403U +#define GPIO_26_SPICLKB 0x00081406U +#define GPIO_26_SD2_D2 0x00081407U + +#define GPIO_27_GPIO27 0x00081600U +#define GPIO_27_OUTPUTXBAR4 0x00081601U +#define GPIO_27_EQEP2S 0x00081602U +#define GPIO_27_MFSXB 0x00081603U +#define GPIO_27_SPISTEB 0x00081606U +#define GPIO_27_SD2_C2 0x00081607U + +#define GPIO_28_GPIO28 0x00081800U +#define GPIO_28_SCIRXDA 0x00081801U +#define GPIO_28_EM1CS4N 0x00081802U +#define GPIO_28_OUTPUTXBAR5 0x00081805U +#define GPIO_28_EQEP3A 0x00081806U +#define GPIO_28_SD2_D3 0x00081807U + +#define GPIO_29_GPIO29 0x00081A00U +#define GPIO_29_SCITXDA 0x00081A01U +#define GPIO_29_EM1SDCKE 0x00081A02U +#define GPIO_29_OUTPUTXBAR6 0x00081A05U +#define GPIO_29_EQEP3B 0x00081A06U +#define GPIO_29_SD2_C3 0x00081A07U + +#define GPIO_30_GPIO30 0x00081C00U +#define GPIO_30_CANRXA 0x00081C01U +#define GPIO_30_EM1CLK 0x00081C02U +#define GPIO_30_OUTPUTXBAR7 0x00081C05U +#define GPIO_30_EQEP3S 0x00081C06U +#define GPIO_30_SD2_D4 0x00081C07U + +#define GPIO_31_GPIO31 0x00081E00U +#define GPIO_31_CANTXA 0x00081E01U +#define GPIO_31_EM1WEN 0x00081E02U +#define GPIO_31_OUTPUTXBAR8 0x00081E05U +#define GPIO_31_EQEP3I 0x00081E06U +#define GPIO_31_SD2_C4 0x00081E07U + +#define GPIO_32_GPIO32 0x00460000U +#define GPIO_32_SDAA 0x00460001U +#define GPIO_32_EM1CS0N 0x00460002U + +#define GPIO_33_GPIO33 0x00460200U +#define GPIO_33_SCLA 0x00460201U +#define GPIO_33_EM1RNW 0x00460202U + +#define GPIO_34_GPIO34 0x00460400U +#define GPIO_34_OUTPUTXBAR1 0x00460401U +#define GPIO_34_EM1CS2N 0x00460402U +#define GPIO_34_SDAB 0x00460406U +#define GPIO_34_OFSD_2_N 0x0046040FU + +#define GPIO_35_GPIO35 0x00460600U +#define GPIO_35_SCIRXDA 0x00460601U +#define GPIO_35_EM1CS3N 0x00460602U +#define GPIO_35_SCLB 0x00460606U +#define GPIO_35_IID 0x0046060FU + +#define GPIO_36_GPIO36 0x00460800U +#define GPIO_36_SCITXDA 0x00460801U +#define GPIO_36_EM1WAIT 0x00460802U +#define GPIO_36_CANRXA 0x00460806U +#define GPIO_36_ISESSEND 0x0046080FU + +#define GPIO_37_GPIO37 0x00460A00U +#define GPIO_37_OUTPUTXBAR2 0x00460A01U +#define GPIO_37_EM1OEN 0x00460A02U +#define GPIO_37_CANTXA 0x00460A06U +#define GPIO_37_IAVALID 0x00460A0FU + +#define GPIO_38_GPIO38 0x00460C00U +#define GPIO_38_EM1A0 0x00460C02U +#define GPIO_38_SCITXDC 0x00460C05U +#define GPIO_38_CANTXB 0x00460C06U + +#define GPIO_39_GPIO39 0x00460E00U +#define GPIO_39_EM1A1 0x00460E02U +#define GPIO_39_SCIRXDC 0x00460E05U +#define GPIO_39_CANRXB 0x00460E06U + +#define GPIO_40_GPIO40 0x00461000U +#define GPIO_40_EM1A2 0x00461002U +#define GPIO_40_SDAB 0x00461006U + +#define GPIO_41_GPIO41 0x00461200U +#define GPIO_41_EM1A3 0x00461202U +#define GPIO_41_EMU1 0x00461203U +#define GPIO_41_SCLB 0x00461206U + +#define GPIO_42_GPIO42 0x00461400U +#define GPIO_42_SDAA 0x00461406U +#define GPIO_42_SCITXDA 0x0046140FU + +#define GPIO_43_GPIO43 0x00461600U +#define GPIO_43_SCLA 0x00461606U +#define GPIO_43_SCIRXDA 0x0046160FU + +#define GPIO_44_GPIO44 0x00461800U +#define GPIO_44_EM1A4 0x00461802U +#define GPIO_44_IXRCV 0x0046180FU + +#define GPIO_45_GPIO45 0x00461A00U +#define GPIO_45_EM1A5 0x00461A02U +#define GPIO_45_IDM 0x00461A0FU + +#define GPIO_46_GPIO46 0x00461C00U +#define GPIO_46_EM1A6 0x00461C02U +#define GPIO_46_SCIRXDD 0x00461C06U +#define GPIO_46_IDP 0x00461C0FU + +#define GPIO_47_GPIO47 0x00461E00U +#define GPIO_47_EM1A7 0x00461E02U +#define GPIO_47_SCITXDD 0x00461E06U +#define GPIO_47_OFSD_1_N 0x00461E0FU + +#define GPIO_48_GPIO48 0x00480000U +#define GPIO_48_OUTPUTXBAR3 0x00480001U +#define GPIO_48_EM1A8 0x00480002U +#define GPIO_48_SCITXDA 0x00480006U +#define GPIO_48_SD1_D1 0x00480007U + +#define GPIO_49_GPIO49 0x00480200U +#define GPIO_49_OUTPUTXBAR4 0x00480201U +#define GPIO_49_EM1A9 0x00480202U +#define GPIO_49_SCIRXDA 0x00480206U +#define GPIO_49_SD1_C1 0x00480207U + +#define GPIO_50_GPIO50 0x00480400U +#define GPIO_50_EQEP1A 0x00480401U +#define GPIO_50_EM1A10 0x00480402U +#define GPIO_50_SPISIMOC 0x00480406U +#define GPIO_50_SD1_D2 0x00480407U + +#define GPIO_51_GPIO51 0x00480600U +#define GPIO_51_EQEP1B 0x00480601U +#define GPIO_51_EM1A11 0x00480602U +#define GPIO_51_SPISOMIC 0x00480606U +#define GPIO_51_SD1_C2 0x00480607U + +#define GPIO_52_GPIO52 0x00480800U +#define GPIO_52_EQEP1S 0x00480801U +#define GPIO_52_EM1A12 0x00480802U +#define GPIO_52_SPICLKC 0x00480806U +#define GPIO_52_SD1_D3 0x00480807U + +#define GPIO_53_GPIO53 0x00480A00U +#define GPIO_53_EQEP1I 0x00480A01U +#define GPIO_53_EM1D31 0x00480A02U +#define GPIO_53_EM2D15 0x00480A03U +#define GPIO_53_SPISTEC 0x00480A06U +#define GPIO_53_SD1_C3 0x00480A07U + +#define GPIO_54_GPIO54 0x00480C00U +#define GPIO_54_SPISIMOA 0x00480C01U +#define GPIO_54_EM1D30 0x00480C02U +#define GPIO_54_EM2D14 0x00480C03U +#define GPIO_54_EQEP2A 0x00480C05U +#define GPIO_54_SCITXDB 0x00480C06U +#define GPIO_54_SD1_D4 0x00480C07U + +#define GPIO_55_GPIO55 0x00480E00U +#define GPIO_55_SPISOMIA 0x00480E01U +#define GPIO_55_EM1D29 0x00480E02U +#define GPIO_55_EM2D13 0x00480E03U +#define GPIO_55_EQEP2B 0x00480E05U +#define GPIO_55_SCIRXDB 0x00480E06U +#define GPIO_55_SD1_C4 0x00480E07U + +#define GPIO_56_GPIO56 0x00481000U +#define GPIO_56_SPICLKA 0x00481001U +#define GPIO_56_EM1D28 0x00481002U +#define GPIO_56_EM2D12 0x00481003U +#define GPIO_56_EQEP2S 0x00481005U +#define GPIO_56_SCITXDC 0x00481006U +#define GPIO_56_SD2_D1 0x00481007U + +#define GPIO_57_GPIO57 0x00481200U +#define GPIO_57_SPISTEA 0x00481201U +#define GPIO_57_EM1D27 0x00481202U +#define GPIO_57_EM2D11 0x00481203U +#define GPIO_57_EQEP2I 0x00481205U +#define GPIO_57_SCIRXDC 0x00481206U +#define GPIO_57_SD2_C1 0x00481207U + +#define GPIO_58_GPIO58 0x00481400U +#define GPIO_58_MCLKRA 0x00481401U +#define GPIO_58_EM1D26 0x00481402U +#define GPIO_58_EM2D10 0x00481403U +#define GPIO_58_OUTPUTXBAR1 0x00481405U +#define GPIO_58_SPICLKB 0x00481406U +#define GPIO_58_SD2_D2 0x00481407U +#define GPIO_58_SPISIMOA 0x0048140FU + +#define GPIO_59_GPIO59 0x00481600U +#define GPIO_59_MFSRA 0x00481601U +#define GPIO_59_EM1D25 0x00481602U +#define GPIO_59_EM2D9 0x00481603U +#define GPIO_59_OUTPUTXBAR2 0x00481605U +#define GPIO_59_SPISTEB 0x00481606U +#define GPIO_59_SD2_C2 0x00481607U +#define GPIO_59_SPISOMIA 0x0048160FU + +#define GPIO_60_GPIO60 0x00481800U +#define GPIO_60_MCLKRB 0x00481801U +#define GPIO_60_EM1D24 0x00481802U +#define GPIO_60_EM2D8 0x00481803U +#define GPIO_60_OUTPUTXBAR3 0x00481805U +#define GPIO_60_SPISIMOB 0x00481806U +#define GPIO_60_SD2_D3 0x00481807U +#define GPIO_60_SPICLKA 0x0048180FU + +#define GPIO_61_GPIO61 0x00481A00U +#define GPIO_61_MFSRB 0x00481A01U +#define GPIO_61_EM1D23 0x00481A02U +#define GPIO_61_EM2D7 0x00481A03U +#define GPIO_61_OUTPUTXBAR4 0x00481A05U +#define GPIO_61_SPISOMIB 0x00481A06U +#define GPIO_61_SD2_C3 0x00481A07U +#define GPIO_61_SPISTEA 0x00481A0FU + +#define GPIO_62_GPIO62 0x00481C00U +#define GPIO_62_SCIRXDC 0x00481C01U +#define GPIO_62_EM1D22 0x00481C02U +#define GPIO_62_EM2D6 0x00481C03U +#define GPIO_62_EQEP3A 0x00481C05U +#define GPIO_62_CANRXA 0x00481C06U +#define GPIO_62_SD2_D4 0x00481C07U + +#define GPIO_63_GPIO63 0x00481E00U +#define GPIO_63_SCITXDC 0x00481E01U +#define GPIO_63_EM1D21 0x00481E02U +#define GPIO_63_EM2D5 0x00481E03U +#define GPIO_63_EQEP3B 0x00481E05U +#define GPIO_63_CANTXA 0x00481E06U +#define GPIO_63_SD2_C4 0x00481E07U +#define GPIO_63_SPISIMOB 0x00481E0FU + +#define GPIO_64_GPIO64 0x00860000U +#define GPIO_64_EM1D20 0x00860002U +#define GPIO_64_EM2D4 0x00860003U +#define GPIO_64_EQEP3S 0x00860005U +#define GPIO_64_SCIRXDA 0x00860006U +#define GPIO_64_SPISOMIB 0x0086000FU + +#define GPIO_65_GPIO65 0x00860200U +#define GPIO_65_EM1D19 0x00860202U +#define GPIO_65_EM2D3 0x00860203U +#define GPIO_65_EQEP3I 0x00860205U +#define GPIO_65_SCITXDA 0x00860206U +#define GPIO_65_SPICLKB 0x0086020FU + +#define GPIO_66_GPIO66 0x00860400U +#define GPIO_66_EM1D18 0x00860402U +#define GPIO_66_EM2D2 0x00860403U +#define GPIO_66_SDAB 0x00860406U +#define GPIO_66_SPISTEB 0x0086040FU + +#define GPIO_67_GPIO67 0x00860600U +#define GPIO_67_EM1D17 0x00860602U +#define GPIO_67_EM2D1 0x00860603U + +#define GPIO_68_GPIO68 0x00860800U +#define GPIO_68_EM1D16 0x00860802U +#define GPIO_68_EM2D0 0x00860803U + +#define GPIO_69_GPIO69 0x00860A00U +#define GPIO_69_EM1D15 0x00860A02U +#define GPIO_69_EMU0 0x00860A03U +#define GPIO_69_SCLB 0x00860A06U +#define GPIO_69_SPISIMOC 0x00860A0FU + +#define GPIO_70_GPIO70 0x00860C00U +#define GPIO_70_EM1D14 0x00860C02U +#define GPIO_70_EMU0 0x00860C03U +#define GPIO_70_CANRXA 0x00860C05U +#define GPIO_70_SCITXDB 0x00860C06U +#define GPIO_70_SPISOMIC 0x00860C0FU + +#define GPIO_71_GPIO71 0x00860E00U +#define GPIO_71_EM1D13 0x00860E02U +#define GPIO_71_EMU1 0x00860E03U +#define GPIO_71_CANTXA 0x00860E05U +#define GPIO_71_SCIRXDB 0x00860E06U +#define GPIO_71_SPICLKC 0x00860E0FU + +#define GPIO_72_GPIO72 0x00861000U +#define GPIO_72_EM1D12 0x00861002U +#define GPIO_72_CANTXB 0x00861005U +#define GPIO_72_SCITXDC 0x00861006U +#define GPIO_72_SPISTEC 0x0086100FU + +#define GPIO_73_GPIO73 0x00861200U +#define GPIO_73_EM1D11 0x00861202U +#define GPIO_73_XCLKOUT 0x00861203U +#define GPIO_73_CANRXB 0x00861205U +#define GPIO_73_SCIRXDC 0x00861206U + +#define GPIO_74_GPIO74 0x00861400U +#define GPIO_74_EM1D10 0x00861402U + +#define GPIO_75_GPIO75 0x00861600U +#define GPIO_75_EM1D9 0x00861602U + +#define GPIO_76_GPIO76 0x00861800U +#define GPIO_76_EM1D8 0x00861802U +#define GPIO_76_SCITXDD 0x00861806U + +#define GPIO_77_GPIO77 0x00861A00U +#define GPIO_77_EM1D7 0x00861A02U +#define GPIO_77_SCIRXDD 0x00861A06U + +#define GPIO_78_GPIO78 0x00861C00U +#define GPIO_78_EM1D6 0x00861C02U +#define GPIO_78_EQEP2A 0x00861C06U + +#define GPIO_79_GPIO79 0x00861E00U +#define GPIO_79_EM1D5 0x00861E02U +#define GPIO_79_EQEP2B 0x00861E06U + +#define GPIO_80_GPIO80 0x00880000U +#define GPIO_80_EM1D4 0x00880002U +#define GPIO_80_EQEP2S 0x00880006U + +#define GPIO_81_GPIO81 0x00880200U +#define GPIO_81_EM1D3 0x00880202U +#define GPIO_81_EQEP2I 0x00880206U + +#define GPIO_82_GPIO82 0x00880400U +#define GPIO_82_EM1D2 0x00880402U + +#define GPIO_83_GPIO83 0x00880600U +#define GPIO_83_EM1D1 0x00880602U + +#define GPIO_84_GPIO84 0x00880800U +#define GPIO_84_SCITXDA 0x00880805U +#define GPIO_84_MDXB 0x00880806U +#define GPIO_84_MDXA 0x0088080FU + +#define GPIO_85_GPIO85 0x00880A00U +#define GPIO_85_EM1D0 0x00880A02U +#define GPIO_85_SCIRXDA 0x00880A05U +#define GPIO_85_MDRB 0x00880A06U +#define GPIO_85_MDRA 0x00880A0FU + +#define GPIO_86_GPIO86 0x00880C00U +#define GPIO_86_EM1A13 0x00880C02U +#define GPIO_86_EM1CAS 0x00880C03U +#define GPIO_86_SCITXDB 0x00880C05U +#define GPIO_86_MCLKXB 0x00880C06U +#define GPIO_86_MCLKXA 0x00880C0FU + +#define GPIO_87_GPIO87 0x00880E00U +#define GPIO_87_EM1A14 0x00880E02U +#define GPIO_87_EM1RAS 0x00880E03U +#define GPIO_87_SCIRXDB 0x00880E05U +#define GPIO_87_MFSXB 0x00880E06U +#define GPIO_87_MFSXA 0x00880E0FU + +#define GPIO_88_GPIO88 0x00881000U +#define GPIO_88_EM1A15 0x00881002U +#define GPIO_88_EM1DQM0 0x00881003U + +#define GPIO_89_GPIO89 0x00881200U +#define GPIO_89_EM1A16 0x00881202U +#define GPIO_89_EM1DQM1 0x00881203U +#define GPIO_89_SCITXDC 0x00881206U + +#define GPIO_90_GPIO90 0x00881400U +#define GPIO_90_EM1A17 0x00881402U +#define GPIO_90_EM1DQM2 0x00881403U +#define GPIO_90_SCIRXDC 0x00881406U + +#define GPIO_91_GPIO91 0x00881600U +#define GPIO_91_EM1A18 0x00881602U +#define GPIO_91_EM1DQM3 0x00881603U +#define GPIO_91_SDAA 0x00881606U + +#define GPIO_92_GPIO92 0x00881800U +#define GPIO_92_EM1A19 0x00881802U +#define GPIO_92_EM1BA1 0x00881803U +#define GPIO_92_SCLA 0x00881806U + +#define GPIO_93_GPIO93 0x00881A00U +#define GPIO_93_EM1A20 0x00881A02U +#define GPIO_93_EM1BA0 0x00881A03U +#define GPIO_93_SCITXDD 0x00881A06U + +#define GPIO_94_GPIO94 0x00881C00U +#define GPIO_94_EM1A21 0x00881C02U +#define GPIO_94_SCIRXDD 0x00881C06U + +#define GPIO_95_GPIO95 0x00881E00U + +#define GPIO_96_GPIO96 0x00C60000U +#define GPIO_96_EM2DQM1 0x00C60003U +#define GPIO_96_EQEP1A 0x00C60005U + +#define GPIO_97_GPIO97 0x00C60200U +#define GPIO_97_EM2DQM0 0x00C60203U +#define GPIO_97_EQEP1B 0x00C60205U + +#define GPIO_98_GPIO98 0x00C60400U +#define GPIO_98_EM2A0 0x00C60403U +#define GPIO_98_EQEP1S 0x00C60405U + +#define GPIO_99_GPIO99 0x00C60600U +#define GPIO_99_EM2A1 0x00C60603U +#define GPIO_99_EQEP1I 0x00C60605U + +#define GPIO_100_GPIO100 0x00C60800U +#define GPIO_100_EM2A2 0x00C60803U +#define GPIO_100_EQEP2A 0x00C60805U +#define GPIO_100_SPISIMOC 0x00C60806U + +#define GPIO_101_GPIO101 0x00C60A00U +#define GPIO_101_EM2A3 0x00C60A03U +#define GPIO_101_EQEP2B 0x00C60A05U +#define GPIO_101_SPISOMIC 0x00C60A06U + +#define GPIO_102_GPIO102 0x00C60C00U +#define GPIO_102_EM2A4 0x00C60C03U +#define GPIO_102_EQEP2S 0x00C60C05U +#define GPIO_102_SPICLKC 0x00C60C06U + +#define GPIO_103_GPIO103 0x00C60E00U +#define GPIO_103_EM2A5 0x00C60E03U +#define GPIO_103_EQEP2I 0x00C60E05U +#define GPIO_103_SPISTEC 0x00C60E06U + +#define GPIO_104_GPIO104 0x00C61000U +#define GPIO_104_SDAA 0x00C61001U +#define GPIO_104_EM2A6 0x00C61003U +#define GPIO_104_EQEP3A 0x00C61005U +#define GPIO_104_SCITXDD 0x00C61006U + +#define GPIO_105_GPIO105 0x00C61200U +#define GPIO_105_SCLA 0x00C61201U +#define GPIO_105_EM2A7 0x00C61203U +#define GPIO_105_EQEP3B 0x00C61205U +#define GPIO_105_SCIRXDD 0x00C61206U + +#define GPIO_106_GPIO106 0x00C61400U +#define GPIO_106_EM2A8 0x00C61403U +#define GPIO_106_EQEP3S 0x00C61405U +#define GPIO_106_SCITXDC 0x00C61406U + +#define GPIO_107_GPIO107 0x00C61600U +#define GPIO_107_EM2A9 0x00C61603U +#define GPIO_107_EQEP3I 0x00C61605U +#define GPIO_107_SCIRXDC 0x00C61606U + +#define GPIO_108_GPIO108 0x00C61800U +#define GPIO_108_EM2A10 0x00C61803U + +#define GPIO_109_GPIO109 0x00C61A00U +#define GPIO_109_EM2A11 0x00C61A03U + +#define GPIO_110_GPIO110 0x00C61C00U +#define GPIO_110_EM2WAIT 0x00C61C03U + +#define GPIO_111_GPIO111 0x00C61E00U +#define GPIO_111_EM2BA0 0x00C61E03U + +#define GPIO_112_GPIO112 0x00C80000U +#define GPIO_112_EM2BA1 0x00C80003U + +#define GPIO_113_GPIO113 0x00C80200U +#define GPIO_113_EM2CAS 0x00C80203U + +#define GPIO_114_GPIO114 0x00C80400U +#define GPIO_114_EM2RAS 0x00C80403U + +#define GPIO_115_GPIO115 0x00C80600U +#define GPIO_115_EM2CS0N 0x00C80603U + +#define GPIO_116_GPIO116 0x00C80800U +#define GPIO_116_EM2CS2N 0x00C80803U + +#define GPIO_117_GPIO117 0x00C80A00U +#define GPIO_117_EM2SDCKE 0x00C80A03U + +#define GPIO_118_GPIO118 0x00C80C00U +#define GPIO_118_EM2CLK 0x00C80C03U + +#define GPIO_119_GPIO119 0x00C80E00U +#define GPIO_119_EM2RNW 0x00C80E03U + +#define GPIO_120_GPIO120 0x00C81000U +#define GPIO_120_EM2WEN 0x00C81003U +#define GPIO_120_USB0PFLT 0x00C8100FU + +#define GPIO_121_GPIO121 0x00C81200U +#define GPIO_121_EM2OEN 0x00C81203U +#define GPIO_121_USB0EPEN 0x00C8120FU + +#define GPIO_122_GPIO122 0x00C81400U +#define GPIO_122_SPISIMOC 0x00C81406U +#define GPIO_122_SD1_D1 0x00C81407U +#define GPIO_122_ODISCHRGVBUS 0x00C8140FU + +#define GPIO_123_GPIO123 0x00C81600U +#define GPIO_123_SPISOMIC 0x00C81606U +#define GPIO_123_SD1_C1 0x00C81607U +#define GPIO_123_OCHRGVBUS 0x00C8160FU + +#define GPIO_124_GPIO124 0x00C81800U +#define GPIO_124_SPICLKC 0x00C81806U +#define GPIO_124_SD1_D2 0x00C81807U +#define GPIO_124_ODMPULLDN 0x00C8180FU + +#define GPIO_125_GPIO125 0x00C81A00U +#define GPIO_125_SPISTEC 0x00C81A06U +#define GPIO_125_SD1_C2 0x00C81A07U +#define GPIO_125_ODPPULLDN 0x00C81A0FU + +#define GPIO_126_GPIO126 0x00C81C00U +#define GPIO_126_SD1_D3 0x00C81C07U +#define GPIO_126_OLSD_2_N 0x00C81C0FU + +#define GPIO_127_GPIO127 0x00C81E00U +#define GPIO_127_SD1_C3 0x00C81E07U +#define GPIO_127_OLSD_1_N 0x00C81E0FU + +#define GPIO_128_GPIO128 0x01060000U +#define GPIO_128_SD1_D4 0x01060007U +#define GPIO_128_OIDPULLUP 0x0106000FU + +#define GPIO_129_GPIO129 0x01060200U +#define GPIO_129_SD1_C4 0x01060207U +#define GPIO_129_OSPEED 0x0106020FU + +#define GPIO_130_GPIO130 0x01060400U +#define GPIO_130_SD2_D1 0x01060407U +#define GPIO_130_OSUSPEND 0x0106040FU + +#define GPIO_131_GPIO131 0x01060600U +#define GPIO_131_SD2_C1 0x01060607U +#define GPIO_131_OOE 0x0106060FU + +#define GPIO_132_GPIO132 0x01060800U +#define GPIO_132_SD2_D2 0x01060807U +#define GPIO_132_ODMSE1 0x0106080FU + +#define GPIO_133_GPIO133 0x01060A00U +#define GPIO_133_SD2_C2 0x01060A07U +#define GPIO_133_ODPDAT 0x01060A0FU + +#define GPIO_134_GPIO134 0x01060C00U +#define GPIO_134_SD2_D3 0x01060C07U +#define GPIO_134_IVBUSVALID 0x01060C0FU + +#define GPIO_135_GPIO135 0x01060E00U +#define GPIO_135_SCITXDA 0x01060E06U +#define GPIO_135_SD2_C3 0x01060E07U + +#define GPIO_136_GPIO136 0x01061000U +#define GPIO_136_SCIRXDA 0x01061006U +#define GPIO_136_SD2_D4 0x01061007U + +#define GPIO_137_GPIO137 0x01061200U +#define GPIO_137_SCITXDB 0x01061206U +#define GPIO_137_SD2_C4 0x01061207U + +#define GPIO_138_GPIO138 0x01061400U +#define GPIO_138_SCIRXDB 0x01061406U + +#define GPIO_139_GPIO139 0x01061600U +#define GPIO_139_SCIRXDC 0x01061606U + +#define GPIO_140_GPIO140 0x01061800U +#define GPIO_140_SCITXDC 0x01061806U + +#define GPIO_141_GPIO141 0x01061A00U +#define GPIO_141_SCIRXDD 0x01061A06U + +#define GPIO_142_GPIO142 0x01061C00U +#define GPIO_142_SCITXDD 0x01061C06U + +#define GPIO_143_GPIO143 0x01061E00U + +#define GPIO_144_GPIO144 0x01080000U + +#define GPIO_145_GPIO145 0x01080200U +#define GPIO_145_EPWM1A 0x01080201U + +#define GPIO_146_GPIO146 0x01080400U +#define GPIO_146_EPWM1B 0x01080401U + +#define GPIO_147_GPIO147 0x01080600U +#define GPIO_147_EPWM2A 0x01080601U + +#define GPIO_148_GPIO148 0x01080800U +#define GPIO_148_EPWM2B 0x01080801U + +#define GPIO_149_GPIO149 0x01080A00U +#define GPIO_149_EPWM3A 0x01080A01U + +#define GPIO_150_GPIO150 0x01080C00U +#define GPIO_150_EPWM3B 0x01080C01U + +#define GPIO_151_GPIO151 0x01080E00U +#define GPIO_151_EPWM4A 0x01080E01U + +#define GPIO_152_GPIO152 0x01081000U +#define GPIO_152_EPWM4B 0x01081001U + +#define GPIO_153_GPIO153 0x01081200U +#define GPIO_153_EPWM5A 0x01081201U + +#define GPIO_154_GPIO154 0x01081400U +#define GPIO_154_EPWM5B 0x01081401U + +#define GPIO_155_GPIO155 0x01081600U +#define GPIO_155_EPWM6A 0x01081601U + +#define GPIO_156_GPIO156 0x01081800U +#define GPIO_156_EPWM6B 0x01081801U + +#define GPIO_157_GPIO157 0x01081A00U +#define GPIO_157_EPWM7A 0x01081A01U + +#define GPIO_158_GPIO158 0x01081C00U +#define GPIO_158_EPWM7B 0x01081C01U + +#define GPIO_159_GPIO159 0x01081E00U +#define GPIO_159_EPWM8A 0x01081E01U + +#define GPIO_160_GPIO160 0x01460000U +#define GPIO_160_EPWM8B 0x01460001U + +#define GPIO_161_GPIO161 0x01460200U +#define GPIO_161_EPWM9A 0x01460201U + +#define GPIO_162_GPIO162 0x01460400U +#define GPIO_162_EPWM9B 0x01460401U + +#define GPIO_163_GPIO163 0x01460600U +#define GPIO_163_EPWM10A 0x01460601U + +#define GPIO_164_GPIO164 0x01460800U +#define GPIO_164_EPWM10B 0x01460801U + +#define GPIO_165_GPIO165 0x01460A00U +#define GPIO_165_EPWM11A 0x01460A01U + +#define GPIO_166_GPIO166 0x01460C00U +#define GPIO_166_EPWM11B 0x01460C01U + +#define GPIO_167_GPIO167 0x01460E00U +#define GPIO_167_EPWM12A 0x01460E01U + +#define GPIO_168_GPIO168 0x01461000U +#define GPIO_168_EPWM12B 0x01461001U + +#endif // PIN_MAP_H diff --git a/gpio_bitfield_cpu2/device/driverlib/pin_map_legacy.h b/gpio_bitfield_cpu2/device/driverlib/pin_map_legacy.h new file mode 100644 index 0000000..c503ad4 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/pin_map_legacy.h @@ -0,0 +1,95 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Legacy definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_LEGACY_H__ +#define __PIN_MAP_LEGACY_H__ + + +#include "pin_map.h" + +//***************************************************************************** +// Legacy pinmuxing MACROS - Retained for portability across devices ONLY +// Not recommended for new users +//***************************************************************************** +#define GPIO_16_SD_D1 GPIO_16_SD1_D1 + +#define GPIO_17_SD_C1 GPIO_17_SD1_C1 + +#define GPIO_18_SD_D2 GPIO_18_SD1_D2 + +#define GPIO_19_SD_C2 GPIO_19_SD1_C2 + +#define GPIO_20_SD_D3 GPIO_20_SD1_D3 + +#define GPIO_21_SD_C3 GPIO_21_SD1_C3 + +#define GPIO_22_SD_D4 GPIO_22_SD1_D4 + +#define GPIO_23_SD_C4 GPIO_23_SD1_C4 + +#define GPIO_24_SD_D5 GPIO_24_SD2_D1 + +#define GPIO_25_SD_C5 GPIO_25_SD2_C1 + +#define GPIO_26_SD_D6 GPIO_26_SD2_D2 + +#define GPIO_27_SD_C6 GPIO_27_SD2_C2 + +#define GPIO_28_SD_D7 GPIO_28_SD2_D3 + +#define GPIO_29_SD_C7 GPIO_29_SD2_C3 + +#define GPIO_30_SD_D8 GPIO_30_SD2_D4 + +#define GPIO_31_SD_C8 GPIO_31_SD2_C4 + +#define GPIO_36_EM1WAIT1 GPIO_36_EM1WAIT + +#define GPIO_110_EM2WAIT1 GPIO_110_EM2WAIT + +#define GPIO_115_EM2CS0 GPIO_115_EM2CS0N + +#define GPIO_116_EM2CS2 GPIO_116_EM2CS2N + +#define GPIO_132_ODMSE0 GPIO_132_ODMSE1 + +#endif // __PIN_MAP_LEGACY_H__ diff --git a/gpio_bitfield_cpu2/device/driverlib/sci.c b/gpio_bitfield_cpu2/device/driverlib/sci.c new file mode 100644 index 0000000..dfd8e30 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sci.c @@ -0,0 +1,421 @@ +//########################################################################### +// +// FILE: sci.c +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sci.h" + +//***************************************************************************** +// +// SCI_setConfig +// +//***************************************************************************** +void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config) +{ + uint32_t divider; + + // + // Check the arguments. + // Is the required baud rate greater than the maximum rate supported? + // + ASSERT(SCI_isBaseValid(base)); + ASSERT(baud != 0U); + ASSERT((baud * 16U) <= lspclkHz); + + // + // Stop the SCI. + // + SCI_disableModule(base); + + // + // Compute the baud rate divider. + // + divider = ((lspclkHz / (baud * 8U)) - 1U); + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; + + // + // Set parity, data length, and number of stop bits. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK)) | config); + + // + // Start the SCI. + // + SCI_enableModule(base); +} + +//***************************************************************************** +// +// SCI_writeCharArray +// +//***************************************************************************** +void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } + else + { + // + // FIFO is not enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } +} + +//***************************************************************************** +// +// SCI_readCharArray +// +//***************************************************************************** +void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } + else + { + // + // FIFO is not enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive buffer. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } +} + +//***************************************************************************** +// +// SCI_enableInterrupt +// +//***************************************************************************** +void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_disableInterrupt +// +//***************************************************************************** +void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SCI_getInterruptStatus(uint32_t base) +{ + uint32_t interruptStatus = 0; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the interrupt status. + // + if((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == SCI_CTL2_TXRDY) + { + interruptStatus |= SCI_INT_TXRDY; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXERROR) == SCI_RXST_RXERROR) + { + interruptStatus |= SCI_INT_RXERR; + } + if(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == SCI_RXST_RXRDY) || + ((HWREGH(base + SCI_O_RXST) & SCI_RXST_BRKDT) == SCI_RXST_BRKDT)) + { + interruptStatus |= SCI_INT_RXRDY_BRKDT; + } + if((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFINT) == SCI_FFTX_TXFFINT) + { + interruptStatus |= SCI_INT_TXFF; + } + if((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFINT) == SCI_FFRX_RXFFINT) + { + interruptStatus |= SCI_INT_RXFF; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_FE) == SCI_RXST_FE) + { + interruptStatus |= SCI_INT_FE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_OE) == SCI_RXST_OE) + { + interruptStatus |= SCI_INT_OE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_PE) == SCI_RXST_PE) + { + interruptStatus |= SCI_INT_PE; + } + + return(interruptStatus); +} + +//***************************************************************************** +// +// SCI_clearInterruptStatus +// +//***************************************************************************** +void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + if(((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) || + ((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) || + ((intFlags & SCI_INT_FE) == SCI_INT_FE) || + ((intFlags & SCI_INT_OE) == SCI_INT_OE) || + ((intFlags & SCI_INT_PE) == SCI_INT_PE)) + { + SCI_performSoftwareReset(base); + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFINTCLR; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR; + } +} + +//***************************************************************************** +// +// SCI_setBaud +// +//***************************************************************************** +void SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud) +{ + uint32_t divider; + + // + // Compute the baud rate divider {ROUND TO NEAREST INTEGER} + // + divider = ((float)((float)lspclkHz / ((float)baud * 8.0F)) - 1.0F) + 0.5F; + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; +} + +//***************************************************************************** +// +// SCI_setWakeFlag +// +//***************************************************************************** +void SCI_setWakeFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the TX wake flag bit to indicate + // that the next frame is an address frame. + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_TXWAKE; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/sci.h b/gpio_bitfield_cpu2/device/driverlib/sci.h new file mode 100644 index 0000000..454ee12 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sci.h @@ -0,0 +1,1646 @@ +//########################################################################### +// +// FILE: sci.h +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SCI_H +#define SCI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sci_api SCI +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_sci.h" +#include "inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and +// SCI_clearInterruptStatus as the intFlags parameter, and returned from +// SCI_getInterruptStatus. +// +//***************************************************************************** +#define SCI_INT_RXERR 0x01U //!< RXERR interrupt +#define SCI_INT_RXRDY_BRKDT 0x02U //!< RXRDY interrupt +#define SCI_INT_TXRDY 0x04U //!< TXRDY interrupt +#define SCI_INT_TXFF 0x08U //!< TX FIFO level interrupt +#define SCI_INT_RXFF 0x10U //!< RX FIFO level interrupt +#define SCI_INT_FE 0x20U //!< Frame Error +#define SCI_INT_OE 0x40U //!< Overrun Error +#define SCI_INT_PE 0x80U //!< Parity Error + +//***************************************************************************** +// +// Values that can be passed to SCI_setConfig as the config parameter +// and returned by SCI_getConfig in the config parameter. +// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to +// SCI_setParityMode as the parity parameter, and are returned by +// SCI_getParityMode. +// +//***************************************************************************** +#define SCI_CONFIG_WLEN_MASK 0x0007U //!< Mask for extracting word length +#define SCI_CONFIG_WLEN_8 0x0007U //!< 8 bit data +#define SCI_CONFIG_WLEN_7 0x0006U //!< 7 bit data +#define SCI_CONFIG_WLEN_6 0x0005U //!< 6 bit data +#define SCI_CONFIG_WLEN_5 0x0004U //!< 5 bit data +#define SCI_CONFIG_WLEN_4 0x0003U //!< 4 bit data +#define SCI_CONFIG_WLEN_3 0x0002U //!< 3 bit data +#define SCI_CONFIG_WLEN_2 0x0001U //!< 2 bit data +#define SCI_CONFIG_WLEN_1 0x0000U //!< 1 bit data +#define SCI_CONFIG_STOP_MASK 0x0080U //!< Mask for extracting stop bits +#define SCI_CONFIG_STOP_ONE 0x0000U //!< One stop bit +#define SCI_CONFIG_STOP_TWO 0x0080U //!< Two stop bits +#define SCI_CONFIG_PAR_MASK 0x0060U //!< Parity Mask + +//***************************************************************************** +// +//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to +//! describe the parity of the SCI communication. +// +//***************************************************************************** +typedef enum +{ + SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity + SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity + SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity +} SCI_ParityType; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel +//! parameter and returned by SCI_getFIFOInteruptLevel() and +//! SCI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty + SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full + SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full + SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full + SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full + SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full + SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full + SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full + SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full + SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full + SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full + SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full + SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full + SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full + SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full + SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full + SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full +} SCI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel +//! parameter and returned by SCI_getFIFOInterruptLevel() and +//! SCI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty + SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full + SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full + SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full + SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full + SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full + SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full + SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full + SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full + SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full + SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full + SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full + SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full + SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full + SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full + SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full + SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full +} SCI_RxFIFOLevel; + +//***************************************************************************** +// +// Values returned from SCI_getRxStatus(). These correspond to the different +// bits and flags of the SCIRXST register. +// +//***************************************************************************** +#define SCI_RXSTATUS_WAKE 0x0002U //!< Receiver wake up detect +#define SCI_RXSTATUS_PARITY 0x0004U //!< Parity error +#define SCI_RXSTATUS_OVERRUN 0x0008U //!< Overrun error +#define SCI_RXSTATUS_FRAMING 0x0010U //!< Framing error +#define SCI_RXSTATUS_BREAK 0x0020U //!< Break detect +#define SCI_RXSTATUS_READY 0x0040U //!< Receiver ready +#define SCI_RXSTATUS_ERROR 0x0080U //!< Receiver error + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a SCI base address. +//! +//! \param base is the base address of the SCI port. +//! +//! This function determines if a SCI port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SCI_isBaseValid(uint32_t base) +{ + return( + (base == SCIA_BASE) || + (base == SCIB_BASE) || + (base == SCIC_BASE) || + (base == SCID_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param base is the base address of the SCI port. +//! \param parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e parity parameter must be one of the following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setParityMode(uint32_t base, SCI_ParityType parity) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the parity mode. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK)) | (uint16_t)parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param base is the base address of the SCI port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of the +//! following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +// +//***************************************************************************** +static inline SCI_ParityType +SCI_getParityMode(uint32_t base) +{ + uint16_t parity; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current parity setting. + // + parity = (HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK)); + + return((SCI_ParityType)parity); +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to address-bit mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to address-bit mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setAddrMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to idle-line mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to idle-line protocol. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setIdleMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Locks Autobaud. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs an autobaud lock for the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_lockAutobaud(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Prime the baud register + // + HWREGH(base + SCI_O_HBAUD) = 0x0U; + HWREGH(base + SCI_O_LBAUD) = 0x1U; + + // + // Prepare for autobaud detection. + // Set the CDC bit to enable autobaud detection and clear the ABD bit. + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_CDC; + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + + // + // Wait until we correctly read an 'A' or 'a' and lock + // + while((HWREGH(base + SCI_O_FFCT) & SCI_FFCT_ABD) != SCI_FFCT_ABD) + { + } + + // + // After autobaud lock, clear the ABD and CDC bits + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + HWREGH(base + SCI_O_FFCT) &= ~SCI_FFCT_CDC; +} + +//***************************************************************************** +// +//! Sets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as one of +//! the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or +//! \b SCI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as one of +//! the following +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, + SCI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SCI_O_FFTX) = (HWREGH(base + SCI_O_FFTX) & + (~SCI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SCI_O_FFRX) = (HWREGH(base + SCI_O_FFRX) & + (~SCI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is a pointer to storage for the transmit FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel, + SCI_RxFIFOLevel *rxLevel) +{ + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SCI_TxFIFOLevel)(HWREGH(base + SCI_O_FFTX) & + SCI_FFTX_TXFFIL_M); + *rxLevel = (SCI_RxFIFOLevel)(HWREGH(base + SCI_O_FFRX) & + SCI_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Gets the current configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is a pointer to storage for the baud rate. +//! \param config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the SCI is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e config is enumerated the same as the \e config parameter of +//! SCI_setConfig(). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud, + uint32_t *config) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Compute the baud rate. + // + *baud = lspclkHz / + ((1U + (((uint32_t)HWREGH(base + SCI_O_HBAUD) << 8U) | + HWREGH(base + SCI_O_LBAUD))) * 8U); + + // + // Get the parity, data length, and number of stop bits. + // + *config = (uint32_t)HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and +//! RXENA bits which enables transmit and receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX, TX, and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_RXENA | + SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the +//! data has been sent before disable the module during transmission. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~(SCI_FFTX_SCIFFENA); + + // + // Disable the SCI. + // + HWREGH(base + SCI_O_CTL1) &= ~(SCI_CTL1_TXENA | SCI_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA bit +//! which enables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable TX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the TXENA bit +//! which disables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable TX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_TXENA; +} + +//***************************************************************************** +// +//! Enables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the RXENA bit +//! which enables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_RXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the RXENA bit +//! which disables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable RX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXENA; +} + +//***************************************************************************** +// +//! Enables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the sleep mode in SCI by setting the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set sleep bit + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Disables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the sleep mode in SCI by clearing the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear sleep bit + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions enables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIFFENA | SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions disables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Determines if the FIFO enhancement is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not the FIFO enhancement +//! is enabled. +//! +//! \return Returns \b true if the FIFO enhancement is enabled or \b false +//! if the FIFO enhancement is disabled. +// +//***************************************************************************** +static inline bool +SCI_isFIFOEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return true if the FIFO is enabled and false if it is disabled. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_SCIFFENA) == + SCI_FFTX_SCIFFENA) ? true : false); +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the receive FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the transmit FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the SCI Transmit and Receive Channels +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets transmit and receive channels in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetChannels(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the Tx and Rx Channels + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive buffer when the +//! FIFO enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive buffer. +//! +//! \return Returns \b true if there is data in the receive buffer or \b false +//! if there is no data in the receive buffer. +// +//***************************************************************************** +static inline bool +SCI_isDataAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of characters with FIFO disabled. + // + return(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == + SCI_RXST_RXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit buffer when the FIFO +//! enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit buffer when not using the FIFO enhancement. +//! +//! \return Returns \b true if there is space available in the transmit buffer +//! or \b false if there is no space available in the transmit buffer. +// +//***************************************************************************** +static inline bool +SCI_isSpaceAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of space. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == + SCI_CTL2_TXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3 +//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16 +// +//***************************************************************************** +static inline SCI_TxFIFOLevel +SCI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_TxFIFOLevel)((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) >> + SCI_FFTX_TXFFST_S)); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3 +//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16 +// +//***************************************************************************** +static inline SCI_RxFIFOLevel +SCI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_RxFIFOLevel)((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFST_M) >> + SCI_FFRX_RXFFST_S)); +} + +//***************************************************************************** +// +//! Determines whether the SCI transmitter is busy or not. +//! +//! \param base is the base address of the SCI port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware when the FIFO is not enabled. When the FIFO is +//! enabled, this function allows the caller to determine whether there is any +//! data in the FIFO. +//! +//! Without the FIFO enabled, if \b false is returned, the transmit buffer and +//! shift registers are empty and the transmitter is not busy. With the FIFO +//! enabled, if \b false is returned, the FIFO is empty. This does not +//! necessarily mean that the transmitter is not busy. The empty FIFO does not +//! reflect the status of the transmitter shift register. The FIFO may be empty +//! while the transmitter is still transmitting data. +//! +//! \return Returns \b true if the SCI is transmitting or \b false if +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SCI_isTransmitterBusy(uint32_t base) +{ + // + // Check the argument. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // With FIFO enhancement, determine if the SCI is busy. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) != + 0U) ? true : false); + } + else + { + // + // Without FIFO enhancement, determine if the SCI is busy. + // Check if the transmit buffer and shift register empty. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXEMPTY) == + SCI_CTL2_TXEMPTY) ? false : true); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. \e data is a uint16_t but +//! only 8 bits are written to the SCI port. SCI only transmits 8 bit +//! characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! before returning. \e data is a uint16_t but only 8 bits are written to the +//! SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Writes the character \e data to the transmit buffer for the specified port. +//! This function does not block and only writes to the transmit buffer. +//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus() +//! to determine if the transmit buffer or FIFO have space available. +//! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI +//! only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets current receiver status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns the current receiver status flags. The returned +//! error flags are equivalent to the error bits returned via the previous +//! reading or receiving of a character with the exception that the overrun +//! error is set immediately the overrun occurs rather than when a character +//! is next read. +//! +//! \return Returns a bitwise OR combination of the receiver status flags, +//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN, +//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY, +//! and \b SCI_RXSTATUS_ERROR. +// +//***************************************************************************** +static inline uint16_t +SCI_getRxStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(base + SCI_O_RXST)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. Returns immediately in case of Error. +//! +//! \return Returns the character read from the specified port as \e uint16_t +//! or 0x0 in case of Error. The application must use +//! SCI_getRxStatus() API to check if some error occurred before +//! consuming the data +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + // + //If there is any error return + // + if((SCI_getRxStatus(base) & SCI_RXSTATUS_ERROR) != 0U) + { + return(0U); + } + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. If there +//! is no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port as \e uint16_t. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. This +//! function does not block and only reads the receive buffer. The user should +//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if +//! the receive buffer or FIFO have data available. +//! +//! \return Returns \e uin16_t which is read from the receive buffer. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Performs a software reset of the SCI and Clears all reported receiver +//! status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs a software reset of the SCI port. It affects the +//! operating flags of the SCI, but it neither affects the configuration bits +//! nor restores the reset values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_performSoftwareReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SWRESET; + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SWRESET; +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the loop back test mode where the Tx pin is internally connected +//! to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the loop back mode. + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Disables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the loop back test mode where the Tx pin is no longer internally +//! connected to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the loop back mode. + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Get the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the receive FIFO overflow flag status. +//! +//! \return Returns \b true if overflow has occurred, else returned \b false if +//! an overflow hasn't occurred. +// +//***************************************************************************** +static inline bool +SCI_getOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current FIFO overflow status + // + return((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFOVF) == SCI_FFRX_RXFFOVF); +} + +//***************************************************************************** +// +//! Clear the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions clears the receive FIFO overflow flag status. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_clearOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the current FIFO overflow status + // + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFOVRCLR; +} + +//***************************************************************************** +// +//! Sets the configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! \param config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the SCI for operation in the specified data +//! format. The baud rate is provided in the \e baud parameter and the data +//! format in the \e config parameter. +//! +//! The \e config parameter is the bitwise OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8, +//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5, +//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and +//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte +//! (respectively). +//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, +//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity +//! bit, odd parity bit respectively). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! A baud rate divider (BRR) is used in this function to calculate the +//! baud rate. The value of BRR is calculated in float and type casted as int +//! to be fed in the \b SCIHBAUD and \b SCILBAUD registers. This conversion +//! brings an error in the calculated baud rate and the requested. Error will +//! be significant when operating at higher baud rates. The error is due to +//! lower BRR integer value granularity at higher baud rates. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, + uint32_t config); + +//***************************************************************************** +// +//! Waits to send an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be transmitted. +//! It is pointer to the array of characters to be transmitted. +//! \param length is the length of the array, or number of characters in the +//! array to be transmitted. +//! +//! Sends the number of characters specified by \e length, starting at the +//! address \e array, out of the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! and \e length number of characters are transmitted before returning. +//! \e array is a pointer to uint16_ts but only the least significant 8 bits +//! are written to the SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length); + +//***************************************************************************** +// +//! Waits to receive an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be received. +//! It is a pointer to the array of characters to be received. +//! \param length is the length of the array, or number of characters in the +//! array to be received. +//! +//! Receives an array of characters from the receive buffer for the specified +//! port, and stores them as an array of characters starting at address +//! \e array. This function waits until the \e length number of characters are +//! received before returning. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length); + +//***************************************************************************** +// +//! Enables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter is the bitwise OR of any of the following: +//! +//! - \b SCI_INT_RXERR - RXERR Interrupt +//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt +//! - \b SCI_INT_TXRDY - TXRDY Interrupt +//! - \b SCI_INT_TXFF - TX FIFO Level Interrupt +//! - \b SCI_INT_RXFF - RX FIFO Level Interrupt +//! - \b SCI_INT_FE - Frame Error +//! - \b SCI_INT_OE - Overrun Error +//! - \b SCI_INT_PE - Parity Error +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the SCI port. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SCI_enableInterrupt(). +// +//***************************************************************************** +extern uint32_t +SCI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SCI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Sets SCI Baud rate. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! +//! This function configures the SCI for operation in the specified baud rate +//! The baud rate is provided in the \e baud parameter. +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock() +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud); + +//***************************************************************************** +// +//! Sets the SCI TXWAKE flag +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the TXWAKE flag bit to indicate that the next frame +//! is an address frame. +//! TXWAKE bit controls selection of data-transmit feature based on +//! which mode is selected from idle-line and address-bit. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setWakeFlag(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SCI_H diff --git a/gpio_bitfield_cpu2/device/driverlib/sdfm.c b/gpio_bitfield_cpu2/device/driverlib/sdfm.c new file mode 100644 index 0000000..41bc605 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sdfm.c @@ -0,0 +1,188 @@ +//########################################################################### +// +// FILE: sdfm.c +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sdfm.h" + +//***************************************************************************** +// +// Defines for filter configurations. Not intended for use by application code. +// +//***************************************************************************** +// +// Get filter oversampling ratio +// +#define SDFM_GET_OSR(C) ((C) >> 8U) + +// +// Maximum acceptable comparator filter oversampling ratio +// +#define SDFM_MAX_COMP_FILTER_OSR 31U + +// +// Maximum acceptable data filter oversampling ratio +// +#define SDFM_MAX_DATA_FILTER_OSR 255U + +// +// Get the filter type +// +#define SDFM_GET_FILTER_TYPE(C) ((C) & 0x30U) + +// +// Get the filter number +// +#define SDFM_GET_FILTER_NUMBER(C) ((C) & 0x3U) + + +// +// Get data shift value +// +#define SDFM_GET_SHIFT_VALUE(C) (((C) >> 2U) & 0x1FU) + +//***************************************************************************** +// +// SDFM_configComparator +// +//***************************************************************************** +void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_COMP_FILTER_OSR) + { + ratio = SDFM_MAX_COMP_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setComparatorFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setCompFilterOverSamplingRatio(base, filter, ratio); + + // + // Set the comparator high threshold value + // + SDFM_setCompFilterHighThreshold(base, filter, + SDFM_GET_HIGH_THRESHOLD(config2)); + + // + // Set the comparator low threshold value + // + SDFM_setCompFilterLowThreshold(base, filter, + SDFM_GET_LOW_THRESHOLD(config2)); + +} + +//***************************************************************************** +// +// SDFM_configDataFilter +// +//***************************************************************************** +void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_DATA_FILTER_OSR) + { + ratio = SDFM_MAX_DATA_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setFilterOverSamplingRatio(base, filter, ratio); + + // + // If filter switch on + // + if((config2 & SDFM_FILTER_ENABLE) == SDFM_FILTER_ENABLE) + { + SDFM_enableFilter(base, filter); + } + else + { + SDFM_disableFilter(base, filter); + } + + // + // Set output data format + // + SDFM_setOutputDataFormat(base, filter, + (SDFM_OutputDataFormat)(config2 & 0x1U)); + + // + // Set the shift value if data is in 16-bit 2's complement format + // + if((config2 & 0x1U) == (uint16_t)(SDFM_DATA_FORMAT_16_BIT)) + { + SDFM_setDataShiftValue(base, filter, SDFM_GET_SHIFT_VALUE(config2)); + } +} + + diff --git a/gpio_bitfield_cpu2/device/driverlib/sdfm.h b/gpio_bitfield_cpu2/device/driverlib/sdfm.h new file mode 100644 index 0000000..afbdfb7 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sdfm.h @@ -0,0 +1,1178 @@ +//########################################################################### +// +// FILE: sdfm.h +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef SDFM_H +#define SDFM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sdfm_api SDFM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_sdfm.h" +#include "inc/hw_memmap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//! Macro to get the low threshold +//! +#define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C)) + +//! Macro to get the high threshold +//! +#define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U)) + + +//! Macro to convert comparator over sampling ratio to acceptable bit location +//! +#define SDFM_SET_OSR(X) (((X) - 1U) << 8U) +//! Macro to convert the data shift bit values to acceptable bit location +//! +#define SDFM_SHIFT_VALUE(X) ((X) << 2U) + +//! Macro to combine high threshold and low threshold values +//! +#define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L)) + +//! Macro to set the FIFO level to acceptable bit location +//! +#define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U) + +//! Macro to set and enable the zero cross threshold value. +//! +#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X)) + +//! Macros to enable or disable filter. +//! +#define SDFM_FILTER_DISABLE 0x0U +#define SDFM_FILTER_ENABLE 0x2U + +//***************************************************************************** +// +//! Values that can be returned from SDFM_getThresholdStatus() +// +//***************************************************************************** +typedef enum +{ + SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold + SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold + SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold +} SDFM_OutputThresholdStatus; + +//***************************************************************************** +// +//! Values that can be passed to all functions as the \e filterNumber +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SDFM_FILTER_1 = 0, //!< Digital filter 1 + SDFM_FILTER_2 = 1, //!< Digital filter 2 + SDFM_FILTER_3 = 2, //!< Digital filter 3 + SDFM_FILTER_4 = 3 //!< Digital filter 4 +} SDFM_FilterNumber; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setFilterType(), +//! SDFM_setComparatorFilterType() as the \e filterType parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital filter with SincFast structure. + SDFM_FILTER_SINC_FAST = 0x00, + //! Digital filter with Sinc1 structure + SDFM_FILTER_SINC_1 = 0x10, + //! Digital filter with Sinc3 structure. + SDFM_FILTER_SINC_2 = 0x20, + //! Digital filter with Sinc4 structure. + SDFM_FILTER_SINC_3 = 0x30 +} SDFM_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setupModulatorClock(),as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Modulator clock is identical to the data rate + SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0, + //! Modulator clock is half the data rate + SDFM_MODULATOR_CLK_HALF_DATA_RATE = 1, + //! Modulator clock is off. Data is Manchester coded. + SDFM_MODULATOR_CLK_OFF = 2, + //! Modulator clock is double the data rate. + SDFM_MODULATOR_CLK_DOUBLE_DATA_RATE = 3 +} SDFM_ModulatorClockMode; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setOutputDataFormat(),as the +//! \e dataFormat parameter. +// +//***************************************************************************** +typedef enum +{ + //! Filter output is in 16 bits 2's complement format. + SDFM_DATA_FORMAT_16_BIT = 0, + //! Filter output is in 32 bits 2's complement format. + SDFM_DATA_FORMAT_32_BIT = 1 +} SDFM_OutputDataFormat; + +//***************************************************************************** +// +// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt +// as intFlags parameter +// +//***************************************************************************** +//! Interrupt is generated if Modulator fails. +//! +#define SDFM_MODULATOR_FAILURE_INTERRUPT 0x200U +//! Interrupt on Comparator low-level threshold. +//! +#define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT 0x40U +//! Interrupt on Comparator high-level threshold. +//! +#define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT 0x20U +//! Interrupt on Acknowledge flag +//! +#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to SDFM_clearInterruptFlag flags parameter +// +//***************************************************************************** +//! Main interrupt flag +//! +#define SDFM_MAIN_INTERRUPT_FLAG 0x80000000U +//! Filter 1 high -level threshold flag +//! +#define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG 0x1U +//! Filter 1 low -level threshold flag +//! +#define SDFM_FILTER_1_LOW_THRESHOLD_FLAG 0x2U +//! Filter 2 high -level threshold flag +//! +#define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG 0x4U +//! Filter 2 low -level threshold flag +//! +#define SDFM_FILTER_2_LOW_THRESHOLD_FLAG 0x8U +//! Filter 3 high -level threshold flag +//! +#define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG 0x10U +//! Filter 3 low -level threshold flag +//! +#define SDFM_FILTER_3_LOW_THRESHOLD_FLAG 0x20U +//! Filter 4 high -level threshold flag +//! +#define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG 0x40U +//! Filter 4 low -level threshold flag +//! +#define SDFM_FILTER_4_LOW_THRESHOLD_FLAG 0x80U +//! Filter 1 modulator failed flag +//! +#define SDFM_FILTER_1_MOD_FAILED_FLAG 0x100U +//! Filter 2 modulator failed flag +//! +#define SDFM_FILTER_2_MOD_FAILED_FLAG 0x200U +//! Filter 3 modulator failed flag +//! +#define SDFM_FILTER_3_MOD_FAILED_FLAG 0x400U +//! Filter 4 modulator failed flag +//! +#define SDFM_FILTER_4_MOD_FAILED_FLAG 0x800U +//! Filter 1 new data flag +//! +#define SDFM_FILTER_1_NEW_DATA_FLAG 0x1000U +//! Filter 2 new data flag +//! +#define SDFM_FILTER_2_NEW_DATA_FLAG 0x2000U +//! Filter 3 new data flag +//! +#define SDFM_FILTER_3_NEW_DATA_FLAG 0x4000U +//! Filter 4 new data flag +//! +#define SDFM_FILTER_4_NEW_DATA_FLAG 0x8000U + +//***************************************************************************** +// +//! \internal +//! Checks SDFM base address. +//! +//! \param base specifies the SDFM module base address. +//! +//! This function determines if SDFM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SDFM_isBaseValid(uint32_t base) +{ + return( + (base == SDFM1_BASE) || + (base == SDFM2_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables data filter to be reset by an external source (PWM +//! compare output). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables data filter from being reset by an external source +//! (PWM compare output). +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Enable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables the filter specified by the \e filterNumber variable. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables the filter specified by the \e filterNumber +//! variable. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Set filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the filter type or structure. +//! +//! This function sets the filter type or structure to be used as specified by +//! filterType for the selected filter number as specified by filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SST bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_SST_M)) | + ((uint16_t)filterType << 6U); + EDIS; +} + +//***************************************************************************** +// +//! Set data filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the data filter over sampling ratio. +//! +//! This function sets the filter oversampling ratio for the filter specified +//! by the filterNumber variable.Valid values for the variable +//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio +//! will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 256U); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DOSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_DOSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Set modulator clock mode. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param clockMode is the modulator clock mode. +//! +//! This function sets the modulator clock mode specified by clockMode +//! for the filter specified by filterNumber. +//! +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_ModulatorClockMode clockMode) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCTLPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to MOD bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCTLPARM1_MOD_M)) | + (uint16_t)clockMode; + + EDIS; +} + +//***************************************************************************** +// +//! Set the output data format +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param dataFormat is the output data format. +//! +//! This function sets the output data format for the filter specified by +//! filterNumber. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_OutputDataFormat dataFormat) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DR bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_DR)) | + ((uint16_t)dataFormat << 10U); + EDIS; +} + +//***************************************************************************** +// +//! Set data shift value. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param shiftValue is the data shift value. +//! +//! This function sets the shift value for the 16 bit 2's complement data +//! format. The valid maximum value for shiftValue is 31. +//! +//! \b Note: Use this function with 16 bit 2's complement data format only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t shiftValue) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(shiftValue < 32U); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SH bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_SH_M)) | + (shiftValue << SDFM_SDDPARM1_SH_S); + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output high-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param highThreshold is the high-level threshold. +//! +//! This function sets the unsigned high-level threshold value for the +//! Comparator filter output. If the output value of the filter exceeds +//! highThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t highThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(highThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPH1 + ((uint32_t)filterNumber * 16U); + + // + // Write to HLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPH1_HLT_M) | highThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output low-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param lowThreshold is the low-level threshold. +//! +//! This function sets the unsigned low-level threshold value for the +//! Comparator filter output. If the output value of the filter gets below +//! lowThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t lowThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(lowThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPL1 + ((uint32_t)filterNumber * 16U); + + // + // Write to LLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPL1_LLT_M) | lowThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Enable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function enables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter specified +//! by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, Modulator failure + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) |= + (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) |= SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Disable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function disables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter +//! specified by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, modulator failure interrupts + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) &= + ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) &= ~SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Set the comparator filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the comparator filter type or structure. +//! +//! This function sets the Comparator filter type or structure to be used as +//! specified by filterType for the selected filter number as specified by +//! filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to CS1_CS0 bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_CS1_CS0_M)) | + ((uint16_t)filterType << 3U); + EDIS; +} + +//***************************************************************************** +// +//! Set Comparator filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the comparator filter over sampling ration. +//! +//! This function sets the comparator filter oversampling ratio for the filter +//! specified by the filterNumber.Valid values for the variable +//! overSamplingRatio are 0 to 31 inclusive. +//! The actual oversampling ratio will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setCompFilterOverSamplingRatio(uint32_t base, + SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 32U); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to COSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_COSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Get the filter data output. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the latest data filter output. Depending on the +//! filter data output format selected, the valid value will be the lower 16 +//! bits or the whole 32 bits of the returned value. +//! +//! \return Returns the latest data filter output. +//***************************************************************************** +static inline uint32_t +SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDDATA bits + // + return(HWREG(base + SDFM_O_SDDATA1 + ((uint32_t)filterNumber * 16U))); +} + +//***************************************************************************** +// +//! Get the Comparator threshold status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Comparator output threshold status for the given +//! filterNumber. +//! +//! \return Returns the following status flags. +//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the +//! specified threshold. +//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high +//! threshold +//! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low +//! threshold. +//! +//***************************************************************************** +static inline SDFM_OutputThresholdStatus +SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG high/low threshold bits + // + return((SDFM_OutputThresholdStatus)((HWREG(base + SDFM_O_SDIFLG) >> + (2U * (uint16_t)filterNumber)) & 0x3U)); +} + +//***************************************************************************** +// +//! Get the Modulator status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Modulator status. +//! +//! \return Returns true if the Modulator is operating normally +//! Returns false if the Modulator has failed +//! +//***************************************************************************** +static inline bool +SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MF1, MF2, MF3 OR MF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 8U)) & + 0x1U) != 0x1U); +} + +//***************************************************************************** +// +//! Check if new Filter data is available. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns new filter data status. +//! +//! \return Returns \b true if new filter data is available +//! Returns \b false if no new filter data is available +//! +//***************************************************************************** +static inline bool +SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG AF1, AF2, AF3 OR AF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 12U)) & + 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Get pending interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function returns any pending interrupt status. +//! +//! \return Returns \b true if there is a pending interrupt. +//! Returns \b false if no interrupt is pending. +//! +//***************************************************************************** +static inline bool +SDFM_getIsrStatus(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MIF + // + return((HWREG(base + SDFM_O_SDIFLG) >> 31U) == 0x1U); +} + +//***************************************************************************** +// +//! Clear pending flags. +//! +//! \param base is the base address of the SDFM module +//! \param flag is the SDFM status +//! +//! This function clears the specified pending interrupt flag. +//! Valid values are +//! SDFM_MAIN_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG, +//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG, +//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG, +//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG, +//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG or any combination of the above +//! flags. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_clearInterruptFlag(uint32_t base, uint32_t flag) +{ + ASSERT(SDFM_isBaseValid(base)); + ASSERT((flag & 0x8000FFFFU) == flag); + + // + // Write to SDIFLGCLR register + // + HWREG(base + SDFM_O_SDIFLGCLR) |= flag; +} + +//***************************************************************************** +// +//! Enable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) |= SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) &= ~SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Enable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) |= SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) &= ~SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Configures SDFM comparator for filter config & threshold values +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio. +//! \param config2 is high-level and low-level threshold values. +//! +//! This function configures the comparator filter for filter config and +//! threshold values based on provided inputs. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] filter number +//! - config1.[7:4] filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. +//! For example the value +//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) +//! will select Filter 1, SINC 2 type with an oversampling ratio of 16. +//! +//! The config2 parameter is the logical OR of the filter high and low +//! threshold values. +//! The bit definitions for config2 are as follow: +//! - config2.[15:0] low threshold +//! - config2.[31:16] high threshold +//! The upper 16 bits define the high threshold and the lower +//! 16 bits define the low threshold. +//! SDFM_THRESHOLD(H,L) can be used to combine the high and low thresholds. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2); + +//***************************************************************************** +// +//! Configure SDFM data filter +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio +//! configuration. +//! \param config2 is filter switch, data representation and data shift values +//! configuration. +//! +//! This function configures the data filter based on configurations +//! config1 and config2. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] Filter number +//! - config1.[7:4] Filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio , which ranges [1,256] inclusive , in the appropriate bit location +//! for config1. For example the value +//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) +//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. +//! +//! The config2 parameter is the logical OR of data representation, filter +//! switch, and data shift values +//! The bit definitions for config2 are as follow: +//! - config2.[0] Data representation +//! - config2.[1] Filter switch +//! - config2.[15:2] Shift values +//! Valid values for data representation are given in SDFM_OutputDataFormat +//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the +//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value +//! of the data shift value,which ranges [0,31] inclusive, in the appropriate +//! bit location for config2. +//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data +//! representation format. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif +#endif // SDFM_H diff --git a/gpio_bitfield_cpu2/device/driverlib/spi.c b/gpio_bitfield_cpu2/device/driverlib/spi.c new file mode 100644 index 0000000..b077369 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/spi.c @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: spi.c +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "spi.h" + +//***************************************************************************** +// +// SPI_setConfig +// +//***************************************************************************** +void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth) +{ + uint16_t regValue; + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + ASSERT((dataWidth >= 1U) && (dataWidth <= 16U)); + ASSERT((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPISWRESET) == 0U); + + // + // Set polarity and data width. + // + regValue = (((uint16_t)protocol << 6U) & SPI_CCR_CLKPOLARITY) | + (dataWidth - 1U); + + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & + ~(SPI_CCR_CLKPOLARITY | SPI_CCR_SPICHAR_M)) | + regValue; + + // + // Set the mode and phase. + // + regValue = (uint16_t)mode | (((uint16_t)protocol << 2U) & + SPI_CTL_CLK_PHASE); + + HWREGH(base + SPI_O_CTL) = (HWREGH(base + SPI_O_CTL) & + ~(SPI_CTL_TALK | SPI_CTL_CONTROLLER_PERIPHERAL | + SPI_CTL_CLK_PHASE)) | regValue; + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_setBaudRate +// +//***************************************************************************** +void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate) +{ + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_enableInterrupt +// +//***************************************************************************** +void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_SPIINTENA; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_OVERRUNINTENA; + } + + // + // Enable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFIENA; + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SPI_disableInterrupt +// +//***************************************************************************** +void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_SPIINTENA); + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_OVERRUNINTENA); + } + + // + // Disable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_TXFFIENA); + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) &= ~(SPI_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// SPI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SPI_getInterruptStatus(uint32_t base) +{ + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + if((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0U) + { + temp |= SPI_INT_RX_DATA_TX_EMPTY; + } + + if((HWREGH(base + SPI_O_STS) & SPI_STS_OVERRUN_FLAG) != 0U) + { + temp |= SPI_INT_RX_OVERRUN; + } + + if((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFINT) != 0U) + { + temp |= SPI_INT_TXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFINT) != 0U) + { + temp |= SPI_INT_RXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFOVF) != 0U) + { + temp |= SPI_INT_RXFF_OVERFLOW; + } + + return(temp); +} + +//***************************************************************************** +// +// SPI_clearInterruptStatus +// +//***************************************************************************** +void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the specified non-FIFO interrupt sources. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_STS) |= SPI_STS_OVERRUN_FLAG; + } + + // + // Clear the specified FIFO-mode interrupt sources. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF_OVERFLOW) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFOVFCLR; + } +} +//***************************************************************************** +// +// SPI_pollingNonFIFOTransaction +// +//***************************************************************************** +uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, uint16_t data) +{ + uint16_t rxData; + + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + ASSERT(data < ((uint32_t)1U << charLength)); + + // + // Write to SPI Transmit buffer + // + SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength)); + + // + // Read SPI Receive buffer + // + rxData = SPI_readDataBlockingNonFIFO(base); + + return(rxData); +} +//***************************************************************************** +// +// SPI_pollingFIFOTransaction +// +//***************************************************************************** + +void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay) +{ + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + + // + // Reset the TX / RX FIFO buffers to default state + // + SPI_disableFIFO(base); // Disable FIFO register + SPI_enableFIFO(base); // Enable FIFO register + + // + // Configure the FIFO Transmit Delay + // + SPI_setTxFifoTransmitDelay(base, txDelay); + + // + // Determine the number of 16-level words from number of words to be + // transmitted / received + // + uint16_t numOfSixteenWords = numOfWords / (uint16_t)SPI_FIFO_TXFULL; + + // + // Determine the number of remaining words from number of words to be + // transmitted / received + // + uint16_t remainingWords = numOfWords % (uint16_t)SPI_FIFO_TXFULL; + + uint16_t count = 0; + uint16_t i = 0; + uint16_t txBuffer_pos = 0; + uint16_t rxBuffer_pos = 0; + + // + // Number of transactions is based on numOfSixteenWords + // Each transaction will transmit and receive 16 words. + // + while(count < numOfSixteenWords) + { + // + // Fill-up the SPI Transmit FIFO buffers + // + for(i = 1; i <= (uint16_t)SPI_FIFO_TXFULL; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer is full + // + while(SPI_getRxFIFOStatus(base) < SPI_FIFO_RXFULL) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 1U; i <= (uint16_t)SPI_FIFO_RXFULL; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + count++; + } + + // + // Number of transactions is based on remainingWords + // + for(i = 0U; i < remainingWords; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer remaining words + // + while((uint16_t)SPI_getRxFIFOStatus(base) < remainingWords) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 0; i < remainingWords; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + // + // Disable SPI FIFO + // + SPI_disableFIFO(base); +} + +//***************************************************************************** +// +// SPI_transmit24Bits +// +//***************************************************************************** +void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t rxBuffer[3]; + uint16_t txBuffer[3]; + + ASSERT(data < ((uint32_t)1U << 24U)); + + // + // Empty Receive buffer + // + for(i = 0U; i < 3U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[23:16] + txBuffer[1] = (uint16_t)(data) >> 8U; // data[15:8] + txBuffer[2] = (uint16_t)(data) & 0x00FFU; // data[7:0] + + // + // Three 8-bits make a 24-bit + // Character length = 8 + // number of bytes = 3 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); +} +//***************************************************************************** +// +// SPI_receive16Bits +// +//***************************************************************************** + +uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + uint16_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 2U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 2U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = (rxBuffer[1] << 8) | rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = (rxBuffer[0] << 8) | rxBuffer[1]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_receive24Bits +// +//***************************************************************************** + +uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[3]; + uint16_t rxBuffer[3]; + uint32_t rxData = 0; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 3U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Two 8-bits make a 16-bit + // Character length = 8 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[2] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[2]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_transmit32Bits +// +//***************************************************************************** + +void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + + // + // Empty Receive buffer + // + for(i = 0U; i < 2U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[31:16] + txBuffer[1] = (uint16_t)(data); // data[15:0] + + // + // Two 16-bits make a 32-bit + // Character length = 16 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 16U, txBuffer, rxBuffer, 2U, txDelay); +} +//***************************************************************************** +// +// SPI_receive32Bits +// +//***************************************************************************** + +uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[4]; + uint16_t rxBuffer[4]; + uint32_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 4U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Four 8-bits make a 32-bit + // Character length = 8 + // number of bytes = 4 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 4U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[3] << 24U) | + ((uint32_t)rxBuffer[2] << 16U) | + ((uint32_t)rxBuffer[1] << 8U) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 24U) | + ((uint32_t)rxBuffer[1] << 16U) | + ((uint32_t)rxBuffer[2] << 8U) | + (uint32_t)rxBuffer[3]; + } + + return(rxData); +} diff --git a/gpio_bitfield_cpu2/device/driverlib/spi.h b/gpio_bitfield_cpu2/device/driverlib/spi.h new file mode 100644 index 0000000..b9e0d38 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/spi.h @@ -0,0 +1,1743 @@ +//########################################################################### +// +// FILE: spi.h +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SPI_H +#define SPI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup spi_api SPI +//! \brief This module is used for SPI configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_spi.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(), +// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by +// SPI_getInterruptStatus(). +// +//***************************************************************************** +#define SPI_INT_RX_OVERRUN 0x0001U //!< Receive overrun interrupt +#define SPI_INT_RX_DATA_TX_EMPTY 0x0002U //!< Data received, transmit empty +#define SPI_INT_RXFF 0x0004U //!< RX FIFO level interrupt +#define SPI_INT_TXFF 0x0008U //!< TX FIFO level interrupt +#define SPI_INT_RXFF_OVERFLOW 0x0010U //!< RX FIFO overflow +#endif + + +//***************************************************************************** +// +//! This macro definition is used to transmit a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitByte(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 8U, txData) + +//***************************************************************************** +// +//! This macro definition is used to transmit a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a 16-bit word of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmit16Bits(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 16U, txData) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of bytes to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' bytes of data. +//! This macro definition uses SPI_pollingFIFOTransaction function. +//! +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNBytes(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' 16-bit words of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit 'N' 16-bit words of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitN16BitWord(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' with previously +//! configured SPI character length +//! +//! \param base specifies the SPI module base address +//! \param charLength specifies the SPI character length +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' with configurable +//! SPI character length. +//! +//! This macro uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNWordsWithCharLength(base, charLength, txBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, txBuffer, NULL, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition is used to receive a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! +//! This macro definition is to receive a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received byte. +// +//***************************************************************************** +#define SPI_receiveByte(base, dummyData) \ + SPI_pollingNonFIFOTransaction(base, 8U, dummyData) + +//***************************************************************************** +// +//! This macro is used to receive 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of bytes to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' bytes of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNBytes(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' 16-bits words of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of 16-bit words to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' 16-bit words of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveN16BitWord(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' words with previously configured character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of words with specified character +//! length +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' words with specified character length +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNWordsWithcharLength(base, charLength, rxBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, NULL, rxBuffer, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e protocol parameter. +// +//***************************************************************************** +typedef enum +{ + //! Mode 0. Polarity 0, phase 0. Rising edge without delay. + SPI_PROT_POL0PHA0 = 0x0000U, + //! Mode 1. Polarity 0, phase 1. Rising edge with delay. + SPI_PROT_POL0PHA1 = 0x0002U, + //! Mode 2. Polarity 1, phase 0. Falling edge without delay. + SPI_PROT_POL1PHA0 = 0x0001U, + //! Mode 3. Polarity 1, phase 1. Falling edge with delay. + SPI_PROT_POL1PHA1 = 0x0003U +} SPI_TransferProtocol; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_MODE_PERIPHERAL = 0x0002U, //!< SPI peripheral + SPI_MODE_CONTROLLER = 0x0006U, //!< SPI controller + SPI_MODE_PERIPHERAL_OD = 0x0000U, //!< SPI peripheral w/ output disabled + SPI_MODE_CONTROLLER_OD = 0x0004U //!< SPI controller w/ output disabled +} SPI_Mode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by SPI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} SPI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by SPI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset +} SPI_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after midway in the bit stream + SPI_EMULATION_STOP_MIDWAY = 0x0000U, + //! Continue SPI operation regardless + SPI_EMULATION_FREE_RUN = 0x0010U, + //! Transmission will stop after a started transmission completes + SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U +} SPI_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setPTESignalPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_PTE_ACTIVE_LOW = 0x0000U, //!< SPIPTE is active low (normal) + SPI_PTE_ACTIVE_HIGH = SPI_PRI_PTEINV //!< SPIPTE is active high (inverted) +} SPI_PTEPolarity; + +//***************************************************************************** +// +//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(), +//! SPI_receive32Bits() +// +//***************************************************************************** +typedef enum +{ + SPI_DATA_LITTLE_ENDIAN = 0U, //!< LITTLE ENDIAN + SPI_DATA_BIG_ENDIAN = 1U, //!< BIG ENDIAN +} SPI_endianess; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an SPI base address. +//! +//! \param base specifies the SPI module base address. +//! +//! This function determines if a SPI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SPI_isBaseValid(uint32_t base) +{ + return( + (base == SPIA_BASE) || + (base == SPIB_BASE) || + (base == SPIC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function enables operation of the serial peripheral interface. The +//! serial peripheral interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; +} + +//***************************************************************************** +// +//! Disables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function disables operation of the serial peripheral interface. Call +//! this function before doing any configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); +} + +//***************************************************************************** +// +//! Sets the character length of SPI transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the character length of SPI transaction +//! +//! This function configures the character length of SPI transaction. +//! SPI character length can be from anywhere between 1-bit word to 16 bit word +//! of character length +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setcharLength(uint32_t base, uint16_t charLength) +{ + // + // Check the arguments. + // + ASSERT((charLength >= 1U) && (charLength <= 16U)); + + bool originalStatus = ((HWREGH(base + SPI_O_CCR) & (SPI_CCR_SPISWRESET)) + == SPI_CCR_SPISWRESET ); + + SPI_disableModule(base); + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & ~SPI_CCR_SPICHAR_M) | + (charLength - 1U); + // + // Restore original status + // + if(originalStatus){ + SPI_enableModule(base); + } +} + + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions enables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions disables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO); + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the transmit FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFIFO; +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the receive FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the RX FIFO. + // + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or +//! \b SPI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or +//! \b SPI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel, + SPI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SPI_O_FFTX) = (HWREGH(base + SPI_O_FFTX) & + (~SPI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SPI_O_FFRX) = (HWREGH(base + SPI_O_FFRX) & + (~SPI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, +//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, +//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel, + SPI_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SPI_TxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFTX) & + SPI_FFTX_TXFFIL_M)); + *rxLevel = (SPI_RxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFRX) & + SPI_FFRX_RXFFIL_M)); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3, +//! ..., or \b SPI_FIFO_TX16 +// +//***************************************************************************** +static inline SPI_TxFIFOLevel +SPI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_TxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) >> + SPI_FFTX_TXFFST_S))); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3, +//! ..., or \b SPI_FIFO_RX16 +// +//***************************************************************************** +static inline SPI_RxFIFOLevel +SPI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_RxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFST_M) >> + SPI_FFRX_RXFFST_S))); +} + +//***************************************************************************** +// +//! Determines whether the SPI transmitter is busy or not. +//! +//! \param base is the base address of the SPI port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. This function is only valid when operating in +//! FIFO mode. +//! +//! \return Returns \b true if the SPI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SPI_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Determine if the SPI is busy. + // + return((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) != 0U); +} + +//***************************************************************************** +// +//! Puts a data element into the SPI transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets a data element from the SPI receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function gets received data from the receive buffer of the specified +//! SPI module and returns it. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for space in the FIFO and then puts data into the transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once space is available in the transmit FIFO. This +//! function should only be used when the FIFO is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until space is available in the receive FIFO. + // + while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data in the FIFO and then reads it from the receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits until there is data in the receive FIFO and then reads +//! received data from the receive buffer. This function should only be used +//! when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data is available in the receive FIFO. + // + while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for the transmit buffer to empty and then writes data to it. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once it is empty. This function should not be used +//! when FIFO mode is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until the transmit buffer is not full. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_BUFFULL_FLAG) != 0U) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data to be received and then reads it from the buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits for data to be received and then reads it from the +//! receive buffer of the specified SPI module. This function should not be +//! used when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data has been received. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) == 0U) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Enables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables 3-wire mode. When in controller mode, this allows +//! SPIPICO to become SPICOCI and SPIPOCI to become free for non-SPI use. +//! When in peripheral mode, SPIPOCI because the SPIPIPO pin and SPIPICO is +//! free for non-SPI use. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the tri-wire bit to enable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) |= SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Disables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the tri-wire bit to disable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) &= ~SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Enables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables loopback mode. This mode is only valid during +//! controller mode and is helpful during device testing as it internally +//! connects PICO and POCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Disables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Set the peripheral select (SPIPTE) signal polarity. +//! +//! \param base is the base address of the SPI port. +//! \param polarity is the SPIPTE signal polarity. +//! +//! This function sets the polarity of the peripheral select (SPIPTE) signal. +//! The two modes to choose from for the \e polarity parameter are +//! \b SPI_PTE_ACTIVE_LOW for active-low polarity (typical) and +//! \b SPI_PTE_ACTIVE_HIGH for active-high polarity (considered inverted). +//! +//! \note This has no effect on the PTE signal when in controller mode. It is +//! only applicable to peripheral mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setPTESignalPolarity(uint32_t base, SPI_PTEPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the polarity of the SPIPTE signal to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & ~SPI_PRI_PTEINV) | + (uint16_t)polarity; +} + +//***************************************************************************** +// +//! Enables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables high speed mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Disables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables high speed mode. High speed mode is disabled by +//! default after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Sets SPI emulation mode. +//! +//! \param base is the base address of the SPI port. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the SPI operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit +//! stream. The rest of the bits will be transmitting after the suspend is +//! deasserted. +//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the +//! first SPICLK pulse, the transmission will not start. If it occurs later, +//! the transmission will be completed. +//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & + ~(SPI_PRI_FREE | SPI_PRI_SOFT)) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Configures the FIFO Transmit Delay +//! +//! \param base is the base address of the SPI port. +//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF) +//! +//! This function sets the delay between every transfer from FIFO +//! transmit buffer to transmit shift register. The delay is defined in +//! number SPI serial clock cycles. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(delay <= 0xFFU); + + // + // Configure the FIFO Transmit Delay Bits + // + HWREGH(base + SPI_O_FFCT) = delay; +} + +//***************************************************************************** +// +//! Returns the Emulation Buffer Received Data +//! +//! \param base is the base address of the SPI port. +//! +//! This function returns the Emulation Buffer Received Data +//! +//! \return Rx emulation buffer data +// +//***************************************************************************** +static inline uint16_t +SPI_readRxEmulationBuffer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Return Emulation Buffer Received Data + // + return(HWREGH(base + SPI_O_RXEMU)); +} + +//***************************************************************************** +// +//! Enable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function sets the TALK bit enabling the data trasnmission. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_enableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) |= SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Disable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function clears the TALK bit disabling the data trasnmission. The +//! output pin will be put in high-impedance state. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_disableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) &= ~SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Reset SPI transmit and receive channels +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the SPI transmit and receive channels. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_reset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write to SPRST bit the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_SPIRST; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIRST; +} + +//***************************************************************************** +// +//! Configures the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param protocol specifies the data transfer protocol. +//! \param mode specifies the mode of operation. +//! \param bitRate specifies the clock rate in Hz. +//! \param dataWidth specifies number of bits transferred per frame. +//! +//! This function configures the serial peripheral interface. It sets the SPI +//! protocol, mode of operation, bit rate, and data width. +//! +//! The \e protocol parameter defines the data frame format. The \e protocol +//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0, +//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or +//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity +//! and phase configurations: +//! +//! 

    +//! Polarity Phase       Mode
+//!   0       0   SPI_PROT_POL0PHA0
+//!   0       1   SPI_PROT_POL0PHA1
+//!   1       0   SPI_PROT_POL1PHA0
+//!   1       1   SPI_PROT_POL1PHA1
+//!
    +//! +//! The \e mode parameter defines the operating mode of the SPI module. The +//! SPI module can operate as a controller or peripheral; the SPI can also be be +//! configured to disable output on its serial output line. The \e mode +//! parameter can be one of the following values: \b SPI_MODE_CONTROLLER, +//! \b SPI_MODE_PERIPHERAL, \b SPI_MODE_CONTROLLER_OD or +//! \b SPI_MODE_PERIPHERAL_OD ("OD" indicates "output disabled"). +//! +//! The \e bitRate parameter defines the bit rate for the SPI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - \e bitRate can be no greater than lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The \e dataWidth parameter defines the width of the data transfers and +//! can be a value between 1 and 16, inclusive. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI operation should be disabled via SPI_disableModule() before any +//! changes to its configuration. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth); + +//***************************************************************************** +// +//! Configures the baud rate of the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param bitRate specifies the clock rate in Hz. +//! +//! This function configures the SPI baud rate. The \e bitRate parameter +//! defines the bit rate for the SPI. This bit rate must satisfy the following +//! clock ratio criteria: +//! +//! - \e bitRate can be no greater than \e lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate() +//! if you wish to configure it separately from protocol and mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate); + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. The \e intFlags parameter can be +//! any of the following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level +//! interrupt (and RX FIFO overflow) +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. The +//! \e intFlags parameter can be any of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW) +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base specifies the SPI module base address. +//! +//! This function returns the interrupt status for the SPI module. +//! +//! \return The current interrupt status, enumerated as a bit field of the +//! following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF - RX FIFO level interrupt +//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +// +//***************************************************************************** +extern uint32_t +SPI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SPI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e intFlags parameter can consist of a bit field of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF +//! - \b SPI_INT_RXFF_OVERFLOW +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive +//! receive buffer, so it usually doesn't need to be cleared using this +//! function. +//! +//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + + +//***************************************************************************** +// +//! This function can be used to transmit a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 24-bit word of data. +//! 24-bit word data is divided into three bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay); + +//***************************************************************************** +// +//! This function can be used to transmit a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 32-bit word of data. +//! 32-bit word data is divided into four bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to receive a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 16-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 16-bit word. +// +//***************************************************************************** +extern uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 24-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 24-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 32-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 32-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param data specified the data to be transmitted +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return . +// +//***************************************************************************** +extern uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t data); + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length and 'N' words of transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param pTxBuffer specifies the pointer to transmit buffer +//! \param pRxBuffer specifies the pointer to receive buffer +//! \param numOfWords specified the number of data to be transmitted / received +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return none +// +//***************************************************************************** +extern void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SPI_H diff --git a/gpio_bitfield_cpu2/device/driverlib/sysctl.c b/gpio_bitfield_cpu2/device/driverlib/sysctl.c new file mode 100644 index 0000000..f4708f2 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sysctl.c @@ -0,0 +1,1469 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cputimer.h" +#include "sysctl.h" + +// +// Define to isolate inline assembly +// +#define SYSCTL_DELAY __asm(" .if __TI_EABI__\n" \ + " .asg SysCtl_delay , _SysCtl_delay\n" \ + " .endif\n" \ + " .def _SysCtl_delay\n" \ + " .sect \".TI.ramfunc\"\n" \ + " .global _SysCtl_delay\n" \ + "_SysCtl_delay:\n" \ + " SUB ACC,#1\n" \ + " BF _SysCtl_delay, GEQ\n" \ + " LRETR\n") +#define SYSCTL_CLRC_DBGM __asm(" CLRC DBGM") + +// +// Define Timer1 and Timer2 seed values +// +#define TMR1SYSCLKCTR 0xF0000000U +#define TMR2INPCLKCTR 0x800U + +#define XTAL_CPUTIMER_PERIOD 1023U + +//***************************************************************************** +// +// SysCtl_delay() +// +//***************************************************************************** +SYSCTL_DELAY; + + +static void +SysCtl_pollCpuTimer(void) +{ + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + SysCtl_delay(2000); + + // + // Wait for cpu timer 2 to overflow + // + while(CPUTimer_getTimerOverflowStatus(CPUTIMER2_BASE) == false); + { + // + // If your application is stuck in this loop, please check if the + // input clock source is valid. + // + } + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); +} + +//***************************************************************************** +// +// SysCtl_getClock() +// +//***************************************************************************** +uint32_t +SysCtl_getClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + // + // Don't proceed if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning the INTOSC1 rate. You need + // to handle the MCD and clear the failure. + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (uint32_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + if((oscSource == (SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) || + (oscSource == (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S))) + { + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) & + (SYSCTL_SYSPLLCTL1_PLLEN | SYSCTL_SYSPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_FMULT_M) >> + SYSCTL_SYSPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier and fixed divide by 2 + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_IMULT_M) >> + SYSCTL_SYSPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)); + } + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getAuxClock() +// +//***************************************************************************** +uint32_t SysCtl_getAuxClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + (uint32_t)SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M; + + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + if(oscSource == (SYSCTL_AUXPLL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) + { + // + // 10MHz Internal Clock + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) & + (SYSCTL_AUXPLLCTL1_PLLEN | SYSCTL_AUXPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M) >> + SYSCTL_AUXPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_IMULT_M) >> + SYSCTL_AUXPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + clockOut /= (1U << (HWREG(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)); + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_setClock() +// +//***************************************************************************** +bool +SysCtl_setClock(uint32_t config) +{ + uint16_t divSel; + uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div; + bool status, sysclkInvalidFreq = true; + uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus; + uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t1PRD, t2PRD, ctr1; + float32_t sysclkToInClkError, mult; + + // + // Check the arguments. + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Don't proceed to the PLL initialization if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning false. You'll need to clear + // the MCD error. + // + status = false; + } + else + { + // + // Configure oscillator source + // + SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M); + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure PLL if enabled + // + EALLOW; + if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) + { + if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) & + SYSCTL_SYSDBGCTL_BIT_0) != 0U) + { + // + // The user can optionally insert handler code here. This will + // only be executed if a watchdog reset occurred after a failed + // system PLL initialization. See your device user's guide for + // more information. + // + // If the application has a watchdog reset handler, this bit + // should be checked to determine if the watchdog reset + // occurred because of the PLL. + // + // No action here will continue with retrying the PLL as + // normal. + // + } + + // + // Set dividers to /1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U; + + // + // Get the PLL multiplier settings from config + // + iMult |= (uint16_t)(config & SYSCTL_IMULT_M); + fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S); + pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) | + (fMult << SYSCTL_SYSPLLMULT_FMULT_S); + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase + // this number according to allotted system initialization time. + // + for(i = 0U; i < 5U; i++) + { + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + asm(" RPT #60 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + } + } + + // + // Configure Dividers. Set divider to produce slower output frequency + // to limit current increase. + // + divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if(divSel != (126U / 2U)) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U); + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the + // PLLstartup sequence. If your application has already cleared the + // watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended + // not to clear this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR); + tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR); + tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR); + + // + // Disable windowed functionality, reset counter + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U; + SysCtl_serviceWatchdog(); + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + + // + // This bit is reset only by power-on-reset (POR) and will not be + // cleared by a WD reset + // + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN; + + EDIS; + + // + // Delay to ensure system is clocking from PLL prior to clearing + // status bit + // + SysCtl_delay(3U); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer + // counts are off by +/- 10%. At a minimum, SYSCLK check is performed. + // Re-lock attempt is carried out if SLIPS bit is set. + // This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will + // be aborted by watchdog reset. + // + while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) && + (sysclkInvalidFreq == true)) + { + EALLOW; + + // + // Perform PLL re-lock only if SLIPS bit is set, otherwise monitor + // SYSCLK frequency with timers + // + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_SLIPS) == 1U) + { + // + // Bypass PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + SysCtl_delay(12U); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + ; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |= + SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay to ensure system is clocking from PLL prior to + // clearing status bit + // + SysCtl_delay(12U); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR); + t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD); + t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR); + t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH); + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + + // + // Stop timer 1 + // Seed timer1 counter + // Set sysclock divider + // Reload timer with value in PRD + // Clear interrupt flag + // Enable interrupt + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + + // + // Configure timer2 to count Input clock cycles + // + switch (config & SYSCTL_OSCSRC_M) + { + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INT_OSC1 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 1U; + break; + + case SYSCTL_OSCSRC_OSC2: + // + // Clk Src = INT_OSC2 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 2U; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Clk Src = XTAL + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 3U; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + + // + // Clear interrupt flag + // Enable interrupt + // Stop timer 2 + // Seed timer2 counter + // Set sysclock divider + // Reload timer with value in PRD + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Stop/Start timer counters + // + + // + // Stop timer 1 + // Stop timer 2 + // Reload timer1 with value in PRD + // Reload timer2 with value in PRD + // Clear timer2 interrupt flag + // Start timer2 + // Start timer1 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Wait for Timers - Stop if either timer overflows + // + while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U) && + ((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U)) + { + ; + } + + // + // Stop timer 1 and 2 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + // + // Calculate elapsed counts on timer1 + // + ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE + + CPUTIMER_O_TIM); + + // + // Restore timer settings + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float32_t)iMult + ((float32_t)fMult / 4.0F); + + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U) + { + div = 1U; + } + else + { + div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + 0x3FU) << 1; + } + + sysclkToInClkError = (mult / (float32_t)div) - + ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is + // off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) || + (sysclkToInClkError < -0.10F)); + + EDIS; + } + + // + // Clear bit + // + EALLOW; + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0; + EDIS; + + // + // Restore user watchdog, first resetting counter + // + SysCtl_serviceWatchdog(); + + // + // Set the KEY bits and make sure not to set the WDOVERRIDE bit + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS; + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE; + EDIS; + + // + // Restore state of ST1[INTM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x1U) == 0U) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x2U) == 0U) + { + SYSCTL_CLRC_DBGM; + } + + // + // ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + SysCtl_delay(40U); + + // + // Set the divider to user value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + status = true; + } + + return(status); +} +//***************************************************************************** +// +// SysCtl_setAuxClock() +// +//***************************************************************************** +void SysCtl_setAuxClock(uint32_t config) +{ + uint16_t pllMult = 0U; + uint16_t counter = 0U, started = 0U, attempts = 0U; + uint16_t mult; + uint16_t i, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Check the arguments + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure oscillator source + // + SysCtl_selectOscSourceAuxPLL(config & SYSCTL_OSCSRC_M); + + // + // Get the PLL multiplier settings from config + // + pllMult |= (uint16_t)((config & SYSCTL_IMULT_M) << + SYSCTL_AUXPLLMULT_IMULT_S); + pllMult |= (uint16_t)(((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << + SYSCTL_AUXPLLMULT_FMULT_S); + + // + // Get the PLL multipliers currently programmed + // + mult = (uint16_t)((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_M) >> + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_S); + mult |= (uint16_t)(HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M); + + // + // Lock PLL only if the multipliers need update + // + if(mult != pllMult) + { + + // + // Configure PLL if enabled + // + if((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE) + { + // + // Backup Timer 2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // - Clock source to AUXPLL + // - Clock divider to divide by 1 + // - Small period to detect overflow + // - Interrupt disabled + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = 6U; + + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = 10U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK / 2 + // while using Timer 2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = 0x3U; + SYSCTL_REGWRITE_DELAY; + EDIS; + + // + // Lock the PLL up to five times. + //CPU Timer 2 will monitor a successful + // lock and break out of the loop earlier if detected. + // + while((counter < 5U) && (started == 0U)) + { + EALLOW; + + // + // Turn off AUXPLL and delay for it to power down. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= + ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically + // turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + SYSCTL_REGWRITE_DELAY; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLEN; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. + // This is used to test that the PLL has successfully started. + // + // Reload and start the timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Check to see timer is counting properly + // + for(i = 0U; i < 1000U; i++) + { + // + // Check overflow flag + // + if((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) != 0U) + { + // + // Clear overflow flag + // + HWREGH(CPUTIMER2_BASE + + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + + // + // Set flag to indicate PLL started and break out of + // for-loop + // + started = 1U; + break; + } + } + + // + // Stop timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + counter++; + EDIS; + } + + if(started == 0U) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass + // PLL). + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) = 0U; + EDIS; + + // + // The user should put some handler code here based on how + // this condition should be handled in their application. + // + ESTOP0; + } + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Reload period value + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + EDIS; + } + } + else + { + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + EDIS; + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + while(((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_SLIPS) != 0U) && (attempts < 10U) && + ((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE)) + { + EALLOW; + + // + // Bypass AUXPLL + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLEN; + + // + // Wait for the AUXPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + + SysCtl_delay(3U); + + attempts++; + + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + SYSCTL_REGWRITE_DELAY; + EDIS; + +} + + +//***************************************************************************** +// +// SysCtl_selectXTAL() +// +//***************************************************************************** +void +SysCtl_selectXTAL(void) +{ + uint16_t t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Backup CPU timer2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Backup AUX clock settings + // + uint16_t clksrcctl2 = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2); + uint16_t auxpllctl1 = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1); + uint16_t auxclkdivsel = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL); + + // + // Set AUX clock source to XTAL, bypass mode. + // AUXCLK is used as the CPUTimer Clock source. SYSCLK frequency must be + // atleast twice the frequency of AUXCLK. SYSCLK = INTOSC2(10MHz) + // Set the AUX divider to 8. The above condition will be met for XTAL + // frequencies up to 40MHz + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = 0x0U; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = SYSCTL_AUXPLLCLK_DIV_8; + SYSCTL_REGWRITE_DELAY; + + + // + // Disable cpu timer 2 interrupt + // + CPUTimer_disableInterrupt(CPUTIMER2_BASE); + + // + // Stop cpu timer 2 if running + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Initialize cpu timer 2 period + // + CPUTimer_setPeriod(CPUTIMER2_BASE, XTAL_CPUTIMER_PERIOD); + + // + // Set cpu timer 2 clock source to XTAL + // + CPUTimer_selectClockSource(CPUTIMER2_BASE, CPUTIMER_CLOCK_SOURCE_AUX, + CPUTIMER_CLOCK_PRESCALER_1); + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); + + // + // Start cpu timer 2 + // + CPUTimer_startTimer(CPUTIMER2_BASE); + + EALLOW; + // + // Turn on XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_XTALOFF; + EDIS; + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + + // + // If a missing clock failure was detected, try waiting for the cpu timer 2 + // to overflow again. + // + while(SysCtl_isMCDClockFailureDetected()) + { + // + // Clear the MCD failure + // + SysCtl_resetMCD(); + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + } + + // + // Stop cpu timer 2 + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Restore AUX clock settings + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = clksrcctl2; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = auxpllctl1; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = auxclkdivsel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSource() +// +//***************************************************************************** +void +SysCtl_selectOscSource(uint32_t oscSource) +{ + ASSERT((oscSource == SYSCTL_OSCSRC_OSC1) || + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL)); + + // + // Select the specified source. + // + EALLOW; + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Select XTAL in crystal mode and wait for it to power up + // + SysCtl_selectXTAL(); + break; + + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INTOSC1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M) | + (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S); + + SYSCTL_CLKSRCCTL_DELAY; + + // + //Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSourceAuxPLL() +// +//***************************************************************************** +void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource) +{ + bool status = false; + + EALLOW; + + switch(oscSource) + { + case SYSCTL_AUXPLL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_INTOSC2OFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M); + break; + + case SYSCTL_AUXPLL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_XTALOFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + break; + + case SYSCTL_AUXPLL_OSCSRC_AUXCLKIN: + // + // Clk Src = AUXCLKIN + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (2U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + SYSCTL_CLKSRCCTL_DELAY; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_getLowSpeedClock() +// +//***************************************************************************** +uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz) +{ + uint32_t clockOut; + + // + // Get the main system clock + // + clockOut = SysCtl_getClock(clockInHz); + + // + // Apply the divider to the main clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M)); + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getDeviceParametric() +// +//***************************************************************************** +uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric) +{ + uint32_t value; + + // + // Get requested parametric value + // + switch(parametric) + { + case SYSCTL_DEVICE_QUAL: + // + // Qualification Status + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_QUAL_M) >> SYSCTL_PARTIDL_QUAL_S); + break; + + case SYSCTL_DEVICE_PINCOUNT: + // + // Pin Count + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + break; + + case SYSCTL_DEVICE_INSTASPIN: + // + // InstaSPIN Feature Set + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_INSTASPIN_M) >> + SYSCTL_PARTIDL_INSTASPIN_S); + break; + + case SYSCTL_DEVICE_FLASH: + // + // Flash Size (KB) + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_FLASH_SIZE_M) >> + SYSCTL_PARTIDL_FLASH_SIZE_S); + break; + + case SYSCTL_DEVICE_PARTID: + // + // PARTID Format Revision + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M) >> + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S); + break; + + case SYSCTL_DEVICE_FAMILY: + // + // Device Family + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_FAMILY_M) >> SYSCTL_PARTIDH_FAMILY_S); + break; + + case SYSCTL_DEVICE_PARTNO: + // + // Part Number + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_PARTNO_M) >> SYSCTL_PARTIDH_PARTNO_S); + break; + + case SYSCTL_DEVICE_CLASSID: + // + // Class ID + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_DEVICE_CLASS_ID_M) >> + SYSCTL_PARTIDH_DEVICE_CLASS_ID_S); + break; + + default: + // + // Not a valid value for PARTID register + // + value = 0U; + break; + } + + return((uint16_t)value); +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/sysctl.h b/gpio_bitfield_cpu2/device/driverlib/sysctl.h new file mode 100644 index 0000000..8b263eb --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/sysctl.h @@ -0,0 +1,3531 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SYSCTL_H +#define SYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sysctl_api SysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_nmi.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_otp.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + + +// +// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1 +// register. +// Delay = 300 NOPs +// +#define SYSCTL_CLKSRCCTL_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP") + +// +// Macro used for adding delay between 2 consecutive writes to memory mapped +// register in System control +// Total delay = 3 * (DEVICE_SYSCLK_FREQ / INTOSC1 Freq) + 9 +// +#define SYSCTL_REGWRITE_DELAY asm(" RPT #69 || NOP") + +//***************************************************************************** +// +// Defines for system control functions. Not intended for use by application +// code. +// +//***************************************************************************** + +// +// Shifted pattern for WDCR register's WDCHK field. +// +#define SYSCTL_WD_CHKBITS 0x0028U + +// +// Keys for WDKEY field. The first enables resets and the second resets. +// +#define SYSCTL_WD_ENRSTKEY 0x0055U +#define SYSCTL_WD_RSTKEY 0x00AAU + +// +// Values to help decode peripheral parameter +// +#define SYSCTL_PERIPH_REG_M 0x001FU +#define SYSCTL_PERIPH_REG_S 0x0000U +#define SYSCTL_PERIPH_BIT_M 0x1F00U +#define SYSCTL_PERIPH_BIT_S 0x0008U + +// +//Keys for the System control registers write protection +// +#define SYSCTL_REG_KEY 0xA5A50000U +#define SYSCTL_PLL_KEY 0XCAFE0000U + +// +//Values to help access shifting of bits +// +#define SYSCTL_TYPE_LOCK_S 0xFU + + +// +// LPM defines for LPMCR.LPM +// +#define SYSCTL_LPM_IDLE 0x0000U +#define SYSCTL_LPM_STANDBY 0x0001U +#define SYSCTL_LPM_HALT 0x0002U +#define SYSCTL_LPM_HIB 0x0003U + +// +// Bit shift for DAC to configure the CPUSEL register +// +#define SYSCTL_CPUSEL_DAC_S 0x10U + +// +// Default internal oscillator frequency, 10 MHz +// +#define SYSCTL_DEFAULT_OSC_FREQ 10000000U + +// +// Mask for SYNCSELECT.SYNCIN +// +#define SYSCTL_SYNCSELECT_SYNCIN_M SYSCTL_SYNCSELECT_EPWM4SYNCIN_M + +// +// Boot ROM Booting and Reset Status +// +#if defined(CPU2) +#define SYSCTL_BOOT_ROM_STATUS 0x0002U +#else +#define SYSCTL_BOOT_ROM_STATUS 0x002CU +#endif +#define SYSCTL_BOOT_ROM_POR 0x8000U +#define SYSCTL_BOOT_ROM_XRS 0x4000U + +#define SYSCTL_DEVICECAL_CONTEXT_SAVE asm(" PUSH ACC \n\ + PUSH DP \n\ + PUSH XAR0 \n\ + PUSH XAR2 \n\ + PUSH XAR3 \n\ + PUSH XAR4 \n\ + PUSH XAR5 \n\ + ") + +#define SYSCTL_DEVICECAL_CONTEXT_RESTORE asm(" POP XAR5 \n\ + POP XAR4 \n\ + POP XAR3 \n\ + POP XAR2 \n\ + POP XAR0 \n\ + POP DP \n\ + POP ACC \n\ + ") + +// +// Device_cal function which is available in OTP memory +// This function is called in SysCtl_resetPeripheral after resetting +// analog peripherals +// +#define Device_cal ((void (*)(void))((uintptr_t)0x070282)) + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setClock() API as +// the config parameter. +// +//***************************************************************************** +// +// System clock divider (SYSDIV) +// + + + +#define SYSCTL_SYSDIV_M 0x00001F80UL // Mask for SYSDIV value in config +#define SYSCTL_SYSDIV_S 7U // Shift for SYSDIV value in config + +//! Macro to format system clock divider value. x must be 1 or even values up +//! to 126. +#define SYSCTL_SYSDIV(x) ((((x) / 2U) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +// +// Integer multiplier (IMULT) +// +#define SYSCTL_IMULT_M 0x0000007FUL // Mask for IMULT value in config +#define SYSCTL_IMULT_S 0U // Shift for IMULT value in config +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#ifndef DOXYGEN_PDF_IGNORE +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_FMULT_M 0x00006000UL // Mask for FMULT value in config +#define SYSCTL_FMULT_S 13U // Shift for FMULT value in config +#define SYSCTL_FMULT_NONE 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_0 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_1_4 0x00002000UL //!< Fractional multiplier of 0.25 +#define SYSCTL_FMULT_1_2 0x00004000UL //!< Fractional multiplier of 0.50 +#define SYSCTL_FMULT_3_4 0x00006000UL //!< Fractional multiplier of 0.75 + +// +// Oscillator source +// +// Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), +// and SysCtl_turnOffOsc() functions as the oscSource parameter. +// +#define SYSCTL_OSCSRC_M 0x00030000UL // Mask for OSCSRC value in config +#define SYSCTL_OSCSRC_S 16U // Shift for OSCSRC value in config +//! Internal oscillator INTOSC2 +#define SYSCTL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) in crystal mode +#define SYSCTL_OSCSRC_XTAL 0x00010000U +//! Internal oscillator INTOSC1 +#define SYSCTL_OSCSRC_OSC1 0x00020000UL + +// +// Enable/disable PLL +// +#define SYSCTL_PLL_ENABLE 0x80000000U //!< Enable PLL +#define SYSCTL_PLL_DISABLE 0x00000000U //!< Disable PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setAuxClock() API +// as the config parameter. +// +//***************************************************************************** +// +// Auxiliary clock divider (AUXCLKDIV) +// +#define SYSCTL_AUXPLL_DIV_1 0x00000000UL //!< Auxiliary PLL divide by 1 +#define SYSCTL_AUXPLL_DIV_2 0x00000080UL //!< Auxiliary PLL divide by 2 +#define SYSCTL_AUXPLL_DIV_4 0x00000100UL //!< Auxiliary PLL divide by 4 +#define SYSCTL_AUXPLL_DIV_8 0x00000180UL //!< Auxiliary PLL divide by 8 + +// +// Integer multiplier (IMULT) +// +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_AUXPLL_IMULT(x) SYSCTL_IMULT((x)) + +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_AUXPLL_FMULT_NONE 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_0 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_1_4 0x00002000UL //!< Fractional multiplier - 0.25 +#define SYSCTL_AUXPLL_FMULT_1_2 0x00004000UL //!< Fractional multiplier - 0.50 +#define SYSCTL_AUXPLL_FMULT_3_4 0x00006000UL //!< Fractional multiplier - 0.75 + +// +// Oscillator source +// +//! Internal oscillator INTOSC2 as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_XTAL 0x00010000UL +//! AUXCLKIN (from GPIO) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_AUXCLKIN 0x00020000U + +// +// Enable/disable PLL +// +#define SYSCTL_AUXPLL_ENABLE 0x80000000U //!< Enable AUXPLL +#define SYSCTL_AUXPLL_DISABLE 0x00000000U //!< Disable AUXPLL + +//***************************************************************************** +// +// Values that can be passed to SysCtl_selectSecController() as the +// periFrame1Config and periFrame2Config parameters. +// +//***************************************************************************** +//! Configure CLA as the secondary controller +#define SYSCTL_SEC_CONTROLLER_CLA 0x0U +//! Configure DMA a secondary controller +#define SYSCTL_SEC_CONTROLLER_DMA 0x1U + +//***************************************************************************** +// +// Values that can be passed to SysCtl_clearNMIStatus(), +// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and +// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by +// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). +// +//***************************************************************************** +#define SYSCTL_NMI_NMIINT 0x1U //!< NMI Interrupt Flag +#define SYSCTL_NMI_CLOCKFAIL 0x2U //!< Clock Fail Interrupt Flag +#define SYSCTL_NMI_RAMUNCERR 0x4U //!< RAM Uncorrectable Error NMI Flag +#define SYSCTL_NMI_FLUNCERR 0x8U //!< Flash Uncorrectable Error NMI Flag +#define SYSCTL_NMI_CPU1HWBISTERR 0x10U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_CPU2HWBISTERR 0x20U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_PIEVECTERR 0x40U //!< PIE Vector Fetch Error Flag +#define SYSCTL_NMI_CLBNMI 0x100U //!< Configurable Logic Block NMI Flag +#define SYSCTL_NMI_CPU2WDRSN 0x200U //!< CPU2 WDRSn Reset Indication Flag +#define SYSCTL_NMI_CPU2NMIWDRSN 0x400U //!< CPU2 NMIWDRSn Reset Indication Flag + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_clearResetCause() +// API as rstCauses or returned by the SysCtl_getResetCause() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_POR 0x00000001U //!< Power-on reset +#define SYSCTL_CAUSE_XRS 0x00000002U //!< External reset pin +#define SYSCTL_CAUSE_WDRS 0x00000004U //!< Watchdog reset +#define SYSCTL_CAUSE_NMIWDRS 0x00000008U //!< NMI watchdog reset +#define SYSCTL_CAUSE_SCCRESET 0x00000100U //!< SCCRESETn by DCSM +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_enablePeripheral() +//! and SysCtl_disablePeripheral() as the \e peripheral parameter. +//! The EPWM Clock enable bit is also used to enable clocking for CLB. +//! The EPWM and CLB clock enable bits are mapped to same value, +// +//***************************************************************************** +#define SYSCTL_PERIPH_CLK_CLB1 SYSCTL_PERIPH_CLK_EPWM1 //!< CLB1 clock +#define SYSCTL_PERIPH_CLK_CLB2 SYSCTL_PERIPH_CLK_EPWM2 //!< CLB2 clock +#define SYSCTL_PERIPH_CLK_CLB3 SYSCTL_PERIPH_CLK_EPWM3 //!< CLB3 clock +#define SYSCTL_PERIPH_CLK_CLB4 SYSCTL_PERIPH_CLK_EPWM4 //!< CLB4 clock +//***************************************************************************** +// +// The following values define the adcsocSrc parameter for +// SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). +// +//***************************************************************************** +#define SYSCTL_ADCSOC_SRC_PWM1SOCA 0x1U //! EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT, //!< EPWM7SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT //!< EPWM10SYNCOUT --> EXTSYNCOUT + +} SysCtl_SyncOutputSource; + +//***************************************************************************** +// +//! The following values define the \e parametric parameter for +//! SysCtl_getDeviceParametric(). +// +//***************************************************************************** +typedef enum +{ + SYSCTL_DEVICE_QUAL, //!< Device Qualification Status + SYSCTL_DEVICE_PINCOUNT, //!< Device Pin Count + SYSCTL_DEVICE_INSTASPIN, //!< Device InstaSPIN Feature Set + SYSCTL_DEVICE_FLASH, //!< Device Flash size (KB) + SYSCTL_DEVICE_PARTID, //!< Device Part ID Format Revision + SYSCTL_DEVICE_FAMILY, //!< Device Family + SYSCTL_DEVICE_PARTNO, //!< Device Part Number + SYSCTL_DEVICE_CLASSID //!< Device Class ID +} SysCtl_DeviceParametric; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setXClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_XCLKOUT_DIV_1 = 0, //!< XCLKOUT = XCLKOUT / 1 + SYSCTL_XCLKOUT_DIV_2 = 1, //!< XCLKOUT = XCLKOUT / 2 + SYSCTL_XCLKOUT_DIV_4 = 2, //!< XCLKOUT = XCLKOUT / 4 + SYSCTL_XCLKOUT_DIV_8 = 3 //!< XCLKOUT = XCLKOUT / 8 + +}SysCtl_XClkDivider; + + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setAuxPLLClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_AUXPLLCLK_DIV_1, //!< AUXPLL clock = AUXPLL clock / 1 + SYSCTL_AUXPLLCLK_DIV_2, //!< AUXPLL clock = AUXPLL clock / 2 + SYSCTL_AUXPLLCLK_DIV_4, //!< AUXPLL clock = AUXPLL clock / 4 + SYSCTL_AUXPLLCLK_DIV_8, //!< AUXPLL clock = AUXPLL clock / 8 + SYSCTL_AUXPLLCLK_DIV_3, //!< AUXPLL clock = AUXPLL clock / 3 + SYSCTL_AUXPLLCLK_DIV_5, //!< AUXPLL clock = AUXPLL clock / 5 + SYSCTL_AUXPLLCLK_DIV_6, //!< AUXPLL clock = AUXPLL clock / 6 + SYSCTL_AUXPLLCLK_DIV_7 //!< AUXPLL clock = AUXPLL clock / 7 + +}SysCtl_AuxPLLClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setCputimer2Clk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKPRESCALE_1, //!< Cputimer2 clock = Cputimer2 clock / 1 + SYSCTL_TMR2CLKPRESCALE_2, //!< Cputimer2 clock = Cputimer2 clock / 2 + SYSCTL_TMR2CLKPRESCALE_4, //!< Cputimer2 clock = Cputimer2 clock / 4 + SYSCTL_TMR2CLKPRESCALE_8, //!< Cputimer2 clock = Cputimer2 clock / 8 + SYSCTL_TMR2CLKPRESCALE_16 //!< Cputimer2 clock = Cputimer2 clock / 16 + +}SysCtl_Cputimer2ClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_setCputimer2Clk() +//! as \e source parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKSRCSEL_SYSCLK = 0U, //!< System Clock + SYSCTL_TMR2CLKSRCSEL_INTOSC1 = 1U, //!< Internal Oscillator 1 + SYSCTL_TMR2CLKSRCSEL_INTOSC2 = 2U, //!< Internal Oscillator 2 + SYSCTL_TMR2CLKSRCSEL_XTAL = 3U, //!< Crystal oscillator + SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK = 6U //!< Aux PLL CLock + +}SysCtl_Cputimer2ClkSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Wrapper function for Device_cal function +//! +//! \param None +//! +//! This is a wrapper function for the Device_cal function available in the OTP +//! memory. +//! The function saves and restores the core registers which are being +//! used by the Device_cal function +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_deviceCal(void) +{ + // + // Save the core registers used by Device_cal function in the stack + // + SYSCTL_DEVICECAL_CONTEXT_SAVE; + + // + // Call the Device_cal function + // + Device_cal(); + + // + // Restore the core registers + // + SYSCTL_DEVICECAL_CONTEXT_RESTORE; +} + +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param peripheral is the peripheral to reset. +//! +//! This function uses the SOFTPRESx registers to reset a specified peripheral. +//! Module registers will be returned to their reset states. +//! +//! \note This includes registers containing trim values.The peripheral +//! software reset needed by CPU2 can be communicated to CPU1 via +//! IPC for all shared peripherals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Sets the appropriate reset bit and then clears it. + // + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) |= (1UL << bitIndex); + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) &= ~(1UL << bitIndex); + + // + // Call Device_cal function + // + if((((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU) || // ADCx + (((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0x10U) // DACx + ) + { + SysCtl_deviceCal(); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note Note that there should be atleast 5 cycles delay between enabling the +//! peripheral clock and accessing the peripheral registers. The delay should be +//! added by the user if the peripheral is accessed immediately after this +//! function call. +//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn on the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) |= (1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn off the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) &= ~(1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a watchdog reset of the device. +//! +//! \return This function does not return. +// +//***************************************************************************** +static inline void +SysCtl_resetDevice(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + + // + // Enable the watchdog + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + // + // Write a bad check value + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = 0U; + SYSCTL_REGWRITE_DELAY; + + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while((bool)1) + { + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset +//! statuses won't be accurate. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getResetCause(void) +{ + uint32_t resetCauses; + + // + // Read CPU reset register + // + resetCauses = HWREG(CPUSYS_BASE + SYSCTL_O_RESC) & + ((uint32_t)SYSCTL_RESC_POR | (uint32_t)SYSCTL_RESC_XRSN | + (uint32_t)SYSCTL_RESC_WDRSN | + (uint32_t)SYSCTL_RESC_NMIWDRSN | + (uint32_t)SYSCTL_RESC_SCCRESETN + ); + + // + // Set POR and XRS Causes from boot ROM Status + // + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_POR) == + (uint32_t)SYSCTL_BOOT_ROM_POR) + { + resetCauses |= SYSCTL_RESC_POR; + } + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_XRS) == + (uint32_t)SYSCTL_BOOT_ROM_XRS) + { + resetCauses |= SYSCTL_RESC_XRSN; + } + + // + // Return the reset reasons. + // + return(resetCauses); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param rstCauses are the reset causes to be cleared; must be a logical +//! OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtl_getResetCause(). +//! +//! \note Some reset causes are cleared by the boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearResetCause(uint32_t rstCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(CPUSYS_BASE + SYSCTL_O_RESC) = rstCauses; +} + +//***************************************************************************** +// +//! Sets the low speed peripheral clock rate prescaler. +//! +//! \param prescaler is the LSPCLK rate relative to SYSCLK +//! +//! This function configures the clock rate of the low speed peripherals. The +//! \e prescaler parameter is the value by which the SYSCLK rate is divided to +//! get the LSPCLK rate. For example, a \e prescaler of +//! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter +//! of the SYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = + (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + ~(uint32_t)SYSCTL_LOSPCP_LSPCLKDIV_M) | (uint32_t)prescaler; + EDIS; +} + +//***************************************************************************** +// +//! Sets the ePWM clock divider. +//! +//! \param divider is the value by which PLLSYSCLK is divided +//! +//! This function configures the clock rate of the EPWMCLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an +//! EPWMCLK rate that is half the PLLSYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) & + ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF1 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF1CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF1CLK rate. For example, \b SYSCTL_EMIF1CLK_DIV_2 will select an +//! EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF1CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF2 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF2CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF2CLK rate. For example, \b SYSCTL_EMIF2CLK_DIV_2 will select an +//! EMIF2CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF2ClockDivider(SysCtl_EMIF2CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF2CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Selects a clock source to mux to an external GPIO pin (XCLKOUT). +//! +//! \param source is the internal clock source to be configured. +//! +//! This function configures the specified clock source to be muxed to an +//! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a +//! value of one of the following values: +//! - \b SYSCTL_CLOCKOUT_PLLSYS +//! - \b SYSCTL_CLOCKOUT_PLLRAW +//! - \b SYSCTL_CLOCKOUT_SYSCLK +//! - \b SYSCTL_CLOCKOUT_INTOSC1 +//! - \b SYSCTL_CLOCKOUT_INTOSC2 +//! - \b SYSCTL_CLOCKOUT_XTALOSC +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectClockOutSource(SysCtl_ClockOut source) +{ + EALLOW; + + // + // Clear clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) &= + ~SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M; + SYSCTL_CLKSRCCTL_DELAY; + + // + // Set clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) |= (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the external oscillator counter value. +//! +//! This function returns the X1 clock counter value. When the return value +//! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external +//! oscillator (XTAL), an application should call this function to make sure +//! the counter is saturated. +//! +//! \return Returns the value of the 10-bit X1 clock counter. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getExternalOscCounterValue(void) +{ + return(HWREGH(CLKCFG_BASE + SYSCTL_O_X1CNT) & SYSCTL_X1CNT_X1CNT_M); +} + +//***************************************************************************** +// +//! Turns on the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns on the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOnOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Turns off the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns off the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOffOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn off INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enters IDLE mode. +//! +//! This function puts the device into IDLE mode. The CPU clock is gated while +//! all peripheral clocks are left running. Any enabled interrupt will wake the +//! CPU up from IDLE mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterIdleMode(void) +{ + EALLOW; + + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters STANDBY mode. +//! +//! This function puts the device into STANDBY mode. This will gate both the +//! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is +//! left active, and an NMI or an optional watchdog interrupt will wake the +//! CPU subsystem from STANDBY mode. +//! +//! GPIOs may be configured to wake the CPU subsystem. See +//! SysCtl_enableLPMWakeupPin(). +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterStandbyMode(void) +{ + EALLOW; + + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters HALT mode. +//! +//! This function puts the device into HALT mode. This will gate almost all +//! systems and clocks and allows for the power-down of oscillators and analog +//! blocks. The watchdog may be left clocked to produce a reset. See +//! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be +//! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). +//! +//! Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHaltMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + asm(" IDLE"); + +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into HALT mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +// +//! Enters Hibernate mode. +//! +//! This function puts the device into Hibernate mode. Hibernate (HIB) is a +//! global low-power mode that gates the supply voltages to most of the system. +//! This mode affects both CPU subsystems. HIB is essentially a controlled +//! power-down with remote wakeup capability, and can be used to save power +//! during long periods of inactivity. +//! +//! To wake the device from HIB mode: +//! 1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the +//! power-up of the device clock sources. +//! 2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the +//! rest of the device. +//! +//! To enter Hibernate mode in dual CPU put CPU2 in STANDBY mode first. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHibernateMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + asm(" IDLE"); +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into Hibernate mode when IDLE is executed + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HIB; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +//! Enables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function connects a pin to the LPM circuit, allowing an event on the +//! pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of +//! being connected to the LPM circuit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) |= pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) |= pinMask; + } + + EDIS; +} + +//***************************************************************************** +//! Disables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function disconnects a pin to the LPM circuit, disallowing an event on +//! the pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) &= ~pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the number of cycles to qualify an input on waking from STANDBY mode. +//! +//! \param cycles is the number of OSCCLK cycles. +//! +//! This function sets the number of OSCCLK clock cycles used to qualify the +//! selected inputs when waking from STANDBY mode. The \e cycles parameter +//! should be passed a cycle count between 2 and 65 cycles inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setStandbyQualificationPeriod(uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT((cycles >= 2U) && (cycles <= 65U)); + + EALLOW; + + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint16_t)SYSCTL_LPMCR_QUALSTDBY_M) | + ((cycles - 2U) << SYSCTL_LPMCR_QUALSTDBY_S); + + EDIS; +} + +//***************************************************************************** +// +//! Enable the device to wake from STANDBY mode upon a watchdog interrupt. +//! +//! \note In order to use this option, you must configure the watchdog to +//! generate an interrupt using SysCtl_setWatchdogMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Set the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) |= SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the device from waking from STANDBY mode upon a watchdog interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Clear the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) &= ~SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the watchdog to run while in HALT mode. +//! +//! This function configures the watchdog to continue to run while in HALT +//! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the +//! system enters HALT mode. By default the watchdog is gated when the system +//! enters HALT. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogInHalt(void) +{ + EALLOW; + + // + // Set the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the watchdog from running while in HALT mode. +//! +//! This function gates the watchdog when the system enters HALT mode. INTOSC1 +//! and INTOSC2 will be powered down. This is the default behavior of the +//! device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogInHalt(void) +{ + EALLOW; + + // + // Clear the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the watchdog generates a reset or an interrupt signal. +//! +//! \param mode is a flag to select the watchdog mode. +//! +//! This function configures the action taken when the watchdog counter reaches +//! its maximum value. When the \e mode parameter is +//! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog +//! interrupt signal and disables the generation of a reset signal. This will +//! allow the watchdog module to wake up the device from IDLE +//! or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()). +//! +//! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will +//! be put into reset mode and generation of a watchdog interrupt signal will +//! be disabled. This is how the watchdog is configured by default. +//! +//! \note Check the status of the watchdog interrupt using +//! SysCtl_isWatchdogInterruptActive() before calling this function. If the +//! interrupt is still active, switching from interrupt mode to reset mode will +//! immediately reset the device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogMode(SysCtl_WDMode mode) +{ + EALLOW; + + // + // Either set or clear the WDENINT bit to that will determine whether the + // watchdog will generate a reset signal or an interrupt signal. Take care + // not to write a 1 to WDOVERRIDE. + // + if(mode == SYSCTL_WD_MODE_INTERRUPT) + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) = + (HWREGH(WD_BASE + SYSCTL_O_SCSR) & ~SYSCTL_SCSR_WDOVERRIDE) | + SYSCTL_SCSR_WDENINT; + } + else + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) &= ~(SYSCTL_SCSR_WDENINT | + SYSCTL_SCSR_WDOVERRIDE); + } + + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of the watchdog interrupt signal. +//! +//! This function returns the status of the watchdog interrupt signal. If the +//! interrupt is active, this function will return \b true. If \b false, the +//! interrupt is NOT active. +//! +//! \note Make sure to call this function to ensure that the interrupt is not +//! active before making any changes to the configuration of the watchdog to +//! prevent any unexpected behavior. For instance, switching from interrupt +//! mode to reset mode while the interrupt is active will immediately reset the +//! device. +//! +//! \return \b true if the interrupt is active and \b false if it is not. +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogInterruptActive(void) +{ + // + // If the status bit is cleared, the WDINTn signal is active. + // + return((HWREGH(WD_BASE + SYSCTL_O_SCSR) & SYSCTL_SCSR_WDINTS) == 0U); +} + +//***************************************************************************** +// +//! Disables the watchdog. +//! +//! This function disables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdog(void) +{ + EALLOW; + + // + // Set the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) |= SYSCTL_WD_CHKBITS | SYSCTL_WDCR_WDDIS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Enables the watchdog. +//! +//! This function enables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdog(void) +{ + EALLOW; + + // + // Clear the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~SYSCTL_WDCR_WDDIS) | SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Checks if the watchdog is enabled or not +//! +//! This function returns the watchdog status whether it is enabled or disabled +//! +//! \return \b true if the watchdog is enabled & \b false if the watchdog is +//! disabled +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogEnabled(void) +{ + + // + // Get the watchdog enable status + // + return ((HWREGH(WD_BASE + SYSCTL_O_WDCR) & SYSCTL_WDCR_WDDIS) == 0U); +} + +//***************************************************************************** +// +//! Services the watchdog. +//! +//! This function resets the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_serviceWatchdog(void) +{ + EALLOW; + + // + // Enable the counter to be reset and then reset it. + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the first key to enter the watchdog reset. +//! +//! This function writes the first key to enter the watchdog reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogReset(void) +{ + EALLOW; + + // + // Enable the counter to be reset + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the second key to reset the watchdog. +//! +//! This function writes the second key to reset the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetWatchdog(void) +{ + EALLOW; + + // + // Reset the watchdog counter + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up watchdog clock (WDCLK) prescaler. +//! +//! \param prescaler is the value that configures the watchdog clock relative +//! to the value from the pre-divider. +//! +//! This function sets up the watchdog clock (WDCLK) prescaler. The +//! \e prescaler parameter divides INTOSC1 down to WDCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) +{ + uint16_t regVal; + + regVal = (uint16_t)prescaler | (uint16_t)SYSCTL_WD_CHKBITS; + + EALLOW; + + // + // Write the prescaler to the appropriate register. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~(SYSCTL_WDCR_WDPS_M)) | regVal; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the watchdog counter value. +//! +//! \return Returns the current value of the 8-bit watchdog counter. If this +//! count value overflows, a watchdog output pulse is generated. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getWatchdogCounterValue(void) +{ + // + // Read and return the value of the watchdog counter. + // + return(HWREGH(WD_BASE + SYSCTL_O_WDCNTR)); +} + +//***************************************************************************** +// +//! Gets the watchdog reset status. +//! +//! This function returns the watchdog reset status. If this function returns +//! \b true, that indicates that a watchdog reset generated the last reset +//! condition. Otherwise, it was an external device or power-up reset +//! condition. +//! +//! \return Returns \b true if the watchdog generated the last reset condition. +// +//***************************************************************************** +static inline bool +SysCtl_getWatchdogResetStatus(void) +{ + // + // Read and return the status of the watchdog reset status flag. + // + return((HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) & SYSCTL_RESC_WDRSN) != 0U); +} + +//***************************************************************************** +// +//! Clears the watchdog reset status. +//! +//! This function clears the watchdog reset status. To check if it was set +//! first, see SysCtl_getWatchdogResetStatus(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogResetStatus(void) +{ + EALLOW; + + // + // Read and return the status of the watchdog reset status flag. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) = SYSCTL_RESC_WDRSN; + + EDIS; +} + +//***************************************************************************** +// +//! Set the minimum threshold value for windowed watchdog +//! +//! \param value is the value to set the window threshold +//! +//! This function sets the minimum threshold value used to define the lower +//! limit of the windowed watchdog functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogWindowValue(uint16_t value) +{ + EALLOW; + + // + // Clear the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) &= ~SYSCTL_WDWCR_MIN_M; + + // + // Set the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) |= (value & SYSCTL_WDWCR_MIN_M); + + EDIS; +} + +//***************************************************************************** +// +//! Clears the watchdog override. +//! +//! This function clears the watchdog override and locks the watchdog timer +//! module to remain in its prior state which could be either enable /disable. +//! The watchdog timer will remain in this state until the next system reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogOverride(void) +{ + EALLOW; + + HWREGH(WD_BASE + SYSCTL_O_SCSR) |= SYSCTL_SCSR_WDOVERRIDE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the NMI Global interrupt bit +//! +//! \b Note: This bit should be set after the device security related +//! initialization is complete. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableNMIGlobalInterrupt(void) +{ + EALLOW; + + HWREGH(NMI_BASE + NMI_O_CFG) |= NMI_CFG_NMIE; + + EDIS; +} + +//***************************************************************************** +// +//! Read NMI interrupts. +//! +//! Read the current state of NMI interrupt. +//! +//! \return \b true if NMI interrupt is triggered, \b false if not. +// +//***************************************************************************** +static inline bool +SysCtl_getNMIStatus(void) +{ + // + // Read and return the current value of the NMI flag register, masking out + // all but the NMI bit. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & NMI_FLG_NMIINT) != 0U); +} + +//***************************************************************************** +// +//! Read NMI Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMIFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIFlagStatus(void) +{ + // + // Read and return the current value of the NMI flag register. + // + return(HWREGH(NMI_BASE + NMI_O_FLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI interrupts are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Function to clear individual NMI interrupts. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Clear NMI interrupt flags that correspond with the passed in bit mask. +//! +//! \b Note: The NMI Interrupt flag is always cleared by default and +//! therefore doesn't have to be included in the bit mask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearNMIStatus(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Clear the individual flags as well as NMI Interrupt flag + // + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Clear all the NMI Flags that are currently set. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearAllNMIFlags(void) +{ + uint16_t nmiFlags; + + // + // Read the flag status register and then write to the clear register, + // clearing all the flags that were returned plus the NMI flag. + // + EALLOW; + + nmiFlags = SysCtl_getNMIFlagStatus(); + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Function to force individual NMI interrupt fail flags +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_forceNMIFlags(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Set the Flags for the individual interrupts in the NMI flag + // force register + // + HWREGH(NMI_BASE + NMI_O_FLGFRC) |= nmiFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog counter value. +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns the NMI watchdog counter register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogCounter(void) +{ + // + // Read and return the NMI watchdog counter register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDCNT)); +} + +//***************************************************************************** +// +//! Sets the NMI watchdog period value. +//! +//! \param wdPeriod is the 16-bit value at which a reset is generated. +//! +//! This function writes to the NMI watchdog period register that holds the +//! value to which the NMI watchdog counter is compared. When the two registers +//! match, a reset is generated. By default, the period is 0xFFFF. +//! +//! \note If a value smaller than the current counter value is passed into the +//! \e wdPeriod parameter, a NMIRSn will be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) +{ + EALLOW; + + // + // Write to the period register. + // + HWREGH(NMI_BASE + NMI_O_WDPRD) = wdPeriod; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog period value. +//! +//! \return Returns the NMI watchdog period register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogPeriod(void) +{ + // + // Read and return the NMI watchdog period register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDPRD)); +} + +//***************************************************************************** +// +//! Read NMI Shadow Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMISHDFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint32_t +SysCtl_getNMIShadowFlagStatus(void) +{ + // + // Read and return the current value of the NMI shadow flag register. + // + return(HWREGH(NMI_BASE + NMI_O_SHDFLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI shadow flags are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIShadowFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_SHDFLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Enable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_MCLKOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Get the missing clock detection Failure Status +//! +//! \note A failure means the oscillator clock is missing +//! +//! \return Returns \b true if a failure is detected or \b false if a +//! failure isn't detected +// +//***************************************************************************** +static inline bool +SysCtl_isMCDClockFailureDetected(void) +{ + // + // Check the status bit to determine failure + // + return((HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) & SYSCTL_MCDCR_MCLKSTS) != 0U); +} + +//***************************************************************************** +// +//! Reset the missing clock detection logic after clock failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Re-connect missing clock detection clock source to stop simulating clock +//! failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_connectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_OSCOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disconnect missing clock detection clock source to simulate clock failure. +//! This is for testing the MCD functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disconnectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_OSCOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the sync input source for the ePWM and eCAP signals. +//! +//! \param syncInput is the sync input being configured +//! \param syncSrc is sync input source selection. +//! +//! This function configures the sync input source for the ePWM and eCAP +//! modules. The \e syncInput parameter is the sync input being configured. It +//! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM +//! or eCAP instance the sync signal is entering. +//! +//! The \e syncSrc parameter is the sync signal selected as the source of the +//! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, +//! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. +//! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a +//! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the +//! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. +//! +//! Note that some \e syncSrc values are only valid for certain values of +//! \e syncInput. See device technical reference manual for details on +//! time-base counter synchronization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, + SysCtl_SyncInputSource syncSrc) +{ + uint32_t clearMask; + + // + // Write the input sync source selection to the appropriate register. + // + EALLOW; + clearMask = (uint32_t)SYSCTL_SYNCSELECT_SYNCIN_M << (uint32_t)syncInput; + + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & ~clearMask) | + ((uint32_t)syncSrc << (uint32_t)syncInput); + + EDIS; +} +//***************************************************************************** +// +//! Configures the sync output source. +//! +//! \param syncSrc is sync output source selection. +//! +//! This function configures the sync output source from the ePWM modules. The +//! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is +//! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) +{ + // + // Write the sync output source selection to the appropriate register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & + ~((uint32_t)SYSCTL_SYNCSELECT_SYNCOUT_M)) | + ((uint32_t)syncSrc << SYSCTL_SYNCSELECT_SYNCOUT_S); + EDIS; + +} +//***************************************************************************** +// +//! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be enabled +//! +//! This function configures which ePWM SOC signals are enabled as a source for +//! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR +//! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Set the bits that correspond to signal to be enabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) |= adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Disables ePWM SOC signals from driving an external ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be disabled +//! +//! This function configures which ePWM SOC signals are disabled as a source +//! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical +//! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Clear the bits that correspond to signal to be disabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) &= ~adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Locks the SOC Select of the Trig X-BAR. +//! +//! This function locks the external ADC SOC select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockExtADCSOCSelect(void) +{ + // + // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = + SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT; + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the dual ported bridge is connected with DMA or +//! CLA as the secondary controller. +//! +//! \param periFrame1Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 1. +//! \param periFrame2Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 2. +//! +//! One of the following values can be passed as parameter. +//! \b SYSCTL_SEC_CONTROLLER_CLA +//! \b SYSCTL_SEC_CONTROLLER_DMA +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectSecController(uint16_t periFrame1Config, uint16_t periFrame2Config) +{ + EALLOW; + + HWREG(CPUSYS_BASE + SYSCTL_O_SECMSEL) = + (((periFrame1Config << SYSCTL_SECMSEL_PF1SEL_S) & + SYSCTL_SECMSEL_PF1SEL_M) | + ((periFrame2Config << SYSCTL_SECMSEL_PF2SEL_S) & + SYSCTL_SECMSEL_PF2SEL_M)); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the Sync Select of the Trig X-BAR. +//! +//! This function locks Sync Input and Output Select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockSyncSelect(void) +{ + // + // Lock the SYNCSELECT register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = SYSCTL_SYNCSOCLOCK_SYNCSELECT; + EDIS; +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeriphInstance +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheralInstance(SysCtl_CPUSelPeriphInstance peripheral, + SysCtl_CPUSel cpuInst) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Identify the register index and bit position + // + regIndex = 2U * ((uint16_t)peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Configure the CPU owner for the specified peripheral instance + // + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) = + (HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) & ~(1UL << bitIndex)) | + ((uint32_t)cpuInst << bitIndex); + + EDIS; + +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param peripheralInst is the instance for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! The \e peripheralInst parameter is the instance number for example +//! 1 for EPWM1, 2 for EPWM2 so on.For instances which are named with alphabets +//! (instead of numbers) the following convention needs to be followed. +//! 1 for A (SPI_A), 2 for B (SPI_B), 3 for C (SPI_C) so on... +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \note This function is retained for compatibility puposes. Recommended to +//! to use the function \e SysCtl_selectCPUForPeripheralInstance() +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheral(SysCtl_CPUSelPeripheral peripheral, + uint16_t peripheralInst, SysCtl_CPUSel cpuInst) +{ + uint32_t tempValue; + uint16_t shift; + + if(SYSCTL_CPUSEL14_DAC == peripheral) + { + shift = peripheralInst + SYSCTL_CPUSEL_DAC_S - 1U; + } + else + { + shift = peripheralInst - 1U; + } + + tempValue = + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) & + (~(1UL << shift)); + + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) = + tempValue | ((uint32_t)cpuInst << shift); + EDIS; +} +//***************************************************************************** +// +//! Get the Device Silicon Revision ID +//! +//! This function returns the silicon revision ID for the device. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the silicon revision ID value. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceRevision(void) +{ + // + // Returns the device silicon revision ID + // + return(HWREG(DEVCFG_BASE + SYSCTL_O_REVID)); +} + +//***************************************************************************** +// +//! Locks the CPU select registers for the peripherals +//! +//! \param peripheral is the peripheral for which CPU needs to be selected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockCPUSelectRegs(SysCtl_CPUSelPeripheral peripheral) +{ + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_DEVCFGLOCK1) |= (1UL << (uint32_t)peripheral); + EDIS; +} + + +//***************************************************************************** +// +//! Gets the error status of the Efuse +//! +//! The function provides both the Efuse Autoload & the Efuse Self Test +//! Error Status. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Fuse Error status. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getEfuseError(void) +{ + return(HWREGH(DEVCFG_BASE + SYSCTL_O_FUSEERR)); +} + +//***************************************************************************** +// +//! Sets up XCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the XCLK divider. There is only one +//! divider that scales INTOSC1 to XCLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_XClkDivider +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setXClk(SysCtl_XClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) & + ~(SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M)) | + (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up PLLSYSCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the PLLSYSCLK divider. There is only one +//! divider that scales PLLSYSCLK to generate the system clock. +//! +//! The \e divider parameter can have one value from the set below: +//! 0x0 = /1 +//! 0x1 = /2 +//! 0x2 = /4 (default on reset) +//! 0x3 = /6 +//! 0x4 = /8 +//! ...... +//! 0x3F =/126 +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setPLLSysClk(uint16_t divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)) | divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up AUXPLLCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the AUXPLLCLK divider. There is only one +//! divider that scales AUXPLLCLK to generate the system clock. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_AuxPLLClkDivider +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setAuxPLLClk(SysCtl_AuxPLLClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + ~(SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up CPU Timer 2 CLK source & divider. +//! +//! \param divider is the value that configures the divider. +//! \param source is the source for the clock divider +//! +//! This function sets up the CPU Timer 2 CLK divider based on the source that +//! is selected. There is only one divider that scales the "source" to +//! CPU Timer 2 CLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkDivider +//! The \e source parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkSource +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider, + SysCtl_Cputimer2ClkSource source) +{ + // + // Clears the divider & the source, then configures it. + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~(SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M | + SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M)); + SYSCTL_REGWRITE_DELAY; + + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= + ((uint16_t)divider << SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S) | + ((uint16_t)source << SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S); + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Gets the PIE Vector Fetch Error Handler Routine Address. +//! +//! The function indicates the address of the PIE Vector Fetch Error +//! handler routine. +//! +//! \return Error Handler Address. +//! +//! \note Its the responsibility of user to initialize this register. If this +//! register is not initialized, a default error handler at address +//! 0x3fffbe will get executed. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getPIEVErrAddr(void) +{ + return(HWREG(CPUSYS_BASE + SYSCTL_O_PIEVERRADDR)); +} + +//***************************************************************************** +// +//! Check if the Internal PHY is present or not for the USB module +//! +//! Provides the USB module Internal PHY presence +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return \b true if Internal USB PHY Module is present \b false if +//! Internal USB PHY Module is not present +// +//***************************************************************************** +static inline bool +SysCtl_isPresentUSBPHY(void) +{ + return((HWREG(DEVCFG_BASE + SYSCTL_O_PERCNF1) & + SYSCTL_PERCNF1_USB_A_PHY) != 0U); +} + +//***************************************************************************** +// +//! Get the device UID_UNIQUE value +//! +//! This function returns the device UID_UNIQUE value +//! +//! \return Returns the device UID_UNIQUE value +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceUID(void) +{ + // + // Returns the device UID_UNIQUE value + // + return(HWREG(UID_BASE + OTP_O_UID_UNIQUE)); +} + +//***************************************************************************** +// +//! Delays for a fixed number of cycles. +//! +//! \param count is the number of delay loop iterations to perform. +//! +//! This function generates a constant length delay using assembly code. The +//! loop takes 5 cycles per iteration plus 9 cycles of overhead. +//! +//! \note If count is equal to zero, the loop will underflow and run for a +//! very long time. +//! +//! \note Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to +//! insert a delay in microseconds. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_delay(uint32_t count); + +//***************************************************************************** +// +//! Calculates the system clock frequency (SYSCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the system clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the PLL +//! and clock divider configuration registers. +//! +//! \return Returns the system clock frequency. If a missing clock is detected, +//! the function will return the INTOSC1 frequency. This needs to be +//! corrected and cleared (see SysCtl_resetMCD()) before trying to call this +//! function again. +// +//***************************************************************************** +extern uint32_t +SysCtl_getClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Calculates the system auxiliary clock frequency (AUXPLLCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source +//! (AUXOSCCLK). +//! +//! This function determines the frequency of the auxiliary clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the AUXPLL +//! and clock divider configuration registers. +//! +//! \return Returns the auxiliary clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getAuxClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Configures the clocking of the device. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) +//! where x is either 1 or an even value up to 126. +//! +//! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or +//! \b SYSCTL_PLL_DISABLE. +//! +//! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value +//! from 1 to 127. +//! +//! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, +//! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. +//! +//! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, +//! \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! This function uses the watchdog as a monitor for the PLL. The user +//! watchdog settings will be modified and restored upon completion. Make sure +//! that the WDOVERRIDE bit isn't set before calling this function. Re-lock +//! attempt is carried out if either SLIP condition occurs or SYSCLK to input +//! clock ratio is off by 10%. +//! +//! This function uses the following resources to support PLL initialization: +//! - Watchdog +//! - CPU Timer 1 +//! - CPU Timer 2 +//! +//! +//! \note See your device errata for more details about locking the PLL. +//! +//! \return Returns \b false if a missing clock error is detected. This needs +//! to be cleared (see SysCtl_resetMCD()) before trying to call this function +//! again. Otherwise, returns \b true. +// +//***************************************************************************** +extern bool +SysCtl_setClock(uint32_t config); + +//***************************************************************************** +// +//! Configures the external oscillator for the clocking of the device. +//! +//! This function configures the external oscillator (XTAL) to be used for the +//! clocking of the device in crystal mode. It follows the procedure to turn on +//! the oscillator, wait for it to power up, and select it as the source of the +//! system clock. +//! +//! Please note that this function blocks while it waits for the XTAL to power +//! up. If the XTAL does not manage to power up properly, the function will +//! loop for a long time. It is recommended that you modify this function to +//! add an appropriate timeout and error-handling procedure. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectXTAL(void); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the clocking of the device. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! device. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSource(uint32_t oscSource); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the AUXPLL. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! AUXPLL. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource); + +//***************************************************************************** +// +//! Calculates the low-speed peripheral clock frequency (LSPCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the low-speed peripheral clock +//! based on the frequency of the oscillator clock source (from \e clockInHz) +//! and the PLL and clock divider configuration registers. +//! +//! \return Returns the low-speed peripheral clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Get the device part parametric value +//! +//! \param parametric is the requested device parametric value +//! +//! This function gets the device part parametric value. +//! +//! The \e parametric parameter can have one the following enumerated values: +//! - \b SYSCTL_DEVICE_QUAL - Device Qualification Status +//! - \b SYSCTL_DEVICE_PINCOUNT - Device Pin Count +//! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set +//! - \b SYSCTL_DEVICE_FLASH - Device Flash size (KB) +//! - \b SYSCTL_DEVICE_PARTID - Device Part ID Format Revision +//! - \b SYSCTL_DEVICE_FAMILY - Device Family +//! - \b SYSCTL_DEVICE_PARTNO - Device Part Number +//! - \b SYSCTL_DEVICE_CLASSID - Device Class ID +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the specified parametric value. +// +//***************************************************************************** +extern uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric); + +//***************************************************************************** +// +//! Configures the auxiliary PLL for clocking USB. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clock source for auxiliary PLL, the integer +//! multiplier, fractional multiplier and divider. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with one of the following macros: +//! \b SYSCTL_AUXPLL_DIV_1, +//! \b SYSCTL_AUXPLL_DIV_2, +//! \b SYSCTL_AUXPLL_DIV_4, +//! \b SYSCTL_AUXPLL_DIV_8 +//! +//! - The use of the PLL is chosen with either \b SYSCTL_AUXPLL_ENABLE or +//! \b SYSCTL_AUXPLL_DISABLE. +//! +//! - The integer multiplier is chosen with \b SYSCTL_AUXPLL_IMULT(x) where x +//! is a value from 1 to 127. +//! +//! - The oscillator source chosen with one of +//! \b SYSCTL_AUXPLL_OSCSRC_OSC2, +//! \b SYSCTL_AUXPLL_OSCSRC_XTAL, +//! \b SYSCTL_AUXPLL_OSCSRC_AUXCLKIN, +//! +//! \note This function uses CPU Timer 2 to monitor a successful lock of the +//! AUXPLL. For this function to properly detect the PLL startup +//! SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +//! User configuration of CPU Timer 2 will be backed up and restored. +//! \note See your device errata for more details about locking the PLL. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_setAuxClock(uint32_t config); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SYSCTL_H diff --git a/gpio_bitfield_cpu2/device/driverlib/upp.c b/gpio_bitfield_cpu2/device/driverlib/upp.c new file mode 100644 index 0000000..a3fb8da --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/upp.c @@ -0,0 +1,298 @@ +//########################################################################### +// +// FILE: upp.c +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "upp.h" + +//***************************************************************************** +// +// UPP_setDMAReadThreshold +// +//***************************************************************************** +void +UPP_setDMAReadThreshold(uint32_t base, UPP_DMAChannel channel, + UPP_ThresholdSize size) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Set DMA read threshold for channel I. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEI_M) | + (uint16_t)size; + } + else + { + // + // Set DMA read threshold for channel Q. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEQ_M) | + ((uint16_t)size << UPP_THCFG_RDSIZEQ_S); + } +} + +//***************************************************************************** +// +// UPP_setDMADescriptor +// +//***************************************************************************** +void +UPP_setDMADescriptor(uint32_t base, UPP_DMAChannel channel, + const UPP_DMADescriptor * const desc) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Sets DMA descriptors for channel I. + // + HWREG(base + UPP_O_CHIDESC0) = desc->addr; + HWREG(base + UPP_O_CHIDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHIDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHIDESC2) = desc->lineOffset; + } + else + { + // + // Sets DMA descriptors for channel Q. + // + HWREG(base + UPP_O_CHQDESC0) = desc->addr; + HWREG(base + UPP_O_CHQDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHQDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHQDESC2) = desc->lineOffset; + } +} + +//***************************************************************************** +// +// UPP_getDMAChannelStatus +// +//***************************************************************************** +void +UPP_getDMAChannelStatus(uint32_t base, UPP_DMAChannel channel, + UPP_DMAChannelStatus * const status) +{ + uint32_t cntStatus; + + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the current status for channel I. + // + cntStatus = HWREG(base + UPP_O_CHIST1); + status->curAddr = HWREG(base + UPP_O_CHIST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHIDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHIDESC1_LCNT_S); + } + else + { + // + // Return the current status for channel Q. + // + cntStatus = HWREG(base + UPP_O_CHQST1); + status->curAddr = HWREG(base + UPP_O_CHQST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHQDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHQDESC1_LCNT_S); + } +} + +//***************************************************************************** +// +// UPP_isDescriptorPending +// +//***************************************************************************** +bool +UPP_isDescriptorPending(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the pend status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_PEND) == UPP_CHIST2_PEND); + } + else + { + // + // Return the pend status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_PEND) == UPP_CHQST2_PEND); + } + return(status); +} + +//***************************************************************************** +// +// UPP_isDescriptorActive +// +//***************************************************************************** +bool +UPP_isDescriptorActive(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Returns active status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_ACT) == UPP_CHIST2_ACT); + } + else + { + // + // Returns active status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_ACT) == UPP_CHQST2_ACT); + } + return(status); +} + +//***************************************************************************** +// +// UPP_getDMAFIFOWatermark +// +//***************************************************************************** +uint16_t +UPP_getDMAFIFOWatermark(uint32_t base, UPP_DMAChannel channel) +{ + uint16_t status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_WM_M) >> UPP_CHIST2_WM_S); + } + else + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_WM_M) >> UPP_CHQST2_WM_S); + } + return(status); +} + +//***************************************************************************** +// +// UPP_readRxMsgRAM +// +//***************************************************************************** +void +UPP_readRxMsgRAM(uint32_t rxBase, uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isRxBaseValid(rxBase)); + ASSERT((length + offset) < UPP_RX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Read one 16-bit word. + // + array[i] = HWREGH(rxBase + offset + i); + } +} + +//***************************************************************************** +// +// UPP_writeTxMsgRAM +// +//***************************************************************************** +void +UPP_writeTxMsgRAM(uint32_t txBase, const uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isTxBaseValid(txBase)); + ASSERT((length + offset) < UPP_TX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Write one 16-bit word. + // + HWREGH(txBase + offset + i) = array[i]; + } +} diff --git a/gpio_bitfield_cpu2/device/driverlib/upp.h b/gpio_bitfield_cpu2/device/driverlib/upp.h new file mode 100644 index 0000000..128d077 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/upp.h @@ -0,0 +1,1574 @@ +//########################################################################### +// +// FILE: upp.h +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef UPP_H +#define UPP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup upp_api UPP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_upp.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines that can be passed as addr field of UPP_DMADescriptor to +// UPP_setDMADescriptor(). Since the addresses for Tx & Rx MSG RAMs are +// different for CPU & DMA views, these defines can be used as DMA descriptor +// addresses. +// +//***************************************************************************** +#define UPP_DMA_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_DMA_RX_MSGRAM_STARTADDR 0x00007000U + +//***************************************************************************** +// +// Defines that can be used in user program as start address for CPU/CLA write +// to TX MSG RAM for transmitting data & for CPU/CLA read from RX MSG RAM for +// receiving data. Since the addresses for Tx & Rx MSG RAMs are different for +// CPU & DMA views, these defines can be used for CPU read/writes. +// +//***************************************************************************** +#define UPP_CPU_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_CPU_RX_MSGRAM_STARTADDR UPP_RX_MSG_RAM_BASE + +//***************************************************************************** +// +// Defines to specify the size of the uPP Tx and Rx MSG RAMs. +// +//***************************************************************************** +#define UPP_TX_MSGRAM_MAX_SIZE 0x200U +#define UPP_RX_MSGRAM_MAX_SIZE 0x200U + +//***************************************************************************** +// +// Define to specify 32 cycle delay between software reset issue & release in +// UPP_performSoftReset(). +// +//***************************************************************************** +#ifndef UPP_32_CYCLE_NOP +#define UPP_32_CYCLE_NOP __asm(" RPT #31 || NOP") +#endif + +//***************************************************************************** +// +// Define to specify mask for setting emulation mode in UPP_setEmulationMode(). +// +//***************************************************************************** +#define UPP_SOFT_FREE_M ((uint16_t)UPP_PERCTL_SOFT | \ + (uint16_t)UPP_PERCTL_FREE) + +//***************************************************************************** +// +// Defines to specify masks for enabling/disabling uPP Tx/Rx control signals in +// UPP_setTxControlSignalMode() & UPP_setRxControlSignalMode() respectively. +// +//***************************************************************************** +#define UPP_TX_SIGNAL_MODE_M UPP_IFCFG_WAITA +#define UPP_RX_SIGNAL_MODE_M ((uint16_t)UPP_IFCFG_STARTA | \ + (uint16_t)UPP_IFCFG_ENAA) + +//***************************************************************************** +// +// Define to specify mask for configuring polarities for uPP control signals +// in UPP_setControlSignalPolarity(). +// +//***************************************************************************** +#define UPP_SIGNAL_POLARITY_M ((uint16_t)UPP_IFCFG_WAITPOLA | \ + (uint16_t)UPP_IFCFG_ENAPOLA | \ + (uint16_t)UPP_IFCFG_STARTPOLA) + +//***************************************************************************** +// +// Define to specify masks for returning interrupt status in +// UPP_getInterruptStatus() & UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_M ((uint16_t)UPP_ENINTST_DPEI | (uint16_t)UPP_ENINTST_UOEI | \ + (uint16_t)UPP_ENINTST_EOWI | (uint16_t)UPP_ENINTST_EOLI | \ + (uint16_t)UPP_ENINTST_DPEQ | (uint16_t)UPP_ENINTST_UOEQ | \ + (uint16_t)UPP_ENINTST_EOWQ | (uint16_t)UPP_ENINTST_EOLQ) + +//***************************************************************************** +// +// Values that can be passed to UPP_enableInterrupt(), +// UPP_disableInterrupt() and UPP_clearInterruptStatus() as the +// intFlags parameter and returned by UPP_getInterruptStatus() & +// UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_CHI_DMA_PROG_ERR 0x0001U //! +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "debug.h" +#include "sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16U + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16U + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10U) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0U) || (ui32Endpoint == 1U) || (ui32Endpoint == 2U) || + (ui32Endpoint == 3U)); + ASSERT((ui32Size == 1U) || (ui32Size == 2U)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1U) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USBA_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0U; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = 0U; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0U); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0U; + *pui32IntStatusEP = 0U; + uint32_t usbis = 0U; + uint32_t rxis = 0U; + uint32_t txis = 0U; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Do-While to make sure that all status registers are cleared before + // continuing. This eliminates the race condition which can cause the USB + // interrupt to stay high and never get triggered again. + // + do + { + // + // Get the general interrupt status. + // + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + + // + // Get the transmit interrupt status. + // + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + + // + // Get the receive interrupt status. + // + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // + // Get the general interrupt status, these bits go into the lower 8 bits + // of the returned value. + // + ui32Status |= usbis; + + // + // Get the transmit interrupt status. + // + *pui32IntStatusEP |= txis; + + // + // Get the receive interrupt status, these bits go into the second byte + // of the returned value. + // + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while((usbis != 0x0000U) || (txis != 0x0000U) || (rxis != 0x0000U)); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << + USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) + << USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0U); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + if((pui32Flags != NULL) && (pui32MaxPacketSize != NULL)) + { + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size + // has been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change. If they decode the returned mode, however, they + // may be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size + // max packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change.If they decode the returned mode, however, they may + // be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOSZ, 1U); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOSZ, 1U); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0U); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0U; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xFFU; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8U) & 0xFFU; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0U); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0U) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0U); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16U; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2U)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xFU << (ui32Channel * 4U); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4U); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0U; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4U * (USBEPToIndex(ui32Endpoint) - 1U))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15U); +} + diff --git a/gpio_bitfield_cpu2/device/driverlib/usb.h b/gpio_bitfield_cpu2/device/driverlib/usb.h new file mode 100644 index 0000000..ae3c7ad --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/usb.h @@ -0,0 +1,560 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef USB_H +#define USB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup usb_api USB +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001U +#define USB_ID_HOST 0x0002U +#define USB_ID_DEVICE 0x0000U +#define USB_PFLT_ACTIVE 0x0004U + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FFUL // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FFUL // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080UL // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040UL // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040UL // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020UL // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010UL // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008UL // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004UL // Babble signaled +#define USB_INTCTRL_RESET 0x00000004UL // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002UL // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001UL // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200UL // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100UL // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFFUL // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000UL // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000UL // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000UL // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000UL // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000UL // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000UL // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000UL // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000UL // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000UL // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000UL // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000UL // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000UL // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000UL // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000UL // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000UL // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000UL // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000UL // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000UL // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000UL // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000UL // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000UL // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000UL // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000UL // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000UL // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000UL // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000UL // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000UL // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000UL // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000UL // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000UL // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000UL // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000UL // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFEUL // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000UL // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000UL // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000UL // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000UL // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800UL // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400UL // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200UL // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100UL // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080UL // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040UL // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020UL // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010UL // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008UL // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004UL // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002UL // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFEUL // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000UL // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000UL // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000UL // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000UL // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800UL // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400UL // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200UL // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100UL // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080UL // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040UL // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020UL // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010UL // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008UL // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004UL // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002UL // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000UL // Current speed is undefined +#define USB_FULL_SPEED 0x00000001UL // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000UL // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000UL // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000UL // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000UL // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000UL // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000UL // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000UL // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000UL // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000UL // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFFUL // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080UL // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020UL // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004UL // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002UL // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001UL // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040UL // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010UL // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004UL // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001UL // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000UL // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000UL // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000UL // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000UL // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000UL // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080UL // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020UL // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004UL // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002UL // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001UL // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010UL // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004UL // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002UL // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001UL // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001UL // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002UL // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004UL // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008UL // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010UL // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000UL // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100UL // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200UL // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300UL // Control endpoint +#define USB_EP_MODE_MASK 0x00000300UL // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000UL // Low Speed +#define USB_EP_SPEED_FULL 0x00001000UL // Full Speed +#define USB_EP_HOST_IN 0x00000000UL // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000UL // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000UL // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000UL // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010UL +#define USB_HOST_PWRFLT_HIGH 0x00000030UL +#define USB_HOST_PWRFLT_EP_NONE 0x00000000UL +#define USB_HOST_PWRFLT_EP_TRI 0x00000140UL +#define USB_HOST_PWRFLT_EP_LOW 0x00000240UL +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340UL +#define USB_HOST_PWREN_MAN_LOW 0x00000000UL +#define USB_HOST_PWREN_MAN_HIGH 0x00000001UL +#define USB_HOST_PWREN_AUTOLOW 0x00000002UL +#define USB_HOST_PWREN_AUTOHIGH 0x00000003UL +#define USB_HOST_PWREN_FILTER 0x00010000UL + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64U + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000UL // Endpoint 0 +#define USB_EP_1 0x00000010UL // Endpoint 1 +#define USB_EP_2 0x00000020UL // Endpoint 2 +#define USB_EP_3 0x00000030UL // Endpoint 3 +#define USB_EP_4 0x00000040UL // Endpoint 4 +#define USB_EP_5 0x00000050UL // Endpoint 5 +#define USB_EP_6 0x00000060UL // Endpoint 6 +#define USB_EP_7 0x00000070UL // Endpoint 7 +#define USB_EP_8 0x00000080UL // Endpoint 8 +#define USB_EP_9 0x00000090UL // Endpoint 9 +#define USB_EP_10 0x000000A0UL // Endpoint 10 +#define USB_EP_11 0x000000B0UL // Endpoint 11 +#define USB_EP_12 0x000000C0UL // Endpoint 12 +#define USB_EP_13 0x000000D0UL // Endpoint 13 +#define USB_EP_14 0x000000E0UL // Endpoint 14 +#define USB_EP_15 0x000000F0UL // Endpoint 15 +#define NUM_USB_EP 16U // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4U) & 0xFFU) +#define USBEPToIndex(x) ((x) >> 4U) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000UL // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001UL // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002UL // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003UL // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004UL // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005UL // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006UL // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007UL // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008UL // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009UL // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010UL // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011UL // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012UL // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013UL // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014UL // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015UL // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016UL // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017UL // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018UL // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010UL +#define USBFIFOSizeToBytes(x) ((uint32_t)8U << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102UL // Normal OUT transaction +#define USB_TRANS_IN 0x00000102UL // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010AUL // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110AUL // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142UL // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001UL // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081UL // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080UL // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001DUL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009UL // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011UL // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009DUL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080UL // OTG controller mode is not set. + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0FUL // All Interrupt sources +#define USB_INT_STATUS 0xFF000000UL // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000UL // VBUS Error +#define USB_INT_SESSION_START 0x40000000UL // Session Start Detected +#define USB_INT_SESSION_END 0x20000000UL // Session End Detected +#define USB_INT_DISCONNECT 0x20000000UL // Disconnect Detected +#define USB_INT_CONNECT 0x10000000UL // Device Connect Detected +#define USB_INT_SOF 0x08000000UL // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000UL // Babble signaled +#define USB_INT_RESET 0x04000000UL // Reset signaled +#define USB_INT_RESUME 0x02000000UL // Resume detected +#define USB_INT_SUSPEND 0x01000000UL // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000UL // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000UL // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00UL // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00UL // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800UL // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400UL // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200UL // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800UL // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400UL // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200UL // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000EUL // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000EUL // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008UL // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004UL // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002UL // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008UL // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004UL // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002UL // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // USB_H diff --git a/gpio_bitfield_cpu2/device/driverlib/version.c b/gpio_bitfield_cpu2/device/driverlib/version.c new file mode 100644 index 0000000..ced29c1 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/version.c @@ -0,0 +1,54 @@ +//########################################################################### +// +// FILE: version.c +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "version.h" + +//***************************************************************************** +// +// Version_getLibVersion +// +//***************************************************************************** +uint32_t +Version_getLibVersion(void) +{ + return(VERSION_NUMBER); +} diff --git a/gpio_bitfield_cpu2/device/driverlib/version.h b/gpio_bitfield_cpu2/device/driverlib/version.h new file mode 100644 index 0000000..8a3b431 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/version.h @@ -0,0 +1,101 @@ +//########################################################################### +// +// FILE: version.h +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef VERSION_H +#define VERSION_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup version_api Version +//! @{ +// +//***************************************************************************** +#include + +//! Version number to be returned by Version_getLibVersion() +//! +#define VERSION_NUMBER 26000000U + +//***************************************************************************** +// +//! Returns the driverlib version number +//! +//! This function can be used to check the version number of the driverlib.lib +//! that is in use. The version number will take the format yy.mm.pp.bb, so for +//! yy-Year, mm-Major Release version, pp-Patch Release Version, bb- Build Number. +//! example, if the function returns 26000000, the driverlib version being used +//! is 26.00.00.00. +//! +//! \return Returns an integer value indicating the driverlib version. +// +//***************************************************************************** +extern uint32_t +Version_getLibVersion(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // VERSION_H diff --git a/gpio_bitfield_cpu2/device/driverlib/xbar.c b/gpio_bitfield_cpu2/device/driverlib/xbar.c new file mode 100644 index 0000000..008145a --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/xbar.c @@ -0,0 +1,255 @@ +//########################################################################### +// +// FILE: xbar.c +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "xbar.h" + +//***************************************************************************** +// +// XBAR_setOutputMuxConfig +// +//***************************************************************************** +void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)output << 1U) + 2U; + } + else + { + offset = (uint16_t)output << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR output. + // + EALLOW; + + HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) = + (HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) & + ~((uint32_t)0x3U << shift)) | + (((uint32_t)muxConfig & 0x3U) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setEPWMMuxConfig +// +//***************************************************************************** +void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)trip << 1U) + 2U; + } + else + { + offset = (uint16_t)trip << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR trip. + // + EALLOW; + + HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setCLBMuxConfig +// +//***************************************************************************** +void +XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, XBAR_CLBMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)auxSignal << 1U) + 2U; + } + else + { + offset = (uint16_t)auxSignal << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR auxSignal. + // + EALLOW; + + + HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_getInputFlagStatus +// +//***************************************************************************** +bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_FLG1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_FLG2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_FLG3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Get the status of the X-BAR input latch. + // + inputMask = (uint32_t)1U << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + + return((HWREG(XBAR_BASE + offset) & inputMask) != 0U); +} + +//***************************************************************************** +// +// XBAR_clearInputFlag +// +//***************************************************************************** +void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag clear register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_CLR1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_CLR2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_CLR3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Set the bit that clears the X-BAR input latch. + // + inputMask = 1UL << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + HWREG(XBAR_BASE + offset) = inputMask; +} diff --git a/gpio_bitfield_cpu2/device/driverlib/xbar.h b/gpio_bitfield_cpu2/device/driverlib/xbar.h new file mode 100644 index 0000000..02e4e68 --- /dev/null +++ b/gpio_bitfield_cpu2/device/driverlib/xbar.h @@ -0,0 +1,1294 @@ +//########################################################################### +// +// FILE: xbar.h +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef XBAR_H +#define XBAR_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup xbar_api XBAR +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clbxbar.h" +#include "inc/hw_epwmxbar.h" +#include "inc/hw_inputxbar.h" +#include "inc/hw_outputxbar.h" +#include "inc/hw_xbar.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. +// Not intended for use by application code. +// +//***************************************************************************** +#define XBAR_OUTPUT_CFG_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUX0TO15CFG) +#define XBAR_OUTPUT_EN_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE) +#define XBAR_EPWM_CFG_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUX0TO15CFG) +#define XBAR_EPWM_EN_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUXENABLE) +#define XBAR_CLB_CFG_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUX0TO15CFG) +#define XBAR_CLB_EN_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUXENABLE) +#define XBAR_INPUT_BASE (INPUTXBAR_BASE + XBAR_O_INPUT1SELECT) + +#define XBAR_INPUT_FLG_INPUT_M 0x00FFU +#define XBAR_INPUT_FLG_REG_M 0xFF00U +#define XBAR_INPUT_FLG_REG_1 0x0000U +#define XBAR_INPUT_FLG_REG_2 0x0100U +#define XBAR_INPUT_FLG_REG_3 0x0200U + +#define XBAR_GPIO_MAX_CNT 168U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following values define the muxes parameter for XBAR_enableEPWMMux(), +// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and +// XBAR_disableOutputMux(). +// +//***************************************************************************** +#define XBAR_MUX00 0x00000001U //!< Mask for X-BAR mux 0 +#define XBAR_MUX01 0x00000002U //!< Mask for X-BAR mux 1 +#define XBAR_MUX02 0x00000004U //!< Mask for X-BAR mux 2 +#define XBAR_MUX03 0x00000008U //!< Mask for X-BAR mux 3 +#define XBAR_MUX04 0x00000010U //!< Mask for X-BAR mux 4 +#define XBAR_MUX05 0x00000020U //!< Mask for X-BAR mux 5 +#define XBAR_MUX06 0x00000040U //!< Mask for X-BAR mux 6 +#define XBAR_MUX07 0x00000080U //!< Mask for X-BAR mux 7 +#define XBAR_MUX08 0x00000100U //!< Mask for X-BAR mux 8 +#define XBAR_MUX09 0x00000200U //!< Mask for X-BAR mux 9 +#define XBAR_MUX10 0x00000400U //!< Mask for X-BAR mux 10 +#define XBAR_MUX11 0x00000800U //!< Mask for X-BAR mux 11 +#define XBAR_MUX12 0x00001000U //!< Mask for X-BAR mux 12 +#define XBAR_MUX13 0x00002000U //!< Mask for X-BAR mux 13 +#define XBAR_MUX14 0x00004000U //!< Mask for X-BAR mux 14 +#define XBAR_MUX15 0x00008000U //!< Mask for X-BAR mux 15 +#define XBAR_MUX16 0x00010000U //!< Mask for X-BAR mux 16 +#define XBAR_MUX17 0x00020000U //!< Mask for X-BAR mux 17 +#define XBAR_MUX18 0x00040000U //!< Mask for X-BAR mux 18 +#define XBAR_MUX19 0x00080000U //!< Mask for X-BAR mux 19 +#define XBAR_MUX20 0x00100000U //!< Mask for X-BAR mux 20 +#define XBAR_MUX21 0x00200000U //!< Mask for X-BAR mux 21 +#define XBAR_MUX22 0x00400000U //!< Mask for X-BAR mux 22 +#define XBAR_MUX23 0x00800000U //!< Mask for X-BAR mux 23 +#define XBAR_MUX24 0x01000000U //!< Mask for X-BAR mux 24 +#define XBAR_MUX25 0x02000000U //!< Mask for X-BAR mux 25 +#define XBAR_MUX26 0x04000000U //!< Mask for X-BAR mux 26 +#define XBAR_MUX27 0x08000000U //!< Mask for X-BAR mux 27 +#define XBAR_MUX28 0x10000000U //!< Mask for X-BAR mux 28 +#define XBAR_MUX29 0x20000000U //!< Mask for X-BAR mux 29 +#define XBAR_MUX30 0x40000000U //!< Mask for X-BAR mux 30 +#define XBAR_MUX31 0x80000000U //!< Mask for X-BAR mux 31 +#endif + +//***************************************************************************** +// +//! The following values define the \e output parameter for +//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and +//! XBAR_disableOutputMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR + XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR + XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR + XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR + XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR + XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR + XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR + XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR +} XBAR_OutputNum; + +//***************************************************************************** +// +//! The following values define the \e trip parameter for +//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(), +//! and XBAR_disableEPWMMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR + XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR + XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR + XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR + XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR + XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR + XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR + XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR +} XBAR_TripNum; + +//***************************************************************************** +// +// The following values define the trip parameter for XBAR_setCLBMuxConfig(), +// XBAR_enableCLBMux(), and XBAR_disableCLBMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_AUXSIG0 = 0, + XBAR_AUXSIG1 = 2, + XBAR_AUXSIG2 = 4, + XBAR_AUXSIG3 = 6, + XBAR_AUXSIG4 = 8, + XBAR_AUXSIG5 = 10, + XBAR_AUXSIG6 = 12, + XBAR_AUXSIG7 = 14 +} XBAR_AuxSigNum; + +//***************************************************************************** +// +//! The following values define the \e input parameter for XBAR_setInputPin(). +// +//***************************************************************************** +typedef enum +{ + XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs + XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs + XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs + XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1 + XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2 + XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3 + XBAR_INPUT7, //!< eCAP1, X-BARs + XBAR_INPUT8, //!< eCAP2, X-BARs + XBAR_INPUT9, //!< eCAP3, X-BARs + XBAR_INPUT10, //!< eCAP4, X-BARs + XBAR_INPUT11, //!< eCAP5, X-BARs + XBAR_INPUT12, //!< eCAP6, X-BARs + XBAR_INPUT13, //!< XINT4, X-BARs + XBAR_INPUT14 //!< XINT5, X-BARs +} XBAR_InputNum; + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setOutputMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + // + //OUTPUTXBAR + // + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000, + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001, + XBAR_OUT_MUX00_ADCAEVT1 = 0x0002, + XBAR_OUT_MUX00_ECAP1_OUT = 0x0003, + XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200, + XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201, + XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202, + XBAR_OUT_MUX01_ADCCEVT1 = 0x0203, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401, + XBAR_OUT_MUX02_ADCAEVT2 = 0x0402, + XBAR_OUT_MUX02_ECAP2_OUT = 0x0403, + XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600, + XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601, + XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602, + XBAR_OUT_MUX03_ADCCEVT2 = 0x0603, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801, + XBAR_OUT_MUX04_ADCAEVT3 = 0x0802, + XBAR_OUT_MUX04_ECAP3_OUT = 0x0803, + XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00, + XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01, + XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02, + XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03, + XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00, + XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001, + XBAR_OUT_MUX08_ADCBEVT1 = 0x1002, + XBAR_OUT_MUX08_ECAP5_OUT = 0x1003, + XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200, + XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201, + XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202, + XBAR_OUT_MUX09_ADCDEVT1 = 0x1203, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401, + XBAR_OUT_MUX10_ADCBEVT2 = 0x1402, + XBAR_OUT_MUX10_ECAP6_OUT = 0x1403, + XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600, + XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601, + XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602, + XBAR_OUT_MUX11_ADCDEVT2 = 0x1603, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801, + XBAR_OUT_MUX12_ADCBEVT3 = 0x1802, + XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00, + XBAR_OUT_MUX13_ADCSOCA = 0x1A01, + XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_OUT_MUX13_ADCDEVT3 = 0x1A03, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH = 0x1C00, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH_OR_L = 0x1C01, + XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02, + XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_OUT_MUX15_CMPSS8_CTRIPOUTL = 0x1E00, + XBAR_OUT_MUX15_ADCSOCB = 0x1E01, + XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_OUT_MUX15_ADCDEVT4 = 0x1E03, + XBAR_OUT_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_OUT_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_OUT_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_OUT_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_OUT_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_OUT_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_OUT_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_OUT_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_OUT_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_OUT_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_OUT_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_OUT_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_OUT_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_OUT_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_OUT_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_OUT_MUX31_SD2FLT4_COMPL = 0x3E00, + +} XBAR_OutputMuxConfig; + +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setEPWMMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002, + XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003, + XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201, + XBAR_EPWM_MUX01_CLB1_OUT4 = 0x0202, + XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402, + XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403, + XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601, + XBAR_EPWM_MUX03_CLB1_OUT5 = 0x0602, + XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802, + XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803, + XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_EPWM_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02, + XBAR_EPWM_MUX06_ECAP4_OUT = 0x0C03, + XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_EPWM_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002, + XBAR_EPWM_MUX08_ECAP5_OUT = 0x1003, + XBAR_EPWM_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201, + XBAR_EPWM_MUX09_CLB3_OUT4 = 0x1202, + XBAR_EPWM_MUX09_ADCDEVT1 = 0x1203, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402, + XBAR_EPWM_MUX10_ECAP6_OUT = 0x1403, + XBAR_EPWM_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601, + XBAR_EPWM_MUX11_CLB3_OUT5 = 0x1602, + XBAR_EPWM_MUX11_ADCDEVT2 = 0x1603, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802, + XBAR_EPWM_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_EPWM_MUX13_ADCSOCA = 0x1A01, + XBAR_EPWM_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_EPWM_MUX13_ADCDEVT3 = 0x1A03, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02, + XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_EPWM_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_EPWM_MUX15_ADCSOCB = 0x1E01, + XBAR_EPWM_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_EPWM_MUX15_ADCDEVT4 = 0x1E03, + XBAR_EPWM_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_EPWM_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_EPWM_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_EPWM_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_EPWM_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_EPWM_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_EPWM_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_EPWM_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_EPWM_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_EPWM_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_EPWM_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_EPWM_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_EPWM_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_EPWM_MUX31_SD2FLT4_COMPL = 0x3E00 +} XBAR_EPWMMuxConfig; + +//***************************************************************************** +// +// The following values define the muxConfig parameter for +// XBAR_setCLBMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_CLB_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_CLB_MUX00_ADCAEVT1 = 0x0002, + XBAR_CLB_MUX00_ECAP1_OUT = 0x0003, + XBAR_CLB_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_CLB_MUX01_INPUTXBAR1 = 0x0201, + XBAR_CLB_MUX01_CLB1_OUT4 = 0x0202, + XBAR_CLB_MUX01_ADCCEVT1 = 0x0203, + XBAR_CLB_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_CLB_MUX02_ADCAEVT2 = 0x0402, + XBAR_CLB_MUX02_ECAP2_OUT = 0x0403, + XBAR_CLB_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_CLB_MUX03_INPUTXBAR2 = 0x0601, + XBAR_CLB_MUX03_CLB1_OUT5 = 0x0602, + XBAR_CLB_MUX03_ADCCEVT2 = 0x0603, + XBAR_CLB_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_CLB_MUX04_ADCAEVT3 = 0x0802, + XBAR_CLB_MUX04_ECAP3_OUT = 0x0803, + XBAR_CLB_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_CLB_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_CLB_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_CLB_MUX05_ADCCEVT3 = 0x0A03, + XBAR_CLB_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_CLB_MUX06_ADCAEVT4 = 0x0C02, + XBAR_CLB_MUX06_ECAP4_OUT = 0x0C03, + XBAR_CLB_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_CLB_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_CLB_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_CLB_MUX07_ADCCEVT4 = 0x0E03, + XBAR_CLB_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_CLB_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_CLB_MUX08_ADCBEVT1 = 0x1002, + XBAR_CLB_MUX08_ECAP5_OUT = 0x1003, + XBAR_CLB_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_CLB_MUX09_INPUTXBAR5 = 0x1201, + XBAR_CLB_MUX09_CLB3_OUT4 = 0x1202, + XBAR_CLB_MUX09_ADCDEVT1 = 0x1203, + XBAR_CLB_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_CLB_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_CLB_MUX10_ADCBEVT2 = 0x1402, + XBAR_CLB_MUX10_ECAP6_OUT = 0x1403, + XBAR_CLB_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_CLB_MUX11_INPUTXBAR6 = 0x1601, + XBAR_CLB_MUX11_CLB3_OUT5 = 0x1602, + XBAR_CLB_MUX11_ADCDEVT2 = 0x1603, + XBAR_CLB_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_CLB_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_CLB_MUX12_ADCBEVT3 = 0x1802, + XBAR_CLB_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_CLB_MUX13_ADCSOCA = 0x1A01, + XBAR_CLB_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_CLB_MUX13_ADCDEVT3 = 0x1A03, + XBAR_CLB_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_CLB_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_CLB_MUX14_ADCBEVT4 = 0x1C02, + XBAR_CLB_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_CLB_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_CLB_MUX15_ADCSOCB = 0x1E01, + XBAR_CLB_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_CLB_MUX15_ADCDEVT4 = 0x1E03, + XBAR_CLB_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_CLB_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_CLB_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_CLB_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_CLB_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_CLB_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_CLB_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_CLB_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_CLB_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_CLB_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_CLB_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_CLB_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_CLB_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_CLB_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_CLB_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_CLB_MUX31_SD2FLT4_COMPL = 0x3E00, +} XBAR_CLBMuxConfig; + + +//***************************************************************************** +// +//! The following values define the \e inputFlag parameter for +//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag(). +// +//***************************************************************************** +typedef enum +{ + // + // XBARFLG1 + // + XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000, + XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001, + XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002, + XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003, + XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004, + XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005, + XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006, + XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007, + XBAR_INPUT_FLG_CMPSS5_CTRIPL = 0x0008, + XBAR_INPUT_FLG_CMPSS5_CTRIPH = 0x0009, + XBAR_INPUT_FLG_CMPSS6_CTRIPL = 0x000A, + XBAR_INPUT_FLG_CMPSS6_CTRIPH = 0x000B, + XBAR_INPUT_FLG_CMPSS7_CTRIPL = 0x000C, + XBAR_INPUT_FLG_CMPSS7_CTRIPH = 0x000D, + XBAR_INPUT_FLG_CMPSS8_CTRIPL = 0x000E, + XBAR_INPUT_FLG_CMPSS8_CTRIPH = 0x000F, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL = 0x0018, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH = 0x0019, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL = 0x001A, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH = 0x001B, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL = 0x001C, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH = 0x001D, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL = 0x001E, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH = 0x001F, + // + // XBARFLG2 + // + XBAR_INPUT_FLG_INPUT1 = 0x0100, + XBAR_INPUT_FLG_INPUT2 = 0x0101, + XBAR_INPUT_FLG_INPUT3 = 0x0102, + XBAR_INPUT_FLG_INPUT4 = 0x0103, + XBAR_INPUT_FLG_INPUT5 = 0x0104, + XBAR_INPUT_FLG_INPUT6 = 0x0105, + XBAR_INPUT_FLG_ADCSOCA = 0x0106, + XBAR_INPUT_FLG_ADCSOCB = 0x0107, + XBAR_INPUT_FLG_CLB1_OUT4 = 0x0108, + XBAR_INPUT_FLG_CLB1_OUT5 = 0x0109, + XBAR_INPUT_FLG_CLB2_OUT4 = 0x010A, + XBAR_INPUT_FLG_CLB2_OUT5 = 0x010B, + XBAR_INPUT_FLG_CLB3_OUT4 = 0x010C, + XBAR_INPUT_FLG_CLB3_OUT5 = 0x010D, + XBAR_INPUT_FLG_CLB4_OUT4 = 0x010E, + XBAR_INPUT_FLG_CLB4_OUT5 = 0x010F, + XBAR_INPUT_FLG_ECAP1_OUT = 0x0110, + XBAR_INPUT_FLG_ECAP2_OUT = 0x0111, + XBAR_INPUT_FLG_ECAP3_OUT = 0x0112, + XBAR_INPUT_FLG_ECAP4_OUT = 0x0113, + XBAR_INPUT_FLG_ECAP5_OUT = 0x0114, + XBAR_INPUT_FLG_ECAP6_OUT = 0x0115, + XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116, + XBAR_INPUT_FLG_ADCAEVT1 = 0x0117, + XBAR_INPUT_FLG_ADCAEVT2 = 0x0118, + XBAR_INPUT_FLG_ADCAEVT3 = 0x0119, + XBAR_INPUT_FLG_ADCAEVT4 = 0x011A, + XBAR_INPUT_FLG_ADCBEVT1 = 0x011B, + XBAR_INPUT_FLG_ADCBEVT2 = 0x011C, + XBAR_INPUT_FLG_ADCBEVT3 = 0x011D, + XBAR_INPUT_FLG_ADCBEVT4 = 0x011E, + XBAR_INPUT_FLG_ADCCEVT1 = 0x011F, + // + // XBARFLG3 + // + XBAR_INPUT_FLG_ADCCEVT2 = 0x0200, + XBAR_INPUT_FLG_ADCCEVT3 = 0x0201, + XBAR_INPUT_FLG_ADCCEVT4 = 0x0202, + XBAR_INPUT_FLG_ADCDEVT1 = 0x0203, + XBAR_INPUT_FLG_ADCDEVT2 = 0x0204, + XBAR_INPUT_FLG_ADCDEVT3 = 0x0205, + XBAR_INPUT_FLG_ADCDEVT4 = 0x0206, + XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207, + XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208, + XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209, + XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A, + XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B, + XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C, + XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D, + XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E, + XBAR_INPUT_FLG_SD2FLT1_COMPL = 0x020F, + XBAR_INPUT_FLG_SD2FLT1_COMPH = 0x0210, + XBAR_INPUT_FLG_SD2FLT2_COMPL = 0x0211, + XBAR_INPUT_FLG_SD2FLT2_COMPH = 0x0212, + XBAR_INPUT_FLG_SD2FLT3_COMPL = 0x0213, + XBAR_INPUT_FLG_SD2FLT3_COMPH = 0x0214, + XBAR_INPUT_FLG_SD2FLT4_COMPL = 0x0215, + XBAR_INPUT_FLG_SD2FLT4_COMPH = 0x0216 +} XBAR_InputFlag; +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Output X-BAR mux values to be passed to the output signal. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) |= muxes; + + EDIS; + + +} + +//***************************************************************************** +// +//! Disables the Output X-BAR mux values from being passed to the output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values from being passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Enables or disables the output latch to drive the selected output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param enable is a flag that determines whether or not the latch is +//! selected to drive the X-BAR output. +//! +//! This function sets the Output X-BAR output signal latch mode. If the +//! \e enable parameter is \b true, the output specified by \e output will be +//! driven by the output latch. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setOutputLatchMode(XBAR_OutputNum output, bool enable) +{ + EALLOW; + + // + // Set or clear the latch setting bit based on the enable parameter. + // + if(enable) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Returns the status of the output latch +//! +//! \param output is the X-BAR output being checked. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! \return Returns \b true if the output corresponding to \e output was +//! triggered. If not, it will return \b false. +// +//***************************************************************************** +static inline bool +XBAR_getOutputLatchStatus(XBAR_OutputNum output) +{ + // + // Get the status of the Output X-BAR output latch. + // + return((HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCH) & + (0x1U << ((uint16_t)output / 2U))) != 0U); +} + +//***************************************************************************** +// +//! Clears the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function clears the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_clearOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that clears the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHCLR) |= + 0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Forces the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function forces the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_forceOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that forces the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHFRC) = + (uint16_t)0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Configures the polarity of an Output X-BAR output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the Output X-BAR signal if the \e invert parameter is +//! \b true. If \e invert is \b false, the signal will be passed as is. The +//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output +//! number between 1 and 8 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertOutputSignal(XBAR_OutputNum output, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) |= muxes; + EDIS; +} + +//***************************************************************************** +// +//! Disables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an ePWM X-BAR output. +//! +//! \param trip is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the ePWM X-BAR trip signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertEPWMSignal(XBAR_TripNum trip, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) |= + 0x1U << ((uint16_t)trip / 2U); + } + else + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) &= + ~(0x1U << ((uint16_t)trip / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the GPIO pin for an Input X-BAR input. +//! +//! \param input is the X-BAR input being configured. +//! \param pin is the identifying number of the pin. +//! +//! This function configures which GPIO is assigned to an Input X-BAR input. +//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy +//! where y is a the input number for the Input X-BAR. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setInputPin(XBAR_InputNum input, uint16_t pin) +{ + // + // Check the argument. + // + ASSERT(pin <= XBAR_GPIO_MAX_CNT); + + // + // Write the requested pin to the appropriate input select register. + // + EALLOW; + + HWREGH(XBAR_INPUT_BASE + (uint16_t)input) = pin; + + EDIS; +} + +//***************************************************************************** +// +//! Locks an input to the Input X-BAR. +//! +//! \param input is an input to the Input X-BAR. +//! +//! This function locks the specific input on the Input X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockInput(XBAR_InputNum input) +{ + // + // lock the input in the INPUTSELECTLOCK register. + // + EALLOW; + HWREG(INPUTXBAR_BASE + XBAR_O_INPUTSELECTLOCK) = + 1UL << (uint16_t)input; + EDIS; +} + +//***************************************************************************** +// +//! Locks the Output X-BAR. +//! +//! This function locks the Output X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockOutput(void) +{ + // + // Lock the Output X-BAR with the OUTPUTLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLOCK) = + ((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) | + (uint32_t)XBAR_OUTPUTLOCK_LOCK; + + EDIS; +} + +//***************************************************************************** +// +//! Locks the ePWM X-BAR. +//! +//! This function locks the ePWM X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockEPWM(void) +{ + // + // Lock the ePWM X-BAR with the TRIPLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(EPWMXBAR_BASE + XBAR_O_TRIPLOCK) = + ((uint32_t)0x5A5A << XBAR_TRIPLOCK_KEY_S) | + (uint32_t)XBAR_TRIPLOCK_LOCK; + EDIS; +} + +//***************************************************************************** +// +//! Enables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) |= muxes; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an CLB X-BAR output. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the CLB X-BAR auxSignal signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) |= + 0x1U << ((uint16_t)auxSignal / 2U); + } + else + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) &= + ~(0x1U << ((uint16_t)auxSignal / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the Output X-BAR mux that determines the signals passed to an +//! output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an Output X-BAR mux. This determines which +//! signal(s) should be passed through the X-BAR to a GPIO. The \e output +//! parameter is a value \b XBAR_OUTPUTy where y is a the output number +//! between 1 and 8 inclusive. +//! +//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration +//! value that specifies which signal will be passed from the mux. The +//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is +//! the signal and nn is the mux number. +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the output signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig); + +//***************************************************************************** +// +//! Configures the ePWM X-BAR mux that determines the signals passed to an +//! ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an ePWM X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an ePWM module. The \e trip +//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip +//! signal on the ePWM. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the trip signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig); + +//***************************************************************************** +// +//! Returns the status of the input latch. +//! +//! \param inputFlag is the X-BAR input latch being checked. Values are in the +//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal. +//! +//! \return Returns \b true if the X-BAR input corresponding to the +//! \e inputFlag has been triggered. If not, it will return \b false. +// +//***************************************************************************** +extern bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Clears the input latch for the specified input latch. +//! +//! \param inputFlag is the X-BAR input latch being cleared. +//! +//! This function clears the Input X-BAR input latch. The input latch to be +//! cleared is specified by the \e inputFlag parameter. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Configures the CLB X-BAR mux that determines the signals passed to a +//! CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an CLB X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an CLB module. The \e auxSignal +//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the +//! signal on the CLB. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, + XBAR_CLBMuxConfig muxConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // XBAR_H diff --git a/gpio_bitfield_cpu2/gpio_bitfield_cpu2.c b/gpio_bitfield_cpu2/gpio_bitfield_cpu2.c new file mode 100644 index 0000000..e69de29 diff --git a/gpio_bitfield_cpu2/targetConfigs/TMS320F28377D.ccxml b/gpio_bitfield_cpu2/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 0000000..79dd5cc --- /dev/null +++ b/gpio_bitfield_cpu2/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_bitfield_cpu2/targetConfigs/readme.txt b/gpio_bitfield_cpu2/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/gpio_bitfield_cpu2/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file diff --git a/gpio_driverlib_cpu1/.ccsproject b/gpio_driverlib_cpu1/.ccsproject new file mode 100644 index 0000000..f062ad6 --- /dev/null +++ b/gpio_driverlib_cpu1/.ccsproject @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu1/.clangd b/gpio_driverlib_cpu1/.clangd new file mode 100644 index 0000000..c9859d6 --- /dev/null +++ b/gpio_driverlib_cpu1/.clangd @@ -0,0 +1,8 @@ +# This is an auto-generated file - do not add it to source-control + +CompileFlags: + CompilationDatabase: CPU1_RAM/.clangd + +Diagnostics: + Suppress: '*' + diff --git a/gpio_driverlib_cpu1/.cproject b/gpio_driverlib_cpu1/.cproject new file mode 100644 index 0000000..9581708 --- /dev/null +++ b/gpio_driverlib_cpu1/.cproject @@ -0,0 +1,185 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu1/.project b/gpio_driverlib_cpu1/.project new file mode 100644 index 0000000..9093a87 --- /dev/null +++ b/gpio_driverlib_cpu1/.project @@ -0,0 +1,33 @@ + + + gpio_driverlib_cpu1 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + + + + + + com.ti.ccstudio.core.ccsNature + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.core.ccnature + + + + driverlib.lib + 1 + COM_TI_C2000WARE_INSTALL_DIR/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib + + + + + C2000WARE_DLIB_ROOT + $%7BCOM_TI_C2000WARE_INSTALL_DIR%7D/driverlib/f2837xd/driverlib + + + diff --git a/gpio_driverlib_cpu1/.settings/org.eclipse.cdt.codan.core.prefs b/gpio_driverlib_cpu1/.settings/org.eclipse.cdt.codan.core.prefs new file mode 100644 index 0000000..f653028 --- /dev/null +++ b/gpio_driverlib_cpu1/.settings/org.eclipse.cdt.codan.core.prefs @@ -0,0 +1,3 @@ +eclipse.preferences.version=1 +inEditor=false +onBuild=false diff --git a/gpio_driverlib_cpu1/.settings/org.eclipse.core.resources.prefs b/gpio_driverlib_cpu1/.settings/org.eclipse.core.resources.prefs new file mode 100644 index 0000000..1e8c9e0 --- /dev/null +++ b/gpio_driverlib_cpu1/.settings/org.eclipse.core.resources.prefs @@ -0,0 +1,9 @@ +eclipse.preferences.version=1 +encoding//CPU1_RAM/device/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM/device/subdir_vars.mk=UTF-8 +encoding//CPU1_RAM/makefile=UTF-8 +encoding//CPU1_RAM/objects.mk=UTF-8 +encoding//CPU1_RAM/sources.mk=UTF-8 +encoding//CPU1_RAM/subdir_rules.mk=UTF-8 +encoding//CPU1_RAM/subdir_vars.mk=UTF-8 +encoding/=UTF-8 diff --git a/gpio_driverlib_cpu1/2837xD_FLASH_lnk_cpu1.cmd b/gpio_driverlib_cpu1/2837xD_FLASH_lnk_cpu1.cmd new file mode 100644 index 0000000..0c4b505 --- /dev/null +++ b/gpio_driverlib_cpu1/2837xD_FLASH_lnk_cpu1.cmd @@ -0,0 +1,176 @@ + +MEMORY +{ +PAGE 0 : /* Program Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE1 for data allocation */ + /* BEGIN is used for the "boot to Flash" bootloader mode */ + + BEGIN : origin = 0x080000, length = 0x000002 + RAMM0 : origin = 0x000123, length = 0x0002DD + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : /* Data Memory */ + /* Memory (RAM/FLASH) blocks can be moved to PAGE0 for program allocation */ + + BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + +// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */ + +// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 +} + +SECTIONS +{ + /* Allocate program areas: */ + .cinit : > FLASHB PAGE = 0, ALIGN(8) + .text : >> FLASHB | FLASHC | FLASHD | FLASHE PAGE = 0, ALIGN(8) + codestart : > BEGIN PAGE = 0, ALIGN(8) + /* Allocate uninitalized data sections: */ + .stack : > RAMM1 PAGE = 1 + .switch : > FLASHB PAGE = 0, ALIGN(8) + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + +#if defined(__TI_EABI__) + .init_array : > FLASHB, PAGE = 0, ALIGN(8) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .bss:cio : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .const : > FLASHF, PAGE = 0, ALIGN(8) +#else + .pinit : > FLASHB, PAGE = 0, ALIGN(8) + .ebss : >> RAMLS5 | RAMGS0 | RAMGS1, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 + .cio : > RAMLS5, PAGE = 1 + /* Initalized sections go in Flash */ + .econst : >> FLASHF PAGE = 0, ALIGN(8) +#endif + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + SHARERAMGS0 : > RAMGS0, PAGE = 1 + SHARERAMGS1 : > RAMGS1, PAGE = 1 + SHARERAMGS2 : > RAMGS2, PAGE = 1 + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + #if defined(__TI_EABI__) + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(RamfuncsLoadStart), + LOAD_SIZE(RamfuncsLoadSize), + LOAD_END(RamfuncsLoadEnd), + RUN_START(RamfuncsRunStart), + RUN_SIZE(RamfuncsRunSize), + RUN_END(RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #else + .TI.ramfunc : {} LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + #else + ramfuncs : LOAD = FLASHD, + RUN = RAMLS0, + LOAD_START(_RamfuncsLoadStart), + LOAD_SIZE(_RamfuncsLoadSize), + LOAD_END(_RamfuncsLoadEnd), + RUN_START(_RamfuncsRunStart), + RUN_SIZE(_RamfuncsRunSize), + RUN_END(_RamfuncsRunEnd), + PAGE = 0, ALIGN(8) + #endif + +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git a/gpio_driverlib_cpu1/2837xD_RAM_lnk_cpu1.cmd b/gpio_driverlib_cpu1/2837xD_RAM_lnk_cpu1.cmd new file mode 100644 index 0000000..5d5167a --- /dev/null +++ b/gpio_driverlib_cpu1/2837xD_RAM_lnk_cpu1.cmd @@ -0,0 +1,141 @@ + +MEMORY +{ +PAGE 0 : + /* BEGIN is used for the "boot to SARAM" bootloader mode */ + + BEGIN : origin = 0x000000, length = 0x000002 + RAMM0 : origin = 0x000123, length = 0x0002DD + RAMD0 : origin = 0x00B000, length = 0x000800 + RAMLS0 : origin = 0x008000, length = 0x000800 + RAMLS1 : origin = 0x008800, length = 0x000800 + RAMLS2 : origin = 0x009000, length = 0x000800 + RAMLS3 : origin = 0x009800, length = 0x000800 + RAMLS4 : origin = 0x00A000, length = 0x000800 + RESET : origin = 0x3FFFC0, length = 0x000002 + + /* Flash sectors */ + FLASHA : origin = 0x080002, length = 0x001FFE /* on-chip Flash */ + FLASHB : origin = 0x082000, length = 0x002000 /* on-chip Flash */ + FLASHC : origin = 0x084000, length = 0x002000 /* on-chip Flash */ + FLASHD : origin = 0x086000, length = 0x002000 /* on-chip Flash */ + FLASHE : origin = 0x088000, length = 0x008000 /* on-chip Flash */ + FLASHF : origin = 0x090000, length = 0x008000 /* on-chip Flash */ + FLASHG : origin = 0x098000, length = 0x008000 /* on-chip Flash */ + FLASHH : origin = 0x0A0000, length = 0x008000 /* on-chip Flash */ + FLASHI : origin = 0x0A8000, length = 0x008000 /* on-chip Flash */ + FLASHJ : origin = 0x0B0000, length = 0x008000 /* on-chip Flash */ + FLASHK : origin = 0x0B8000, length = 0x002000 /* on-chip Flash */ + FLASHL : origin = 0x0BA000, length = 0x002000 /* on-chip Flash */ + FLASHM : origin = 0x0BC000, length = 0x002000 /* on-chip Flash */ + FLASHN : origin = 0x0BE000, length = 0x001FF0 /* on-chip Flash */ + +// FLASHN_RSVD : origin = 0x0BFFF0, length = 0x000010 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + +PAGE 1 : + + BOOT_RSVD : origin = 0x000002, length = 0x000121 /* Part of M0, BOOT rom will use this for stack */ + RAMM1 : origin = 0x000400, length = 0x0003F8 /* on-chip RAM block M1 */ +// RAMM1_RSVD : origin = 0x0007F8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + RAMD1 : origin = 0x00B800, length = 0x000800 + + RAMLS5 : origin = 0x00A800, length = 0x000800 + + RAMGS0 : origin = 0x00C000, length = 0x001000 + RAMGS1 : origin = 0x00D000, length = 0x001000 + RAMGS2 : origin = 0x00E000, length = 0x001000 + RAMGS3 : origin = 0x00F000, length = 0x001000 + RAMGS4 : origin = 0x010000, length = 0x001000 + RAMGS5 : origin = 0x011000, length = 0x001000 + RAMGS6 : origin = 0x012000, length = 0x001000 + RAMGS7 : origin = 0x013000, length = 0x001000 + RAMGS8 : origin = 0x014000, length = 0x001000 + RAMGS9 : origin = 0x015000, length = 0x001000 + RAMGS10 : origin = 0x016000, length = 0x001000 + +// RAMGS11 : origin = 0x017000, length = 0x000FF8 /* Uncomment for F28374D, F28376D devices */ + +// RAMGS11_RSVD : origin = 0x017FF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + + RAMGS11 : origin = 0x017000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS12 : origin = 0x018000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS13 : origin = 0x019000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS14 : origin = 0x01A000, length = 0x001000 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + RAMGS15 : origin = 0x01B000, length = 0x000FF8 /* Only Available on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + +// RAMGS15_RSVD : origin = 0x01BFF8, length = 0x000008 /* Reserve and do not use for code as per the errata advisory "Memory: Prefetching Beyond Valid Memory" */ + /* Only on F28379D, F28377D, F28375D devices. Remove line on other devices. */ + + CPU2TOCPU1RAM : origin = 0x03F800, length = 0x000400 + CPU1TOCPU2RAM : origin = 0x03FC00, length = 0x000400 + + CANA_MSG_RAM : origin = 0x049000, length = 0x000800 + CANB_MSG_RAM : origin = 0x04B000, length = 0x000800 +} + + +SECTIONS +{ + codestart : > BEGIN, PAGE = 0 + .text : >> RAMD0 | RAMLS0 | RAMLS1 | RAMLS2 | RAMLS3 | RAMLS4, PAGE = 0 + .cinit : > RAMM0, PAGE = 0 + .switch : > RAMM0, PAGE = 0 + .reset : > RESET, PAGE = 0, TYPE = DSECT /* not used, */ + .stack : > RAMM1, PAGE = 1 + +#if defined(__TI_EABI__) + .bss : > RAMLS5, PAGE = 1 + .bss:output : > RAMLS3, PAGE = 0 + .init_array : > RAMM0, PAGE = 0 + .const : > RAMLS5, PAGE = 1 + .data : > RAMLS5, PAGE = 1 + .sysmem : > RAMLS5, PAGE = 1 +#else + .pinit : > RAMM0, PAGE = 0 + .ebss : > RAMLS5, PAGE = 1 + .econst : > RAMLS5, PAGE = 1 + .esysmem : > RAMLS5, PAGE = 1 +#endif + + Filter_RegsFile : > RAMGS0, PAGE = 1 + + + ramgs0 : > RAMGS0, PAGE = 1 + ramgs1 : > RAMGS1, PAGE = 1 + +#ifdef __TI_COMPILER_VERSION__ + #if __TI_COMPILER_VERSION__ >= 15009000 + .TI.ramfunc : {} > RAMM0, PAGE = 0 + #else + ramfuncs : > RAMM0 PAGE = 0 + #endif +#endif + + /* The following section definitions are required when using the IPC API Drivers */ + GROUP : > CPU1TOCPU2RAM, PAGE = 1 + { + PUTBUFFER + PUTWRITEIDX + GETREADIDX + } + + GROUP : > CPU2TOCPU1RAM, PAGE = 1 + { + GETBUFFER : TYPE = DSECT + GETWRITEIDX : TYPE = DSECT + PUTREADIDX : TYPE = DSECT + } + + /* The following section definition are for SDFM examples */ + Filter1_RegsFile : > RAMGS1, PAGE = 1, fill=0x1111 + Filter2_RegsFile : > RAMGS2, PAGE = 1, fill=0x2222 + Filter3_RegsFile : > RAMGS3, PAGE = 1, fill=0x3333 + Filter4_RegsFile : > RAMGS4, PAGE = 1, fill=0x4444 + Difference_RegsFile : >RAMGS5, PAGE = 1, fill=0x3333 +} + +/* +//=========================================================================== +// End of file. +//=========================================================================== +*/ diff --git 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/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/adc.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdbool.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_ti_config.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/linkage.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/_stdint40.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/cdefs.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_types.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_types.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/machine/_stdint.h +device/device.obj: /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include/sys/_stdint.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_adc.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_sysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_types.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/cpu.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/debug.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/asysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_asysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/can.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_can.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/sysctl.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_nmi.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_otp.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/interrupt.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_ints.h +device/device.obj: /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/inc/hw_pie.h +device/device.obj: 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b/gpio_driverlib_cpu1/CPU1_RAM/device/subdir_rules.mk new file mode 100644 index 0000000..40eff9e --- /dev/null +++ b/gpio_driverlib_cpu1/CPU1_RAM/device/subdir_rules.mk @@ -0,0 +1,18 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +device/%.obj: ../device/%.asm $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_driverlib_cpu1" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_driverlib_cpu1/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="device/$(basename $(> Linked Thu Jul 16 13:56:24 2026 + +OUTPUT FILE NAME: +ENTRY POINT SYMBOL: "code_start" address: 00000000 + + +MEMORY CONFIGURATION + + name origin length used unused attr fill +---------------------- -------- --------- -------- -------- ---- -------- +PAGE 0: + BEGIN 00000000 00000002 00000002 00000000 RWIX + RAMM0 00000123 000002dd 00000016 000002c7 RWIX + RAMLS0 00008000 00000800 00000397 00000469 RWIX + RAMLS1 00008800 00000800 00000000 00000800 RWIX + RAMLS2 00009000 00000800 00000000 00000800 RWIX + RAMLS3 00009800 00000800 00000000 00000800 RWIX + RAMLS4 0000a000 00000800 00000000 00000800 RWIX + RAMD0 0000b000 00000800 000007fd 00000003 RWIX + FLASHA 00080002 00001ffe 00000000 00001ffe RWIX + FLASHB 00082000 00002000 00000000 00002000 RWIX + FLASHC 00084000 00002000 00000000 00002000 RWIX + FLASHD 00086000 00002000 00000000 00002000 RWIX + FLASHE 00088000 00008000 00000000 00008000 RWIX + FLASHF 00090000 00008000 00000000 00008000 RWIX + FLASHG 00098000 00008000 00000000 00008000 RWIX + FLASHH 000a0000 00008000 00000000 00008000 RWIX + FLASHI 000a8000 00008000 00000000 00008000 RWIX + FLASHJ 000b0000 00008000 00000000 00008000 RWIX + FLASHK 000b8000 00002000 00000000 00002000 RWIX + FLASHL 000ba000 00002000 00000000 00002000 RWIX + FLASHM 000bc000 00002000 00000000 00002000 RWIX + FLASHN 000be000 00001ff0 00000000 00001ff0 RWIX + RESET 003fffc0 00000002 00000000 00000002 RWIX + +PAGE 1: + BOOT_RSVD 00000002 00000121 00000000 00000121 RWIX + RAMM1 00000400 000003f8 00000100 000002f8 RWIX + RAMLS5 0000a800 00000800 000001f1 0000060f RWIX + RAMD1 0000b800 00000800 00000000 00000800 RWIX + RAMGS0 0000c000 00001000 00000000 00001000 RWIX + RAMGS1 0000d000 00001000 00000000 00001000 RWIX + RAMGS2 0000e000 00001000 00000000 00001000 RWIX + RAMGS3 0000f000 00001000 00000000 00001000 RWIX + RAMGS4 00010000 00001000 00000000 00001000 RWIX + RAMGS5 00011000 00001000 00000000 00001000 RWIX + RAMGS6 00012000 00001000 00000000 00001000 RWIX + RAMGS7 00013000 00001000 00000000 00001000 RWIX + RAMGS8 00014000 00001000 00000000 00001000 RWIX + RAMGS9 00015000 00001000 00000000 00001000 RWIX + RAMGS10 00016000 00001000 00000000 00001000 RWIX + RAMGS11 00017000 00001000 00000000 00001000 RWIX + RAMGS12 00018000 00001000 00000000 00001000 RWIX + RAMGS13 00019000 00001000 00000000 00001000 RWIX + RAMGS14 0001a000 00001000 00000000 00001000 RWIX + RAMGS15 0001b000 00000ff8 00000000 00000ff8 RWIX + CPU2TOCPU1RAM 0003f800 00000400 00000000 00000400 RWIX + CPU1TOCPU2RAM 0003fc00 00000400 00000000 00000400 RWIX + CANA_MSG_RAM 00049000 00000800 00000000 00000800 RWIX + CANB_MSG_RAM 0004b000 00000800 00000000 00000800 RWIX + + +SECTION ALLOCATION MAP + + output attributes/ +section page origin length input sections +-------- ---- ---------- ---------- ---------------- +codestart +* 0 00000000 00000002 + 00000000 00000002 F2837xD_CodeStartBranch.obj (codestart) + +.cinit 0 00000128 00000012 + 00000128 00000009 (.cinit..data.load) [load image, compression = lzss] + 00000131 00000001 --HOLE-- [fill = 0] + 00000132 00000004 (__TI_handler_table) + 00000136 00000004 (__TI_cinit_table) + +.reset 0 003fffc0 00000000 DSECT + +.stack 1 00000400 00000100 UNINITIALIZED + 00000400 00000100 --HOLE-- + +.init_array +* 0 00000123 00000000 UNINITIALIZED + +.const 1 0000a800 000001e1 + 0000a800 000000c2 driverlib_eabi.lib : sysctl.obj (.const:.string) + 0000a8c2 000000bc : gpio.obj (.const:.string) + 0000a97e 00000050 gpio_driverlib_cpu1.obj (.const:.string) + 0000a9ce 00000013 device.obj (.const:.string) + +.data 1 0000a9e2 00000010 UNINITIALIZED + 0000a9e2 00000006 device.obj (.data) + 0000a9e8 00000006 rts2800_fpu32_eabi.lib : exit.c.obj (.data) + 0000a9ee 00000002 : _lock.c.obj (.data:_lock) + 0000a9f0 00000002 : _lock.c.obj (.data:_unlock) + +.TI.ramfunc +* 0 00000123 00000004 + 00000123 00000004 driverlib_eabi.lib : sysctl.obj (.TI.ramfunc) + +GETBUFFER +* 0 0003f800 00000000 DSECT + +GETWRITEIDX +* 0 0003f800 00000000 DSECT + +PUTREADIDX +* 0 0003f800 00000000 DSECT + +.text.1 0 00008000 00000397 + 00008000 00000051 driverlib_eabi.lib : sysctl.obj (.text:SysCtl_getClock) + 00008051 00000051 gpio_driverlib_cpu1.obj (.text) + 000080a2 00000048 driverlib_eabi.lib : sysctl.obj (.text:SysCtl_selectOscSource) + 000080ea 00000037 : gpio.obj (.text:GPIO_setControllerCore) + 00008121 00000037 : gpio.obj (.text:GPIO_setPinConfig) + 00008158 00000037 : gpio.obj (.text:GPIO_setQualificationMode) + 0000818f 00000031 : gpio.obj (.text:GPIO_setDirectionMode) + 000081c0 0000002e rts2800_fpu32_eabi.lib : copy_decompress_lzss.c.obj (.text:decompress:lzss) + 000081ee 0000002b : autoinit.c.obj (.text:__TI_auto_init_nobinit_nopinit) + 00008219 00000029 : exit.c.obj (.text) + 00008242 00000028 driverlib_eabi.lib : sysctl.obj (.text:CPUTimer_selectClockSource) + 0000826a 0000001f : sysctl.obj (.text:CPUTimer_getTimerOverflowStatus) + 00008289 0000001a : sysctl.obj (.text:CPUTimer_startTimer) + 000082a3 0000001a : sysctl.obj (.text:SysCtl_getLowSpeedClock) + 000082bd 00000017 : sysctl.obj (.text:CPUTimer_isBaseValid) + 000082d4 00000017 rts2800_fpu32_eabi.lib : boot28.asm.obj (.text) + 000082eb 00000014 driverlib_eabi.lib : sysctl.obj (.text:CPUTimer_stopTimer) + 000082ff 00000012 : sysctl.obj (.text:CPUTimer_clearOverflowFlag) + 00008311 00000012 : sysctl.obj (.text:CPUTimer_disableInterrupt) + 00008323 00000012 rts2800_fpu32_eabi.lib : args_main.c.obj (.text) + 00008335 00000011 driverlib_eabi.lib : sysctl.obj (.text:CPUTimer_setPeriod) + 00008346 0000000f : sysctl.obj (.text:SysCtl_pollCpuTimer) + 00008355 0000000e : gpio.obj (.text:GPIO_isPinValid) + 00008363 0000000b : sysctl.obj (.text:SysCtl_isMCDClockFailureDetected) + 0000836e 00000009 : sysctl.obj (.text:SysCtl_serviceWatchdog) + 00008377 00000009 rts2800_fpu32_eabi.lib : _lock.c.obj (.text) + 00008380 00000008 F2837xD_CodeStartBranch.obj (.text) + 00008388 00000008 rts2800_fpu32_eabi.lib : copy_decompress_none.c.obj (.text:decompress:none) + 00008390 00000007 driverlib_eabi.lib : sysctl.obj (.text:SysCtl_resetMCD) + +.text.2 0 0000b000 000007fd + 0000b000 000003ff device.obj (.text) + 0000b3ff 00000209 driverlib_eabi.lib : sysctl.obj (.text:SysCtl_setClock) + 0000b608 00000090 : sysctl.obj (.text:SysCtl_selectXTAL) + 0000b698 00000088 rts2800_fpu32_eabi.lib : fs_div28.asm.obj (.text) + 0000b720 00000068 driverlib_eabi.lib : sysctl.obj (.text:SysCtl_getDeviceParametric) + 0000b788 00000052 : gpio.obj (.text:GPIO_setPadConfig) + 0000b7da 00000020 rts2800_fpu32_eabi.lib : memcpy.c.obj (.text) + 0000b7fa 00000002 : pre_init.c.obj (.text) + 0000b7fc 00000001 : startup.c.obj (.text) + +MODULE SUMMARY + + Module code ro data rw data + ------ ---- ------- ------- + ./ + gpio_driverlib_cpu1.obj 81 80 0 + +--+-----------------------------+------+---------+---------+ + Total: 81 80 0 + + ./device/ + device.obj 1023 19 6 + F2837xD_CodeStartBranch.obj 10 0 0 + +--+-----------------------------+------+---------+---------+ + Total: 1033 19 6 + + /Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib_eabi.lib + sysctl.obj 1187 194 0 + gpio.obj 310 188 0 + +--+-----------------------------+------+---------+---------+ + Total: 1497 382 0 + + /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib/rts2800_fpu32_eabi.lib + fs_div28.asm.obj 136 0 0 + exit.c.obj 41 0 6 + copy_decompress_lzss.c.obj 46 0 0 + autoinit.c.obj 43 0 0 + memcpy.c.obj 32 0 0 + boot28.asm.obj 23 0 0 + args_main.c.obj 18 0 0 + _lock.c.obj 9 0 4 + copy_decompress_none.c.obj 8 0 0 + pre_init.c.obj 2 0 0 + startup.c.obj 1 0 0 + +--+-----------------------------+------+---------+---------+ + Total: 359 0 10 + + Stack: 0 0 256 + Linker Generated: 0 17 0 + +--+-----------------------------+------+---------+---------+ + Grand Total: 2970 498 272 + + +LINKER GENERATED COPY TABLES + +__TI_cinit_table @ 00000136 records: 1, size/record: 4, table size: 4 + .data: load addr=00000128, load size=00000009 bytes, run addr=0000a9e2, run size=00000010 bytes, compression=lzss + + +LINKER GENERATED HANDLER TABLE + +__TI_handler_table @ 00000132 records: 2, size/record: 2, table size: 4 + index: 0, handler: __TI_decompress_lzss + index: 1, handler: __TI_decompress_none + + +GLOBAL DATA SYMBOLS: SORTED BY DATA PAGE + +address data page name +-------- ---------------- ---- +00000400 10 (00000400) __stack + +0000a9e2 2a7 (0000a9c0) Example_Result +0000a9e4 2a7 (0000a9c0) Example_PassCount +0000a9e6 2a7 (0000a9c0) Example_Fail +0000a9e8 2a7 (0000a9c0) __TI_enable_exit_profile_output +0000a9ea 2a7 (0000a9c0) __TI_cleanup_ptr +0000a9ec 2a7 (0000a9c0) __TI_dtors_ptr +0000a9ee 2a7 (0000a9c0) _lock +0000a9f0 2a7 (0000a9c0) _unlock + + +GLOBAL SYMBOLS: SORTED ALPHABETICALLY BY Name + +page address name +---- ------- ---- +0 00008219 C$$EXIT +0 0000b273 Device_bootCPU2 +0 0000b242 Device_configureTMXAnalogTrim +0 0000b0f0 Device_enableAllPeripherals +0 0000b22c Device_enableUnbondedGPIOPullups +0 0000b20f Device_enableUnbondedGPIOPullupsFor100Pin +0 0000b1fc Device_enableUnbondedGPIOPullupsFor176Pin +0 0000b0ae Device_init +0 0000b1db Device_initGPIO +1 0000a9e6 Example_Fail +1 0000a9e4 Example_PassCount +1 0000a9e2 Example_Result +0 0000b3fe Example_done +0 0000b3f9 Example_setResultFail +0 0000b3f4 Example_setResultPass +0 000080ea GPIO_setControllerCore +0 0000818f GPIO_setDirectionMode +0 0000b788 GPIO_setPadConfig +0 00008121 GPIO_setPinConfig +0 00008158 GPIO_setQualificationMode +0 00000123 SysCtl_delay +0 00008000 SysCtl_getClock +0 0000b720 SysCtl_getDeviceParametric +0 000082a3 SysCtl_getLowSpeedClock +0 000080a2 SysCtl_selectOscSource +0 0000b608 SysCtl_selectXTAL +0 0000b3ff SysCtl_setClock +0 00000136 __TI_CINIT_Base +0 0000013a __TI_CINIT_Limit +0 0000013a __TI_CINIT_Warm +0 00000132 __TI_Handler_Table_Base +0 00000136 __TI_Handler_Table_Limit +1 00000500 __TI_STACK_END +abs 00000100 __TI_STACK_SIZE +0 000081ee __TI_auto_init_nobinit_nopinit +1 0000a9ea __TI_cleanup_ptr +0 000081c0 __TI_decompress_lzss +0 00008388 __TI_decompress_none +1 0000a9ec __TI_dtors_ptr +1 0000a9e8 __TI_enable_exit_profile_output +abs ffffffff __TI_pprof_out_hndl +abs ffffffff __TI_prof_data_size +abs ffffffff __TI_prof_data_start +0 0000b698 __c28xabi_divf +abs ffffffff __c_args__ +0 0000b3ed __error__ +1 00000400 __stack +0 00008323 _args_main +0 000082d4 _c_int00 +1 0000a9ee _lock +0 0000837f _nop +0 0000837b _register_lock +0 00008377 _register_unlock +0 0000b7fc _system_post_cinit +0 0000b7fa _system_pre_init +1 0000a9f0 _unlock +0 00008219 abort +0 00000000 code_start +0 0000821b exit +0 00008084 main +0 0000b7da memcpy + + +GLOBAL SYMBOLS: SORTED BY Symbol Address + +page address name +---- ------- ---- +0 00000000 code_start +0 00000123 SysCtl_delay +0 00000132 __TI_Handler_Table_Base +0 00000136 __TI_CINIT_Base +0 00000136 __TI_Handler_Table_Limit +0 0000013a __TI_CINIT_Limit +0 0000013a __TI_CINIT_Warm +0 00008000 SysCtl_getClock +0 00008084 main +0 000080a2 SysCtl_selectOscSource +0 000080ea GPIO_setControllerCore +0 00008121 GPIO_setPinConfig +0 00008158 GPIO_setQualificationMode +0 0000818f GPIO_setDirectionMode +0 000081c0 __TI_decompress_lzss +0 000081ee __TI_auto_init_nobinit_nopinit +0 00008219 C$$EXIT +0 00008219 abort +0 0000821b exit +0 000082a3 SysCtl_getLowSpeedClock +0 000082d4 _c_int00 +0 00008323 _args_main +0 00008377 _register_unlock +0 0000837b _register_lock +0 0000837f _nop +0 00008388 __TI_decompress_none +0 0000b0ae Device_init +0 0000b0f0 Device_enableAllPeripherals +0 0000b1db Device_initGPIO +0 0000b1fc Device_enableUnbondedGPIOPullupsFor176Pin +0 0000b20f Device_enableUnbondedGPIOPullupsFor100Pin +0 0000b22c Device_enableUnbondedGPIOPullups +0 0000b242 Device_configureTMXAnalogTrim +0 0000b273 Device_bootCPU2 +0 0000b3ed __error__ +0 0000b3f4 Example_setResultPass +0 0000b3f9 Example_setResultFail +0 0000b3fe Example_done +0 0000b3ff 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0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS2 + 0x0 + 0x9000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS3 + 0x0 + 0x9800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMLS4 + 0x0 + 0xa000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMD0 + 0x0 + 0xb000 + 0x800 + 0x7fd + 0x3 + RWIX + + + 0xb000 + 0x7fd + + + + 0xb7fd + 0x3 + + + + + FLASHA + 0x0 + 0x80002 + 0x1ffe + 0x0 + 0x1ffe + RWIX + + + + + FLASHB + 0x0 + 0x82000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHC + 0x0 + 0x84000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHD + 0x0 + 0x86000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHE + 0x0 + 0x88000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHF + 0x0 + 0x90000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHG + 0x0 + 0x98000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHH + 0x0 + 0xa0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHI + 0x0 + 0xa8000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHJ + 0x0 + 0xb0000 + 0x8000 + 0x0 + 0x8000 + RWIX + + + + + FLASHK + 0x0 + 0xb8000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHL + 0x0 + 0xba000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHM + 0x0 + 0xbc000 + 0x2000 + 0x0 + 0x2000 + RWIX + + + + + FLASHN + 0x0 + 0xbe000 + 0x1ff0 + 0x0 + 0x1ff0 + RWIX + + + + + RESET + 0x0 + 0x3fffc0 + 0x2 + 0x0 + 0x2 + RWIX + + + + + BOOT_RSVD + 0x1 + 0x2 + 0x121 + 0x0 + 0x121 + RWIX + + + + + RAMM1 + 0x1 + 0x400 + 0x3f8 + 0x100 + 0x2f8 + RWIX + + + 0x400 + 0x100 + + + + 0x500 + 0x2f8 + + + + + RAMLS5 + 0x1 + 0xa800 + 0x800 + 0x1f1 + 0x60f + RWIX + + + 0xa800 + 0x1e1 + + + + 0xa9e1 + 0x1 + + + 0xa9e2 + 0x10 + + + + 0xa9f2 + 0x60e + + + + + RAMD1 + 0x1 + 0xb800 + 0x800 + 0x0 + 0x800 + RWIX + + + + + RAMGS0 + 0x1 + 0xc000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS1 + 0x1 + 0xd000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS2 + 0x1 + 0xe000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS3 + 0x1 + 0xf000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS4 + 0x1 + 0x10000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS5 + 0x1 + 0x11000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS6 + 0x1 + 0x12000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS7 + 0x1 + 0x13000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS8 + 0x1 + 0x14000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS9 + 0x1 + 0x15000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS10 + 0x1 + 0x16000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS11 + 0x1 + 0x17000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS12 + 0x1 + 0x18000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS13 + 0x1 + 0x19000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS14 + 0x1 + 0x1a000 + 0x1000 + 0x0 + 0x1000 + RWIX + + + + + RAMGS15 + 0x1 + 0x1b000 + 0xff8 + 0x0 + 0xff8 + RWIX + + + + + CPU2TOCPU1RAM + 0x1 + 0x3f800 + 0x400 + 0x0 + 0x400 + RWIX + + + + + CPU1TOCPU2RAM + 0x1 + 0x3fc00 + 0x400 + 0x0 + 0x400 + RWIX + + + + + CANA_MSG_RAM + 0x1 + 0x49000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + CANB_MSG_RAM + 0x1 + 0x4b000 + 0x800 + 0x0 + 0x800 + RWIX + + + + + + + __TI_cinit_table + + .data + 0x128 + 0x9 + 0xa9e2 + 0x10 + lzss + + + + + __TI_handler_table + + 0x0 + __TI_decompress_lzss + + + 0x1 + __TI_decompress_none + + + + + __TI_CINIT_Base + 0x136 + + + __TI_CINIT_Limit + 0x13a + + + __TI_CINIT_Warm + 0x13a + + + __TI_Handler_Table_Base + 0x132 + + + __TI_Handler_Table_Limit + 0x136 + + + __TI_STACK_SIZE + 0x100 + + + __TI_STACK_END + 0x500 + + + __c_args__ + 0xffffffff + + + __TI_pprof_out_hndl + 0xffffffff + + + __TI_prof_data_start + 0xffffffff + + + __TI_prof_data_size + 0xffffffff + + + main + 0x8084 + + + + code_start + 0x0 + + + + Device_enableAllPeripherals + 0xb0f0 + + + + Device_initGPIO + 0xb1db + + + + Example_Fail + 0xa9e6 + + + + Example_setResultFail + 0xb3f9 + + + + Device_bootCPU2 + 0xb273 + + + + Device_init + 0xb0ae + + + + Example_Result + 0xa9e2 + + + + Device_enableUnbondedGPIOPullups + 0xb22c + + + + __error__ + 0xb3ed + + + + Example_setResultPass + 0xb3f4 + + + + Device_configureTMXAnalogTrim + 0xb242 + + + + Device_enableUnbondedGPIOPullupsFor176Pin + 0xb1fc + + + + Example_done + 0xb3fe + + + + Example_PassCount + 0xa9e4 + + + + Device_enableUnbondedGPIOPullupsFor100Pin + 0xb20f + + + + GPIO_setQualificationMode + 0x8158 + + + + GPIO_setPadConfig + 0xb788 + + + + GPIO_setDirectionMode + 0x818f + + + + GPIO_setPinConfig + 0x8121 + + + + GPIO_setControllerCore + 0x80ea + + + + SysCtl_delay + 0x123 + + + + SysCtl_getDeviceParametric + 0xb720 + + + + SysCtl_selectXTAL + 0xb608 + + + + SysCtl_selectOscSource + 0x80a2 + + + + SysCtl_getLowSpeedClock + 0x82a3 + + + + SysCtl_setClock + 0xb3ff + + + + SysCtl_getClock + 0x8000 + + + + _c_int00 + 0x82d4 + + + + __stack + 0x400 + + + + __c28xabi_divf + 0xb698 + + + + _system_pre_init + 0xb7fa + + + + __TI_auto_init_nobinit_nopinit + 0x81ee + + + + __TI_decompress_none + 0x8388 + + + + __TI_decompress_lzss + 0x81c0 + + + + C$$EXIT + 0x8219 + + + + abort + 0x8219 + + + + exit + 0x821b + + + + __TI_dtors_ptr + 0xa9ec + + + + __TI_cleanup_ptr + 0xa9ea + + + + __TI_enable_exit_profile_output + 0xa9e8 + + + + _nop + 0x837f + + + + _lock + 0xa9ee + + + + _unlock + 0xa9f0 + + + + _register_lock + 0x837b + + + + _register_unlock + 0x8377 + + + + _args_main + 0x8323 + + + + memcpy + 0xb7da + + + + _system_post_cinit + 0xb7fc + + + + Link successful +     diff --git a/gpio_driverlib_cpu1/CPU1_RAM/makefile b/gpio_driverlib_cpu1/CPU1_RAM/makefile new file mode 100644 index 0000000..c5463b7 --- /dev/null +++ b/gpio_driverlib_cpu1/CPU1_RAM/makefile @@ -0,0 +1,149 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +CG_TOOL_ROOT := /Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS + +GEN_OPTS__FLAG := +GEN_CMDS__FLAG := + +ORDERED_OBJS += \ +"./gpio_driverlib_cpu1.obj" \ +"./device/F2837xD_CodeStartBranch.obj" \ +"./device/device.obj" \ +"../2837xD_RAM_lnk_cpu1.cmd" \ +"/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/ccs/Debug/driverlib.lib" \ +$(GEN_CMDS__FLAG) \ +-llibc.a \ + +-include ../makefile.init + +RM := rm -rf +RMDIR := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include subdir_vars.mk +-include device/subdir_vars.mk +-include subdir_rules.mk +-include device/subdir_rules.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(C55_DEPS)),) +-include $(C55_DEPS) +endif +ifneq ($(strip $(C_UPPER_DEPS)),) +-include $(C_UPPER_DEPS) +endif +ifneq ($(strip $(S67_DEPS)),) +-include $(S67_DEPS) +endif +ifneq ($(strip $(S62_DEPS)),) +-include $(S62_DEPS) +endif +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(OPT_DEPS)),) +-include $(OPT_DEPS) +endif +ifneq ($(strip $(C??_DEPS)),) +-include $(C??_DEPS) +endif +ifneq ($(strip $(ASM_UPPER_DEPS)),) +-include $(ASM_UPPER_DEPS) +endif +ifneq ($(strip $(S??_DEPS)),) +-include $(S??_DEPS) +endif +ifneq ($(strip $(C64_DEPS)),) +-include $(C64_DEPS) +endif +ifneq ($(strip $(CXX_DEPS)),) +-include $(CXX_DEPS) +endif +ifneq ($(strip $(S64_DEPS)),) +-include $(S64_DEPS) +endif +ifneq ($(strip $(CLA_DEPS)),) +-include $(CLA_DEPS) +endif +ifneq ($(strip $(S55_DEPS)),) +-include $(S55_DEPS) +endif +ifneq ($(strip $(SV7A_DEPS)),) +-include $(SV7A_DEPS) +endif +ifneq ($(strip $(C62_DEPS)),) +-include $(C62_DEPS) +endif +ifneq ($(strip $(C67_DEPS)),) +-include $(C67_DEPS) +endif +ifneq ($(strip $(K_DEPS)),) +-include $(K_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +ifneq ($(strip $(CC_DEPS)),) +-include $(CC_DEPS) +endif +ifneq ($(strip $(C++_DEPS)),) +-include $(C++_DEPS) +endif +ifneq ($(strip $(C43_DEPS)),) +-include $(C43_DEPS) +endif +ifneq ($(strip $(S43_DEPS)),) +-include $(S43_DEPS) +endif +ifneq ($(strip $(ASM_DEPS)),) +-include $(ASM_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(CPP_DEPS)),) +-include $(CPP_DEPS) +endif +ifneq ($(strip $(SA_DEPS)),) +-include $(SA_DEPS) +endif +endif + +-include ../makefile.defs + +# Add inputs and outputs from these tool invocations to the build variables +EXE_OUTPUTS += \ +gpio_driverlib_cpu1.out + +EXE_OUTPUTS__QUOTED += \ +"gpio_driverlib_cpu1.out" + + +# All Target +all: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @$(MAKE) --no-print-directory -Onone "gpio_driverlib_cpu1.out" + +# Tool invocations +gpio_driverlib_cpu1.out: $(OBJS) $(CMD_SRCS) $(LIB_SRCS) $(GEN_CMDS) + @echo 'C2000 Linker - building target: "$@"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi -z -m"gpio_driverlib_cpu1.map" --stack_size=0x100 --warn_sections -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/lib" -i"/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --reread_libs --diag_wrap=off --display_error_number --xml_link_info="gpio_driverlib_cpu1_linkInfo.xml" --entry_point=code_start --rom_model -o "gpio_driverlib_cpu1.out" $(ORDERED_OBJS) + @echo 'Finished building target: "$@"' + @echo ' ' + +# Other Targets +clean: + -$(RM) $(EXE_OUTPUTS__QUOTED) + -$(RM) "gpio_driverlib_cpu1.obj" "device/F2837xD_CodeStartBranch.obj" "device/device.obj" + -$(RM) "gpio_driverlib_cpu1.d" "device/device.d" + -$(RM) "device/F2837xD_CodeStartBranch.d" + -@echo ' ' + +.PHONY: all clean dependents +.SECONDARY: + +-include ../makefile.targets + diff --git a/gpio_driverlib_cpu1/CPU1_RAM/objects.mk b/gpio_driverlib_cpu1/CPU1_RAM/objects.mk new file mode 100644 index 0000000..ad64ce9 --- /dev/null +++ b/gpio_driverlib_cpu1/CPU1_RAM/objects.mk @@ -0,0 +1,8 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +USER_OBJS := + +LIBS := -llibc.a + diff --git a/gpio_driverlib_cpu1/CPU1_RAM/sources.mk b/gpio_driverlib_cpu1/CPU1_RAM/sources.mk new file mode 100644 index 0000000..beb2fed --- /dev/null +++ b/gpio_driverlib_cpu1/CPU1_RAM/sources.mk @@ -0,0 +1,110 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +C55_SRCS := +A_SRCS := +ASM_UPPER_SRCS := +EXE_SRCS := +LDS_UPPER_SRCS := +CPP_SRCS := +CMD_SRCS := +O_SRCS := +ELF_SRCS := +C??_SRCS := +C64_SRCS := +C67_SRCS := +SA_SRCS := +S64_SRCS := +OPT_SRCS := +CXX_SRCS := +S67_SRCS := +S??_SRCS := +SV7A_SRCS := +K_SRCS := +CLA_SRCS := +S55_SRCS := +LD_UPPER_SRCS := +OUT_SRCS := +LIB_SRCS := +ASM_SRCS := +S_UPPER_SRCS := +S43_SRCS := +LD_SRCS := +CMD_UPPER_SRCS := +C_UPPER_SRCS := +C++_SRCS := +C43_SRCS := +OBJ_SRCS := +LDS_SRCS := +S_SRCS := +CC_SRCS := +S62_SRCS := +C62_SRCS := +C_SRCS := +C55_DEPS := +C_UPPER_DEPS := +S67_DEPS := +S62_DEPS := +S_DEPS := +OPT_DEPS := +C??_DEPS := +ASM_UPPER_DEPS := +S??_DEPS := +C64_DEPS := +CXX_DEPS := +S64_DEPS := +CLA_DEPS := +S55_DEPS := +SV7A_DEPS := +EXE_OUTPUTS := +C62_DEPS := +C67_DEPS := +K_DEPS := +C_DEPS := +CC_DEPS := +BIN_OUTPUTS := +C++_DEPS := +C43_DEPS := +S43_DEPS := +OBJS := +ASM_DEPS := +S_UPPER_DEPS := +CPP_DEPS := +SA_DEPS := +C++_DEPS__QUOTED := +OPT_DEPS__QUOTED := +SA_DEPS__QUOTED := +S_UPPER_DEPS__QUOTED := +C??_DEPS__QUOTED := +S67_DEPS__QUOTED := +C55_DEPS__QUOTED := +CC_DEPS__QUOTED := +ASM_UPPER_DEPS__QUOTED := +SV7A_DEPS__QUOTED := +S??_DEPS__QUOTED := +OBJS__QUOTED := +C67_DEPS__QUOTED := +K_DEPS__QUOTED := +S55_DEPS__QUOTED := +C62_DEPS__QUOTED := +C_DEPS__QUOTED := +C_UPPER_DEPS__QUOTED := +C43_DEPS__QUOTED := +CPP_DEPS__QUOTED := +BIN_OUTPUTS__QUOTED := +C64_DEPS__QUOTED := +CXX_DEPS__QUOTED := +CLA_DEPS__QUOTED := +S_DEPS__QUOTED := +ASM_DEPS__QUOTED := +S43_DEPS__QUOTED := +EXE_OUTPUTS__QUOTED := +S64_DEPS__QUOTED := +S62_DEPS__QUOTED := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +. \ +device \ + diff --git a/gpio_driverlib_cpu1/CPU1_RAM/subdir_rules.mk b/gpio_driverlib_cpu1/CPU1_RAM/subdir_rules.mk new file mode 100644 index 0000000..e2a189c --- /dev/null +++ b/gpio_driverlib_cpu1/CPU1_RAM/subdir_rules.mk @@ -0,0 +1,12 @@ +################################################################################ +# Automatically-generated file. Do not edit! +################################################################################ + +# Each subdirectory must supply rules for building sources it contributes +%.obj: ../%.c $(GEN_OPTS) | $(GEN_FILES) $(GEN_MISC_FILES) + @echo 'C2000 Compiler - building file: "$<"' + "/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/bin/cl2000" -v28 -ml -mt --cla_support=cla1 --float_support=fpu32 --tmu_support=tmu0 --vcu_support=vcu2 -Ooff --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_driverlib_cpu1" --include_path="/Users/gmarx/lwc/workshops/f28379d/lab-examples/2-gpios-dual-alternative/gpio_driverlib_cpu1/device" --include_path="/Applications/ti/c2000/C2000Ware_26_00_00_00/driverlib/f2837xd/driverlib/" --include_path="/Applications/ti/ccs2050/ccs/tools/compiler/ti-cgt-c2000_25.11.0.LTS/include" --define=DEBUG --define=CPU1 --diag_suppress=10063 --diag_warning=225 --diag_wrap=off --display_error_number --abi=eabi --preproc_with_compile --preproc_dependency="$(basename $(>6 ;Set data page for WDCR register + MOV @7029h, #0068h ;Set WDDIS bit in WDCR to disable WD + EDIS ;Disable EALLOW protected register access + LB _c_int00 ;Branch to start of boot._asm in RTS library + + .endif + +;end wd_disable + + .end + +;// +;// End of file. +;// diff --git a/gpio_driverlib_cpu1/device/device.c b/gpio_driverlib_cpu1/device/device.c new file mode 100644 index 0000000..b64b33d --- /dev/null +++ b/gpio_driverlib_cpu1/device/device.c @@ -0,0 +1,706 @@ +//############################################################################# +// +// FILE: device.c +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "device.h" +#include "driverlib.h" +#include "inc/hw_ipc.h" + +#ifdef CMDTOOL +#include "device_cmd.h" +#endif + +#ifdef __cplusplus +using std::memcpy; +#endif + +#define PASS 0 +#define FAIL 1 + +uint32_t Example_Result = FAIL; +uint32_t Example_PassCount = 0; +uint32_t Example_Fail = 0; + +//***************************************************************************** +// +// Function to initialize the device. Primarily initializes system control to a +// known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +// and enabling the clocks to the peripherals. +// +//***************************************************************************** +void Device_init(void) +{ + // + // Disable the watchdog + // + SysCtl_disableWatchdog(); + +#ifdef CMDTOOL + CMD_init(); +#endif + +#ifdef _FLASH +#ifndef CMDTOOL + // + // Copy time critical code and flash setup code to RAM. This includes the + // following functions: InitFlash(); + // + // The RamfuncsLoadStart, RamfuncsLoadSize, and RamfuncsRunStart symbols + // are created by the linker. Refer to the device .cmd file. + // + memcpy(&RamfuncsRunStart, &RamfuncsLoadStart, (size_t)&RamfuncsLoadSize); +#endif + + // + // Call Flash Initialization to setup flash waitstates. This function must + // reside in RAM. + // + Flash_initModule(FLASH0CTRL_BASE, FLASH0ECC_BASE, DEVICE_FLASH_WAITSTATES); +#endif +#ifdef CPU1 + + // + // Configure Analog Trim in case of untrimmed or TMX sample + // + if((SysCtl_getDeviceParametric(SYSCTL_DEVICE_QUAL) == 0x0U) && + (HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) == 0x0U)) + { + Device_configureTMXAnalogTrim(); + } + + // + // Set up PLL control and clock dividers + // + SysCtl_setClock(DEVICE_SETCLOCK_CFG); + + // + // Make sure the LSPCLK divider is set to the default (divide by 4) + // + SysCtl_setLowSpeedClock(SYSCTL_LSPCLK_PRESCALE_4); + + // + // These asserts will check that the #defines for the clock rates in + // device.h match the actual rates that have been configured. If they do + // not match, check that the calculations of DEVICE_SYSCLK_FREQ and + // DEVICE_LSPCLK_FREQ are accurate. Some examples will not perform as + // expected if these are not correct. + // + ASSERT(SysCtl_getClock(DEVICE_OSCSRC_FREQ) == DEVICE_SYSCLK_FREQ); + ASSERT(SysCtl_getLowSpeedClock(DEVICE_OSCSRC_FREQ) == DEVICE_LSPCLK_FREQ); + +#ifndef _FLASH + // + // Call Device_cal function when run using debugger + // This function is called as part of the Boot code. The function is called + // in the Device_init function since during debug time resets, the boot code + // will not be executed and the gel script will reinitialize all the + // registers and the calibrated values will be lost. + // Sysctl_deviceCal is a wrapper function for Device_Cal + // + SysCtl_deviceCal(); +#endif + +#endif + // + // Turn on all peripherals + // + Device_enableAllPeripherals(); + + // + // Initialize result parameter as FAIL + // + Example_Result = FAIL; +} + +//***************************************************************************** +// +// Function to turn on all peripherals, enabling reads and writes to the +// peripherals' registers. +// +// Note that to reduce power, unused peripherals should be disabled. +// +//***************************************************************************** +void Device_enableAllPeripherals(void) +{ + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CLA1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DMA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER0); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TIMER2); +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_HRPWM); +#endif + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_TBCLKSYNC); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EMIF2); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM8); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM9); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM10); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM11); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EPWM12); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ECAP6); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_EQEP3); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SD2); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCIC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SCID); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_SPIC); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_I2CB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANB); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_MCBSPB); + +#ifdef CPU1 + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_USBA); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_UPPA); +#endif + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS1); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS2); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS3); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS4); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS5); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS6); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS7); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CMPSS8); + + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_DACC); +} + +//***************************************************************************** +// +// Function to disable pin locks on GPIOs. +// +//***************************************************************************** +void Device_initGPIO(void) +{ + // + // Disable pin locks. + // + GPIO_unlockPortConfig(GPIO_PORT_A, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_B, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_D, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_E, 0xFFFFFFFF); + GPIO_unlockPortConfig(GPIO_PORT_F, 0xFFFFFFFF); + + // + // Enable GPIO Pullups + // + Device_enableUnbondedGPIOPullups(); +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 176PTP package: +// GPIOs Grp Bits +// 95-132 C 31 +// D 31:0 +// E 4:0 +// 134-168 E 31:6 +// F 8:0 +// +//***************************************************************************** + +void Device_enableUnbondedGPIOPullupsFor176Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0x80000000U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFDFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ package: +// GPIOs Grp Bits +// 0-1 A 1:0 +// 5-9 A 9:5 +// 22-40 A 31:22 +// B 8:0 +// 44-57 B 25:12 +// 67-68 C 4:3 +// 74-77 C 13:10 +// 79-83 C 19:15 +// 93-168 C 31:29 +// D 31:0 +// E 31:0 +// F 8:0 +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullupsFor100Pin(void) +{ + EALLOW; + HWREG(GPIOCTRL_BASE + GPIO_O_GPAPUD) = ~0xFFC003E3U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPBPUD) = ~0x03FFF1FFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPCPUD) = ~0xE10FBC18U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPDPUD) = ~0xFFFFFFF7U; + HWREG(GPIOCTRL_BASE + GPIO_O_GPEPUD) = ~0xFFFFFFFFU; + HWREG(GPIOCTRL_BASE + GPIO_O_GPFPUD) = ~0x000001FFU; + EDIS; +} + +//***************************************************************************** +// +// Function to enable pullups for the unbonded GPIOs on the 100PZ or +// 176PTP package. +// +//***************************************************************************** +void Device_enableUnbondedGPIOPullups(void) +{ + // + // bits 8-10 have pin count + // + uint16_t pinCount = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + (uint32_t)SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + + /* + * 5 = 100 pin + * 6 = 176 pin + * 7 = 337 pin + */ + if(pinCount == 5) + { + Device_enableUnbondedGPIOPullupsFor100Pin(); + } + else if(pinCount == 6) + { + Device_enableUnbondedGPIOPullupsFor176Pin(); + } + else + { + // + // Do nothing - this is 337 pin package + // + } +} + +#ifdef CPU1 +//***************************************************************************** +// +// Function to implement Analog trim of TMX devices +// +//***************************************************************************** +void Device_configureTMXAnalogTrim(void) +{ + // + // Enable ADC clock + // + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_ADCD); + + // + // Configure ADC reference trim for TMX devices + // + EALLOW; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMA) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMB) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMC) = 0x7BDDU; + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_ANAREFTRIMD) = 0x7BDDU; + + // + // Configure ADC offset trim. The user should generate the trim values + // by following the instructions in the "ADC Zero Offset Calibration" + // section in device TRM. The below lines needs to be uncommented and + // updated with the correct trim values. + // +// HWREGH(ADCA_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCB_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCC_BASE + ADC_O_OFFTRIM) = 0x0U; +// HWREGH(ADCD_BASE + ADC_O_OFFTRIM) = 0x0U; + + // + // Configure internal oscillator trim. If the internal oscillator trim + // contains all zeros, the user can adjust the lowest 10 bits of the + // oscillator trim register between 1 (minimum) and 1023 (maximum) + // while observing the system clock on the XCLOCKOUT pin. The below + // lines needs to be uncommented and updated with the correct trim values. + // +// if(HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) == 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC1TRIM) = 0x0U; +// } +// if( HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U) +// { +// HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_INTOSC2TRIM) = 0x0U; +// } + + EDIS; + + // + // Disable ADC clock + // + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCA); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCB); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCC); + SysCtl_disablePeripheral(SYSCTL_PERIPH_CLK_ADCD); +} + +//***************************************************************************** +//! Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +uint16_t +Device_bootCPU2(uint32_t bootMode) +{ + uint32_t bootStatus; + uint16_t pin; + uint16_t returnStatus = STATUS_PASS; + + // + // If CPU2 has already booted, return a fail to let the application + // know that something is out of the ordinary. + // + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & 0x0000000FU; + + if(bootStatus == C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK) + { + // + // Check if MSB is set as well + // + bootStatus = ((uint32_t)(HWREG(IPC_BASE + IPC_O_BOOTSTS) & + 0x80000000U)) >> 31U; + + if(bootStatus != 0) + { + returnStatus = STATUS_FAIL; + + return returnStatus; + } + } + + // + // Wait until CPU02 control system boot ROM is ready to receive + // CPU01 to CPU02 INT1 interrupts. + // + do + { + bootStatus = HWREG(IPC_BASE + IPC_O_BOOTSTS) & + C2_BOOTROM_BOOTSTS_SYSTEM_READY; + } while ((bootStatus != C2_BOOTROM_BOOTSTS_SYSTEM_READY)); + + // + // Loop until CPU02 control system IPC flags 1 and 32 are available + // + while (((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC0) != 0U) || + ((HWREG(IPC_BASE + IPC_O_FLG) & IPC_FLG_IPC31) != 0U)) + { + + } + + if (bootMode >= C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE) + { + returnStatus = STATUS_FAIL; + } + else + { + // + // Based on boot mode, enable pull-ups on peripheral pins and + // give GPIO pin control to CPU02 control system. + // + switch (bootMode) + { + case C1C2_BROM_BOOTMODE_BOOT_FROM_SCI: + + // + //SCIA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL5_SCI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(29, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(29, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_29_SCITXDA); + GPIO_setMasterCore(29, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(28, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(28, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_28_SCIRXDA); + GPIO_setMasterCore(28, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_SPI: + + // + //SPI-A connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL6_SPI, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU02 bootrom to take control of clock configuration + // registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + EDIS; + + GPIO_setDirectionMode(16, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(16, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_16_SPISIMOA); + GPIO_setMasterCore(16, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(17, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(17, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_17_SPISOMIA); + GPIO_setMasterCore(17, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(18, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(18, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_18_SPICLKA); + GPIO_setMasterCore(18, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(19, GPIO_DIR_MODE_OUT); + GPIO_setQualificationMode(19, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_19_GPIO19); + GPIO_setMasterCore(19, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_I2C: + + // + //I2CA connected to CPU02 + // + SysCtl_selectCPUForPeripheral(SYSCTL_CPUSEL7_I2C, 1, + SYSCTL_CPUSEL_CPU2); + + // + //Allows CPU2 bootrom to take control of clock + //configuration registers + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSEM) = 0xA5A50000U; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = 0x0002U; + EDIS; + + GPIO_setDirectionMode(32, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(32, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_32_SDAA); + GPIO_setMasterCore(32, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(33, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(33, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_33_SCLA); + GPIO_setMasterCore(33, GPIO_CORE_CPU2); + + break; + + case C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL: + + for(pin=58;pin<=65;pin++) + { + GPIO_setDirectionMode(pin, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(pin, GPIO_QUAL_ASYNC); + GPIO_setMasterCore(pin, GPIO_CORE_CPU2); + } + + GPIO_setDirectionMode(69, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(69, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_69_GPIO69); + GPIO_setMasterCore(69, GPIO_CORE_CPU2); + + GPIO_setDirectionMode(70, GPIO_DIR_MODE_IN); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + GPIO_setPinConfig(GPIO_70_GPIO70); + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + + break; + + + case C1C2_BROM_BOOTMODE_BOOT_FROM_CAN: + // + //Set up the GPIO mux to bring out CANATX on GPIO71 + //and CANARX on GPIO70 + // + GPIO_unlockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + GPIO_setMasterCore(71, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_71_CANTXA); + GPIO_setQualificationMode(71, GPIO_QUAL_ASYNC); + + GPIO_setMasterCore(70, GPIO_CORE_CPU2); + GPIO_setPinConfig(GPIO_70_CANRXA); + GPIO_setQualificationMode(70, GPIO_QUAL_ASYNC); + + + GPIO_lockPortConfig(GPIO_PORT_C, 0xFFFFFFFFU); + + // + // Set CANA Bit-Clock Source Select = SYSCLK and enable CAN + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + SYSCTL_CLKSRCCTL2_CANABCLKSEL_M; + EDIS; + SysCtl_enablePeripheral(SYSCTL_PERIPH_CLK_CANA); + + break; + + } + + // + //CPU01 to CPU02 IPC Boot Mode Register + // + HWREG(IPC_BASE + IPC_O_BOOTMODE) = bootMode; + + // + // CPU01 To CPU02 IPC Command Register + // + HWREG(IPC_BASE + IPC_O_SENDCOM) = BROM_IPC_EXECUTE_BOOTMODE_CMD; + + // + // CPU01 to CPU02 IPC flag register + // + HWREG(IPC_BASE + IPC_O_SET) = 0x80000001U; + + } + return returnStatus; +} +#endif // #ifdef CPU1 +//***************************************************************************** +// +// Error handling function to be called when an ASSERT is violated +// +//***************************************************************************** +void __error__(const char *filename, uint32_t line) +{ + // + // An ASSERT condition was evaluated as false. You can use the filename and + // line parameters to determine what went wrong. + // + ESTOP0; +} + +void Example_setResultPass(void) +{ + Example_Result = PASS; +} + +void Example_setResultFail(void) +{ + Example_Result = FAIL; +} + +void Example_done(void) +{ + while(1); +} diff --git a/gpio_driverlib_cpu1/device/device.h b/gpio_driverlib_cpu1/device/device.h new file mode 100644 index 0000000..ec143e5 --- /dev/null +++ b/gpio_driverlib_cpu1/device/device.h @@ -0,0 +1,394 @@ +//############################################################################# +// +// FILE: device.h +// +// TITLE: Device setup for examples. +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +// +// Included Files +// +#include "driverlib.h" + +#if (!defined(CPU1) && !defined(CPU2)) +#error "You must define CPU1 or CPU2 in your project properties. Otherwise, \ +the offsets in your header files will be inaccurate." +#endif + +#if (defined(CPU1) && defined(CPU2)) +#error "You have defined both CPU1 and CPU2 in your project properties. Only \ +a single CPU should be defined." +#endif + +//***************************************************************************** +// +// Defines for pin numbers and other GPIO configuration +// +//***************************************************************************** +// +// LEDs +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD10 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD9 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD10 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD9 +#else +#define DEVICE_GPIO_PIN_LED1 31U // GPIO number for LD2 +#define DEVICE_GPIO_PIN_LED2 34U // GPIO number for LD3 +#define DEVICE_GPIO_CFG_LED1 GPIO_31_GPIO31 // "pinConfig" for LD2 +#define DEVICE_GPIO_CFG_LED2 GPIO_34_GPIO34 // "pinConfig" for LD3 +#endif + + +// +// SCI for USB-to-UART adapter on FTDI chip +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_PIN_SCIRXDA 43U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 42U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_43_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_42_SCITXDA // "pinConfig" for SCI TX +#else +#define DEVICE_GPIO_PIN_SCIRXDA 28U // GPIO number for SCI RX +#define DEVICE_GPIO_PIN_SCITXDA 29U // GPIO number for SCI TX +#define DEVICE_GPIO_CFG_SCIRXDA GPIO_28_SCIRXDA // "pinConfig" for SCI RX +#define DEVICE_GPIO_CFG_SCITXDA GPIO_29_SCITXDA // "pinConfig" for SCI TX +#endif + +// +// GPIO assignment for CAN-A and CAN-B +// +#ifdef _LAUNCHXL_F28379D +#define DEVICE_GPIO_CFG_CANRXA GPIO_36_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_37_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_17_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_12_CANTXB // "pinConfig" for CANB TX +#else +#define DEVICE_GPIO_CFG_CANRXA GPIO_30_CANRXA // "pinConfig" for CANA RX +#define DEVICE_GPIO_CFG_CANTXA GPIO_31_CANTXA // "pinConfig" for CANA TX +#define DEVICE_GPIO_CFG_CANRXB GPIO_10_CANRXB // "pinConfig" for CANB RX +#define DEVICE_GPIO_CFG_CANTXB GPIO_8_CANTXB // "pinConfig" for CANB TX + +//I2CA GPIO pins +#define DEVICE_GPIO_PIN_SDAA 104 +#define DEVICE_GPIO_PIN_SCLA 105 + +#define DEVICE_GPIO_CFG_SDAA GPIO_104_SDAA +#define DEVICE_GPIO_CFG_SCLA GPIO_105_SCLA + + +//I2CB GPIO pins +#define DEVICE_GPIO_PIN_SDAB 40 +#define DEVICE_GPIO_PIN_SCLB 41 + +#define DEVICE_GPIO_CFG_SDAB GPIO_40_SDAB +#define DEVICE_GPIO_CFG_SCLB GPIO_41_SCLB + +#endif + +//***************************************************************************** +// +// Defines related to clock configuration +// +//***************************************************************************** +// +// Launchpad Configuration +// +#ifdef _LAUNCHXL_F28379D + +// +// 10MHz XTAL on LaunchPad. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 10000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 10MHz (XTAL_OSC) * 40 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(40) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 40 * 1) / 2) + +// +// ControlCARD Configuration +// +#else + +// +// 20MHz XTAL on controlCARD. For use with SysCtl_getClock(). +// +#define DEVICE_OSCSRC_FREQ 20000000U + +// +// Define to pass to SysCtl_setClock(). Will configure the clock as follows: +// PLLSYSCLK = 20MHz (XTAL_OSC) * 20 (IMULT) * 1 (FMULT) / 2 (PLLCLK_BY_2) +// +#define DEVICE_SETCLOCK_CFG (SYSCTL_OSCSRC_XTAL | SYSCTL_IMULT(20) | \ + SYSCTL_FMULT_NONE | SYSCTL_SYSDIV(2) | \ + SYSCTL_PLL_ENABLE) + +// +// 200MHz SYSCLK frequency based on the above DEVICE_SETCLOCK_CFG. Update the +// code below if a different clock configuration is used! +// +#define DEVICE_SYSCLK_FREQ ((DEVICE_OSCSRC_FREQ * 20 * 1) / 2) + +#endif + +// +// 50MHz LSPCLK frequency based on the above DEVICE_SYSCLK_FREQ and a default +// low speed peripheral clock divider of 4. Update the code below if a +// different LSPCLK divider is used! +// +#define DEVICE_LSPCLK_FREQ (DEVICE_SYSCLK_FREQ / 4) + +//***************************************************************************** +// +// Macro to call SysCtl_delay() to achieve a delay in microseconds. The macro +// will convert the desired delay in microseconds to the count value expected +// by the function. \b x is the number of microseconds to delay. +// +//***************************************************************************** +#define DEVICE_DELAY_US(x) SysCtl_delay(((((long double)(x)) / (1000000.0L / \ + (long double)DEVICE_SYSCLK_FREQ)) - 9.0L) / 5.0L) + +// +// The macros that can be used as parameter to the function Device_bootCPU2 +// +#define C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL 0x00000000U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SCI 0x00000001U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_SPI 0x00000004U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_I2C 0x00000005U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_CAN 0x00000007U +#define C1C2_BROM_BOOTMODE_BOOT_FROM_RAM 0x0000000AU +#define C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH 0x0000000BU + +// +// Other macros that are needed for the Device_bootCPU2 function +// +#define BROM_IPC_EXECUTE_BOOTMODE_CMD 0x00000013U +#define C1C2_BROM_BOOTMODE_BOOT_COMMAND_MAX_SUPPORT_VALUE 0x0000000CU +#define C2_BOOTROM_BOOTSTS_C2TOC1_IGNORE 0x00000000U +#define C2_BOOTROM_BOOTSTS_SYSTEM_START_BOOT 0x00000001U +#define C2_BOOTROM_BOOTSTS_SYSTEM_READY 0x00000002U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_ACK 0x00000003U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_NOT_SUPPORTED 0x00000004U +#define C2_BOOTROM_BOOTSTS_C2TOC1_BOOT_CMD_NAK_STATUS_BUSY_WITH_BOOT 0x00000005U + +// +// Macros used as return value by the Device_bootCPU2 function +// +#define STATUS_FAIL 0x0001 +#define STATUS_PASS 0x0000 + +//***************************************************************************** +// +// Defines, Globals, and Header Includes related to Flash Support +// +//***************************************************************************** +#ifdef _FLASH +#include + +extern uint16_t RamfuncsLoadStart; +extern uint16_t RamfuncsLoadEnd; +extern uint16_t RamfuncsLoadSize; +extern uint16_t RamfuncsRunStart; +extern uint16_t RamfuncsRunEnd; +extern uint16_t RamfuncsRunSize; + +#define DEVICE_FLASH_WAITSTATES 3 + +#endif + +extern uint32_t Example_PassCount; +extern uint32_t Example_Fail; + +//***************************************************************************** +// +// Function Prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \addtogroup device_api +//! @{ +// +//***************************************************************************** +//***************************************************************************** +// +//! @brief Function to initialize the device. Primarily initializes system control to a +//! known state by disabling the watchdog, setting up the SYSCLKOUT frequency, +//! and enabling the clocks to the peripherals. +//! +//! \param None. +//! \return None. +// +//***************************************************************************** +extern void Device_init(void); +//***************************************************************************** +//! +//! +//! @brief Function to turn on all peripherals, enabling reads and writes to the +//! peripherals' registers. +//! +//! Note that to reduce power, unused peripherals should be disabled. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableAllPeripherals(void); +//***************************************************************************** +//! +//! +//! @brief Function to disable pin locks on GPIOs. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_initGPIO(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 176PTP package: +//! GPIOs Grp Bits +//! 95-132 C 31 +//! D 31:0 +//! E 4:0 +//! 134-168 E 31:6 +//! F 8:0 +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor176Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the 100PZ package: +//! GPIOs Grp Bits +//! 0-1 A 1:0 +//! 5-9 A 9:5 +//! 22-40 A 31:22 +//! B 8:0 +//! 44-57 B 25:12 +//! 67-68 C 4:3 +//! 74-77 C 13:10 +//! 79-83 C 19:15 +//! 93-168 C 31:29 +//! D 31:0 +//! E 31:0 +//! F 8:0 +//! @param None +//! @return None +// +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullupsFor100Pin(void); +//***************************************************************************** +//! +//! @brief Function to enable pullups for the unbonded GPIOs on the +//! 176PTP package. +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_enableUnbondedGPIOPullups(void); +#ifdef CPU1 +//***************************************************************************** +//! +//! @brief Function to implement Analog trim of TMX devices +//! +//! @param None +//! @return None +// +//***************************************************************************** +extern void Device_configureTMXAnalogTrim(void); +//***************************************************************************** +//! @brief Executes a CPU02 control system bootloader. +//! +//! \param bootMode specifies which CPU02 control system boot mode to execute. +//! +//! This function will allow the CPU01 master system to boot the CPU02 control +//! system via the following modes: Boot to RAM, Boot to Flash, Boot via SPI, +//! SCI, I2C, or parallel I/O. This function blocks and waits until the +//! control system boot ROM is configured and ready to receive CPU01 to CPU02 +//! IPC INT0 interrupts. It then blocks and waits until IPC INT0 and +//! IPC FLAG31 are available in the CPU02 boot ROM prior to sending the +//! command to execute the selected bootloader. +//! +//! The \e bootMode parameter accepts one of the following values: +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_PARALLEL +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SCI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_SPI +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_I2C +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_CAN +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_RAM +//! - \b C1C2_BROM_BOOTMODE_BOOT_FROM_FLASH +//! +//! \return 0 (success) if command is sent, or 1 (failure) if boot mode is +//! invalid and command was not sent. +// +//***************************************************************************** +extern uint16_t Device_bootCPU2(uint32_t ulBootMode); +#endif +//***************************************************************************** +//! +//! @brief Error handling function to be called when an ASSERT is violated +//! +//! @param *filename File name in which the error has occurred +//! @param line Line number within the file +//! @return None +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); +extern void Example_setResultPass(void); +extern void Example_setResultFail(void); +extern void Example_done(void); + +// +// End of file +// diff --git a/gpio_driverlib_cpu1/device/driverlib.h b/gpio_driverlib_cpu1/device/driverlib.h new file mode 100644 index 0000000..932ace6 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib.h @@ -0,0 +1,87 @@ +//############################################################################# +// +// FILE: driverlib.h +// +// TITLE: C28x Driverlib Header File +// +//############################################################################# +// +// $Release Date: $ +// $Copyright: +// Copyright (C) 2013-2026 Texas Instruments Incorporated - http://www.ti.com/ +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# +#ifndef DRIVERLIB_H +#define DRIVERLIB_H + +#include "inc/hw_memmap.h" + +#include "adc.h" +#include "asysctl.h" +#include "can.h" +#include "cla.h" +#include "clb.h" +#include "cmpss.h" +#include "cpu.h" +#include "cputimer.h" +#include "dac.h" +#include "dcsm.h" +#include "debug.h" +#include "dma.h" +#include "ecap.h" +#include "emif.h" +#include "epwm.h" +#include "eqep.h" +#include "flash.h" +#include "gpio.h" +#include "hrpwm.h" +#include "i2c.h" +#include "interrupt.h" +#include "ipc.h" +#include "mcbsp.h" +#include "memcfg.h" +#include "pin_map.h" +#include "pin_map_legacy.h" +#include "sci.h" +#include "sdfm.h" +#include "spi.h" +#include "sysctl.h" +#include "upp.h" +#include "version.h" +#include "xbar.h" + +#include "driver_inclusive_terminology_mapping.h" + +#endif // end of DRIVERLIB_H definition + +// +// End of file +// diff --git a/gpio_driverlib_cpu1/device/driverlib/adc.c b/gpio_driverlib_cpu1/device/driverlib/adc.c new file mode 100644 index 0000000..9e74809 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/adc.c @@ -0,0 +1,342 @@ +//########################################################################### +// +// FILE: adc.c +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "adc.h" + +//***************************************************************************** +// +// Defines for locations of ADC calibration functions in OTP for use in +// ADC_setMode() ONLY. Not intended for use by application code. +// +//***************************************************************************** +// +// The following functions calibrate the ADC linearity. Use them in the +// ADC_setMode() function only. +// +#define ADC_calADCAINL 0x0703B4U +#define ADC_calADCBINL 0x0703B2U +#define ADC_calADCCINL 0x0703B0U +#define ADC_calADCDINL 0x0703AEU + +// +// This function looks up the ADC offset trim for a given condition. Use this +// in the ADC_setMode() function only. +// +#define ADC_getOffsetTrim 0x0703ACU + +//***************************************************************************** +// +// ADC_setMode +// +//***************************************************************************** +void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Check for correct signal mode & resolution. In this device: + // Single ended signal conversions are supported in 12-bit mode only + // Differential signal conversions are supported in 16-bit mode only + // + if(signalMode == ADC_MODE_SINGLE_ENDED) + { + ASSERT(resolution == ADC_RESOLUTION_12BIT); + } + else + { + ASSERT(resolution == ADC_RESOLUTION_16BIT); + } + + + // + // Apply the resolution and signalMode to the specified ADC. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~(ADC_CTL2_RESOLUTION | ADC_CTL2_SIGNALMODE)) | + ((uint16_t)resolution | (uint16_t)signalMode); + EDIS; + + // + // Apply INL and offset trims + // + ADC_setINLTrim(base); + ADC_setOffsetTrim(base); +} + +//***************************************************************************** +// +// ADC_setINLTrim +// +//***************************************************************************** +void +ADC_setINLTrim(uint32_t base) +{ + ADC_Resolution resolution; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + + EALLOW; + switch(base) + { + case ADCA_BASE: + if(HWREGH(ADC_calADCAINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCAINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCB_BASE: + if(HWREGH(ADC_calADCBINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCBINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCC_BASE: + if(HWREGH(ADC_calADCCINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCCINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + case ADCD_BASE: + if(HWREGH(ADC_calADCDINL) != 0xFFFFU) + { + // + // Trim function is programmed into OTP, so call it + // + (*((void (*)(void))ADC_calADCDINL))(); + } + else + { + // + // Do nothing, no INL trim function populated + // + } + break; + default: + // + // Invalid base address! Do nothing! + // + break; + } + + // + // Apply linearity trim workaround for 12-bit resolution + // + if(resolution == ADC_RESOLUTION_12BIT) + { + // + // 12-bit linearity trim workaround + // + HWREG(base + ADC_O_INLTRIM1) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM2) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM4) &= 0xFFFF0000U; + HWREG(base + ADC_O_INLTRIM5) &= 0xFFFF0000U; + } + EDIS; +} + +//***************************************************************************** +// +// ADC_setOffsetTrim +// +//***************************************************************************** +void +ADC_setOffsetTrim(uint32_t base) +{ + uint16_t offsetIndex = 0U; + uint16_t offsetTrim = 0U; + ADC_Resolution resolution; + ADC_SignalMode signalMode; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + resolution = (ADC_Resolution) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_RESOLUTION); + signalMode = (ADC_SignalMode) + (HWREGH(base + ADC_O_CTL2) & ADC_CTL2_SIGNALMODE); + + switch(base) + { + case ADCA_BASE: + offsetIndex = (uint16_t)(0U * 4U); + break; + case ADCB_BASE: + offsetIndex = (uint16_t)(1U * 4U); + break; + case ADCC_BASE: + offsetIndex = (uint16_t)(2U * 4U); + break; + case ADCD_BASE: + offsetIndex = (uint16_t)(3U * 4U); + break; + default: + // + // Invalid base address! + // + offsetIndex = 0U; + break; + } + + // + // Offset trim function is programmed into OTP, so call it + // + if(HWREGH(ADC_getOffsetTrim) != 0xFFFFU) + { + // + // Calculate the index into OTP table of offset trims and call + // function to return the correct offset trim + // + offsetIndex += ((signalMode == ADC_MODE_DIFFERENTIAL) ? 1U : 0U) + + (2U * ((resolution == ADC_RESOLUTION_16BIT) ? 1U : 0U)); + + offsetTrim = + (*((uint16_t (*)(uint16_t index))ADC_getOffsetTrim))(offsetIndex); + } + else + { + // + // Offset trim function is not populated, so set offset trim to 0 + // + offsetTrim = 0U; + } + + // + // Apply the offset trim. Offset Trim is not updated here in case of TMX or + // untrimmed devices. The default trims for TMX devices should be handled in + // Device_init(). Refer to Device_init() and Device_configureTMXAnalogTrim() + // APIs for more details. + // + if(offsetTrim > 0x0U) + { + EALLOW; + HWREGH(base + ADC_O_OFFTRIM) = offsetTrim; + EDIS; + } +} + + +//***************************************************************************** +// +// ADC_setPPBTripLimits +// +//***************************************************************************** +void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit) +{ + uint32_t ppbHiOffset; + uint32_t ppbLoOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((tripHiLimit <= 65535) && (tripHiLimit >= -65536)); + ASSERT((tripLoLimit <= 65535) && (tripLoLimit >= -65536)); + + // + // Get the offset to the appropriate trip limit registers. + // + ppbHiOffset = (ADC_PPBxTRIPHI_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPHI; + ppbLoOffset = (ADC_PPBxTRIPLO_STEP * (uint32_t)ppbNumber) + + ADC_O_PPB1TRIPLO; + + EALLOW; + + // + // Set the trip high limit. + // + HWREG(base + ppbHiOffset) = + (HWREG(base + ppbHiOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripHiLimit & ADC_PPBTRIP_MASK); + + // + // Set the trip low limit. + // + HWREG(base + ppbLoOffset) = + (HWREG(base + ppbLoOffset) & ~ADC_PPBTRIP_MASK) | + ((uint32_t)tripLoLimit & ADC_PPBTRIP_MASK); + + EDIS; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/adc.h b/gpio_driverlib_cpu1/device/driverlib/adc.h new file mode 100644 index 0000000..136638d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/adc.h @@ -0,0 +1,2098 @@ +//########################################################################### +// +// FILE: adc.h +// +// TITLE: C28x ADC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ADC_H +#define ADC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup adc_api ADC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_adc.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define ADC_NUM_INTERRUPTS 4U + +#define ADC_SOCxCTL_OFFSET_BASE ADC_O_SOC0CTL +#define ADC_RESULTx_OFFSET_BASE ADC_O_RESULT0 +#define ADC_INTSELxNy_OFFSET_BASE ADC_O_INTSEL1N2 +#define ADC_PPBxRESULT_OFFSET_BASE ADC_O_PPB1RESULT + + +#define ADC_PPBxCONFIG_STEP (ADC_O_PPB2CONFIG - ADC_O_PPB1CONFIG) +#define ADC_PPBxTRIPHI_STEP (ADC_O_PPB2TRIPHI - ADC_O_PPB1TRIPHI) +#define ADC_PPBxTRIPLO_STEP (ADC_O_PPB2TRIPLO - ADC_O_PPB1TRIPLO) +#define ADC_PPBxOFFCAL_STEP (ADC_O_PPB2OFFCAL - ADC_O_PPB1OFFCAL) +#define ADC_PPBxOFFREF_STEP (ADC_O_PPB2OFFREF - ADC_O_PPB1OFFREF) +#define ADC_PPBxSTAMP_STEP (ADC_O_PPB2STAMP - ADC_O_PPB1STAMP) + +#define ADC_PPBTRIP_MASK ((uint32_t)ADC_PPB1TRIPHI_LIMITHI_M |\ + (uint32_t)ADC_PPB1TRIPHI_HSIGN) +// +// Slope of the temperature sensor based in degrees C in fixed point Q15 format +// +#define ADC_getTempSlope() (*(int16_t (*)(void))0x7036E)() + +// +// Offset of the temp sensor output at 0 degrees C +// +#define ADC_getTempOffset() (*(int16_t (*)(void))0x70372)() + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to ADC_enablePPBEvent(), ADC_disablePPBEvent(), +// ADC_enablePPBEventInterrupt(), ADC_disablePPBEventInterrupt(), and +// ADC_clearPPBEventStatus() as the intFlags and evtFlags parameters. They also +// make up the enumerated bit field returned by ADC_getPPBEventStatus(). +// +//***************************************************************************** +#define ADC_EVT_TRIPHI 0x0001U //!< Trip High Event +#define ADC_EVT_TRIPLO 0x0002U //!< Trip Low Event +#define ADC_EVT_ZERO 0x0004U //!< Zero Crossing Event +#endif + +//***************************************************************************** +// +// Values that can be passed to ADC_forceMultipleSOC() as socMask parameter. +// These values can be OR'd together to trigger multiple SOCs at a time. +// +//***************************************************************************** +#define ADC_FORCE_SOC0 0x0001U //!< SW trigger ADC SOC 0 +#define ADC_FORCE_SOC1 0x0002U //!< SW trigger ADC SOC 1 +#define ADC_FORCE_SOC2 0x0004U //!< SW trigger ADC SOC 2 +#define ADC_FORCE_SOC3 0x0008U //!< SW trigger ADC SOC 3 +#define ADC_FORCE_SOC4 0x0010U //!< SW trigger ADC SOC 4 +#define ADC_FORCE_SOC5 0x0020U //!< SW trigger ADC SOC 5 +#define ADC_FORCE_SOC6 0x0040U //!< SW trigger ADC SOC 6 +#define ADC_FORCE_SOC7 0x0080U //!< SW trigger ADC SOC 7 +#define ADC_FORCE_SOC8 0x0100U //!< SW trigger ADC SOC 8 +#define ADC_FORCE_SOC9 0x0200U //!< SW trigger ADC SOC 9 +#define ADC_FORCE_SOC10 0x0400U //!< SW trigger ADC SOC 10 +#define ADC_FORCE_SOC11 0x0800U //!< SW trigger ADC SOC 11 +#define ADC_FORCE_SOC12 0x1000U //!< SW trigger ADC SOC 12 +#define ADC_FORCE_SOC13 0x2000U //!< SW trigger ADC SOC 13 +#define ADC_FORCE_SOC14 0x4000U //!< SW trigger ADC SOC 14 +#define ADC_FORCE_SOC15 0x8000U //!< SW trigger ADC SOC 15 + + + +//***************************************************************************** +// +//! Values that can be passed to ADC_setPrescaler() as the \e clkPrescale +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_CLK_DIV_1_0 = 0U, //!< ADCCLK = (input clock) / 1.0 + ADC_CLK_DIV_2_0 = 2U, //!< ADCCLK = (input clock) / 2.0 + ADC_CLK_DIV_2_5 = 3U, //!< ADCCLK = (input clock) / 2.5 + ADC_CLK_DIV_3_0 = 4U, //!< ADCCLK = (input clock) / 3.0 + ADC_CLK_DIV_3_5 = 5U, //!< ADCCLK = (input clock) / 3.5 + ADC_CLK_DIV_4_0 = 6U, //!< ADCCLK = (input clock) / 4.0 + ADC_CLK_DIV_4_5 = 7U, //!< ADCCLK = (input clock) / 4.5 + ADC_CLK_DIV_5_0 = 8U, //!< ADCCLK = (input clock) / 5.0 + ADC_CLK_DIV_5_5 = 9U, //!< ADCCLK = (input clock) / 5.5 + ADC_CLK_DIV_6_0 = 10U, //!< ADCCLK = (input clock) / 6.0 + ADC_CLK_DIV_6_5 = 11U, //!< ADCCLK = (input clock) / 6.5 + ADC_CLK_DIV_7_0 = 12U, //!< ADCCLK = (input clock) / 7.0 + ADC_CLK_DIV_7_5 = 13U, //!< ADCCLK = (input clock) / 7.5 + ADC_CLK_DIV_8_0 = 14U, //!< ADCCLK = (input clock) / 8.0 + ADC_CLK_DIV_8_5 = 15U //!< ADCCLK = (input clock) / 8.5 +} ADC_ClkPrescale; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e resolution +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_RESOLUTION_12BIT = 0x00U, //!< 12-bit conversion resolution + ADC_RESOLUTION_16BIT = 0x40U //!< 16-bit conversion resolution +} ADC_Resolution; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setMode() as the \e signalMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_MODE_SINGLE_ENDED = 0x00U, //!< Sample on single pin with VREFLO + ADC_MODE_DIFFERENTIAL = 0x80U //!< Sample on pair of pins +} ADC_SignalMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e trigger +//! parameter to specify the event that will trigger a conversion to start. +//! It is also used with ADC_setBurstModeConfig() and +//! ADC_triggerRepeaterSelect(). +// +//***************************************************************************** +typedef enum +{ + ADC_TRIGGER_SW_ONLY = 0U, //!< Software only + ADC_TRIGGER_CPU1_TINT0 = 1U, //!< CPU1 Timer 0, TINT0 + ADC_TRIGGER_CPU1_TINT1 = 2U, //!< CPU1 Timer 1, TINT1 + ADC_TRIGGER_CPU1_TINT2 = 3U, //!< CPU1 Timer 2, TINT2 + ADC_TRIGGER_GPIO = 4U, //!< GPIO, ADCEXTSOC + ADC_TRIGGER_EPWM1_SOCA = 5U, //!< ePWM1, ADCSOCA + ADC_TRIGGER_EPWM1_SOCB = 6U, //!< ePWM1, ADCSOCB + ADC_TRIGGER_EPWM2_SOCA = 7U, //!< ePWM2, ADCSOCA + ADC_TRIGGER_EPWM2_SOCB = 8U, //!< ePWM2, ADCSOCB + ADC_TRIGGER_EPWM3_SOCA = 9U, //!< ePWM3, ADCSOCA + ADC_TRIGGER_EPWM3_SOCB = 10U, //!< ePWM3, ADCSOCB + ADC_TRIGGER_EPWM4_SOCA = 11U, //!< ePWM4, ADCSOCA + ADC_TRIGGER_EPWM4_SOCB = 12U, //!< ePWM4, ADCSOCB + ADC_TRIGGER_EPWM5_SOCA = 13U, //!< ePWM5, ADCSOCA + ADC_TRIGGER_EPWM5_SOCB = 14U, //!< ePWM5, ADCSOCB + ADC_TRIGGER_EPWM6_SOCA = 15U, //!< ePWM6, ADCSOCA + ADC_TRIGGER_EPWM6_SOCB = 16U, //!< ePWM6, ADCSOCB + ADC_TRIGGER_EPWM7_SOCA = 17U, //!< ePWM7, ADCSOCA + ADC_TRIGGER_EPWM7_SOCB = 18U, //!< ePWM7, ADCSOCB + ADC_TRIGGER_EPWM8_SOCA = 19U, //!< ePWM8, ADCSOCA + ADC_TRIGGER_EPWM8_SOCB = 20U, //!< ePWM8, ADCSOCB + ADC_TRIGGER_EPWM9_SOCA = 21U, //!< ePWM9, ADCSOCA + ADC_TRIGGER_EPWM9_SOCB = 22U, //!< ePWM9, ADCSOCB + ADC_TRIGGER_EPWM10_SOCA = 23U, //!< ePWM10, ADCSOCA + ADC_TRIGGER_EPWM10_SOCB = 24U, //!< ePWM10, ADCSOCB + ADC_TRIGGER_EPWM11_SOCA = 25U, //!< ePWM11, ADCSOCA + ADC_TRIGGER_EPWM11_SOCB = 26U, //!< ePWM11, ADCSOCB + ADC_TRIGGER_EPWM12_SOCA = 27U, //!< ePWM12, ADCSOCA + ADC_TRIGGER_EPWM12_SOCB = 28U, //!< ePWM12, ADCSOCB + ADC_TRIGGER_CPU2_TINT0 = 29U, //!< CPU2 Timer 0, TINT0 + ADC_TRIGGER_CPU2_TINT1 = 30U, //!< CPU2 Timer 1, TINT1 + ADC_TRIGGER_CPU2_TINT2 = 31U //!< CPU2 Timer 2, TINT2 +} ADC_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setupSOC() as the \e channel +//! parameter. This is the input pin on which the signal to be converted is +//! located. +// +//***************************************************************************** +typedef enum +{ + ADC_CH_ADCIN0 = 0U, //!< single-ended, ADCIN0 + ADC_CH_ADCIN1 = 1U, //!< single-ended, ADCIN1 + ADC_CH_ADCIN2 = 2U, //!< single-ended, ADCIN2 + ADC_CH_ADCIN3 = 3U, //!< single-ended, ADCIN3 + ADC_CH_ADCIN4 = 4U, //!< single-ended, ADCIN4 + ADC_CH_ADCIN5 = 5U, //!< single-ended, ADCIN5 + ADC_CH_ADCIN6 = 6U, //!< single-ended, ADCIN6 + ADC_CH_ADCIN7 = 7U, //!< single-ended, ADCIN7 + ADC_CH_ADCIN8 = 8U, //!< single-ended, ADCIN8 + ADC_CH_ADCIN9 = 9U, //!< single-ended, ADCIN9 + ADC_CH_ADCIN10 = 10U, //!< single-ended, ADCIN10 + ADC_CH_ADCIN11 = 11U, //!< single-ended, ADCIN11 + ADC_CH_ADCIN12 = 12U, //!< single-ended, ADCIN12 + ADC_CH_ADCIN13 = 13U, //!< single-ended, ADCIN13 + ADC_CH_ADCIN14 = 14U, //!< single-ended, ADCIN14 + ADC_CH_ADCIN15 = 15U, //!< single-ended, ADCIN15 + ADC_CH_ADCIN0_ADCIN1 = 0U, //!< differential, ADCIN0 and ADCIN1 + ADC_CH_ADCIN2_ADCIN3 = 2U, //!< differential, ADCIN2 and ADCIN3 + ADC_CH_ADCIN4_ADCIN5 = 4U, //!< differential, ADCIN4 and ADCIN5 + ADC_CH_ADCIN6_ADCIN7 = 6U, //!< differential, ADCIN6 and ADCIN7 + ADC_CH_ADCIN8_ADCIN9 = 8U, //!< differential, ADCIN8 and ADCIN9 + ADC_CH_ADCIN10_ADCIN11 = 10U, //!< differential, ADCIN10 and ADCIN11 + ADC_CH_ADCIN12_ADCIN13 = 12U, //!< differential, ADCIN12 and ADCIN13 + ADC_CH_ADCIN14_ADCIN15 = 14U //!< differential, ADCIN14 and ADCIN15 +} ADC_Channel; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setInterruptPulseMode() as the +//! \e pulseMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Occurs at the end of the acquisition window + ADC_PULSE_END_OF_ACQ_WIN = 0x00U, + //! Occurs at the end of the conversion + ADC_PULSE_END_OF_CONV = 0x04U +} ADC_PulseMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_enableInterrupt(), ADC_disableInterrupt(), +//! and ADC_getInterruptStatus() as the \e adcIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_NUMBER1 = 0U, //!< ADCINT1 Interrupt + ADC_INT_NUMBER2 = 1U, //!< ADCINT2 Interrupt + ADC_INT_NUMBER3 = 2U, //!< ADCINT3 Interrupt + ADC_INT_NUMBER4 = 3U //!< ADCINT4 Interrupt +} ADC_IntNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e ppbNumber parameter for several +//! functions. +// +//***************************************************************************** +typedef enum +{ + ADC_PPB_NUMBER1 = 0U, //!< Post-processing block 1 + ADC_PPB_NUMBER2 = 1U, //!< Post-processing block 2 + ADC_PPB_NUMBER3 = 2U, //!< Post-processing block 3 + ADC_PPB_NUMBER4 = 3U //!< Post-processing block 4 +} ADC_PPBNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e socNumber parameter for several +//! functions. This value identifies the start-of-conversion (SOC) that a +//! function is configuring or accessing. Note that in some cases (for example, +//! ADC_setInterruptSource()) \e socNumber is used to refer to the +//! corresponding end-of-conversion (EOC). +// +//***************************************************************************** +typedef enum +{ + ADC_SOC_NUMBER0 = 0U, //!< SOC/EOC number 0 + ADC_SOC_NUMBER1 = 1U, //!< SOC/EOC number 1 + ADC_SOC_NUMBER2 = 2U, //!< SOC/EOC number 2 + ADC_SOC_NUMBER3 = 3U, //!< SOC/EOC number 3 + ADC_SOC_NUMBER4 = 4U, //!< SOC/EOC number 4 + ADC_SOC_NUMBER5 = 5U, //!< SOC/EOC number 5 + ADC_SOC_NUMBER6 = 6U, //!< SOC/EOC number 6 + ADC_SOC_NUMBER7 = 7U, //!< SOC/EOC number 7 + ADC_SOC_NUMBER8 = 8U, //!< SOC/EOC number 8 + ADC_SOC_NUMBER9 = 9U, //!< SOC/EOC number 9 + ADC_SOC_NUMBER10 = 10U, //!< SOC/EOC number 10 + ADC_SOC_NUMBER11 = 11U, //!< SOC/EOC number 11 + ADC_SOC_NUMBER12 = 12U, //!< SOC/EOC number 12 + ADC_SOC_NUMBER13 = 13U, //!< SOC/EOC number 13 + ADC_SOC_NUMBER14 = 14U, //!< SOC/EOC number 14 + ADC_SOC_NUMBER15 = 15U //!< SOC/EOC number 15 +} ADC_SOCNumber; + +//***************************************************************************** +// +//! Values that can be passed in as the \e trigger parameter for the +//! ADC_setInterruptSOCTrigger() function. +// +//***************************************************************************** +typedef enum +{ + ADC_INT_SOC_TRIGGER_NONE = 0U, //!< No ADCINT will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT1 = 1U, //!< ADCINT1 will trigger the SOC + ADC_INT_SOC_TRIGGER_ADCINT2 = 2U //!< ADCINT2 will trigger the SOC +} ADC_IntSOCTrigger; + +//***************************************************************************** +// +//! Values that can be passed to ADC_setSOCPriority() as the \e priMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_PRI_ALL_ROUND_ROBIN = 0U, //!< Round robin mode is used for all + ADC_PRI_SOC0_HIPRI = 1U, //!< SOC 0 hi pri, others in round robin + ADC_PRI_THRU_SOC1_HIPRI = 2U, //!< SOC 0-1 hi pri, others in round robin + ADC_PRI_THRU_SOC2_HIPRI = 3U, //!< SOC 0-2 hi pri, others in round robin + ADC_PRI_THRU_SOC3_HIPRI = 4U, //!< SOC 0-3 hi pri, others in round robin + ADC_PRI_THRU_SOC4_HIPRI = 5U, //!< SOC 0-4 hi pri, others in round robin + ADC_PRI_THRU_SOC5_HIPRI = 6U, //!< SOC 0-5 hi pri, others in round robin + ADC_PRI_THRU_SOC6_HIPRI = 7U, //!< SOC 0-6 hi pri, others in round robin + ADC_PRI_THRU_SOC7_HIPRI = 8U, //!< SOC 0-7 hi pri, others in round robin + ADC_PRI_THRU_SOC8_HIPRI = 9U, //!< SOC 0-8 hi pri, others in round robin + ADC_PRI_THRU_SOC9_HIPRI = 10U, //!< SOC 0-9 hi pri, others in round robin + ADC_PRI_THRU_SOC10_HIPRI = 11U, //!< SOC 0-10 hi pri, others in round robin + ADC_PRI_THRU_SOC11_HIPRI = 12U, //!< SOC 0-11 hi pri, others in round robin + ADC_PRI_THRU_SOC12_HIPRI = 13U, //!< SOC 0-12 hi pri, others in round robin + ADC_PRI_THRU_SOC13_HIPRI = 14U, //!< SOC 0-13 hi pri, others in round robin + ADC_PRI_THRU_SOC14_HIPRI = 15U, //!< SOC 0-14 hi pri, SOC15 in round robin + ADC_PRI_ALL_HIPRI = 16U //!< All priorities based on SOC number +} ADC_PriorityMode; + +//***************************************************************************** +// +//! Values that can be passed to ADC_configOSDetectMode() as the \e modeVal +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ADC_OSDETECT_MODE_DISABLED = 0x0U,//!< Open/Shorts detection cir- + //!< cuit(O/S DC) is disabled + ADC_OSDETECT_MODE_VSSA = 0x1U,//!< O/S DC is enabled at zero + //!< scale + ADC_OSDETECT_MODE_VDDA = 0x2U,//!< O/S DC is enabled at full + //!< scale + ADC_OSDETECT_MODE_5BY12_VDDA = 0x3U,//!< O/S DC is enabled at 5/12 + //!< scale + ADC_OSDETECT_MODE_7BY12_VDDA = 0x4U,//!< O/S DC is enabled at 7/12 + //!< scale + ADC_OSDETECT_MODE_5K_PULLDOWN_TO_VSSA = 0x5U,//!< O/S DC is enabled at 5K + //!< pulldown to VSSA + ADC_OSDETECT_MODE_5K_PULLUP_TO_VDDA = 0x6U,//!< O/S DC is enabled at 5K + //!< pullup to VDDA + ADC_OSDETECT_MODE_7K_PULLDOWN_TO_VSSA = 0x7U //!< O/S DC is enabled at 7K + //!< pulldown to VSSA +} ADC_OSDetectMode; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an ADC base address. +//! +//! \param base specifies the ADC module base address. +//! +//! This function determines if a ADC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +ADC_isBaseValid(uint32_t base) +{ + return( + (base == ADCA_BASE) || + (base == ADCB_BASE) || + (base == ADCC_BASE) || + (base == ADCD_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Configures the analog-to-digital converter module prescaler. +//! +//! \param base is the base address of the ADC module. +//! \param clkPrescale is the ADC clock prescaler. +//! +//! This function configures the ADC module's ADCCLK. +//! +//! The \e clkPrescale parameter specifies the value by which the input clock +//! is divided to make the ADCCLK. The clkPrescale value can be specified with +//! any of the following enum values: +//! \b ADC_CLK_DIV_1_0, \b ADC_CLK_DIV_2_0, \b ADC_CLK_DIV_2_5, ..., +//! \b ADC_CLK_DIV_7_5, \b ADC_CLK_DIV_8_0, or \b ADC_CLK_DIV_8_5. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setPrescaler(uint32_t base, ADC_ClkPrescale clkPrescale) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the configuration of the ADC module prescaler. + // + EALLOW; + HWREGH(base + ADC_O_CTL2) = (HWREGH(base + ADC_O_CTL2) & + ~ADC_CTL2_PRESCALE_M) | (uint16_t)clkPrescale; + EDIS; +} + +//***************************************************************************** +// +//! Configures a start-of-conversion (SOC) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the source that will cause the SOC. +//! \param channel is the number associated with the input signal. +//! \param sampleWindow is the acquisition window duration. +//! +//! This function configures the a start-of-conversion (SOC) in the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the event that causes the SOC such as software, a +//! timer interrupt, an ePWM event, or an ADC interrupt. It should be a value +//! in the format of \b ADC_TRIGGER_XXXX where XXXX is the event such as +//! \b ADC_TRIGGER_SW_ONLY, \b ADC_TRIGGER_CPU1_TINT0, \b ADC_TRIGGER_GPIO, +//! \b ADC_TRIGGER_EPWM1_SOCA, and so on. +//! +//! The \e channel parameter specifies the channel to be converted. In +//! single-ended mode this is a single pin given by \b ADC_CH_ADCINx where x is +//! the number identifying the pin between 0 and 15 inclusive. In differential +//! mode, two pins are used as inputs and are passed in the \e channel +//! parameter as \b ADC_CH_ADCIN0_ADCIN1, \b ADC_CH_ADCIN2_ADCIN3, ..., or +//! \b ADC_CH_ADCIN14_ADCIN15. +//! +//! The \e sampleWindow parameter is the acquisition window duration in SYSCLK +//! cycles. It should be a value between 1 and 512 cycles inclusive. The +//! selected duration must be at least as long as one ADCCLK cycle. Also, the +//! datasheet will specify a minimum window duration requirement in +//! nanoseconds. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupSOC(uint32_t base, ADC_SOCNumber socNumber, ADC_Trigger trigger, + ADC_Channel channel, uint32_t sampleWindow) +{ + uint32_t ctlRegAddr, mask; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((sampleWindow >= 1U) && (sampleWindow <= 512U)); + + mask = (ADC_SOC0CTL_CHSEL_M | ADC_SOC0CTL_TRIGSEL_M | ADC_SOC0CTL_ACQPS_M); + + // + // Calculate address for the SOC control register. + // + ctlRegAddr = base + ADC_SOCxCTL_OFFSET_BASE + ((uint32_t)socNumber * 2U); + + // + // Set the configuration of the specified SOC. + // + EALLOW; + + HWREG(ctlRegAddr) = (HWREG(ctlRegAddr) & ~(mask)) | + ((uint32_t)channel << ADC_SOC0CTL_CHSEL_S) | + ((uint32_t)trigger << ADC_SOC0CTL_TRIGSEL_S) | + (sampleWindow - 1U); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the interrupt SOC trigger of an SOC. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! \param trigger the interrupt source that will cause the SOC. +//! +//! This function configures the interrupt start-of-conversion trigger in +//! the ADC module. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC is to be configured on the ADC module +//! specified by \e base. +//! +//! The \e trigger specifies the interrupt that causes a start of conversion or +//! none. It should be one of the following values. +//! +//! - \b ADC_INT_SOC_TRIGGER_NONE +//! - \b ADC_INT_SOC_TRIGGER_ADCINT1 +//! - \b ADC_INT_SOC_TRIGGER_ADCINT2 +//! +//! This functionality is useful for creating continuous conversions. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSOCTrigger(uint32_t base, ADC_SOCNumber socNumber, + ADC_IntSOCTrigger trigger) +{ + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each SOC has a 2-bit field in this register. + // + shiftVal = (uint16_t)socNumber << 1U; + + // + // Set the configuration of the specified SOC. Not that we're treating + // ADCINTSOCSEL1 and ADCINTSOCSEL2 as one 32-bit register here. + // + EALLOW; + HWREG(base + ADC_O_INTSOCSEL1) = (HWREG(base + ADC_O_INTSOCSEL1) & + ~((uint32_t)ADC_INTSOCSEL1_SOC0_M << + shiftVal)) | + ((uint32_t)trigger << shiftVal); + EDIS; +} + +//***************************************************************************** +// +//! Sets the timing of the end-of-conversion pulse +//! +//! \param base is the base address of the ADC module. +//! \param pulseMode is the generation mode of the EOC pulse. +//! +//! This function configures the end-of-conversion (EOC) pulse generated by ADC. +//! This pulse will be generated either at the end of the acquisition window +//!(pass \b ADC_PULSE_END_OF_ACQ_WIN into \e pulseMode) or at the end of the +//! voltage conversion, one cycle prior to the ADC result latching into it's +//! result register (pass \b ADC_PULSE_END_OF_CONV into \e pulseMode). +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptPulseMode(uint32_t base, ADC_PulseMode pulseMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the position of the pulse. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) = (HWREGH(base + ADC_O_CTL1) & + ~ADC_CTL1_INTPULSEPOS) | (uint16_t)pulseMode; + EDIS; +} + + + + +//***************************************************************************** +// +//! Powers up the analog-to-digital converter core. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers up the analog circuitry inside the analog core. +//! +//! \note Allow at least a 500us delay before sampling after calling this API. +//! If you enable multiple ADCs, you can delay after they all have begun +//! powering up. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Set the bit that powers up the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) |= ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Powers down the analog-to-digital converter module. +//! +//! \param base is the base address of the ADC module. +//! +//! This function powers down the analog circuitry inside the analog core. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableConverter(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the bit that powers down the analog circuitry. + // + EALLOW; + HWREGH(base + ADC_O_CTL1) &= ~ADC_CTL1_ADCPWDNZ; + EDIS; +} + +//***************************************************************************** +// +//! Forces a SOC flag to a 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function forces the SOC flag associated with the SOC specified by +//! \e socNumber. This initiates a conversion once that SOC is given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceSOC(uint32_t base, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to the corresponding SOC flag + // + HWREGH(base + ADC_O_SOCFRC1) = ((uint16_t)1U << (uint16_t)socNumber); +} + +//***************************************************************************** +// +//! Forces multiple SOC flags to 1 in the analog-to-digital converter. +//! +//! \param base is the base address of the ADC module. +//! \param socMask is the SOCs to be forced through software +//! +//! This function forces the SOCFRC1 flags associated with the SOCs specified +//! by \e socMask. This initiates a conversion once the desired SOCs are given +//! priority. This software trigger can be used whether or not the SOC has been +//! configured to accept some other specific trigger. +//! Valid values for \e socMask parameter can be any of the individual +//! ADC_FORCE_SOCx values or any of their OR'd combination to trigger multiple +//! SOCs. +//! +//! \note To trigger SOC0, SOC1 and SOC2, value (ADC_FORCE_SOC0 | +//! ADC_FORCE_SOC1 | ADC_FORCE_SOC2) should be passed as socMask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_forceMultipleSOC(uint32_t base, uint16_t socMask) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Write to the register that will force a 1 to desired SOCs + // + HWREGH(base + ADC_O_SOCFRC1) = socMask; +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt status for the analog-to-digital +//! converter. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt status for the given interrupt number of the ADC module. +//! +//! \return \b true if the interrupt flag for the specified interrupt number is +//! set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTFLG) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt sources so that they no +//! longer assert. If not in continuous mode, this function must be called +//! before any further interrupt pulses may occur. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt. + // + HWREGH(base + ADC_O_INTFLGCLR) = (uint16_t)1U << (uint16_t)adcIntNum; + +} + +//***************************************************************************** +// +//! Gets the current ADC interrupt overflow status. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function returns the interrupt overflow status for the +//! analog-to-digital converter. An overflow condition is generated +//! irrespective of the continuous mode. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to get +//! the interrupt overflow status for the given interrupt number. +//! +//! \return \b true if the interrupt overflow flag for the specified interrupt +//! number is set and \b false if it is not. +// +//***************************************************************************** +static inline bool +ADC_getInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the specified ADC interrupt status. + // + return((HWREGH(base + ADC_O_INTOVF) & (1U << (uint16_t)adcIntNum)) != 0U); +} + +//***************************************************************************** +// +//! Clears ADC interrupt overflow sources. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function clears the specified ADC interrupt overflow sources so that +//! they no longer assert. If software tries to clear the overflow in the same +//! cycle that hardware tries to set the overflow, then hardware has priority. +//! +//! \e adcIntNum takes a one of the values \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupt overflow status of the ADC module +//! should be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearInterruptOverflowStatus(uint32_t base, ADC_IntNumber adcIntNum) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Clear the specified interrupt overflow bit. + // + HWREGH(base + ADC_O_INTOVFCLR) = (uint16_t)1U << (uint16_t)adcIntNum; +} + +//***************************************************************************** +// +//! Reads the conversion result. +//! +//! \param resultBase is the base address of the ADC results. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function returns the conversion result that corresponds to the base +//! address passed into \e resultBase and the SOC passed into \e socNumber. +//! +//! The \e socNumber number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which SOC's result is to be read. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the conversion result. +// +//***************************************************************************** +static inline uint16_t +ADC_readResult(uint32_t resultBase, ADC_SOCNumber socNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the ADC result for the selected SOC. + // + return(HWREGH(resultBase + (uint32_t)ADC_RESULTx_OFFSET_BASE + + (uint32_t)socNumber)); +} + +//***************************************************************************** +// +//! Determines whether the ADC is busy or not. +//! +//! \param base is the base address of the ADC. +//! +//! This function allows the caller to determine whether or not the ADC is +//! busy and can sample another channel. +//! +//! \return Returns \b true if the ADC is sampling or \b false if all +//! samples are complete. +// +//***************************************************************************** +static inline bool +ADC_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Determine if the ADC is busy. + // + return((HWREGH(base + ADC_O_CTL1) & ADC_CTL1_ADCBSY) != 0U); +} + +//***************************************************************************** +// +//! Set SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! \param trigger the source that will cause the burst conversion sequence. +//! \param burstSize is the number of SOCs converted during a burst sequence. +//! +//! This function configures the burst trigger and burstSize of an ADC module. +//! Burst mode allows a single trigger to walk through the round-robin SOCs one +//! or more at a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Instead, the source specified through the \e trigger parameter will +//! cause a burst of \e burstSize conversions to occur. +//! +//! The \e trigger parameter takes the same values as the ADC_setupSOC() API +//! The \e burstSize parameter should be a value between 1 and 16 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setBurstModeConfig(uint32_t base, ADC_Trigger trigger, uint16_t burstSize) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(((uint16_t)trigger & ~((uint16_t)0x1FU)) == 0U); + ASSERT((burstSize >= 1U) && (burstSize <= 16U)); + + // + // Write the burst mode configuration to the register. + // + EALLOW; + + regValue = (uint16_t)trigger | ((burstSize - 1U) << + ADC_BURSTCTL_BURSTSIZE_S); + + HWREGH(base + ADC_O_BURSTCTL) = (HWREGH(base + ADC_O_BURSTCTL) & + ~((uint16_t)ADC_BURSTCTL_BURSTTRIGSEL_M | + ADC_BURSTCTL_BURSTSIZE_M)) | regValue; + + EDIS; +} + +//***************************************************************************** +// +//! Enables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function enables SOC burst mode operation of the ADC. Burst mode +//! allows a single trigger to walk through the round-robin SOCs one or more at +//! a time. When burst mode is enabled, the trigger selected by the +//! ADC_setupSOC() API will no longer have an effect on the SOCs in round-robin +//! mode. Use ADC_setBurstMode() to configure the burst trigger and size. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Enable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) |= ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables SOC burst mode. +//! +//! \param base is the base address of the ADC. +//! +//! This function disables SOC burst mode operation of the ADC. SOCs in +//! round-robin mode will be triggered by the trigger configured using the +//! ADC_setupSOC() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableBurstMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Disable burst mode. + // + EALLOW; + HWREGH(base + ADC_O_BURSTCTL) &= ~ADC_BURSTCTL_BURSTEN; + EDIS; +} + +//***************************************************************************** +// +//! Sets the priority mode of the SOCs. +//! +//! \param base is the base address of the ADC. +//! \param priMode is the priority mode of the SOCs. +//! +//! This function sets the priority mode of the SOCs. There are three main +//! modes that can be passed in the \e priMode parameter +//! +//! - All SOCs are in round-robin mode. This means no SOC has an inherent +//! higher priority over another. This is selected by passing in the value +//! \b ADC_PRI_ALL_ROUND_ROBIN. +//! - All priorities are in high priority mode. This means that the priority of +//! the SOC is determined by its SOC number. This option is selected by passing +//! in the value \b ADC_PRI_ALL_HIPRI. +//! - A range of SOCs are assigned high priority, with all others in round +//! robin mode. High priority mode means that an SOC with high priority will +//! interrupt the round robin wheel and insert itself as the next conversion. +//! Passing in the value \b ADC_PRI_SOC0_HIPRI will make SOC0 highest priority, +//! \b ADC_PRI_THRU_SOC1_HIPRI will put SOC0 and SOC 1 in high priority, and so +//! on up to \b ADC_PRI_THRU_SOC14_HIPRI where SOCs 0 through 14 are in high +//! priority. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setSOCPriority(uint32_t base, ADC_PriorityMode priMode) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + EALLOW; + + HWREGH(base + ADC_O_SOCPRICTL) = (HWREGH(base + ADC_O_SOCPRICTL) & + ~ADC_SOCPRICTL_SOCPRIORITY_M) | + (uint16_t)priMode; + + EDIS; +} + +//***************************************************************************** +// +//! Configures Open/Shorts Detection Circuit Mode. +//! +//! \param base is the base address of the ADC. +//! \param modeVal is the desired open/shorts detection circuit mode. +//! +//! This function configures the open/shorts detection circuit mode of the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_configOSDetectMode(uint32_t base, ADC_OSDetectMode modeVal) +{ + // + // Configure open/shorts detection circuit mode. + // + EALLOW; + HWREGH(base + ADC_O_OSDETECT) = ((HWREGH(base + ADC_O_OSDETECT) & + (~ADC_OSDETECT_DETECTCFG_M)) | + (uint16_t)modeVal); + EDIS; +} + +//***************************************************************************** +// +//! Configures a post-processing block (PPB) in the ADC. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function associates a post-processing block with a SOC. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. The \e socNumber +//! number is a value \b ADC_SOC_NUMBERX where X is a number from 0 to 15 +//! specifying which SOC is to be configured on the ADC module specified by +//! \e base. +//! +//! \note You can have more that one PPB associated with the same SOC, but a +//! PPB can only be configured to correspond to one SOC at a time. Also note +//! that when you have multiple PPBs for the same SOC, the calibration offset +//! that actually gets applied will be that of the PPB with the highest number. +//! Since SOC0 is the default for all PPBs, look out for unintentional +//! overwriting of a lower numbered PPB's offset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setupPPB(uint32_t base, ADC_PPBNumber ppbNumber, ADC_SOCNumber socNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Write the configuration to the register. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1CONFIG_CONFIG_M) | + ((uint16_t)socNumber & ADC_PPB1CONFIG_CONFIG_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function enables the indicated ADC PPB event sources. This will allow +//! the specified events to propagate through the X-BAR to a pin or to an ePWM +//! module. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Enable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) |= evtFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event sources to be enabled. +//! +//! This function disables the indicated ADC PPB event sources. This will stop +//! the specified events from propagating through the X-BAR to other modules. +//! The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEvent(uint32_t base, ADC_PPBNumber ppbNumber, uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Disable the specified event. + // + EALLOW; + HWREGH(base + ADC_O_EVTSEL) &= ~(evtFlags << ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Enable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) |= intFlags << ((uint16_t)ppbNumber * 4U); + EDIS; +} + +//***************************************************************************** +// +//! Disables individual ADC PPB event interrupt sources. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param intFlags is a bit mask of the interrupt source to be disabled. +//! +//! This function disables the indicated ADC PPB interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. The \e intFlags +//! parameter can be any of the \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, +//! or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disablePPBEventInterrupt(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((intFlags & ~0x7U) == 0U); + + // + // Disable the specified event interrupts. + // + EALLOW; + HWREGH(base + ADC_O_EVTINTSEL) &= ~(intFlags << + ((uint16_t)ppbNumber * 4U)); + EDIS; +} + +//***************************************************************************** +// +//! Gets the current ADC event status. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the event status for the analog-to-digital converter. +//! +//! \return Returns the current event status, enumerated as a bit field of +//! \b ADC_EVT_TRIPHI, \b ADC_EVT_TRIPLO, and \b ADC_EVT_ZERO. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the event status for the specified post-processing block. + // + return((HWREGH(base + ADC_O_EVTSTAT) >> ((uint16_t)ppbNumber * 4U)) & + 0x7U); +} + +//***************************************************************************** +// +//! Clears ADC event flags. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param evtFlags is a bit mask of the event source to be cleared. +//! +//! This function clears the indicated ADC PPB event flags. After an event +//! occurs this function must be called to allow additional events to be +//! produced. The \e evtFlags parameter can be any of the \b ADC_EVT_TRIPHI, +//! \b ADC_EVT_TRIPLO, or \b ADC_EVT_ZERO values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_clearPPBEventStatus(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t evtFlags) +{ + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT((evtFlags & ~0x7U) == 0U); + + // + // Clear the specified event interrupts. + // + HWREGH(base + ADC_O_EVTCLR) |= evtFlags << ((uint16_t)ppbNumber * 4U); +} + + +//***************************************************************************** +// +//! Reads the processed conversion result from the PPB. +//! +//! \param resultBase is the base address of the ADC results. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the processed conversion result that corresponds to +//! the base address passed into \e resultBase and the PPB passed into +//! \e ppbNumber. +//! +//! \note Take care that you are using a base address for the result registers +//! (ADCxRESULT_BASE) and not a base address for the control registers. +//! +//! \return Returns the signed 32-bit conversion result. +// +//***************************************************************************** +static inline int32_t +ADC_readPPBResult(uint32_t resultBase, ADC_PPBNumber ppbNumber) +{ + // + // Check the arguments. + // + ASSERT( + (resultBase == ADCARESULT_BASE) || + (resultBase == ADCBRESULT_BASE) || + (resultBase == ADCCRESULT_BASE) || + (resultBase == ADCDRESULT_BASE) + ); + // + // Return the result of selected PPB. + // + return((int32_t)HWREG(resultBase + (uint32_t)ADC_PPBxRESULT_OFFSET_BASE + + ((uint32_t)ppbNumber * 2UL))); +} + +//***************************************************************************** +// +//! Reads sample delay time stamp from a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function returns the sample delay time stamp. This delay is the number +//! of system clock cycles between the SOC being triggered and when it began +//! converting. +//! +//! \return Returns the delay time stamp. +// +//***************************************************************************** +static inline uint16_t +ADC_getPPBDelayTimeStamp(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate delay. + // + ppbOffset = (ADC_PPBxSTAMP_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1STAMP; + + // + // Return the delay time stamp. + // + return(HWREGH(base + ppbOffset) & ADC_PPB2STAMP_DLYSTAMP_M); +} + +//***************************************************************************** +// +//! Sets the post processing block offset correction. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 10-bit signed value subtracted from ADC the output. +//! +//! This function sets the PPB offset correction value. This value can be used +//! to digitally remove any system-level offset inherent in the ADCIN circuit +//! before it is stored in the appropriate result register. The \e offset +//! parameter is \b subtracted from the ADC output and is a signed value from +//! -512 to 511 inclusive. For example, when \e offset = 1, ADCRESULT = ADC +//! output - 1. When \e offset = -512, ADCRESULT = ADC output - (-512) or ADC +//! output + 512. +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation, allowing the raw ADC result to be passed unchanged into the +//! result register. +//! +//! \note If multiple PPBs are applied to the same SOC, the offset that will be +//! applied will be that of the PPB with the highest number. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBCalibrationOffset(uint32_t base, ADC_PPBNumber ppbNumber, + int16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFCAL_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFCAL; + + // + // Write the offset amount. + // + EALLOW; + HWREGH(base + ppbOffset) = (HWREGH(base + ppbOffset) & + ~ADC_PPB1OFFCAL_OFFCAL_M) | + ((uint16_t)offset & ADC_PPB1OFFCAL_OFFCAL_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the post processing block reference offset. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param offset is the 16-bit unsigned value subtracted from ADC the output. +//! +//! This function sets the PPB reference offset value. This can be used to +//! either calculate the feedback error or convert a unipolar signal to bipolar +//! by subtracting a reference value. The result will be stored in the +//! appropriate PPB result register which can be read using ADC_readPPBResult(). +//! +//! Passing a zero in to the \e offset parameter will effectively disable the +//! calculation and will pass the ADC result to the PPB result register +//! unchanged. +//! +//! \note If in 12-bit mode, you may only pass a 12-bit value into the \e offset +//! parameter. +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_setPPBReferenceOffset(uint32_t base, ADC_PPBNumber ppbNumber, + uint16_t offset) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate offset register. + // + ppbOffset = (ADC_PPBxOFFREF_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1OFFREF; + + // + // Write the offset amount. + // + HWREGH(base + ppbOffset) = offset; +} + +//***************************************************************************** +// +//! Enables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function enables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When enabled, a two's complement +//! will be performed on the output of the offset subtraction before it is +//! stored in the appropriate PPB result register. In other words, the PPB +//! result will be the reference offset value minus the the ADC result value +//! (ADCPPBxRESULT = ADCSOCxOFFREF - ADCRESULTx). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_enablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Enable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) |= ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Disables two's complement capability in the PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! +//! This function disables two's complement in the post-processing block +//! specified by the \e ppbNumber parameter. When disabled, a two's complement +//! will \b NOT be performed on the output of the offset subtraction before it +//! is stored in the appropriate PPB result register. In other words, the PPB +//! result will be the ADC result value minus the reference offset value +//! (ADCPPBxRESULT = ADCRESULTx - ADCSOCxOFFREF). +//! +//! \return None +// +//***************************************************************************** +static inline void +ADC_disablePPBTwosComplement(uint32_t base, ADC_PPBNumber ppbNumber) +{ + uint32_t ppbOffset; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Get the offset to the appropriate PPB configuration register. + // + ppbOffset = (ADC_PPBxCONFIG_STEP * (uint32_t)ppbNumber) + ADC_O_PPB1CONFIG; + + // + // Disable PPB two's complement. + // + EALLOW; + HWREGH(base + ppbOffset) &= ~ADC_PPB1CONFIG_TWOSCOMPEN; + EDIS; +} + +//***************************************************************************** +// +//! Enables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables the indicated ADC interrupt source. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1E << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables an ADC interrupt source. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables the indicated ADC interrupt source. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt. Disabled sources have no effect on the processor. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module should be disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableInterrupt(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1E << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the source EOC for an analog-to-digital converter interrupt. +//! +//! \param base is the base address of the ADC module. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! \param socNumber is the number of the start-of-conversion. +//! +//! This function sets which conversion is the source of an ADC interrupt. +//! +//! The \e intTrigger number is a value \b ADC_SOC_NUMBERX where X is a number +//! from 0 to 15 specifying which EOC is to be configured on the ADC module +//! specified by \e base. Refer \b ADC_SOCNumber enum for valid values for +//! this input. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_setInterruptSource(uint32_t base, ADC_IntNumber adcIntNum, + uint16_t intTrigger) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + ASSERT(intTrigger < 16U); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Set the specified ADC interrupt source. + // + EALLOW; + + HWREGH(intRegAddr) = + (HWREGH(intRegAddr) & ~(ADC_INTSEL1N2_INT1SEL_M << shiftVal)) | + ((uint16_t)intTrigger << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Enables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function enables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will be generated for the specified +//! ADC interrupt whenever an EOC pulse is generated irrespective of whether or +//! not the flag bit is set. +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_enableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Enable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) |= ADC_INTSEL1N2_INT1CONT << shiftVal; + + EDIS; +} + +//***************************************************************************** +// +//! Disables continuous mode for an ADC interrupt. +//! +//! \param base is the base address of the ADC. +//! \param adcIntNum is interrupt number within the ADC wrapper. +//! +//! This function disables continuous mode for the ADC interrupt passed into +//! \e adcIntNum. This means that pulses will not be generated for the +//! specified ADC interrupt until the corresponding interrupt flag for the +//! previous interrupt occurrence has been cleared using +//! ADC_clearInterruptStatus(). +//! +//! \e adcIntNum can take the value \b ADC_INT_NUMBER1, +//! \b ADC_INT_NUMBER2, \b ADC_INT_NUMBER3 or \b ADC_INT_NUMBER4 to express +//! which of the four interrupts of the ADC module is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ADC_disableContinuousMode(uint32_t base, ADC_IntNumber adcIntNum) +{ + uint32_t intRegAddr; + uint16_t shiftVal; + + // + // Check the arguments. + // + ASSERT(ADC_isBaseValid(base)); + + // + // Each INTSEL register manages two interrupts. If the interrupt number is + // even, we'll be accessing the upper byte and will need to shift. + // + intRegAddr = base + ADC_INTSELxNy_OFFSET_BASE + ((uint32_t)adcIntNum >> 1); + shiftVal = ((uint16_t)adcIntNum & 0x1U) << 3U; + + // + // Disable continuous mode for the specified ADC interrupt. + // + EALLOW; + + HWREGH(intRegAddr) &= ~(ADC_INTSEL1N2_INT1CONT << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees C +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees C. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees C. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureC(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)((((int32_t)temp + (int32_t)0x4000 + + ((int32_t)273 * (int32_t)0x8000)) / + (int32_t)0x8000) - (int32_t)273)); +} + +//***************************************************************************** +// +//! Converts temperature from sensor reading to degrees K +//! +//! \param tempResult is the raw ADC A conversion result from the temp sensor. +//! \param vref is the reference voltage being used (for example 3.3 for 3.3V). +//! +//! This function converts temperature from temp sensor reading to degrees K. +//! Temp sensor values in production test are derived with 2.5V reference. +//! The \b vref argument in the function is used to scale the temp sensor +//! reading accordingly if temp sensor value is read at a different VREF +//! setting. +//! +//! \return Returns the temperature sensor reading converted to degrees K. +// +//***************************************************************************** +static inline int16_t +ADC_getTemperatureK(uint16_t tempResult, float32_t vref) +{ + int16_t tsOffset, tsSlope; + float32_t temp; + + // + // Check the device revision + // + if(HWREGH(DEVCFG_BASE + SYSCTL_O_REVID) >= 3) + { + // + // For production devices (Rev. C), pull the slope and offset from OTP + // +#ifdef __TMS320C28XX__ + + // + // Only accessible from the CPU. + // + tsSlope = (int16_t)ADC_getTempSlope(); + tsOffset = (int16_t)ADC_getTempOffset(); +#endif + } + else + { + // + // For pre-production devices, use these static values for slope + // and offset + // + tsSlope = 5196; + tsOffset = 1788; + } + + // + // The slope is stored as a Q15 fixed point number hence the need to + // to an integer. + // + temp = (((float32_t)tempResult * (vref / 2.5F)) - (float32_t)tsOffset) * + (float32_t)tsSlope; + return((int16_t)(((int32_t)temp + (int32_t)0x4000 + ((int32_t)273 * + (int32_t)0x8000)) / (int32_t)0x8000)); +} + + +//***************************************************************************** +// +//! Configures the analog-to-digital converter resolution and signal mode. +//! +//! \param base is the base address of the ADC module. +//! \param resolution is the resolution of the converter (12 or 16 bits). +//! \param signalMode is the input signal mode of the converter. +//! +//! This function configures the ADC module's conversion resolution and input +//! signal mode and ensures that the corresponding trims are loaded. +//! +//! The \e resolution parameter specifies the resolution of the conversion. +//! It can be 12-bit or 16-bit specified by \b ADC_RESOLUTION_12BIT +//! or \b ADC_RESOLUTION_16BIT. +//! +//! The \e signalMode parameter specifies the signal mode. In single-ended +//! mode, which is indicated by \b ADC_MODE_SINGLE_ENDED, the input voltage is +//! sampled on a single pin referenced to VREFLO. In differential mode, which +//! is indicated by \b ADC_MODE_DIFFERENTIAL, the input voltage to the +//! converter is sampled on a pair of input pins, a positive and a negative. +//! +//! \b Note: In this device, single-ended signal conversions are supported +//! only in 12-bit resolution mode and differential signal +//! conversions are supported only in 16-bit resolution mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setMode(uint32_t base, ADC_Resolution resolution, + ADC_SignalMode signalMode); + + +//***************************************************************************** +// +//! Configures the offset trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the offset trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setOffsetTrim(uint32_t base); + +//***************************************************************************** +// +//! Configures the INL trim for the desired ADC instance +//! +//! \param base is the base address of the ADC module. +//! +//! This function loads the INL trims for the desired ADC instance. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setINLTrim(uint32_t base); + +//***************************************************************************** +// +//! Sets the windowed trip limits for a PPB. +//! +//! \param base is the base address of the ADC module. +//! \param ppbNumber is the number of the post-processing block. +//! \param tripHiLimit is the value is the digital comparator trip high limit. +//! \param tripLoLimit is the value is the digital comparator trip low limit. +//! +//! This function sets the windowed trip limits for a PPB. These values set +//! the digital comparator so that when one of the values is exceeded, either a +//! high or low trip event will occur. +//! +//! The \e ppbNumber is a value \b ADC_PPB_NUMBERX where X is a value from 1 to +//! 4 inclusive that identifies a PPB to be configured. +//! +//! If using 16-bit mode, you may pass a 17-bit number into the \e tripHiLimit +//! and \e tripLoLimit parameters where the 17th bit is the sign bit (that is +//! a value from -65536 and 65535). In 12-bit mode, only bits 12:0 will be +//! compared against bits 12:0 of the PPB result. +//! +//! \note On some devices, signed trip values do not work properly. See the +//! silicon errata for details. +//! +//! \return None. +// +//***************************************************************************** +extern void +ADC_setPPBTripLimits(uint32_t base, ADC_PPBNumber ppbNumber, + int32_t tripHiLimit, int32_t tripLoLimit); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ADC_H diff --git a/gpio_driverlib_cpu1/device/driverlib/asysctl.c b/gpio_driverlib_cpu1/device/driverlib/asysctl.c new file mode 100644 index 0000000..4f3d202 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/asysctl.c @@ -0,0 +1,43 @@ +//########################################################################### +// +// FILE: asysctl.c +// +// TITLE: C28x Driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "asysctl.h" diff --git a/gpio_driverlib_cpu1/device/driverlib/asysctl.h b/gpio_driverlib_cpu1/device/driverlib/asysctl.h new file mode 100644 index 0000000..40e6c5c --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/asysctl.h @@ -0,0 +1,160 @@ +//########################################################################### +// +// FILE: asysctl.h +// +// TITLE: C28x driver for Analog System Control. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef ASYSCTL_H +#define ASYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup asysctl_api ASysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_asysctl.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "debug.h" +#include "cpu.h" + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Enable temperature sensor. +//! +//! This function enables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_enableTemperatureSensor(void) +{ + EALLOW; + + // + // Set the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) |= ASYSCTL_TSNSCTL_ENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable temperature sensor. +//! +//! This function disables the temperature sensor output to the ADC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +ASysCtl_disableTemperatureSensor(void) +{ + EALLOW; + + // + // Clear the temperature sensor enable bit. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_TSNSCTL) &= ~(ASYSCTL_TSNSCTL_ENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the temperature sensor control register. +//! +//! \return None. +// +//***************************************************************************** +static inline void ASysCtl_lockTemperatureSensor(void) +{ + EALLOW; + + // + // Write a 1 to the lock bit in the LOCK register. + // + HWREGH(ANALOGSUBSYS_BASE + ASYSCTL_O_LOCK) |= ASYSCTL_LOCK_TSNSCTL; + + EDIS; +} + + + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ASYSCTL_H diff --git a/gpio_driverlib_cpu1/device/driverlib/can.c b/gpio_driverlib_cpu1/device/driverlib/can.c new file mode 100644 index 0000000..5a33a50 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/can.c @@ -0,0 +1,1122 @@ +//########################################################################### +// +// FILE: can.c +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#include "can.h" + +//***************************************************************************** +// +// CAN_initModule +// +//***************************************************************************** +void +CAN_initModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Place CAN controller in init state, regardless of previous state. This + // will put controller in idle, and allow the message object RAM to be + // programmed. + // + HWREGH(base + CAN_O_CTL) |= ((uint16_t)CAN_CTL_INIT | + (uint16_t)CAN_INIT_PARITY_DISABLE); + + // + // Initialize the message RAM before using it. + // + CAN_initRAM(base); + + // + // Force module to reset state + // + + HWREGH(base + CAN_O_CTL) |= CAN_CTL_SWR; + + // + // Delay for 14 cycles + // + SysCtl_delay(1U); + + // + // Enable write access to the configuration registers + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_CCE; +} + +//***************************************************************************** +// +// CAN_setBitRate +// +//***************************************************************************** +void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime) +{ + uint16_t brp; + uint16_t tPhase; + uint16_t phaseSeg2; + uint16_t tSync = 1U; + uint16_t tProp = 2U; + uint16_t tSeg1; + uint16_t tSeg2; + uint16_t sjw; + uint16_t prescaler; + uint16_t prescalerExtension; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((bitTime > 7U) && (bitTime < 26U)); + ASSERT(bitRate <= 1000000U); + + // + // Calculate bit timing values + // + brp = (uint16_t)(clockFreq / (bitRate * bitTime)); + tPhase = bitTime - (tSync + tProp); + if((tPhase / 2U) <= 8U) + { + phaseSeg2 = tPhase / 2U; + } + else + { + phaseSeg2 = 8U; + } + tSeg1 = ((tPhase - phaseSeg2) + tProp) - 1U; + tSeg2 = phaseSeg2 - 1U; + if(phaseSeg2 > 4U) + { + sjw = 3U; + } + else + { + sjw = tSeg2; + } + prescalerExtension = ((brp - 1U) / 64U); + prescaler = ((brp - 1U) % 64U); + + // + // Set the calculated timing parameters + // + CAN_setBitTiming(base, prescaler, prescalerExtension, tSeg1, tSeg2, sjw); +} + +//***************************************************************************** +// +// CAN_setBitTiming +// +//***************************************************************************** +void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw) +{ + uint16_t savedInit; + uint32_t bitReg; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT(prescaler < 64U); + ASSERT((tSeg1 > 0U) && (tSeg1 < 16U)); + ASSERT(tSeg2 < 8U); + ASSERT(sjw < 4U); + ASSERT(prescalerExtension < 16U); + + // + // To set the bit timing register, the controller must be placed in init + // mode (if not already), and also configuration change bit enabled. + // State of the init bit should be saved so it can be restored at the end. + // + savedInit = HWREGH(base + CAN_O_CTL); + HWREGH(base + CAN_O_CTL) = savedInit | CAN_CTL_INIT | CAN_CTL_CCE; + + // + // Set the bit fields of the bit timing register + // + bitReg = (uint32_t)((uint32_t)prescaler & CAN_BTR_BRP_M); + bitReg |= (uint32_t)(((uint32_t)sjw << CAN_BTR_SJW_S) & CAN_BTR_SJW_M); + bitReg |= (uint32_t)(((uint32_t)tSeg1 << CAN_BTR_TSEG1_S) & + CAN_BTR_TSEG1_M); + bitReg |= (uint32_t)(((uint32_t)tSeg2 << CAN_BTR_TSEG2_S) & + CAN_BTR_TSEG2_M); + bitReg |= (uint32_t)(((uint32_t)prescalerExtension << CAN_BTR_BRPE_S) & + CAN_BTR_BRPE_M); + + HWREG_BP(base + CAN_O_BTR) = bitReg; + + // + // Clear the config change bit, and restore the init bit. + // + savedInit &= ~((uint16_t)CAN_CTL_CCE); + + HWREGH(base + CAN_O_CTL) = savedInit; +} + + +//***************************************************************************** +// +// CAN_clearInterruptStatus +// +//***************************************************************************** +void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intClr == CAN_INT_INT0ID_STATUS) || + ((intClr >= 1U) && (intClr <= 32U))); + + if(intClr == (uint32_t)CAN_INT_INT0ID_STATUS) + { + // + // Simply read and discard the status to clear the interrupt. + // + HWREGH(base + CAN_O_ES); + } + else + { + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + + // + // Only change the interrupt pending state by setting only the + // CAN_IF1CMD_CLRINTPND bit. + // + // Send the clear pending interrupt command to the CAN controller. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CLRINTPND | + (intClr & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait to be sure that this interface is not busy. + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == + CAN_IF1CMD_BUSY) + { + } + } +} + +//***************************************************************************** +// +// CAN_setupMessageObject +// +//***************************************************************************** +void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen) +{ + uint32_t cmdMaskReg = 0U; + uint32_t maskReg = 0U; + uint32_t arbReg = 0U; + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + switch(msgType) + { + // + // Transmit message object. + // + case CAN_MSG_OBJ_TYPE_TX: + { + // + // Set message direction to transmit. + // + arbReg = CAN_IF1ARB_DIR; + break; + } + + // + // Remote frame receive remote, with auto-transmit message object. + // + case CAN_MSG_OBJ_TYPE_RXTX_REMOTE: + { + // + // Set message direction to Tx for remote receivers. + // + arbReg = CAN_IF1ARB_DIR; + + // + // Set this object to auto answer if a matching identifier is seen. + // + msgCtrl = (uint32_t)((uint32_t)CAN_IF1MCTL_RMTEN | + (uint32_t)CAN_IF1MCTL_UMASK); + + break; + } + + // + // Transmit remote request message object (CAN_MSG_OBJ_TYPE_TX_REMOTE) + // or Receive message object (CAN_MSG_OBJ_TYPE_RX). + // + default: + { + // + // Set message direction to read. + // + arbReg = 0U; + + break; + } + } + + // + // Set values based on Extended Frame or Standard Frame + // + if(frame == CAN_MSG_FRAME_EXT) + { + // + // Configure the Mask Registers for 29 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = msgIDMask & CAN_IF1MSK_MSK_M; + } + + // + // Set the 29 bit version of the Identifier for this message + // object. Mark the message as valid and set the extended ID bit. + // + arbReg |= (msgID & CAN_IF1ARB_ID_M) | CAN_IF1ARB_MSGVAL | + CAN_IF1ARB_XTD; + } + else + { + // + // Configure the Mask Registers for 11 bit Identifier mask. + // + if((flags & CAN_MSG_OBJ_USE_ID_FILTER) == CAN_MSG_OBJ_USE_ID_FILTER) + { + maskReg = ((msgIDMask << CAN_IF1ARB_STD_ID_S) & + CAN_IF1ARB_STD_ID_M); + } + + // + // Set the 11 bit version of the Identifier for this message + // object. The lower 18 bits are set to zero. Mark the message as + // valid. + // + arbReg |= ((msgID << CAN_IF1ARB_STD_ID_S) & CAN_IF1ARB_STD_ID_M) | + CAN_IF1ARB_MSGVAL; + } + + // + // If the caller wants to filter on the extended ID bit then set it. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_EXT_FILTER); + + // + // The caller wants to filter on the message direction field. + // + maskReg |= (flags & CAN_MSG_OBJ_USE_DIR_FILTER); + + // + // If any filtering is requested, set the UMASK bit to use mask register + // + if(((flags & CAN_MSG_OBJ_USE_ID_FILTER) | + (flags & CAN_MSG_OBJ_USE_DIR_FILTER) | + (flags & CAN_MSG_OBJ_USE_EXT_FILTER)) != 0U) + { + msgCtrl |= CAN_IF1MCTL_UMASK; + } + + // + // Set the data length for the transfers. This is applicable only for + // Tx mailboxes. For Rx mailboxes, dlc is updated on receving a frame. + // + if((msgType == CAN_MSG_OBJ_TYPE_TX) || + (msgType == CAN_MSG_OBJ_TYPE_RXTX_REMOTE)) + { + msgCtrl |= ((uint32_t)msgLen & CAN_IF1MCTL_DLC_M); + } + + // + // If this is a single transfer or the last mailbox of a FIFO, set EOB bit. + // If this is not the last entry in a FIFO, leave the EOB bit as 0. + // + if((flags & CAN_MSG_OBJ_FIFO) == 0U) + { + msgCtrl |= CAN_IF1MCTL_EOB; + } + + // + // Enable transmit interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_TX_INT_ENABLE); + + // + // Enable receive interrupts if they should be enabled. + // + msgCtrl |= (flags & CAN_MSG_OBJ_RX_INT_ENABLE); + + // + // Set the Control, Arb, and Mask bit so that they get transferred to the + // Message object. + // + cmdMaskReg |= CAN_IF1CMD_ARB; + cmdMaskReg |= CAN_IF1CMD_CONTROL; + cmdMaskReg |= CAN_IF1CMD_MASK; + cmdMaskReg |= CAN_IF1CMD_DIR; + + // + // Write out the registers to program the message object. + // + HWREG_BP(base + CAN_O_IF1MSK) = maskReg; + HWREG_BP(base + CAN_O_IF1ARB) = arbReg; + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M); +} + +//***************************************************************************** +// +// CAN_sendMessage +// +//***************************************************************************** +void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_16bit +// +//***************************************************************************** +void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_16bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_32bit +// +//***************************************************************************** +void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg_32bit(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendMessage_updateDLC +// +//***************************************************************************** +void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + ASSERT(msgLen <= 8U); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Update to the new data length + // + msgCtrl &= ~CAN_IF1MCTL_DLC_M; + msgCtrl |= (msgLen & CAN_IF1MCTL_DLC_M); + + // + // Write out to the register to program the message object + // + HWREG_BP(base + CAN_O_IF1MCTL) = msgCtrl; + + // + // Transfer data to message object RAM + // + HWREG_BP(base + CAN_O_IF1CMD) = + (CAN_IF1CMD_CONTROL | CAN_IF1CMD_DIR | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check provided DLC size with actual Message DLC size + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == msgLen); + + // + // Write the data out to the CAN Data registers. + // + CAN_writeDataReg(msgData, (base + CAN_O_IF1DATA), + (msgCtrl & CAN_IF1MCTL_DLC_M)); + + // + // Set Data to be transferred from IF + // + if(msgLen > 0U) + { + msgCtrl = CAN_IF1CMD_DATA_B | CAN_IF1CMD_DATA_A; + } + else + { + msgCtrl = 0U; + } + + // + // Set Direction to write + // + // Set Tx Request Bit + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = (msgCtrl | (uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_sendRemoteRequestMessage +// +//***************************************************************************** +void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID) +{ + uint32_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID > 0U)); + + // + // Set IF command to read message object control value + // + // Set up the request for data from the message object. + // Transfer the message object to the IF register. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_CONTROL | + (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Read IF message control + // + msgCtrl = HWREGH(base + CAN_O_IF1MCTL); + + // + // Check configured DLC size with 0 as this is a remote frame + // + ASSERT((msgCtrl & CAN_IF1MCTL_DLC_M) == 0U); + + // + // Set Direction to write + // + // Set Tx Request Bit for this remote frame + // + // Transfer the message object to the message object specified by + // objID. + // + HWREG_BP(base + CAN_O_IF1CMD) = ((uint32_t)CAN_IF1CMD_DIR | + (uint32_t)CAN_IF1CMD_TXRQST | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_readMessage +// +//***************************************************************************** +bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData) +{ + bool status; + uint16_t msgCtrl = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID <= 32U) && (objID != 0U)); + + // + // Set the Message Data A, Data B, and control values to be read + // on request for data from the message object. + // + // Transfer the message object to the message object IF register. + // + HWREG_BP(base + CAN_O_IF2CMD) = + ((uint32_t)CAN_IF2CMD_DATA_A | (uint32_t)CAN_IF2CMD_DATA_B | + (uint32_t)CAN_IF2CMD_CONTROL | (objID & CAN_IF2CMD_MSG_NUM_M) | + (uint32_t)CAN_IF2CMD_ARB); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == CAN_IF2CMD_BUSY) + { + } + + // + // Read out the IF control Register. + // + msgCtrl = HWREGH(base + CAN_O_IF2MCTL); + + // + // See if there is new data available. + // + if((msgCtrl & CAN_IF2MCTL_NEWDAT) == CAN_IF2MCTL_NEWDAT) + { + // + // Read out the data from the CAN registers. + // + CAN_readDataReg(msgData, (base + CAN_O_IF2DATA), + ((uint32_t)msgCtrl & CAN_IF2MCTL_DLC_M)); + + status = true; + + // + // Now clear out the new data flag + // + HWREG_BP(base + CAN_O_IF2CMD) = ((uint32_t)CAN_IF2CMD_TXRQST | + (objID & CAN_IF2CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF2CMD) & CAN_IF2CMD_BUSY) == + CAN_IF2CMD_BUSY) + { + } + } + else + { + status = false; + } + + return(status); +} + +//***************************************************************************** +// +// CAN_readMessageWithID +// +//***************************************************************************** +bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData) +{ + bool status; + + // + // Check the pointers. + // + ASSERT(msgID != 0U); + ASSERT(frameType != 0U); + + // + //Read the message first this fills the IF2 registers + //with received message for that mailbox + // + status = CAN_readMessage(base, objID, msgData); + // + // See if there is new data available. + // + if(status) + { + if((HWREG_BP(base + CAN_O_IF2ARB) & CAN_IF2ARB_XTD) != 0U) + { + *frameType = CAN_MSG_FRAME_EXT; + *msgID = ((HWREG_BP(base + CAN_O_IF2ARB)) & CAN_IF2ARB_ID_M); + } + else + { + *frameType = CAN_MSG_FRAME_STD; + *msgID = (((HWREG_BP(base + CAN_O_IF2ARB)) & + CAN_IF2ARB_STD_ID_M) >> + CAN_IF2ARB_STD_ID_S); + } + } + + return(status); +} + +//***************************************************************************** +// +// CAN_transferMessage +// +//***************************************************************************** +void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction) +{ + uint32_t cmdMaskReg; + + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + ASSERT((interface == 1U) || (interface == 2U)); + + // + // This is always a read to the Message object as this call is setting a + // message object. + // + cmdMaskReg = + ((uint32_t)CAN_IF1CMD_DATA_A | (uint32_t)CAN_IF1CMD_DATA_B | + (uint32_t)CAN_IF1CMD_TXRQST | (uint32_t)CAN_IF1CMD_CONTROL | + (uint32_t)CAN_IF1CMD_MASK | (uint32_t)CAN_IF1CMD_ARB) | + (direction ? CAN_IF1CMD_DIR : 0U); + + // + // Ensure this IF isn't busy + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Set up the request for data from the message object. Transfer the + // message object to the message object specified by objID. + // + HWREG_BP(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) = + (cmdMaskReg | (objID & CAN_IF1CMD_MSG_NUM_M)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + ((interface == 2U) ? CAN_O_IF2CMD : CAN_O_IF1CMD)) & + CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } +} + +//***************************************************************************** +// +// CAN_clearMessage +// +//***************************************************************************** +void +CAN_clearMessage(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableMessageObject +// +//***************************************************************************** +void +CAN_disableMessageObject(uint32_t base, uint32_t objID) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((objID >= 1U) && (objID <= 32U)); + + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); +} + +//***************************************************************************** +// +// CAN_disableAllMessageObjects +// +//***************************************************************************** +void +CAN_disableAllMessageObjects(uint32_t base) +{ + uint32_t objID; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Loop to disable all valid message objects + // + for(objID = 0x01UL; objID <= 0x20UL; objID++) + { + // + // Wait for busy bit to clear + // + while((HWREGH(base + CAN_O_IF1CMD) & CAN_IF1CMD_BUSY) == CAN_IF1CMD_BUSY) + { + } + + // + // Clear the message valid bit in the arbitration register. This disables + // the mailbox. + // + HWREG_BP(base + CAN_O_IF1ARB) = 0U; + + // + // Initiate programming the message object + // + HWREG_BP(base + CAN_O_IF1CMD) = + (((uint32_t)CAN_IF1CMD_DIR | (uint32_t)CAN_IF1CMD_ARB) | + (objID & CAN_IF1CMD_MSG_NUM_M)); + } +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/can.h b/gpio_driverlib_cpu1/device/driverlib/can.h new file mode 100644 index 0000000..247d1df --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/can.h @@ -0,0 +1,1924 @@ +//########################################################################### +// +// FILE: can.h +// +// TITLE: C28x CAN driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef CAN_H +#define CAN_H + + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup can_api CAN +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_can.h" +#include "debug.h" +#include "sysctl.h" + +// +// The key value for RAM initialization +// +#define CAN_RAM_INIT_KEY (0xAU) + +// +// RAM Initialization Register Mask +// +#define CAN_RAM_INIT_MASK (0x003FU) + +// +// The Parity disable key value +// +#define CAN_INIT_PARITY_DISABLE (0x1400U) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Miscellaneous defines for Message ID Types +// +//***************************************************************************** +//***************************************************************************** +// +// These are the flags used by the flags parameter when calling +// the CAN_setupMessageObject() function. +// +//***************************************************************************** + +//! This indicates that transmit interrupts should be enabled, or are enabled. +#define CAN_MSG_OBJ_TX_INT_ENABLE CAN_IF1MCTL_TXIE + +//! This indicates that receive interrupts should be enabled, or are +//! enabled. +#define CAN_MSG_OBJ_RX_INT_ENABLE CAN_IF1MCTL_RXIE + +//! This indicates that a message object will use or is using filtering +//! based on the object's message identifier. +#define CAN_MSG_OBJ_USE_ID_FILTER (0x00000001U) + +//! This indicates that a message object will use or is using filtering +//! based on the direction of the transfer. +#define CAN_MSG_OBJ_USE_DIR_FILTER CAN_IF1MSK_MDIR + +//! This indicates that a message object will use or is using message +//! identifier filtering based on the extended identifier. +#define CAN_MSG_OBJ_USE_EXT_FILTER CAN_IF1MSK_MXTD + +//! This indicates that this message object is part of a FIFO structure and +//! not the final message object in a FIFO. +#define CAN_MSG_OBJ_FIFO (0x00000002U) + +//! This indicates that a message object has no flags set. +#define CAN_MSG_OBJ_NO_FLAGS (0x00000000U) + +//***************************************************************************** +// +// These definitions are used to specify interrupt sources to +// CAN_enableInterrupt() and CAN_disableInterrupt(). +// +//***************************************************************************** +//! This flag is used to allow a CAN controller to generate error +//! interrupts. +#define CAN_INT_ERROR (0x00000008UL) + +//! This flag is used to allow a CAN controller to generate status +//! interrupts. +#define CAN_INT_STATUS (0x00000004UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 0 +#define CAN_INT_IE0 (0x00000002UL) + +//! This flag is used to allow a CAN controller to generate interrupts +//! on interrupt line 1 +#define CAN_INT_IE1 (0x00020000UL) + +//***************************************************************************** +// +// The following definitions contain all error or status indicators that can +// be returned when calling the CAN_getStatus() function. +// +//***************************************************************************** + +//! CAN controller has detected a parity error. +#define CAN_STATUS_PERR (0x00000100U) + +//! CAN controller has entered a Bus Off state. +#define CAN_STATUS_BUS_OFF (0x00000080U) + +//! CAN controller error level has reached warning level. +#define CAN_STATUS_EWARN (0x00000040U) + +//! CAN controller error level has reached error passive level. +#define CAN_STATUS_EPASS (0x00000020U) + +//! A message was received successfully since the last read of this status. +#define CAN_STATUS_RXOK (0x00000010U) + +//! A message was transmitted successfully since the last read of this +//! status. +#define CAN_STATUS_TXOK (0x00000008U) + +//! This is the mask for the last error code field. +#define CAN_STATUS_LEC_MSK (0x00000007U) + +//! There was no error. +#define CAN_STATUS_LEC_NONE (0x00000000U) + +//! A bit stuffing error has occurred. +#define CAN_STATUS_LEC_STUFF (0x00000001U) + +//! A formatting error has occurred. +#define CAN_STATUS_LEC_FORM (0x00000002U) + +//! An acknowledge error has occurred. +#define CAN_STATUS_LEC_ACK (0x00000003U) + +//! The bus remained a bit level of 1 for longer than is allowed. +#define CAN_STATUS_LEC_BIT1 (0x00000004U) + +//! The bus remained a bit level of 0 for longer than is allowed. +#define CAN_STATUS_LEC_BIT0 (0x00000005U) + +//! A CRC error has occurred. +#define CAN_STATUS_LEC_CRC (0x00000006U) + +//***************************************************************************** +// +// The following macros are added for the Global Interrupt EN/FLG/CLR +// register +// +//***************************************************************************** +//! CANINT0 global interrupt bit +#define CAN_GLOBAL_INT_CANINT0 (0x00000001U) + +//! CANINT1 global interrupt bit +#define CAN_GLOBAL_INT_CANINT1 (0x00000002U) + +//***************************************************************************** +// +// The following macros are added for accessing the interrupt register and +// the standard arbitration ID in the interface registers. +// +//***************************************************************************** +//! Status of INT0ID +#define CAN_INT_INT0ID_STATUS (0x8000U) + +//! IF1 Arbitration Standard ID Shift Offset +#define CAN_IF1ARB_STD_ID_S (18U) + +//! IF1 Arbitration Standard ID Mask +#define CAN_IF1ARB_STD_ID_M (0x1FFC0000U) + +//! IF2 Arbitration Standard ID Shift Offset +#define CAN_IF2ARB_STD_ID_S (18U) + +//! IF2 Arbitration Standard ID Mask +#define CAN_IF2ARB_STD_ID_M (0x1FFC0000U) + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! This data type is used to decide between STD_ID or EXT_ID for a mailbox. +//! This is used when calling the CAN_setupMessageObject() function. +// +//***************************************************************************** +typedef enum +{ + //! Set the message ID frame to standard. + CAN_MSG_FRAME_STD, + + //! Set the message ID frame to extended. + CAN_MSG_FRAME_EXT +} CAN_MsgFrameType; + +//***************************************************************************** +// +//! This definition is used to determine the type of message object that will +//! be set up via a call to the CAN_setupMessageObject() API. +// +//***************************************************************************** +typedef enum +{ + //! Transmit message object. + CAN_MSG_OBJ_TYPE_TX, + + //! Transmit remote request message object + CAN_MSG_OBJ_TYPE_TX_REMOTE, + + //! Receive message object. + CAN_MSG_OBJ_TYPE_RX, + + //! Remote frame receive remote, with auto-transmit message object. + CAN_MSG_OBJ_TYPE_RXTX_REMOTE +} CAN_MsgObjType; + +//***************************************************************************** +// +//! This definition is used to determine the clock source that will +//! be set up via a call to the CAN_selectClockSource() API. +// +//***************************************************************************** +typedef enum +{ + //! Peripheral System Clock Source + CAN_CLOCK_SOURCE_SYS = 0x0, + + //! External Oscillator Clock Source + CAN_CLOCK_SOURCE_XTAL = 0x1, + + //! Auxiliary Clock Input Source + CAN_CLOCK_SOURCE_AUX = 0x2 +} CAN_ClockSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! +//! Checks a CAN base address. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function determines if a CAN controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CAN_isBaseValid(uint32_t base) +{ + return( + (base == CANA_BASE) || + (base == CANB_BASE) + ); +} +#endif + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_writeDataReg(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = data[idx]; + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 16bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_16bit(const uint16_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = (uint32_t)((data[idx / 2UL]) >> ((idx % 2UL) * 8UL)); + + dataReg++; + } +} + + +//***************************************************************************** +// +//! \internal +//! +//! Copies data (all 32bits) from a buffer to the CAN Data registers. +//! +//! \param data is a pointer to the data to be written out to the CAN +//! controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 0, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy into the CAN controller. +//! +//! This function takes the steps necessary to copy data from a contiguous +//! buffer in memory into the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** + +static inline void +CAN_writeDataReg_32bit(const uint32_t *const data, uint32_t address, + uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Check the dataReg. + // + ASSERT(dataReg != 0U); + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Write out the data 8 bits at a time. + // + HWREGB(dataReg) = ((data[idx / 4UL]) >> ((idx % 4UL) * 8UL)); + + dataReg++; + } +} + +//***************************************************************************** +// +//! \internal +//! +//! Copies data from the CAN Data registers to a buffer. +//! +//! \param data is a pointer to the location to store the data read from the +//! CAN controller's data registers. +//! \param address is a uint32_t value for the first register of the +//! CAN controller's data registers. For example, in order to use the IF1 +//! register set on CAN controller 1, the value would be: \b CANA_BASE \b + +//! \b CAN_O_IF1DATA. +//! \param size is the number of bytes to copy from the CAN controller. +//! +//! This function takes the steps necessary to copy data to a contiguous buffer +//! in memory from the non-contiguous data registers used by the CAN +//! controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_readDataReg(uint16_t *data, const uint32_t address, uint32_t size) +{ + uint32_t idx; + uint32_t dataReg = address; + + // + // Loop always copies 1 byte per iteration. + // + for(idx = 0U; idx < size; idx++) + { + // + // Read out the data + // + data[idx] = HWREGB(dataReg); + + dataReg++; + } +} + +//***************************************************************************** +// +//! Initializes the CAN controller's RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Performs the initialization of the RAM used for the CAN message objects. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_initRAM(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + HWREGH(base + CAN_O_RAM_INIT) = CAN_RAM_INIT_CAN_RAM_INIT | + CAN_RAM_INIT_KEY; + + while(!((HWREGH(base + CAN_O_RAM_INIT) & CAN_RAM_INIT_MASK) == + (CAN_RAM_INIT_RAM_INIT_DONE | CAN_RAM_INIT_KEY2 | + CAN_RAM_INIT_KEY0))) + { + // + // Wait until RAM Init is complete + // + } +} + +//***************************************************************************** +// +//! Select CAN Clock Source +//! +//! \param base is the base address of the CAN controller. +//! \param source is the clock source to use for the CAN controller. +//! +//! This function selects the specified clock source for the CAN controller. +//! +//! The \e source parameter can be any one of the following: +//! - \b CAN_CLOCK_SOURCE_SYS - Peripheral System Clock +//! - \b CAN_CLOCK_SOURCE_XTAL - External Oscillator +//! - \b CAN_CLOCK_SOURCE_AUX - Auxiliary Clock Input from GPIO +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_selectClockSource(uint32_t base, CAN_ClockSource source) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Determine the CAN controller and set specified clock source + // + EALLOW; + + switch(base) + { + case CANA_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANABCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANABCLKSEL_S); + break; + + case CANB_BASE: + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M) | + ((uint16_t)source << SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S); + break; + + default: + + // + // Do nothing. Not a valid mode value. + // + break; + } + + EDIS; + SYSCTL_CLKSRCCTL_DELAY; +} + +//***************************************************************************** +// +//! Starts the CAN Module's Operations +//! +//! \param base is the base address of the CAN controller. +//! +//! This function starts the CAN module's operations after initialization, +//! which includes the CAN protocol controller state machine of the CAN core +//! and the message handler state machine to begin controlling the CAN's +//! internal data flow. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_startModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear Init and CCE bits + // + HWREGH(base + CAN_O_CTL) &= ~(CAN_CTL_INIT | CAN_CTL_CCE); +} + +//***************************************************************************** +// +//! Enables the CAN controller. +//! +//! \param base is the base address of the CAN controller to enable. +//! +//! Enables the CAN controller for message processing. Once enabled, the +//! controller will automatically transmit any pending frames, and process any +//! received frames. The controller can be stopped by calling +//! CAN_disableController(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Disables the CAN controller. +//! +//! \param base is the base address of the CAN controller to disable. +//! +//! Disables the CAN controller for message processing. When disabled, the +//! controller will no longer automatically process data on the CAN bus. The +//! controller can be restarted by calling CAN_enableController(). The state +//! of the CAN controller and the message objects in the controller are left as +//! they were before this call was made. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableController(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the init bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_INIT; +} + +//***************************************************************************** +// +//! Enables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param mode are the the test modes to enable. +//! +//! Enables test modes within the controller. The following valid options for +//! \e mode can be OR'ed together: +//! - \b CAN_TEST_SILENT - Silent Mode +//! - \b CAN_TEST_LBACK - Loopback Mode +//! - \b CAN_TEST_EXL - External Loopback Mode +//! +//! \note Loopback mode and external loopback mode \b can \b not be +//! enabled at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableTestMode(uint32_t base, uint16_t mode) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((mode & (CAN_TEST_LBACK | CAN_TEST_EXL)) != + (CAN_TEST_LBACK | CAN_TEST_EXL)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Enable test mode and set the bits in the test register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_TEST; + HWREGH(base + CAN_O_TEST) |= mode; +} + +//***************************************************************************** +// +//! Disables the test modes of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables test modes within the controller and clears the test bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableTestMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the bits in the test register. + // + HWREGH(base + CAN_O_TEST) &= ~((uint16_t)CAN_TEST_SILENT | + (uint16_t)CAN_TEST_LBACK | + (uint16_t)CAN_TEST_EXL); + + // + // Clear the test mode enable bit + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_TEST; +} + +//***************************************************************************** +// +//! Get the current settings for the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function reads the current configuration of the CAN controller bit +//! clock timing. +//! +//! \return Returns the value of the bit timing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getBitTiming(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read and return BTR register + // + return(HWREG_BP(base + CAN_O_BTR)); +} + +//***************************************************************************** +// +//! Enables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables direct access to the RAM while in Test mode. +//! +//! \note Test Mode must first be enabled to use this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) |= CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Disables direct access to the RAM. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables direct access to the RAM while in Test mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableMemoryAccessMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the RAM direct access bit + // + HWREGH(base + CAN_O_TEST) &= ~CAN_TEST_RDA; +} + +//***************************************************************************** +// +//! Sets the interruption debug mode of the CAN controller. +//! +//! \param base is the base address of the CAN controller. +//! \param enable is a flag to enable or disable the interruption debug mode. +//! +//! This function sets the interruption debug mode of the CAN controller. When +//! the \e enable parameter is \b true, CAN will be configured to interrupt any +//! transmission or reception and enter debug mode immediately after it is +//! requested. When \b false, CAN will wait for a started transmission or +//! reception to be completed before entering debug mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptionDebugMode(uint32_t base, bool enable) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + if(enable) + { + // + // Enable interrupt debug support + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_IDS; + } + else + { + // + // Disable interrupt debug support + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_IDS; + } +} + + +//***************************************************************************** +// +//! Disables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the Auto-Bus-On feature of the CAN controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clear the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Enables Auto-Bus-On. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the Auto-Bus-On feature of the CAN controller. Be sure to also +//! configure the Auto-Bus-On time using the CAN_setAutoBusOnTime function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableAutoBusOn(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the ABO bit in the control register. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_ABO; +} + +//***************************************************************************** +// +//! Sets the time before a Bus-Off recovery sequence is started. +//! +//! \param base is the base address of the CAN controller. +//! \param onTime is number of clock cycles before a Bus-Off recovery sequence +//! is started. +//! +//! This function sets the number of clock cycles before a Bus-Off recovery +//! sequence is started by clearing the Init bit. +//! +//! \note To enable this functionality, use CAN_enableAutoBusOn(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setAutoBusOnTime(uint32_t base, uint32_t onTime) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set bus-off timer value + // + HWREG_BP(base + CAN_O_ABOTR) = onTime; +} + +//***************************************************************************** +// +//! Enables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific interrupt sources of the CAN controller. Only enabled +//! sources will cause a processor interrupt. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_INT_ERROR - a controller error condition has occurred +//! - \b CAN_INT_STATUS - a message transfer has completed, or a bus error has +//! been detected +//! - \b CAN_INT_IE0 - allow CAN controller to generate interrupts on interrupt +//! line 0 +//! - \b CAN_INT_IE1 - allow CAN controller to generate interrupts on interrupt +//! line 1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Enable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual CAN controller interrupt sources. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specified CAN controller interrupt sources. Only enabled +//! interrupt sources can cause a processor interrupt. +//! +//! The \e intFlags parameter has the same definition as in the +//! CAN_enableInterrupt() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_INT_ERROR | CAN_INT_STATUS | CAN_INT_IE0 | + CAN_INT_IE1)) == 0U); + + // + // Disable the specified interrupts. + // + HWREG_BP(base + CAN_O_CTL) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Get the CAN controller Interrupt Line set for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! +//! Gets which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return Returns the value of the interrupt muxing register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMux(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Get the interrupt muxing for the CAN peripheral + // + return(HWREG_BP(base + CAN_O_IP_MUX21)); +} + +//***************************************************************************** +// +//! Set the CAN controller Interrupt Line for each mailbox +//! +//! \param base is the base address of the CAN controller. +//! \param mux bit packed representation of which message objects should +//! generate an interrupt on a given interrupt line. +//! +//! Selects which interrupt line each message object should assert when an +//! interrupt occurs. Bit 0 corresponds to message object 32 and then bits +//! 1 to 31 correspond to message object 1 through 31 respectively. Bits that +//! are asserted indicate the message object should generate an interrupt on +//! interrupt line 1, while bits that are not asserted indicate the message +//! object should generate an interrupt on line 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_setInterruptMux(uint32_t base, uint32_t mux) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Set the interrupt muxing for the CAN peripheral + // + HWREG_BP(base + CAN_O_IP_MUX21) = mux; +} + +//***************************************************************************** +// +//! Enables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Enables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Clearing the DAR bit tells the controller to not disable the + // auto-retry of messages which were not transmitted or received + // correctly. + // + HWREGH(base + CAN_O_CTL) &= ~CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Disables the CAN controller automatic retransmission behavior. +//! +//! \param base is the base address of the CAN controller. +//! +//! Disables the automatic retransmission of messages with detected errors. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableRetry(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Setting the DAR bit tells the controller to disable the auto-retry + // of messages which were not transmitted or received correctly. + // + HWREGH(base + CAN_O_CTL) |= CAN_CTL_DAR; +} + +//***************************************************************************** +// +//! Returns the current setting for automatic retransmission. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the current setting for the automatic retransmission in the CAN +//! controller and returns it to the caller. +//! +//! \return Returns \b true if automatic retransmission is enabled, \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +CAN_isRetryEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the disable automatic retry setting from the CAN controller. + // + return((bool)((HWREGH(base + CAN_O_CTL) & CAN_CTL_DAR) != CAN_CTL_DAR)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error counter register. +//! +//! \param base is the base address of the CAN controller. +//! \param rxCount is a pointer to storage for the receive error counter. +//! \param txCount is a pointer to storage for the transmit error counter. +//! +//! Reads the error counter register and returns the transmit and receive error +//! counts to the caller along with a flag indicating if the controller receive +//! counter has reached the error passive limit. The values of the receive and +//! transmit error counters are returned through the pointers provided as +//! parameters. +//! +//! After this call, \e rxCount will hold the current receive error count +//! and \e txCount will hold the current transmit error count. +//! +//! \return Returns \b true if the receive error count has reached the error +//! passive limit, and \b false if the error count is below the error passive +//! limit. +// +//***************************************************************************** +static inline bool +CAN_getErrorCount(uint32_t base, uint32_t *rxCount, uint32_t *txCount) +{ + uint32_t canError = 0U; + + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read the current count of transmit/receive errors. + // + canError = HWREG_BP(base + CAN_O_ERRC); + + // + // Extract the error numbers from the register value. + // + *rxCount = (canError & CAN_ERRC_REC_M) >> CAN_ERRC_REC_S; + *txCount = (canError & CAN_ERRC_TEC_M) >> CAN_ERRC_TEC_S; + + return((bool)((canError & CAN_ERRC_RP) != 0U)); +} + +//***************************************************************************** +// +//! Reads the CAN controller error and status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the error and status register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint16_t +CAN_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return error and status register value + // + return(HWREGH(base + CAN_O_ES)); +} + +//***************************************************************************** +// +//! Reads the CAN controller TX request register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the TX request register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getTxRequests(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return Tx requests register value + // + return(HWREG_BP(base + CAN_O_TXRQ_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller new data status register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the new data status register of the CAN controller for all message +//! objects. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getNewDataFlags(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return new data register value + // + return(HWREG_BP(base + CAN_O_NDAT_21)); +} + +//***************************************************************************** +// +//! Reads the CAN controller valid message object register. +//! +//! \param base is the base address of the CAN controller. +//! +//! Reads the valid message object register of the CAN controller. +//! +//! \return Returns the value of the register. +// +//***************************************************************************** +static inline uint32_t +CAN_getValidMessageObjects(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Return the valid message register value + // + return(HWREG_BP(base + CAN_O_MVAL_21)); +} + +//***************************************************************************** +// +//! Get the CAN controller interrupt cause. +//! +//! \param base is the base address of the CAN controller. +//! +//! This function returns the value of the interrupt register that indicates +//! the cause of the interrupt. +//! +//! \return Returns the value of the interrupt register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptCause(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read interrupt identifier status + // + return(HWREG_BP(base + CAN_O_INT)); +} + +//***************************************************************************** +// +//! Get the CAN controller pending interrupt message source. +//! +//! \param base is the base address of the CAN controller. +//! +//! Returns the value of the pending interrupts register that indicates +//! which messages are the source of pending interrupts. +//! +//! \return Returns the value of the pending interrupts register. +// +//***************************************************************************** +static inline uint32_t +CAN_getInterruptMessageSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + + // + // Read message object interrupt status + // + return(HWREG_BP(base + CAN_O_IPEN_21)); +} + +//***************************************************************************** +// +//! CAN Global interrupt Enable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt Enable bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt Enable bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_enableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Enable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) |= intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Disable function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the specific CAN interrupt in the global interrupt enable register +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_disableGlobalInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Disable the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_EN) &= ~intFlags; +} + +//***************************************************************************** +// +//! CAN Global interrupt Clear function. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be cleared. +//! +//! Clear the specific CAN interrupt bit in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return None. +// +//***************************************************************************** +static inline void +CAN_clearGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Clear the requested interrupts + // + HWREGH(base + CAN_O_GLB_INT_CLR) |= intFlags; +} + +//***************************************************************************** +// +//! Get the CAN Global Interrupt status. +//! +//! \param base is the base address of the CAN controller. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Check if any interrupt bit is set in the global interrupt flag register. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! - \b CAN_GLOBAL_INT_CANINT0 - Global Interrupt bit for CAN INT0 +//! - \b CAN_GLOBAL_INT_CANINT1 - Global Interrupt bit for CAN INT1 +//! +//! \return True if any of the requested interrupt bits are set. False, if +//! none of the requested bits are set. +// +//***************************************************************************** +static inline bool +CAN_getGlobalInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(CAN_isBaseValid(base)); + ASSERT((intFlags & ~(CAN_GLOBAL_INT_CANINT0 | + CAN_GLOBAL_INT_CANINT1)) == 0U); + + // + // Read and return the global interrupt flag register + // + return((bool)((HWREGH(base + CAN_O_GLB_INT_FLG) & intFlags) != 0U)); +} + +//***************************************************************************** +// +//! Initializes the CAN controller +//! +//! \param base is the base address of the CAN controller. +//! +//! This function initializes the message RAM, which also clears all the +//! message objects, and places the CAN controller in an init state. Write +//! access to the configuration registers is available as a result, allowing +//! the bit timing and message objects to be setup. +//! +//! \note To exit the initialization mode and start the CAN module, use the +//! CAN_startModule() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_initModule(uint32_t base); + +//***************************************************************************** +// +//! Sets the CAN Bit Timing based on requested Bit Rate. +//! +//! \param base is the base address of the CAN controller. +//! \param clockFreq is the CAN module clock frequency before the bit rate +//! prescaler (Hertz) +//! \param bitRate is the desired bit rate (bits/sec) +//! \param bitTime is the number of time quanta per bit required for desired +//! bit time (Tq) and must be in the range from 8 to 25 +//! +//! This function sets the CAN bit timing values for the bit rate passed in the +//! \e bitRate and \e bitTime parameters based on the \e clockFreq parameter. The +//! CAN bit clock is calculated to be an average timing value that should work +//! for most systems. If tighter timing requirements are needed, then the +//! CAN_setBitTiming() function is available for full customization of all of +//! the CAN bit timing values. +//! +//! \note Not all bit-rate and bit-time combinations are valid. +//! For combinations that would yield the correct bit-rate, +//! refer to the DCAN_CANBTR_values.xlsx file in the "docs" directory. +//! The CANBTR register values calculated by the function CAN_setBitRate +//! may not be suitable for your network parameters. If this is the case +//! and you have computed the correct values for your network, you could +//! directly write those parameters in CANBTR register using the +//! function CAN_setBitTiming. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitRate(uint32_t base, uint32_t clockFreq, uint32_t bitRate, + uint16_t bitTime); + +//***************************************************************************** +// +//! Manually set the CAN controller bit timing. +//! +//! \param base is the base address of the CAN controller. +//! \param prescaler is the baud rate prescaler +//! \param prescalerExtension is the baud rate prescaler extension +//! \param tSeg1 is the time segment 1 +//! \param tSeg2 is the time segment 2 +//! \param sjw is the synchronization jump width +//! +//! This function sets the various timing parameters for the CAN bus bit +//! timing: baud rate prescaler, prescaler extension, time segment 1, +//! time segment 2, and the Synchronization Jump Width. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setBitTiming(uint32_t base, uint16_t prescaler, + uint16_t prescalerExtension, uint16_t tSeg1, uint16_t tSeg2, + uint16_t sjw); + + +//***************************************************************************** +// +//! Clears a CAN interrupt source. +//! +//! \param base is the base address of the CAN controller. +//! \param intClr is a value indicating which interrupt source to clear. +//! +//! This function can be used to clear a specific interrupt source. The +//! \e intClr parameter should be either a number from 1 to 32 to clear a +//! specific message object interrupt or can be the following: +//! - \b CAN_INT_INT0ID_STATUS - Clears a status interrupt. +//! +//! It is not necessary to use this function to clear an interrupt. This +//! should only be used if the application wants to clear an interrupt source +//! without taking the normal interrupt action. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearInterruptStatus(uint32_t base, uint32_t intClr); + +//***************************************************************************** +// +//! Setup a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to configure (1-32). +//! \param msgID is the CAN message identifier used for the 11 or 29 bit +//! identifiers +//! \param frame is the CAN ID frame type +//! \param msgType is the message object type +//! \param msgIDMask is the CAN message identifier mask used when identifier +//! filtering is enabled +//! \param flags is the various flags and settings to be set for the message +//! object +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! +//! This function sets the various values required for a message object. +//! +//! The \e frame parameter can be one of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! +//! The \e msgType parameter can be one of the following values: +//! - \b CAN_MSG_OBJ_TYPE_TX - Transmit Message +//! - \b CAN_MSG_OBJ_TYPE_TX_REMOTE - Transmit Remote Message +//! - \b CAN_MSG_OBJ_TYPE_RX - Receive Message +//! - \b CAN_MSG_OBJ_TYPE_RXTX_REMOTE - Receive Remote message with +//! auto-transmit +//! +//! The \e flags parameter can be set as \b CAN_MSG_OBJ_NO_FLAGS if no flags +//! are required or the parameter can be a logical OR of any of the following +//! values: +//! - \b CAN_MSG_OBJ_TX_INT_ENABLE - Enable Transmit Interrupts +//! - \b CAN_MSG_OBJ_RX_INT_ENABLE - Enable Receive Interrupts +//! - \b CAN_MSG_OBJ_USE_ID_FILTER - Use filtering based on the Message ID +//! (Standard or Extended) +//! - \b CAN_MSG_OBJ_USE_EXT_FILTER - Use Extended Identifier Bit for filtering +//! (Only among Extended IDs will be accepted) +//! - \b CAN_MSG_OBJ_USE_DIR_FILTER - Use filtering based on the direction of +//! the transfer +//! - \b CAN_MSG_OBJ_FIFO - Message object is part of a FIFO +//! structure and isn't the final message +//! object in FIFO +//! +//! If filtering is based on message identifier (for Standard or Extended IDs) +//! specified by the \e msgIDMask parameter, the value \b CAN_MSG_OBJ_USE_ID_FILTER +//! has to be logically ORed with the \e flag parameter. +//! If \b CAN_MSG_OBJ_USE_EXT_FILTER is ORed with the \e flag parameter, +//! only extended identifier frames are accepted which can further be masked +//! by using the flag above. +//! +//! \note The \b msgLen Parameter for the Receive Message Object is a "don't +//! care" but its value should be between 0-8 due to the assert. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_setupMessageObject(uint32_t base, uint32_t objID, uint32_t msgID, + CAN_MsgFrameType frame, CAN_MsgObjType msgType, + uint32_t msgIDMask, uint32_t flags, uint16_t msgLen); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendMessage(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 16 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_16bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data (all 32 bits are sent) +//! +//! This function is used to transmit a message object and the message data, +//! if applicable. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_32bit(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint32_t *msgData); + +//***************************************************************************** +// +//! Sends a Message Object while dynamically updating data length +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! \param msgLen is the number of bytes of data in the message object (0-8) +//! \param msgData is a pointer to the message object's data +//! +//! This function is used to transmit a message object and the message data, +//! if applicable and can be used to dynamically update the data length +//! for every subsequent call of this function. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return None. +// +//***************************************************************************** + +extern void +CAN_sendMessage_updateDLC(uint32_t base, uint32_t objID, uint16_t msgLen, + const uint16_t *msgData); + +//***************************************************************************** +// +//! Sends a Remote Request Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to configure (1-32). +//! +//! This function is used to transmit a remote request message object. +//! +//! \note The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function with CAN_MSG_OBJ_TYPE_TX_REMOTE +//! as msgType flag. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_sendRemoteRequestMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Reads the data in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param msgData is a pointer to the array to store the message data +//! +//! This function is used to read the data contents of the specified message +//! object in the CAN controller. The data returned is stored in the +//! \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! -# If the DLC of the received message is larger than the \e msgData +//! buffer provided, then it is possible for a buffer overflow to occur. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool +CAN_readMessage(uint32_t base, uint32_t objID, + uint16_t *msgData); + +//***************************************************************************** +// +//! Reads the data and Message ID in a Message Object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the object number to read (1-32). +//! \param frameType is a pointer to the CAN_MsgFrameType to store the message +//! type that has been received in the mailbox +//! The \e frameType parameter shall be filled as of the following values: +//! - \b CAN_MSG_FRAME_STD - Standard 11 bit identifier +//! - \b CAN_MSG_FRAME_EXT - Extended 29 bit identifier +//! This parameter is filled when return value is true for this function. +//! \param msgID is a pointer to storage for the received Message ID +//! Filled when the return value is true for this function. +//! \param msgData is a pointer to the array to store the message data +//! Filled with read Data when the return value is true for this function. +//! +//! This function is used to read the data contents and the Message ID +//! of the specified message object in the CAN controller.The Message ID returned +//! is stored in the \e msgID parameter and its type in \e frameType parameter. +//! The data returned is stored in the \e msgData parameter. +//! +//! \note +//! -# The message object requested by the \e objID must first be setup +//! using the CAN_setupMessageObject() function. +//! +//! \return Returns \b true if new data was retrieved, else returns +//! \b false to indicate no new data was retrieved. +// +//***************************************************************************** +extern bool CAN_readMessageWithID(uint32_t base, + uint32_t objID, + CAN_MsgFrameType *frameType, + uint32_t *msgID, + uint16_t *msgData); + + + +//***************************************************************************** +// +//! Transfers a CAN message between the IF registers and Message RAM. +//! +//! \param base is the base address of the CAN controller. +//! \param interface is the interface to use for the transfer. Valid value are +//! 1 or 2. +//! \param objID is the object number to transfer (1-32). +//! \param direction is the direction of data transfer. False is Message RAM +//! to IF, True is IF to Message RAM. +//! +//! This function transfers the contents of the interface registers to message +//! RAM or vice versa depending on the value passed to direction. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_transferMessage(uint32_t base, uint16_t interface, uint32_t objID, + bool direction); + +//***************************************************************************** +// +//! Clears a message object so that it is no longer used. +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function frees(disables) the specified message object from use. Once +//! a message object has been cleared, it will no longer automatically send or +//! receive messages, or generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_clearMessage(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables specific message object +//! +//! \param base is the base address of the CAN controller. +//! \param objID is the message object number to disable (1-32). +//! +//! This function disables the specific message object. Once the message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableMessageObject(uint32_t base, uint32_t objID); + +//***************************************************************************** +// +//! Disables all message objects +//! +//! \param base is the base address of the CAN controller. +//! +//! This function disables all message objects. Once a message object +//! has been disabled it will be ignored by the message handler until it +//! is configured again. All message objects are disabled automatically on +//! reset, however this function can be used to restart CAN operations +//! without an external reset. +//! +//! \return None. +// +//***************************************************************************** +extern void +CAN_disableAllMessageObjects(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CAN_H diff --git a/gpio_driverlib_cpu1/device/driverlib/ccs/Debug/driverlib.lib b/gpio_driverlib_cpu1/device/driverlib/ccs/Debug/driverlib.lib new file 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100644 index 0000000..d933af4 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cla.c @@ -0,0 +1,89 @@ +//########################################################################### +// +// FILE: cla.c +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cla.h" + +//***************************************************************************** +// +// CLA_setTriggerSource() +// +//***************************************************************************** +void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger) +{ + uint32_t srcSelReg; + uint32_t shiftVal; + + // + // Calculate the shift value for the specified task. + // + shiftVal = ((uint32_t)taskNumber * SYSCTL_CLA1TASKSRCSEL1_TASK2_S) % 32U; + + // + // Calculate the register address for the specified task. + // + if(taskNumber <= CLA_TASK_4) + { + // + // Tasks 1-4 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL1; + } + else + { + // + // Tasks 5-8 + // + srcSelReg = (uint32_t)DMACLASRCSEL_BASE + SYSCTL_O_CLA1TASKSRCSEL2; + } + + EALLOW; + + // + // Write trigger selection to the appropriate register. + // + HWREG(srcSelReg) &= ~((uint32_t)SYSCTL_CLA1TASKSRCSEL1_TASK1_M + << shiftVal); + HWREG(srcSelReg) = HWREG(srcSelReg) | ((uint32_t)trigger << shiftVal); + + EDIS; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/cla.h b/gpio_driverlib_cpu1/device/driverlib/cla.h new file mode 100644 index 0000000..fee905c --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cla.h @@ -0,0 +1,984 @@ +//########################################################################### +// +// FILE: cla.h +// +// TITLE: CLA Driver Implementation File +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLA_H +#define CLA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cla_api CLA +//! \brief This module is used for configurating CLA. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "cpu.h" +#include "debug.h" +#include "inc/hw_cla.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CLA_NUM_EOT_INTERRUPTS (8U) + + +//***************************************************************************** +// +// Values that can be passed to CLA_clearTaskFlags(), CLA_forceTasks(), +// and CLA_enableTasks(), CLA_disableTasks(), and CLA_enableSoftwareInterrupt() +// as the taskFlags parameter. +// +//***************************************************************************** +#define CLA_TASKFLAG_1 (0x01U) //!< CLA Task 1 Flag +#define CLA_TASKFLAG_2 (0x02U) //!< CLA Task 2 Flag +#define CLA_TASKFLAG_3 (0x04U) //!< CLA Task 3 Flag +#define CLA_TASKFLAG_4 (0x08U) //!< CLA Task 4 Flag +#define CLA_TASKFLAG_5 (0x10U) //!< CLA Task 5 Flag +#define CLA_TASKFLAG_6 (0x20U) //!< CLA Task 6 Flag +#define CLA_TASKFLAG_7 (0x40U) //!< CLA Task 7 Flag +#define CLA_TASKFLAG_8 (0x80U) //!< CLA Task 8 Flag +#define CLA_TASKFLAG_ALL (0xFFU) //!< CLA All Task Flag + +//***************************************************************************** +// +//! Values that can be passed to CLA_getPendingTaskFlag(), +//! CLA_getTaskOverflowFlag(), CLA_getTaskRunStatus(), CLA_setTriggerSource(), +//! CLA_registerEndOfTaskInterrupt(), and CLA_unregisterEndOfTaskInterrupt() +//! as the taskNumber parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TASK_1, //!< CLA Task 1 + CLA_TASK_2, //!< CLA Task 2 + CLA_TASK_3, //!< CLA Task 3 + CLA_TASK_4, //!< CLA Task 4 + CLA_TASK_5, //!< CLA Task 5 + CLA_TASK_6, //!< CLA Task 6 + CLA_TASK_7, //!< CLA Task 7 + CLA_TASK_8 //!< CLA Task 8 +} CLA_TaskNumber; + +#ifdef __TMS320C28XX__ // These enums are only accessible by C28x +//***************************************************************************** +// +//! Values that can be passed to CLA_mapTaskVector() as the \e claIntVect +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_MVECT_1 = CLA_O_MVECT1, //!< Task Interrupt Vector 1 + CLA_MVECT_2 = CLA_O_MVECT2, //!< Task Interrupt Vector 2 + CLA_MVECT_3 = CLA_O_MVECT3, //!< Task Interrupt Vector 3 + CLA_MVECT_4 = CLA_O_MVECT4, //!< Task Interrupt Vector 4 + CLA_MVECT_5 = CLA_O_MVECT5, //!< Task Interrupt Vector 5 + CLA_MVECT_6 = CLA_O_MVECT6, //!< Task Interrupt Vector 6 + CLA_MVECT_7 = CLA_O_MVECT7, //!< Task Interrupt Vector 7 + CLA_MVECT_8 = CLA_O_MVECT8 //!< Task Interrupt Vector 8 +} CLA_MVECTNumber; + +//***************************************************************************** +// +//! Values that can be passed to CLA_setTriggerSource() as the \e trigger +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLA_TRIGGER_SOFTWARE = 0U, //!< CLA Task Trigger Source is Software + + CLA_TRIGGER_ADCA1 = 1U, //!< CLA Task Trigger Source is ADCA1 + CLA_TRIGGER_ADCA2 = 2U, //!< CLA Task Trigger Source is ADCA2 + CLA_TRIGGER_ADCA3 = 3U, //!< CLA Task Trigger Source is ADCA3 + CLA_TRIGGER_ADCA4 = 4U, //!< CLA Task Trigger Source is ADCA4 + CLA_TRIGGER_ADCAEVT = 5U, //!< CLA Task Trigger Source is ADCAEVT + CLA_TRIGGER_ADCB1 = 6U, //!< CLA Task Trigger Source is ADCB1 + CLA_TRIGGER_ADCB2 = 7U, //!< CLA Task Trigger Source is ADCB2 + CLA_TRIGGER_ADCB3 = 8U, //!< CLA Task Trigger Source is ADCB3 + CLA_TRIGGER_ADCB4 = 9U, //!< CLA Task Trigger Source is ADCB4 + CLA_TRIGGER_ADCBEVT = 10U, //!< CLA Task Trigger Source is ADCBEVT + CLA_TRIGGER_ADCC1 = 11U, //!< CLA Task Trigger Source is ADCC1 + CLA_TRIGGER_ADCC2 = 12U, //!< CLA Task Trigger Source is ADCC2 + CLA_TRIGGER_ADCC3 = 13U, //!< CLA Task Trigger Source is ADCC3 + CLA_TRIGGER_ADCC4 = 14U, //!< CLA Task Trigger Source is ADCC4 + CLA_TRIGGER_ADCCEVT = 15U, //!< CLA Task Trigger Source is ADCCEVT + CLA_TRIGGER_ADCD1 = 16U, //!< CLA Task Trigger Source is ADCD1 + CLA_TRIGGER_ADCD2 = 17U, //!< CLA Task Trigger Source is ADCD2 + CLA_TRIGGER_ADCD3 = 18U, //!< CLA Task Trigger Source is ADCD3 + CLA_TRIGGER_ADCD4 = 19U, //!< CLA Task Trigger Source is ADCD4 + CLA_TRIGGER_ADCDEVT = 20U, //!< CLA Task Trigger Source is ADCDEVT + + CLA_TRIGGER_XINT1 = 29U, //!< CLA Task Trigger Source is XINT1 + CLA_TRIGGER_XINT2 = 30U, //!< CLA Task Trigger Source is XINT2 + CLA_TRIGGER_XINT3 = 31U, //!< CLA Task Trigger Source is XINT3 + CLA_TRIGGER_XINT4 = 32U, //!< CLA Task Trigger Source is XINT4 + CLA_TRIGGER_XINT5 = 33U, //!< CLA Task Trigger Source is XINT5 + + CLA_TRIGGER_EPWM1INT = 36U, //!< CLA Task Trigger Source is EPWM1INT + CLA_TRIGGER_EPWM2INT = 37U, //!< CLA Task Trigger Source is EPWM2INT + CLA_TRIGGER_EPWM3INT = 38U, //!< CLA Task Trigger Source is EPWM3INT + CLA_TRIGGER_EPWM4INT = 39U, //!< CLA Task Trigger Source is EPWM4INT + CLA_TRIGGER_EPWM5INT = 40U, //!< CLA Task Trigger Source is EPWM5INT + CLA_TRIGGER_EPWM6INT = 41U, //!< CLA Task Trigger Source is EPWM6INT + CLA_TRIGGER_EPWM7INT = 42U, //!< CLA Task Trigger Source is EPWM7INT + CLA_TRIGGER_EPWM8INT = 43U, //!< CLA Task Trigger Source is EPWM8INT + CLA_TRIGGER_EPWM9INT = 44U, //!< CLA Task Trigger Source is EPWM9INT + CLA_TRIGGER_EPWM10INT = 45U, //!< CLA Task Trigger Source is EPWM10INT + CLA_TRIGGER_EPWM11INT = 46U, //!< CLA Task Trigger Source is EPWM11INT + CLA_TRIGGER_EPWM12INT = 47U, //!< CLA Task Trigger Source is EPWM12INT + + + CLA_TRIGGER_TINT0 = 68U, //!< CLA Task Trigger Source is TINT0 + CLA_TRIGGER_TINT1 = 69U, //!< CLA Task Trigger Source is TINT1 + CLA_TRIGGER_TINT2 = 70U, //!< CLA Task Trigger Source is TINT2 + + CLA_TRIGGER_MXINTA = 71U, //!< CLA Task Trigger Source is MXINTA + CLA_TRIGGER_MRINTA = 72U, //!< CLA Task Trigger Source is MRINTA + CLA_TRIGGER_MXINTB = 73U, //!< CLA Task Trigger Source is MXINTB + CLA_TRIGGER_MRINTB = 74U, //!< CLA Task Trigger Source is MRINTB + + CLA_TRIGGER_ECAP1INT = 75U, //!< CLA Task Trigger Source is ECAP1INT + CLA_TRIGGER_ECAP2INT = 76U, //!< CLA Task Trigger Source is ECAP2INT + CLA_TRIGGER_ECAP3INT = 77U, //!< CLA Task Trigger Source is ECAP3INT + CLA_TRIGGER_ECAP4INT = 78U, //!< CLA Task Trigger Source is ECAP4INT + CLA_TRIGGER_ECAP5INT = 79U, //!< CLA Task Trigger Source is ECAP5INT + CLA_TRIGGER_ECAP6INT = 80U, //!< CLA Task Trigger Source is ECAP6INT + + CLA_TRIGGER_EQEP1INT = 83U, //!< CLA Task Trigger Source is EQEP1INT + CLA_TRIGGER_EQEP2INT = 84U, //!< CLA Task Trigger Source is EQEP2INT + CLA_TRIGGER_EQEP3INT = 85U, //!< CLA Task Trigger Source is EQEP3INT + + + CLA_TRIGGER_SDFM1INT = 95U, //!< CLA Task Trigger Source is SDFM1INT + CLA_TRIGGER_SDFM2INT = 96U, //!< CLA Task Trigger Source is SDFM2INT + + + + CLA_TRIGGER_UPP1INT = 107U, //!< CLA Task Trigger Source is UPP1INT + + CLA_TRIGGER_SPITXAINT = 109U, //!< CLA Task Trigger Source is SPITXAINT + CLA_TRIGGER_SPIRXAINT = 110U, //!< CLA Task Trigger Source is SPIRXAINT + CLA_TRIGGER_SPITXBINT = 111U, //!< CLA Task Trigger Source is SPITXBINT + CLA_TRIGGER_SPIRXBINT = 112U, //!< CLA Task Trigger Source is SPIRXBINT + CLA_TRIGGER_SPITXCINT = 113U, //!< CLA Task Trigger Source is SPITXCINT + CLA_TRIGGER_SPIRXCINT = 114U, //!< CLA Task Trigger Source is SPIRXCINT + + + + + + CLA_TRIGGER_CLB1INT = 127, //!< CLA Task Trigger Source is CLB1INT + CLA_TRIGGER_CLB2INT = 128, //!< CLA Task Trigger Source is CLB2INT + CLA_TRIGGER_CLB3INT = 129, //!< CLA Task Trigger Source is CLB3INT + CLA_TRIGGER_CLB4INT = 130, //!< CLA Task Trigger Source is CLB4INT + +} CLA_Trigger; +#endif // __TMS320C28XX__ + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a CLA base address. +//! +//! \param base is the base address of the CLA controller. +//! +//! This function determines if a CLA controller base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CLA_isBaseValid(uint32_t base) +{ + return(base == CLA1_BASE); +} +#endif + +#ifdef __TMS320C28XX__ // These functions are only accessible from the C28x +//***************************************************************************** +// +//! Map CLA Task Interrupt Vector +//! +//! \param base is the base address of the CLA controller. +//! \param claIntVect is CLA interrupt vector (MVECT1 to MVECT8) +//! the value of claIntVect can be any of the following: +//! - \b CLA_MVECT_1 - Task Interrupt Vector 1 +//! - \b CLA_MVECT_2 - Task Interrupt Vector 2 +//! - \b CLA_MVECT_3 - Task Interrupt Vector 3 +//! - \b CLA_MVECT_4 - Task Interrupt Vector 4 +//! - \b CLA_MVECT_5 - Task Interrupt Vector 5 +//! - \b CLA_MVECT_6 - Task Interrupt Vector 6 +//! - \b CLA_MVECT_7 - Task Interrupt Vector 7 +//! - \b CLA_MVECT_8 - Task Interrupt Vector 8 +//! \param claTaskAddr is the start address of the code for task +//! +//! Each CLA Task (1 to 8) has its own MVECTx register. When a task is +//! triggered, the CLA loads the MVECTx register of the task in question +//! to the MPC (CLA program counter) and begins execution from that point. +//! The CLA has a 16-bit address bus, and can therefore, access the lower +//! 64 KW space. The MVECTx registers take an address anywhere in this space. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_mapTaskVector(uint32_t base, CLA_MVECTNumber claIntVect, + uint16_t claTaskAddr) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + HWREGH(base + (uint16_t)claIntVect) = claTaskAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Hard Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a hard reset of the CLA and set all CLA registers +//! to their default state. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performHardReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Hard reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_HARDRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! Soft Reset +//! +//! \param base is the base address of the CLA controller. +//! +//! This function will cause a soft reset of the CLA. This will stop the +//! current task, clear the MIRUN flag and clear all bits in the MIER register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_performSoftReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Soft reset of the CLA + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_SOFTRESET; + + EDIS; + + // + // Wait for few cycles till the reset is complete + // + NOP; + NOP; + NOP; +} + +//***************************************************************************** +// +//! IACK enable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function enables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) |= CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! IACK disable +//! +//! \param base is the base address of the CLA controller. +//! +//! This function disables the main CPU to use the IACK #16bit instruction to +//! set MIFR bits in the same manner as writing to the MIFRC register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableIACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable the main CPU to use the IACK #16bit instruction + // + HWREGH(base + CLA_O_MCTL) &= ~CLA_MCTL_IACKE; + + EDIS; +} + +//***************************************************************************** +// +//! Query task N to see if it is flagged and pending execution +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the interrupt flag register +//! corresponds to a CLA task. The corresponding bit is automatically set +//! when the task is triggered (either from a peripheral, through software, or +//! through the MIFRC register). The bit gets cleared when the CLA starts to +//! execute the flagged task. +//! +//! \return \b True if the queried task has been triggered but pending +//! execution. +// +//***************************************************************************** +static inline bool +CLA_getPendingTaskFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIFR) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the interrupt flag register (MIFR) +//! +//! \return the value of Interrupt Flag Register (MIFR) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllPendingTaskFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Flag Register (MIFR) since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIFR); + + // + // Return the Interrupt Flag Register value + // + return(status); +} + +//***************************************************************************** +// +//! Get status of Task n Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the overflow flag register +//! corresponds to a CLA task, This bit is set when an interrupt overflow event +//! has occurred for the specific task. +//! +//! \return True if any of task interrupt overflow has occurred. +// +//***************************************************************************** +static inline bool +CLA_getTaskOverflowFlag(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIOVF) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get status of All Task Interrupt Overflow Flag +//! +//! \param base is the base address of the CLA controller. +//! +//! This function gets the value of the Interrupt Overflow Flag Register +//! +//! \return the value of Interrupt Overflow Flag Register(MIOVF) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskOverflowFlags(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return Interrupt Overflow Flag Register(MIOVF) since that is what + // was requested. + // + status = HWREGH(base + CLA_O_MIOVF); + + // + // Return the Interrupt Overflow Flag Register + // + return(status); +} + +//***************************************************************************** +// +//! Clear the task interrupt flag +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be cleared +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to clear all flags. +//! +//! This function is used to manually clear bits in the interrupt +//! flag (MIFR) register +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_clearTaskFlags(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + //Modify protected register + // + EALLOW; + + // + // Clear the task interrupt flag + // + HWREGH(base + CLA_O_MICLR) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Force a CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be forced +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to force all tasks. +//! +//! This function forces a task through software. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Force the task interrupt. + // + HWREGH(base + CLA_O_MIFRC) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enable CLA task(s) +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be enabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to enable all tasks +//! +//! This function allows an incoming interrupt or main CPU software to +//! start the corresponding CLA task. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Enable CLA task + // + HWREGH(base + CLA_O_MIER) |= taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disable CLA task interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks' flags to be disabled +//! CLA_TASKFLAG_N where N is the task number from 1 to 8, or CLA_TASKFLAG_ALL +//! to disable all tasks +//! +//! This function disables CLA task interrupt by setting the MIER register bit +//! to 0, while the corresponding task is executing this will have no effect +//! on the task. The task will continue to run until it hits the MSTOP +//! instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableTasks(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + EALLOW; + + // + // Disable CLA task interrupt + // + HWREGH(base + CLA_O_MIER) &= ~taskFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Get the value of a task run status +//! +//! \param base is the base address of the CLA controller. +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. Do not use CLA_TASKFLAG_ALL. +//! +//! This function gets the status of each bit in the Interrupt Run Status +//! Register which indicates whether the task is currently executing +//! +//! \return True if the task is executing. +// +//***************************************************************************** +static inline bool +CLA_getTaskRunStatus(uint32_t base, CLA_TaskNumber taskNumber) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Read the run status register and return the appropriate value. + // + return(((HWREGH(base + CLA_O_MIRUN) >> (uint16_t)taskNumber) & 1U) != 0U); +} + +//***************************************************************************** +// +//! Get the value of all task run status +//! +//! \param base is the base address of the CLA controller. +//! +//! This function indicates which task is currently executing. +//! +//! \return the value of Interrupt Run Status Register (MIRUN) +// +//***************************************************************************** +static inline uint16_t +CLA_getAllTaskRunStatus(uint32_t base) +{ + uint16_t status; + + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Just return the Interrupt Run Status Register since that is what was + // requested. + // + status = HWREGH(base + CLA_O_MIRUN); + + // + // Return the Interrupt Run Status Register (MIRUN) + // + return(status); +} +#endif // #ifdef __TMS320C28XX__ + +// +// These functions are accessible only from the CLA (Type - 1/2) +// +#if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) +//***************************************************************************** +// +//! Enable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be enabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to enable software interrupts of all tasks +//! +//! This function enables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1SOFTINTEN register. By setting a task's SOFTINT bit, you disable its +//! ability to generate an end-of-task interrupt +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_enableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) |= taskFlags; + + __medis(); +} + +//***************************************************************************** +// +//! Disable the Software Interrupt for a given CLA Task +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the tasks for which software +//! interrupts are to be disabled, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to disable software interrupts of all +//! tasks +//! +//! This function disables the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 0 to the task's bit in the +//! CLA1SOFTINTEN register. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Disabling a given task's software interrupt ability allows that +//! task to generate an End-of-Task interrupt to the main CPU. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_disableSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Enable Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTEN) &= ~taskFlags; + + __medis(); +} +//***************************************************************************** +// +//! Force a particular Task's Software Interrupt +//! +//! \param base is the base address of the CLA controller. +//! \param taskFlags is the bitwise OR of the task's whose software +//! interrupts are to be forced, CLA_TASKFLAG_N where N is the task number +//! from 1 to 8, or CLA_TASKFLAG_ALL to force software interrupts for all tasks +//! +//! This function forces the Software Interrupt for a single, or set of, CLA +//! task(s). It does this by writing a 1 to the task's bit in the +//! CLA1INTFRC register. +//! For example, if we enable Task 2's SOFTINT bit, we disable its ability to +//! generate an end-of-task interrupt, but now any running CLA task has the +//! ability to force task 2's interrupt (through the CLA1INTFRC register) to +//! the main CPU. This interrupt will be handled by the End-of-Task 2 interrupt +//! handler even though the interrupt was not caused by Task 2 running to +//! completion. This allows programmers to generate interrupts while a control +//! task is running. +//! +//! \note +//! -# The CLA1SOFTINTEN and CLA1INTFRC are only writable from the CLA. +//! -# Enabling a given task's software interrupt enable bit disables that +//! task's ability to generate an End-of-Task interrupt to the main CPU, +//! however, should another task force its interrupt (through the CLA1INTFRC +//! register), it will be handled by that task's End-of-Task Interrupt Handler. +//! -# This function will set the INTFRC bit for a task, but does not check +//! that its SOFTINT bit is set. It falls to the user to ensure that software +//! interrupt for a given task is enabled before it can be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CLA_forceSoftwareInterrupt(uint32_t base, uint16_t taskFlags) +{ + // + // Check the arguments. + // + ASSERT(CLA_isBaseValid(base)); + + // + // Modify protected register + // + __meallow(); + + // + // Force Software Interrupt + // + HWREGH(base + CLA_O_SOFTINTFRC) |= taskFlags; + + __medis(); +} + +#endif // #if defined(__TMS320C28XX_CLA1__) || defined(__TMS320C28XX_CLA2__) + +// +// These functions can only be called from the C28x +// +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! Configures CLA task triggers. +//! +//! \param taskNumber is the number of the task CLA_TASK_N where N is a number +//! from 1 to 8. +//! \param trigger is the trigger source to be assigned to the selected task. +//! +//! This function configures the trigger source of a CLA task. The +//! \e taskNumber parameter indicates which task is being configured, and the +//! \e trigger parameter is the interrupt source from a specific peripheral +//! interrupt (or software) that will trigger the task. +//! +//! \return None. +// +//***************************************************************************** +extern void +CLA_setTriggerSource(CLA_TaskNumber taskNumber, CLA_Trigger trigger); + +#endif //#ifdef __TMS320C28XX__ +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLA_H diff --git a/gpio_driverlib_cpu1/device/driverlib/clb.c b/gpio_driverlib_cpu1/device/driverlib/clb.c new file mode 100644 index 0000000..2e79cb4 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/clb.c @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: clb.c +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "clb.h" + +//***************************************************************************** +// +// CLB_configCounterLoadMatch +// +//***************************************************************************** +void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, uint32_t match2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + switch(counterID) + { + case CLB_CTR0: + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_0_MATCH2, match2); + break; + + case CLB_CTR1: + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_1_MATCH2, match2); + break; + + case CLB_CTR2: + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_LOAD, load); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH1, match1); + CLB_writeInterface(base, CLB_ADDR_COUNTER_2_MATCH2, match2); + break; + + default: + // + // Invalid counterID value + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// CLB_clearFIFOs +// +//***************************************************************************** +void CLB_clearFIFOs(uint32_t base) +{ + uint16_t i; + + ASSERT(CLB_isBaseValid(base)); + + for(i = 0U; i < CLB_FIFO_SIZE; i++) + { + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(i)) = 0U; + } + + HWREG(base + CLB_LOGICCTL + CLB_O_BUF_PTR) = 0U; +} + +//***************************************************************************** +// +// CLB_writeFIFOs +// +//***************************************************************************** +void CLB_writeFIFOs(uint32_t base , const uint32_t pullData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Clear the FIFO and pointer + // + CLB_clearFIFOs(base); + + // + // Write data into the FIFO. + // + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(0U)) = pullData[0U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(1U)) = pullData[1U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(2U)) = pullData[2U]; + HWREG(base + CLB_DATAEXCH + CLB_O_PULL(3U)) = pullData[3U]; +} + +//***************************************************************************** +// +// CLB_readFIFOs +// +//***************************************************************************** +void CLB_readFIFOs(uint32_t base , uint32_t pushData[]) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Read data from the FIFO. + // + pushData[0U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(0U)) ; + pushData[1U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(1U)) ; + pushData[2U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(2U)) ; + pushData[3U] = HWREG(base + CLB_DATAEXCH + CLB_O_PUSH(3U)) ; +} + + diff --git a/gpio_driverlib_cpu1/device/driverlib/clb.h b/gpio_driverlib_cpu1/device/driverlib/clb.h new file mode 100644 index 0000000..37cb68f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/clb.h @@ -0,0 +1,1290 @@ +//########################################################################### +// +// FILE: clb.h +// +// TITLE: C28x CLB driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CLB_H +#define CLB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup clb_api CLB +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clb.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Address offsets from LOGICCFG to LOGICCTL and DATAEXCH register memory maps +// +//***************************************************************************** +#define CLB_LOGICCTL 0x0100U +#define CLB_DATAEXCH 0x0200U + +//***************************************************************************** +// +// Address offsets for CLB-internal memory space +// +//***************************************************************************** +#define CLB_ADDR_COUNTER_0_LOAD 0x0U +#define CLB_ADDR_COUNTER_1_LOAD 0x1U +#define CLB_ADDR_COUNTER_2_LOAD 0x2U + +#define CLB_ADDR_COUNTER_0_MATCH1 0x4U +#define CLB_ADDR_COUNTER_1_MATCH1 0x5U +#define CLB_ADDR_COUNTER_2_MATCH1 0x6U + +#define CLB_ADDR_COUNTER_0_MATCH2 0x8U +#define CLB_ADDR_COUNTER_1_MATCH2 0x9U +#define CLB_ADDR_COUNTER_2_MATCH2 0xAU + +#define CLB_ADDR_HLC_R0 0xCU +#define CLB_ADDR_HLC_R1 0xDU +#define CLB_ADDR_HLC_R2 0xEU +#define CLB_ADDR_HLC_R3 0xFU + +#define CLB_ADDR_HLC_BASE 0x20U +#define CLB_NUM_HLC_INSTR 31U + +//***************************************************************************** +// +// PUSH/PULL FIFO size (32-bit registers) +// +//***************************************************************************** +#define CLB_FIFO_SIZE 4U + +//***************************************************************************** +// +// Key to enable writes to the CLB registers +// +//***************************************************************************** +#define CLB_LOCK_KEY 0x5A5AU + +//***************************************************************************** +// +// Shift and masks needed by the API for Input selection +// +//***************************************************************************** +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_M 0x20U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_S 28U +#define CLB_LCL_MUX_SEL_MISC_INPUT_SEL_BITM (uint32_t)1U + +//***************************************************************************** +// +//! Values that can be passed to control the CLB output enable signal. It can +//! be passed to CLB_setOutputMask() as the \e outputMask parameter. +// +//***************************************************************************** +#define CLB_OUTPUT_00 0x00000001U //!< Mask for CLB OUTPUT ENABLE/DISABLE 0 +#define CLB_OUTPUT_01 0x00000002U //!< Mask for CLB OUTPUT ENABLE/DISABLE 1 +#define CLB_OUTPUT_02 0x00000004U //!< Mask for CLB OUTPUT ENABLE/DISABLE 2 +#define CLB_OUTPUT_03 0x00000008U //!< Mask for CLB OUTPUT ENABLE/DISABLE 3 +#define CLB_OUTPUT_04 0x00000010U //!< Mask for CLB OUTPUT ENABLE/DISABLE 4 +#define CLB_OUTPUT_05 0x00000020U //!< Mask for CLB OUTPUT ENABLE/DISABLE 5 +#define CLB_OUTPUT_06 0x00000040U //!< Mask for CLB OUTPUT ENABLE/DISABLE 6 +#define CLB_OUTPUT_07 0x00000080U //!< Mask for CLB OUTPUT ENABLE/DISABLE 7 +#define CLB_OUTPUT_08 0x00000100U //!< Mask for CLB OUTPUT ENABLE/DISABLE 8 +#define CLB_OUTPUT_09 0x00000200U //!< Mask for CLB OUTPUT ENABLE/DISABLE 9 +#define CLB_OUTPUT_10 0x00000400U //!< Mask for CLB OUTPUT ENABLE/DISABLE 10 +#define CLB_OUTPUT_11 0x00000800U //!< Mask for CLB OUTPUT ENABLE/DISABLE 11 +#define CLB_OUTPUT_12 0x00001000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 12 +#define CLB_OUTPUT_13 0x00002000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 13 +#define CLB_OUTPUT_14 0x00004000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 14 +#define CLB_OUTPUT_15 0x00008000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 15 +#define CLB_OUTPUT_16 0x00010000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 16 +#define CLB_OUTPUT_17 0x00020000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 17 +#define CLB_OUTPUT_18 0x00040000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 18 +#define CLB_OUTPUT_19 0x00080000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 19 +#define CLB_OUTPUT_20 0x00100000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 20 +#define CLB_OUTPUT_21 0x00200000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 21 +#define CLB_OUTPUT_22 0x00400000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 22 +#define CLB_OUTPUT_23 0x00800000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 23 +#define CLB_OUTPUT_24 0x01000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 24 +#define CLB_OUTPUT_25 0x02000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 25 +#define CLB_OUTPUT_26 0x04000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 26 +#define CLB_OUTPUT_27 0x08000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 27 +#define CLB_OUTPUT_28 0x10000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 28 +#define CLB_OUTPUT_29 0x20000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 29 +#define CLB_OUTPUT_30 0x40000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 30 +#define CLB_OUTPUT_31 0x80000000U //!< Mask for CLB OUTPUT ENABLE/DISABLE 31 + +//***************************************************************************** +// +//! Values that can be passed to select CLB input signal +// +//***************************************************************************** +typedef enum +{ + CLB_IN0 = 0, //!< Input 0 + CLB_IN1 = 1, //!< Input 1 + CLB_IN2 = 2, //!< Input 2 + CLB_IN3 = 3, //!< Input 3 + CLB_IN4 = 4, //!< Input 4 + CLB_IN5 = 5, //!< Input 5 + CLB_IN6 = 6, //!< Input 6 + CLB_IN7 = 7 //!< Input 7 +} CLB_Inputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB output signal. It can be passed to +//! CLB_configOutputLUT() as the \e outID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_OUT0 = 0, //!< Output 0 + CLB_OUT1 = 1, //!< Output 1 + CLB_OUT2 = 2, //!< Output 2 + CLB_OUT3 = 3, //!< Output 3 + CLB_OUT4 = 4, //!< Output 4 + CLB_OUT5 = 5, //!< Output 5 + CLB_OUT6 = 6, //!< Output 6 + CLB_OUT7 = 7 //!< Output 7 +} CLB_Outputs; + +//***************************************************************************** +// +//! Values that can be passed to select CLB counter. It can be passed to +//! CLB_configCounterLoadMatch() as the \e counterID parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_CTR0 = 0, //!< Counter 0 + CLB_CTR1 = 1, //!< Counter 1 + CLB_CTR2 = 2 //!< Counter 2 +} CLB_Counters; + +//***************************************************************************** +// +//! Values that can be passed to CLB_getRegister() as the \e registerID +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_REG_HLC_R0 = CLB_O_DBG_R0, //!< HLC R0 register + CLB_REG_HLC_R1 = CLB_O_DBG_R1, //!< HLC R1 register + CLB_REG_HLC_R2 = CLB_O_DBG_R2, //!< HLC R2 register + CLB_REG_HLC_R3 = CLB_O_DBG_R3, //!< HLC R3 register + CLB_REG_CTR_C0 = CLB_O_DBG_C0, //!< Counter 0 register + CLB_REG_CTR_C1 = CLB_O_DBG_C1, //!< Counter 1 register + CLB_REG_CTR_C2 = CLB_O_DBG_C2 //!< Counter 2 register +} CLB_Register; + +//***************************************************************************** +// +//! Values that can be passed to CLB_selectInputFilter() as the \e filterType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_FILTER_NONE = 0, //!< No filtering + CLB_FILTER_RISING_EDGE = 1, //!< Rising edge detect + CLB_FILTER_FALLING_EDGE = 2, //!< Falling edge detect + CLB_FILTER_ANY_EDGE = 3 //!< Any edge detect +} CLB_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGPInputMux() as the \e gpMuxCfg +//! parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GP_IN_MUX_EXTERNAL = 0, //!< Use external input path + CLB_GP_IN_MUX_GP_REG = 1 //!< Use CLB_GP_REG bit value as input +} CLB_GPInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configLocalInputMux() as the +//! \e localMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_LOCAL_IN_MUX_GLOBAL_IN = 0, //!< Global input mux selection + CLB_LOCAL_IN_MUX_EPWM_DCAEVT1 = 1, //!< EPWMx DCAEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCAEVT2 = 2, //!< EPWMx DCAEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT1 = 3, //!< EPWMx DCBEVT1 + CLB_LOCAL_IN_MUX_EPWM_DCBEVT2 = 4, //!< EPWMx DCBEVT2 + CLB_LOCAL_IN_MUX_EPWM_DCAH = 5, //!< EPWMx DCAH + CLB_LOCAL_IN_MUX_EPWM_DCAL = 6, //!< EPWMx DCAL + CLB_LOCAL_IN_MUX_EPWM_DCBH = 7, //!< EPWMx DCBH + CLB_LOCAL_IN_MUX_EPWM_DCBL = 8, //!< EPWMx DCBL + CLB_LOCAL_IN_MUX_EPWM_OST = 9, //!< EPWMx OST + CLB_LOCAL_IN_MUX_EPWM_CBC = 10, //!< EPWMx CBC + CLB_LOCAL_IN_MUX_ECAP_ECAPIN = 11, //!< ECAPx ECAPIN + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT = 12, //!< ECAPx ECAP_OUT + CLB_LOCAL_IN_MUX_ECAP_ECAP_OUT_EN = 13, //!< ECAPx ECAP_OUT_EN + CLB_LOCAL_IN_MUX_ECAP_CEVT1 = 14, //!< ECAPx CEVT1 + CLB_LOCAL_IN_MUX_ECAP_CEVT2 = 15, //!< ECAPx CEVT2 + CLB_LOCAL_IN_MUX_ECAP_CEVT3 = 16, //!< ECAPx CEVT3 + CLB_LOCAL_IN_MUX_ECAP_CEVT4 = 17, //!< ECAPx CEVT4 + CLB_LOCAL_IN_MUX_EQEP_EQEPA = 18, //!< EQEPx EQEPA + CLB_LOCAL_IN_MUX_EQEP_EQEPB = 19, //!< EQEPx EQEPB + CLB_LOCAL_IN_MUX_EQEP_EQEPI = 20, //!< EQEPx EQEPI + CLB_LOCAL_IN_MUX_EQEP_EQEPS = 21, //!< EQEPx EQEPS + CLB_LOCAL_IN_MUX_CPU1_TBCLKSYNC = 22, //!< CPU1.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU2_TBCLKSYNC = 23, //!< CPU2.TBCLKSYNC + CLB_LOCAL_IN_MUX_CPU1_HALT = 24, //!< CPU1.HALT + CLB_LOCAL_IN_MUX_CPU2_HALT = 25, //!< CPU2.HALT +} CLB_LocalInputMux; + +//***************************************************************************** +// +//! Values that can be passed to CLB_configGlobalInputMux() as the +//! \e globalMuxCfg parameter. +// +//***************************************************************************** +typedef enum +{ + CLB_GLOBAL_IN_MUX_EPWM1A = 0, //!< EPWM1A + CLB_GLOBAL_IN_MUX_EPWM1A_OE = 1, //!< EPWM1A trip output + CLB_GLOBAL_IN_MUX_EPWM1B = 2, //!< EPWM1B + CLB_GLOBAL_IN_MUX_EPWM1B_OE = 3, //!< EPWM1B trip output + CLB_GLOBAL_IN_MUX_EPWM1_CTR_ZERO = 4, //!< EPWM1 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM1_CTR_PRD = 5, //!< EPWM1 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM1_CTRDIR = 6, //!< EPWM1 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM1_TBCLK = 7, //!< EPWM1 TBCLK + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPA = 8, //!< EPWM1 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPB = 9, //!< EPWM1 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPC = 10, //!< EPWM1 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM1_CTR_CMPD = 11, //!< EPWM1 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM1A_AQ = 12, //!< EPWM1A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_AQ = 13, //!< EPWM1B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM1A_DB = 14, //!< EPWM1A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM1B_DB = 15, //!< EPWM1B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM2A = 16, //!< EPWM2A + CLB_GLOBAL_IN_MUX_EPWM2A_OE = 17, //!< EPWM2A trip output + CLB_GLOBAL_IN_MUX_EPWM2B = 18, //!< EPWM2B + CLB_GLOBAL_IN_MUX_EPWM2B_OE = 19, //!< EPWM2B trip output + CLB_GLOBAL_IN_MUX_EPWM2_CTR_ZERO = 20, //!< EPWM2 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM2_CTR_PRD = 21, //!< EPWM2 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM2_CTRDIR = 22, //!< EPWM2 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM2_TBCLK = 23, //!< EPWM2 TBCLK + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPA = 24, //!< EPWM2 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPB = 25, //!< EPWM2 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPC = 26, //!< EPWM2 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM2_CTR_CMPD = 27, //!< EPWM2 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM2A_AQ = 28, //!< EPWM2A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_AQ = 29, //!< EPWM2B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM2A_DB = 30, //!< EPWM2A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM2B_DB = 31, //!< EPWM2B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM3A = 32, //!< EPWM3A + CLB_GLOBAL_IN_MUX_EPWM3A_OE = 33, //!< EPWM3A trip output + CLB_GLOBAL_IN_MUX_EPWM3B = 34, //!< EPWM3B + CLB_GLOBAL_IN_MUX_EPWM3B_OE = 35, //!< EPWM3B trip output + CLB_GLOBAL_IN_MUX_EPWM3_CTR_ZERO = 36, //!< EPWM3 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM3_CTR_PRD = 37, //!< EPWM3 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM3_CTRDIR = 38, //!< EPWM3 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM3_TBCLK = 39, //!< EPWM3 TBCLK + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPA = 40, //!< EPWM3 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPB = 41, //!< EPWM3 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPC = 42, //!< EPWM3 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM3_CTR_CMPD = 43, //!< EPWM3 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM3A_AQ = 44, //!< EPWM3A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_AQ = 45, //!< EPWM3B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM3A_DB = 46, //!< EPWM3A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM3B_DB = 47, //!< EPWM3B DB submodule output + + CLB_GLOBAL_IN_MUX_EPWM4A = 48, //!< EPWM4A + CLB_GLOBAL_IN_MUX_EPWM4A_OE = 49, //!< EPWM4A trip output + CLB_GLOBAL_IN_MUX_EPWM4B = 50, //!< EPWM4B + CLB_GLOBAL_IN_MUX_EPWM4B_OE = 51, //!< EPWM4B trip output + CLB_GLOBAL_IN_MUX_EPWM4_CTR_ZERO = 52, //!< EPWM4 TBCTR = Zero + CLB_GLOBAL_IN_MUX_EPWM4_CTR_PRD = 53, //!< EPWM4 TBCTR = TBPRD + CLB_GLOBAL_IN_MUX_EPWM4_CTRDIR = 54, //!< EPWM4 CTRDIR + CLB_GLOBAL_IN_MUX_EPWM4_TBCLK = 55, //!< EPWM4 TBCLK + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPA = 56, //!< EPWM4 TBCTR = CMPA + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPB = 57, //!< EPWM4 TBCTR = CMPB + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPC = 58, //!< EPWM4 TBCTR = CMPC + CLB_GLOBAL_IN_MUX_EPWM4_CTR_CMPD = 59, //!< EPWM4 TBCTR = CMPD + CLB_GLOBAL_IN_MUX_EPWM4A_AQ = 60, //!< EPWM4A AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_AQ = 61, //!< EPWM4B AQ submodule output + CLB_GLOBAL_IN_MUX_EPWM4A_DB = 62, //!< EPWM4A DB submodule output + CLB_GLOBAL_IN_MUX_EPWM4B_DB = 63, //!< EPWM4B DB submodule output + + CLB_GLOBAL_IN_MUX_CLB_AUXSIG0 = 64, //!< CLB X-BAR AUXSIG0 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG1 = 65, //!< CLB X-BAR AUXSIG1 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG2 = 66, //!< CLB X-BAR AUXSIG2 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG3 = 67, //!< CLB X-BAR AUXSIG3 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG4 = 68, //!< CLB X-BAR AUXSIG4 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG5 = 69, //!< CLB X-BAR AUXSIG5 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG6 = 70, //!< CLB X-BAR AUXSIG6 + CLB_GLOBAL_IN_MUX_CLB_AUXSIG7 = 71, //!< CLB X-BAR AUXSIG7 + +} CLB_GlobalInputMux; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +// +//! +//! Checks the CLB base address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CLB_isBaseValid(uint32_t base) +{ + return( + (base == CLB1_BASE) || + (base == CLB2_BASE) || + (base == CLB3_BASE) || + (base == CLB4_BASE) + ); +} + +//***************************************************************************** +// +//! +//! Checks the CLB internal memory address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function determines if a CLB base address is valid. +//! +//! \return Returns \b true if the address is valid and \b false otherwise. +// +//***************************************************************************** +static inline bool CLB_isAddressValid(uint32_t address) +{ + return(address <= (CLB_ADDR_HLC_BASE + CLB_NUM_HLC_INSTR)); +} +#endif + +//***************************************************************************** +// +//! Set global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Clear global enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function disables the CLB via global enable register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableCLB(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREGH(base + CLB_LOGICCTL + CLB_O_LOAD_EN) &= ~CLB_LOAD_EN_GLOBAL_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enable CLB lock. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function enables the lock bit of the lock register. The lock can only +//! be set once and can only be cleared by a device reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableLock(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + // + // Setting the lock bit requires key 0x5A5A to be written at the same time + // + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOCK) = + (uint32_t)CLB_LOCK_LOCK | ((uint32_t)CLB_LOCK_KEY << CLB_LOCK_KEY_S); + EDIS; +} + +//***************************************************************************** +// +//! Write value to address. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param address is the address of CLB internal memory. +//! \param value is the value to write to specified address. +//! +//! This function writes the specified value to CLB internal memory. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_writeInterface(uint32_t base, uint32_t address, + uint32_t value) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(CLB_isAddressValid(address)); + + EALLOW; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_ADDR) = address; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_DATA) = value; + HWREG(base + CLB_LOGICCTL + CLB_O_LOAD_EN) |= CLB_LOAD_EN_LOAD_EN; + EDIS; +} + +//***************************************************************************** +// +//! Select input filter type. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param filterType is the selected type of filter applied to the input. +//! +//! This function configures the filter selection for the specified input. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e filterType parameter can have one enumeration value from +//! CLB_FilterType. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectInputFilter(uint32_t base, CLB_Inputs inID, + CLB_FilterType filterType) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 2-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID << 1; + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER) & + ~(CLB_INPUT_FILTER_FIN0_M << shiftVal)) | + ((uint16_t)filterType << shiftVal); +} + +//***************************************************************************** +// +//! Enables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function enables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_enableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) |= + (1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Disables synchronization of an input signal. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! +//! This function disables synchronization on the specified input signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_disableSynchronization(uint32_t base, CLB_Inputs inID) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INPUT_FILTER + 1U) &= + ~(1U << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Configures the general purpose input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param gpMuxCfg is the mux selection for the general purpose input mux. +//! +//! This function configures the general purpose input mux. The \e gpMuxCfg +//! parameter can select either the use of an external input signal +//! (\b CLB_GP_IN_MUX_EXTERNAL) or the use of the corresponding CLB_GP_REG bit +//! as an input (\b CLB_GP_IN_MUX_GP_REG). +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! +//! \sa CLB_setGPREG() to write to the CLB_GP_REG. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGPInputMux(uint32_t base, CLB_Inputs inID, + CLB_GPInputMux gpMuxCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) = + (HWREGH(base + CLB_LOGICCTL + CLB_O_IN_MUX_SEL_0) & + ~(CLB_IN_MUX_SEL_0_SEL_GP_IN_0 << (uint16_t)inID)) | + ((uint16_t)gpMuxCfg << (uint16_t)inID); +} + +//***************************************************************************** +// +//! Sets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param gpRegVal is the value to be written to CLB_GP_REG. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setGPREG(uint32_t base, uint32_t gpRegVal) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG) = gpRegVal; +} + +//***************************************************************************** +// +//! Gets the CLB_GP_REG register value. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function writes to the CLB_GP_REG register. When the general purpose +//! input mux is configured to use CLB_GP_REG, each bit in \e gpRegVal +//! corresponds to an input signal (bit 0 to Input 0, bit 1 to Input 1, and +//! so on). +//! +//! \sa CLB_configGPInputMux() to select the CLB_GP_REG as the source for +//! an input signal. +//! +//! \return CLB_GP_REG value. +// +//***************************************************************************** +static inline uint32_t CLB_getGPREG(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_GP_REG)); +} + +//***************************************************************************** +// +//! Configures the local input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param localMuxCfg is the mux selection for the local input mux. +//! +//! This function configures the local input mux for the specified input +//! signal. +//! +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e localMuxCfg parameter can have one enumeration value from +//! CLB_LocalInputMux. +//! +//! \note The local input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLocalInputMux(uint32_t base, CLB_Inputs inID, + CLB_LocalInputMux localMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each local input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_1) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } + else + { + // + // Calculating shift amount for inputs > input3 + // + shiftVal -= 4U * CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_LCL_MUX_SEL_2) & + ~((uint32_t)CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)localMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Configures the global input mux. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param inID is the specified CLB tile input signal. +//! \param globalMuxCfg is the mux selection for the global input mux. +//! +//! This function configures the global input mux for the specified input +//! signal. +//! The \e inID parameter can have one enumeration value from CLB_Inputs. +//! The \e globalMuxCfg parameter can have one enumeration value from +//! CLB_GlobalInputMux. +//! +//! \note The global input mux options' peripheral sources depend on which +//! instance of the CLB (\e base) you are using. For example, for CLB1 the +//! EPWM signal selections come from EPWM1 but for CLB2 they come from EPWM2. +//! See your technical reference manual for details. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configGlobalInputMux(uint32_t base, CLB_Inputs inID, + CLB_GlobalInputMux globalMuxCfg) +{ + uint16_t shiftVal; + + ASSERT(CLB_isBaseValid(base)); + + // + // Each input has a 5-bit field in this register so need to calculate + // shift amount accordingly. + // + shiftVal = (uint16_t)inID * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + + if(inID < CLB_IN4) + { + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_1) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } + else + { + shiftVal -= 4U * CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S; + HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) = + (HWREG(base + CLB_LOGICCTL + CLB_O_GLBL_MUX_SEL_2) & + ~((uint32_t)CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M << shiftVal)) | + ((uint32_t)globalMuxCfg << shiftVal); + } +} + +//***************************************************************************** +// +//! Controls the output enable. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outputMask is a mask of the outputs to be enabled. +//! \param enable is a switch to decide if the CLB outputs need to be enabled +//! or not. +//! +//! This function is used to enable and disable CLB outputs by writing a mask +//! to CLB_OUT_EN. Each bit corresponds to a CLB output. When a bit is 1, the +//! corresponding output is enabled; when a bit is 0, the output is disabled. +//! +//! The \e outputMask parameter takes a logical OR of any of the CLB_OUTPUT_0x +//! values that correspond to the CLB OUTPUT ENABLE for the respective outputs. +//! The \e enable parameter can have one of the values from: +//! false: Disable the respective CLB outputs +//! true: Enable the respective CLB outputs +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setOutputMask(uint32_t base, uint32_t outputMask , + bool enable) +{ + ASSERT(CLB_isBaseValid(base)); + + if(enable == true) + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) |= outputMask; + } + else + { + HWREG(base + CLB_LOGICCTL + CLB_O_OUT_EN) &= ~outputMask; + } +} + +//***************************************************************************** +// +//! Reads the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the value in the interrupt tag register which is a 6-bit +//! constant set by the HLC. +// +//***************************************************************************** +static inline uint16_t CLB_getInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG)); +} + +//***************************************************************************** +// +//! Clears the interrupt tag register. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the interrupt tag register, setting it to 0. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_clearInterruptTag(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + HWREGH(base + CLB_LOGICCTL + CLB_O_INTR_TAG_REG) = 0U; +} + +//***************************************************************************** +// +//! Selects LUT4 inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4In0 is the value for LUT4 input signal 0. Generated by tool as +//! \b TILEx_CFG_LUT4_IN0. +//! \param lut4In1 is the value for LUT4 input signal 1. Generated by tool as +//! \b TILEx_CFG_LUT4_IN1. +//! \param lut4In2 is the value for LUT4 input signal 2. Generated by tool as +//! \b TILEx_CFG_LUT4_IN2. +//! \param lut4In3 is the value for LUT4 input signal 3. Generated by tool as +//! \b TILEx_CFG_LUT4_IN3. +//! +//! This function configures the LUT4 block's input signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectLUT4Inputs(uint32_t base, uint32_t lut4In0, + uint32_t lut4In1, uint32_t lut4In2, + uint32_t lut4In3) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_IN0) = lut4In0; + HWREG(base + CLB_O_LUT4_IN1) = lut4In1; + HWREG(base + CLB_O_LUT4_IN2) = lut4In2; + HWREG(base + CLB_O_LUT4_IN3) = lut4In3; + EDIS; +} + +//***************************************************************************** +// +//! Configures LUT4 functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param lut4Fn10 is the equation value for LUT4 blocks 0 and 1. Generated by +//! tool as \b TILEx_CFG_LUT4_FN10. +//! \param lut4Fn2 is the equation value for LUT4 block2. Generated by tool as +//! \b TILEx_CFG_LUT4_FN2. +//! +//! This function configures the LUT4 block's equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configLUT4Function(uint32_t base, uint32_t lut4Fn10, + uint32_t lut4Fn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_LUT4_FN1_0) = lut4Fn10; + HWREG(base + CLB_O_LUT4_FN2) = lut4Fn2; + EDIS; +} + +//***************************************************************************** +// +//! Selects FSM inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param external0 is the value for FSM external 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN0. +//! \param external1 is the value for FSM external 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXT_IN1. +//! \param extra0 is the value for FSM extra 0 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN0. +//! \param extra1 is the value for FSM extra 1 input. Generated by tool +//! as \b TILEx_CFG_FSM_EXTRA_IN1. +//! +//! This function configures the FSM block's external inputs and extra external +//! inputs. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectFSMInputs(uint32_t base, uint32_t external0, + uint32_t external1, uint32_t extra0, + uint32_t extra1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_EXTERNAL_IN0) = external0; + HWREG(base + CLB_O_FSM_EXTERNAL_IN1) = external1; + HWREG(base + CLB_O_FSM_EXTRA_IN0) = extra0; + HWREG(base + CLB_O_FSM_EXTRA_IN1) = extra1; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM LUT function. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param fsmLutFn10 is the value for FSM 0 & FSM 1 LUT function. Generated +//! by tool as \b TILEx_CFG_FSM_LUT_FN10. +//! \param fsmLutFn2 is the value for FSM 2 LUT function. Generated by tool as +//! \b TILEx_CFG_FSM_LUT_FN2. +//! +//! This function configures the FSM block's LUT equations. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMLUTFunction(uint32_t base, uint32_t fsmLutFn10, + uint32_t fsmLutFn2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_LUT_FN1_0) = fsmLutFn10; + HWREG(base + CLB_O_FSM_LUT_FN2) = fsmLutFn2; + EDIS; +} + +//***************************************************************************** +// +//! Configures FSM next state. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param nextState0 is the value for FSM 0's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_0. +//! \param nextState1 is the value for FSM 1's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_1. +//! \param nextState2 is the value for FSM 2's next state. Generated by tool as +//! \b TILEx_CFG_FSM_NEXT_STATE_2. +//! +//! This function configures the FSM's next state equation. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configFSMNextState(uint32_t base, uint32_t nextState0, + uint32_t nextState1, + uint32_t nextState2) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_FSM_NEXT_STATE_0) = nextState0; + HWREG(base + CLB_O_FSM_NEXT_STATE_1) = nextState1; + HWREG(base + CLB_O_FSM_NEXT_STATE_2) = nextState2; + EDIS; +} + +//***************************************************************************** +// +//! Selects Counter inputs. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param reset is the value for counter's reset inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_RESET. +//! \param event is the value for counter's event inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_EVENT. +//! \param mode0 is the value for counter's mode 0 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_0. +//! \param mode1 is the value for counter's mode 1 inputs. Generated by tool as +//! \b TILEx_CFG_COUNTER_MODE_1. +//! +//! This function selects the input signals to the counter block. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_selectCounterInputs(uint32_t base, uint32_t reset, + uint32_t event, uint32_t mode0, + uint32_t mode1) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_COUNT_RESET) = reset; + HWREG(base + CLB_O_COUNT_EVENT) = event; + HWREG(base + CLB_O_COUNT_MODE_0) = mode0; + HWREG(base + CLB_O_COUNT_MODE_1) = mode1; + EDIS; +} + +//***************************************************************************** +// +//! Configures Counter and FSM modes. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param miscCtrl is the value to represent counter and FSM modes. +//! Generated by tool as \b TILEx_CFG_MISC_CONTROL. +//! +//! This function configures the counter mode, particularly add/shift, load +//! modes. The function also configures whether the FSM should use state inputs +//! or an extra external input. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configMiscCtrlModes(uint32_t base, uint32_t miscCtrl) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_MISC_CONTROL) = miscCtrl; + EDIS; +} + +//***************************************************************************** +// +//! Configures Output LUT functions. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param outID is the specified CLB tile output signal. +//! \param outputCfg is the value for the output LUT signal function and input +//! signal selections. Generated by tool as \b TILEx_CFG_OUTLUT_n where +//! n is the output number. +//! +//! This function configures the input signals and equations of the output LUT +//! corresponding to the /e outID parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configOutputLUT(uint32_t base, CLB_Outputs outID, + uint32_t outputCfg) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_OUTPUT_LUT_0 + (sizeof(uint32_t) * outID)) = outputCfg; + EDIS; +} + +//***************************************************************************** +// +//! Configures HLC event selection. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param eventSel is the value for HLC event selection. Generated by tool as +//! \b TILEx_HLC_EVENT_SEL. +//! +//! This function configures the event selection for the High Level Controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_configHLCEventSelect(uint32_t base, uint32_t eventSel) +{ + ASSERT(CLB_isBaseValid(base)); + + EALLOW; + HWREG(base + CLB_O_HLC_EVENT_SEL) = eventSel; + EDIS; +} + +//***************************************************************************** +// +//! Program HLC instruction. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param instructionNum is the index into the HLC instruction memory. For +//! example, a value of 0 corresponds to instruction 0 of event 0, +//! a value of 1 corresponds to instruction 1 of event 0, and so on up +//! to a value of 31 which corresponds to instruction 7 of event 3. +//! \param instruction is the instruction to be programmed. Generated by tool +//! as \b TILEx_HLCINSTR_n where n is the instruction number. +//! +//! This function configures the CLB internal memory corresponding to the +//! specified HLC instruction number with the given instruction. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_programHLCInstruction(uint32_t base, + uint32_t instructionNum, + uint32_t instruction) +{ + ASSERT(CLB_isBaseValid(base)); + ASSERT(instructionNum < 32U); + + CLB_writeInterface(base, CLB_ADDR_HLC_BASE + instructionNum, instruction); +} + +//***************************************************************************** +// +//! Set HLC registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param r0Init is the value to write to HLC register R0. Generated by tool +//! as \b TILEx_HLC_R0_INIT. +//! \param r1Init is the value to write to HLC register R1. Generated by tool +//! as \b TILEx_HLC_R1_INIT. +//! \param r2Init is the value to write to HLC register R2. Generated by tool +//! as \b TILEx_HLC_R2_INIT. +//! \param r3Init is the value to write to HLC register R3. Generated by tool +//! as \b TILEx_HLC_R3_INIT. +//! +//! This function configures the CLB internal memory corresponding to the HLC +//! registers R0-R3 with the specified values. +//! +//! \return None. +// +//***************************************************************************** +static inline void CLB_setHLCRegisters(uint32_t base, uint32_t r0Init, + uint32_t r1Init, uint32_t r2Init, + uint32_t r3Init) +{ + ASSERT(CLB_isBaseValid(base)); + + CLB_writeInterface(base, CLB_ADDR_HLC_R0, r0Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R1, r1Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R2, r2Init); + CLB_writeInterface(base, CLB_ADDR_HLC_R3, r3Init); +} + +//***************************************************************************** +// +//! Get HLC or counter register values. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param registerID is the internal register from which to read. Can be +//! either an HLC register (\b CLB_REG_HLC_Rn) or a counter value +//! (\b CLB_REG_CTR_Cn). +//! +//! \return Returns the value in the specified HLC register or counter. +// +//***************************************************************************** +static inline uint32_t CLB_getRegister(uint32_t base, CLB_Register registerID) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + (uint32_t)registerID)); +} + +//***************************************************************************** +// +//! Get output status. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! \return Returns the output status of various components within the CLB tile +//! such as a counter match or LUT output. Use the \b CLB_DBG_OUT_* +//! masks from hw_clb.h to decode the bits. +// +//***************************************************************************** +static inline uint32_t CLB_getOutputStatus(uint32_t base) +{ + ASSERT(CLB_isBaseValid(base)); + + return(HWREG(base + CLB_LOGICCTL + CLB_O_DBG_OUT)); +} + +//***************************************************************************** +// +//! Configures Counter load and match. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param counterID is the specified counter unit. +//! \param load is the value for counter's load mode. Generated by tool as +//! \b TILEx_COUNTER_n_LOAD_VAL where n is the counter number. +//! \param match1 is the value for counter's match 1. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH1_VAL where n is the counter number. +//! \param match2 is the value for counter's match 2. Generated by tool as +//! \b TILEx_COUNTER_n_MATCH2_VAL where n is the counter number. +//! +//! This function configures the CLB internal memory corresponding to the +//! counter block's load and match values. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_configCounterLoadMatch(uint32_t base, CLB_Counters counterID, + uint32_t load, uint32_t match1, + uint32_t match2); + +//***************************************************************************** +// +//! Clear FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! +//! This function clears the PUSH/PULL FIFOs as well as its pointers. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_clearFIFOs(uint32_t base); + +//***************************************************************************** +// +//! Configure the FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pullData[] is a pointer to an array of bytes which needs to be +//! written into the FIFO. The 0th FIFO data is in the 0th index. +//! +//! This function writes to the PULL FIFO. This also clears the FIFOs and +//! its pointer using the CLB_clearFIFOs() API prior to writing to +//! the FIFO. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_writeFIFOs(uint32_t base, const uint32_t pullData[]); + +//***************************************************************************** +// +//! Read FIFO registers. +//! +//! \param base is the base address of a CLB tile's logic config register. +//! \param pushData[] is a pointer to an array of bytes which needs to be +//! read from the FIFO. +//! +//! This function reads from the PUSH FIFO. The 0th FIFO data would be in +//! the 0th index. +//! +//! \return None. +// +//***************************************************************************** +extern void CLB_readFIFOs(uint32_t base , uint32_t pushData[]); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CLB_H diff --git a/gpio_driverlib_cpu1/device/driverlib/cmpss.c b/gpio_driverlib_cpu1/device/driverlib/cmpss.c new file mode 100644 index 0000000..88f9e5f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cmpss.c @@ -0,0 +1,223 @@ +//########################################################################### +// +// FILE: cmpss.c +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cmpss.h" + +//***************************************************************************** +// +// CMPSS_configFilterHigh +// +//***************************************************************************** +void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPHFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPHFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPHFILCTL) & + ~(CMPSS_CTRIPHFILCTL_SAMPWIN_M | CMPSS_CTRIPHFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the high comparator. + // + HWREGH(base + CMPSS_O_CTRIPHFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configFilterLow +// +//***************************************************************************** +void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT((threshold - 1U) >= ((sampleWindow - 1U) / 2U)); + + // + // Shift the sample window and threshold values into the correct positions + // and write them to the appropriate register. + // + regValue = ((sampleWindow - 1U) << CMPSS_CTRIPLFILCTL_SAMPWIN_S) | + ((threshold - 1U) << CMPSS_CTRIPLFILCTL_THRESH_S); + + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) = + (HWREGH(base + CMPSS_O_CTRIPLFILCTL) & + ~(CMPSS_CTRIPLFILCTL_SAMPWIN_M | CMPSS_CTRIPLFILCTL_THRESH_M)) | + regValue; + + // + // Set the filter sample clock prescale for the low comparator. + // + HWREGH(base + CMPSS_O_CTRIPLFILCLKCTL) = samplePrescale; + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configLatchOnPWMSYNC +// +//***************************************************************************** +void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // If the highEnable is true, set the bit that will enable PWMSYNC to reset + // the high comparator digital filter latch. If not, clear the bit. + // + EALLOW; + + if(highEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + } + + // + // If the lowEnable is true, set the bit that will enable PWMSYNC to reset + // the low comparator digital filter latch. If not, clear the bit. + // + if(lowEnable) + { + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + } + else + { + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + } + + EDIS; +} + +//***************************************************************************** +// +// CMPSS_configRamp +// +//***************************************************************************** +void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(delayVal <= CMPSS_RAMPDLYS_DELAY_M); + ASSERT((pwmSyncSrc >= 1U) && (pwmSyncSrc <= 12U)); + + EALLOW; + + // + // Write the ramp generator source to the register + // + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(pwmSyncSrc - 1U) << CMPSS_COMPDACCTL_RAMPSOURCE_S); + + // + // Set or clear the bit that determines from where the max ramp value + // should be loaded. + // + if(useRampValShdw) + { + HWREGH(base + CMPSS_O_COMPDACCTL) |= CMPSS_COMPDACCTL_RAMPLOADSEL; + } + else + { + HWREGH(base + CMPSS_O_COMPDACCTL) &= ~CMPSS_COMPDACCTL_RAMPLOADSEL; + } + + EDIS; + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = maxRampVal; + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = decrementVal; + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = delayVal; +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/cmpss.h b/gpio_driverlib_cpu1/device/driverlib/cmpss.h new file mode 100644 index 0000000..25625c3 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cmpss.h @@ -0,0 +1,1325 @@ +//########################################################################### +// +// FILE: cmpss.h +// +// TITLE: C28x CMPSS driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CMPSS_H +#define CMPSS_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup cmpss_api CMPSS +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_cmpss.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +#define CMPSS_HICMP_CTL_M (CMPSS_COMPCTL_COMPHSOURCE | \ + CMPSS_COMPCTL_COMPHINV | \ + CMPSS_COMPCTL_ASYNCHEN) + +#define CMPSS_LOCMP_CTL_M (CMPSS_COMPCTL_COMPLSOURCE | \ + CMPSS_COMPCTL_COMPLINV | \ + CMPSS_COMPCTL_ASYNCLEN) + +#ifndef DOXYGEN_PDF_IGNORE + + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configLowComparator() and +// CMPSS_configHighComparator() as the config parameter. +// +//***************************************************************************** +// +// Comparator negative input source +// +//! Input driven by internal DAC +#define CMPSS_INSRC_DAC 0x0000U +//! Input driven by external pin +#define CMPSS_INSRC_PIN 0x0001U + +// +// Extra options +// +//! Comparator output is inverted +#define CMPSS_INV_INVERTED 0x0002U +//! Asynch comparator output feeds into OR with latched digital filter output +#define CMPSS_OR_ASYNC_OUT_W_FILT 0x0040U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configOutputsLow() and +// CMPSS_configOutputsHigh() as the config parameter. +// +//***************************************************************************** +// +// Signal driving CTRIPOUT +// +//! Asynchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIPOUT +#define CMPSS_TRIPOUT_SYNC_COMP 0x0010U +//! Filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_FILTER 0x0020U +//! Latched filter output drives CTRIPOUT +#define CMPSS_TRIPOUT_LATCH 0x0030U + +// +// Signal driving CTRIP +// +//! Asynchronous comparator output drives CTRIP +#define CMPSS_TRIP_ASYNC_COMP 0x0000U +//! Synchronous comparator output drives CTRIP +#define CMPSS_TRIP_SYNC_COMP 0x0004U +//! Filter output drives CTRIP +#define CMPSS_TRIP_FILTER 0x0008U +//! Latched filter output drives CTRIP +#define CMPSS_TRIP_LATCH 0x000CU + +//***************************************************************************** +// +// Values that can be returned by CMPSS_getStatus(). +// +//***************************************************************************** +//! High digital filter output +#define CMPSS_STS_HI_FILTOUT 0x0001U +//! Latched value of high digital filter output +#define CMPSS_STS_HI_LATCHFILTOUT 0x0002U +//! Low digital filter output +#define CMPSS_STS_LO_FILTOUT 0x0100U +//! Latched value of low digital filter output +#define CMPSS_STS_LO_LATCHFILTOUT 0x0200U + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configDAC() the config parameter. +// +//***************************************************************************** +// +// When is DAC value loaded from shadow register +// +//! DAC value updated from SYSCLK +#define CMPSS_DACVAL_SYSCLK 0x0000U +//! DAC value updated from PWMSYNC +#define CMPSS_DACVAL_PWMSYNC 0x0080U + +// +// DAC reference voltage +// +//! VDDA is the voltage reference +#define CMPSS_DACREF_VDDA 0x0000U +//! VDAC is the voltage reference +#define CMPSS_DACREF_VDAC 0x0020U + +// +// DAC value source +// +//! DAC value updated from shadow register +#define CMPSS_DACSRC_SHDW 0x0000U +//! DAC value is updated from the ramp register +#define CMPSS_DACSRC_RAMP 0x0001U +#endif + +//***************************************************************************** +// +// Values that can be passed to CMPSS_configRamp() +// as the pwmSyncSrc parameter. +// +//***************************************************************************** +#define CMPSS_PWMSYNC1 1U //!< PWMSYNC1 +#define CMPSS_PWMSYNC2 2U //!< PWMSYNC2 +#define CMPSS_PWMSYNC3 3U //!< PWMSYNC3 +#define CMPSS_PWMSYNC4 4U //!< PWMSYNC4 +#define CMPSS_PWMSYNC5 5U //!< PWMSYNC5 +#define CMPSS_PWMSYNC6 6U //!< PWMSYNC6 +#define CMPSS_PWMSYNC7 7U //!< PWMSYNC7 +#define CMPSS_PWMSYNC8 8U //!< PWMSYNC8 +#define CMPSS_PWMSYNC9 9U //!< PWMSYNC9 +#define CMPSS_PWMSYNC10 10U //!< PWMSYNC10 +#define CMPSS_PWMSYNC11 11U //!< PWMSYNC11 +#define CMPSS_PWMSYNC12 12U //!< PWMSYNC12 + + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks the CMPSS base address. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function determines if a CMPSS base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +CMPSS_isBaseValid(uint32_t base) +{ + return( + (base == CMPSS1_BASE) || + (base == CMPSS2_BASE) || + (base == CMPSS3_BASE) || + (base == CMPSS4_BASE) || + (base == CMPSS5_BASE) || + (base == CMPSS6_BASE) || + (base == CMPSS7_BASE) || + (base == CMPSS8_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function enables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) |= CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CMPSS module. +//! +//! \param base is the base address of the CMPSS module. +//! +//! This function disables the CMPSS module passed into the \e base parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Clear the bit that enables the CMPSS module. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) &= ~CMPSS_COMPCTL_COMPDACE; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the high comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPH or +//! CTRIPOUTH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configHighComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_HICMP_CTL_M) | config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator. +//! +//! This function configures a comparator. The \e config parameter is the +//! result of a logical OR operation between a \b CMPSS_INSRC_xxx value and if +//! desired, \b CMPSS_INV_INVERTED and \b CMPSS_OR_ASYNC_OUT_W_FILT values. +//! +//! The \b CMPSS_INSRC_xxx term can take on the following values to specify +//! the low comparator negative input source: +//! - \b CMPSS_INSRC_DAC - The internal DAC. +//! - \b CMPSS_INSRC_PIN - An external pin. +//! +//! \b CMPSS_INV_INVERTED may be ORed into \e config if the comparator output +//! should be inverted. +//! +//! \b CMPSS_OR_ASYNC_OUT_W_FILT may be ORed into \e config if the +//! asynchronous comparator output should be fed into an OR gate with the +//! latched digital filter output before it is made available for CTRIPL or +//! CTRIPOUTL. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configLowComparator(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = + (HWREGH(base + CMPSS_O_COMPCTL) & ~CMPSS_LOCMP_CTL_M) | (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the high comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the high comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTH: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPH: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsHigh(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the high comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTHSEL_M | + CMPSS_COMPCTL_CTRIPHSEL_M)) | + config; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the output signal configuration for the low comparator. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the low comparator output signals. +//! +//! This function configures a comparator's output signals CTRIP and CTRIPOUT. +//! The \e config parameter is the result of a logical OR operation between the +//! \b CMPSS_TRIPOUT_xxx and \b CMPSS_TRIP_xxx values. +//! +//! The \b CMPSS_TRIPOUT_xxx term can take on the following values to specify +//! which signal drives CTRIPOUTL: +//! - \b CMPSS_TRIPOUT_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIPOUT_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIPOUT_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIPOUT_LATCH - The latched output of the digital filter. +//! +//! The \b CMPSS_TRIP_xxx term can take on the following values to specify +//! which signal drives CTRIPL: +//! - \b CMPSS_TRIP_ASYNC_COMP - The asynchronous comparator output. +//! - \b CMPSS_TRIP_SYNC_COMP - The synchronous comparator output. +//! - \b CMPSS_TRIP_FILTER - The output of the digital filter. +//! - \b CMPSS_TRIP_LATCH - The latched output of the digital filter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configOutputsLow(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the low comparator output settings to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPCTL) = (HWREGH(base + CMPSS_O_COMPCTL) & + ~(CMPSS_COMPCTL_CTRIPOUTLSEL_M | + CMPSS_COMPCTL_CTRIPLSEL_M)) | + (config << 8U); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current comparator status. +//! +//! \param base is the base address of the comparator module. +//! +//! This function returns the current status for the comparator, specifically +//! the digital filter output and latched digital filter output. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b CMPSS_STS_HI_FILTOUT - High digital filter output +//! - \b CMPSS_STS_HI_LATCHFILTOUT - Latched value of high digital filter +//! output +//! - \b CMPSS_STS_LO_FILTOUT - Low digital filter output +//! - \b CMPSS_STS_LO_LATCHFILTOUT - Latched value of low digital filter output +// +//***************************************************************************** +static inline uint16_t +CMPSS_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Return contents of the status register. + // + return(HWREGH(base + CMPSS_O_COMPSTS)); +} + +//***************************************************************************** +// +//! Sets the configuration for the internal comparator DACs. +//! +//! \param base is the base address of the CMPSS module. +//! \param config is the configuration of the internal DAC. +//! +//! This function configures the comparator's internal DAC. The \e config +//! parameter is the result of a logical OR operation between the +//! \b CMPSS_DACVAL_xxx, \b CMPSS_DACREF_xxx, and \b CMPSS_DACSRC_xxx. +//! +//! The \b CMPSS_DACVAL_xxx term can take on the following values to specify +//! when the DAC value is loaded from its shadow register: +//! - \b CMPSS_DACVAL_SYSCLK - Value register updated on system clock. +//! - \b CMPSS_DACVAL_PWMSYNC - Value register updated on PWM sync. +//! +//! The \b CMPSS_DACREF_xxx term can take on the following values to specify +//! which voltage supply is used as reference for the DACs: +//! - \b CMPSS_DACREF_VDDA - VDDA is the voltage reference for the DAC. +//! - \b CMPSS_DACREF_VDAC - VDAC is the voltage reference for the DAC. +//! +//! The \b CMPSS_DACSRC_xxx term can take on the following values to specify +//! the DAC value source for the high comparator's internal DAC: +//! - \b CMPSS_DACSRC_SHDW - The user-programmed DACVALS register. +//! - \b CMPSS_DACSRC_RAMP - The ramp generator RAMPSTS register +//! +//! \note The \b CMPSS_DACVAL_xxx and \b CMPSS_DACREF_xxx terms apply to +//! both the high and low comparators. \b CMPSS_DACSRC_xxx will only affect +//! the high comparator's internal DAC. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configDAC(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC configuration to the appropriate register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPDACCTL) = + (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~(CMPSS_COMPDACCTL_SWLOADSEL | CMPSS_COMPDACCTL_SELREF | + CMPSS_COMPDACCTL_DACSOURCE)) | config; + EDIS; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the high +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueHigh(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACHVALS) = value; +} + +//***************************************************************************** +// +//! Sets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param value is the value actively driven by the DAC. +//! +//! This function sets the 12-bit value driven by the internal DAC of the low +//! comparator. This function will load the value into the shadow register from +//! which the actual DAC value register will be loaded. To configure which +//! event causes this shadow load to take place, use CMPSS_configDAC(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setDACValueLow(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 4096U); + + // + // Write the DAC value to the DAC value shadow register. + // + HWREGH(base + CMPSS_O_DACLVALS) = value; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the high comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterHigh() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the high comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPHFILCTL) |= CMPSS_CTRIPHFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Initializes the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function initializes all the samples in the low comparator digital +//! filter to the filter input value. +//! +//! \note See CMPSS_configFilterLow() for the proper initialization sequence +//! to avoid glitches. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_initFilterLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the low comparator filter initialization bit. + // + EALLOW; + + HWREGH(base + CMPSS_O_CTRIPLFILCTL) |= CMPSS_CTRIPLFILCTL_FILINIT; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the high comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueHigh() writes. +//! +//! \return Returns the value driven by the internal DAC of the high comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACHVALA)); +} + +//***************************************************************************** +// +//! Gets the value of the internal DAC of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! +//! This function gets the value of the internal DAC of the low comparator. +//! The value is read from the \e active register--not the shadow register to +//! which CMPSS_setDACValueLow() writes. +//! +//! \return Returns the value driven by the internal DAC of the low comparator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getDACValueLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the DAC value to the DAC value shadow register. + // + return(HWREGH(base + CMPSS_O_DACLVALA)); +} + +//***************************************************************************** +// +//! Causes a software reset of the high comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the high comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Causes a software reset of the low comparator digital filter output latch. +//! +//! \param base is the base address of the comparator module. +//! +//! This function causes a software reset of the low comparator digital filter +//! output latch. It will generate a single pulse of the latch reset signal. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_clearFilterLatchLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Set the bit that generates a reset pulse to the digital filter latch. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LLATCHCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! \param value the ramp maximum reference value. +//! +//! This function sets the ramp maximum reference value that will be loaded +//! into the ramp generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setMaxRampValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the maximum ramp value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPMAXREFS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator maximum reference value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp maximum reference value that will be +//! loaded into the ramp generator. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getMaxRampValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the maximum ramp value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPMAXREFA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the ramp decrement value. +//! +//! This function sets the value that is subtracted from the ramp value on +//! every system clock cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDecValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp decrement value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDECVALS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator decrement value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp decrement value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDecValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp decrement value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDECVALA)); +} + +//***************************************************************************** +// +//! Sets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! \param value is the 13-bit ramp delay value. +//! +//! This function sets the value that configures the number of system clock +//! cycles to delay the start of the ramp generator decrementer after a PWMSYNC +//! event is received. Delay value can be no greater than 8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setRampDelayValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value < 8192U); + + // + // Write the ramp delay value to the shadow register. + // + HWREGH(base + CMPSS_O_RAMPDLYS) = value; +} + +//***************************************************************************** +// +//! Gets the ramp generator delay value. +//! +//! \param base is the base address of the comparator module. +//! +//! \return Returns the latched ramp delay value that is subtracted from +//! the ramp value on every system clock cycle. +// +//***************************************************************************** +static inline uint16_t +CMPSS_getRampDelayValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Read the ramp delay value from the register. + // + return(HWREGH(base + CMPSS_O_RAMPDLYA)); +} + +//***************************************************************************** +// +//! Configures sync source for comparator +//! +//! \param base is the base address of the comparator module. +//! \param syncSource is the desired EPWMxSYNCPER source +//! +//! This function configures desired EPWMxSYNCPER source for comparator +//! blocks. Configured EPWMxSYNCPER signal can be used to synchronize loading +//! of DAC input value from shadow to active register. It can also be used to +//! synchronize Ramp generator, if applicable. Refer to device manual to check +//! if Ramp generator is available in the desired CMPSS instance. +//! +//! Valid values for \e syncSource parameter can be 1 to n, where n represents +//! the maximum number of EPWMSYNCPER signals available on the device. For +//! instance, passing 2 into \e syncSource will select EPWM2SYNCPER. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_configureSyncSource(uint32_t base, uint16_t syncSource) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + // + // Write the ramp delay value to the shadow register. + // + EALLOW; + HWREGH(base + CMPSS_O_COMPDACCTL) = (HWREGH(base + CMPSS_O_COMPDACCTL) & + ~CMPSS_COMPDACCTL_RAMPSOURCE_M) | + ((uint16_t)(syncSource - 1U) << + CMPSS_COMPDACCTL_RAMPSOURCE_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the comparator hysteresis settings. +//! +//! \param base is the base address of the comparator module. +//! \param value is the amount of hysteresis on the comparator inputs. +//! +//! This function sets the amount of hysteresis on the comparator inputs. The +//! \e value parameter indicates the amount of hysteresis desired. Passing in 0 +//! results in none, passing in 1 results in typical hysteresis, passing in 2 +//! results in 2x of typical hysteresis, and so on where \e value x of typical +//! hysteresis is the amount configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_setHysteresis(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + ASSERT(value <= 4U); + + // + // Read the ramp delay value from the register. + // + EALLOW; + + HWREGH(base + CMPSS_O_COMPHYSCTL) = value; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of HIGH comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of High comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCHigh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_HSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Enables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function enables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_enableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) |= CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Disables reset of LOW comparator digital filter output latch on PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! +//! This function disables EPWMSYNCPER reset of Low comparator digital filter +//! output latch +//! +//! \return None. +// +//***************************************************************************** +static inline void +CMPSS_disableLatchResetOnPWMSYNCLow(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(CMPSS_isBaseValid(base)); + + EALLOW; + + HWREGH(base + CMPSS_O_COMPSTSCLR) &= ~CMPSS_COMPSTSCLR_LSYNCCLREN; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the digital filter of the high comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the high +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configHighComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterHigh() +//! -# Initialize the sample values using CMPSS_initFilterHigh() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsHigh() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterHigh(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures the digital filter of the low comparator. +//! +//! \param base is the base address of the comparator module. +//! \param samplePrescale is the number of system clock cycles between samples. +//! \param sampleWindow is the number of FIFO samples to monitor. +//! \param threshold is the majority threshold of samples to change state. +//! +//! This function configures the operation of the digital filter of the low +//! comparator. +//! +//! The \e samplePrescale parameter specifies the number of system clock cycles +//! not be passed as this parameter. The prescaler used by digital filter is 1 +//! more than \e samplePrescale value. So, the input provided should be 1 less +//! than the expected prescaler. +//! +//! The \e sampleWindow parameter configures the size of the window of FIFO +//! samples taken from the input that will be monitored to determine when to +//! change the filter output. This sample window may be no larger than 32 +//! samples. +//! +//! The \e threshold parameter configures the threshold value to be used by +//! the digital filter. +//! +//! The filter output resolves to the majority value of the sample window where +//! majority is defined by the value passed into the \e threshold parameter. +//! For proper operation, the value of \e threshold must be greater than +//! sampleWindow / 2. +//! +//! To ensure proper operation of the filter, the following is the recommended +//! function call sequence for initialization: +//! +//! -# Configure and enable the comparator using CMPSS_configLowComparator() +//! and CMPSS_enableModule() +//! -# Configure the digital filter using CMPSS_configFilterLow() +//! -# Initialize the sample values using CMPSS_initFilterLow() +//! -# Configure the module output signals CTRIP and CTRIPOUT using +//! CMPSS_configOutputsLow() +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configFilterLow(uint32_t base, uint16_t samplePrescale, + uint16_t sampleWindow, uint16_t threshold); + +//***************************************************************************** +// +//! Configures whether or not the digital filter latches are reset by PWMSYNC +//! +//! \param base is the base address of the comparator module. +//! \param highEnable indicates filter latch settings in the high comparator. +//! \param lowEnable indicates filter latch settings in the low comparator. +//! +//! This function configures whether or not the digital filter latches in both +//! the high and low comparators should be reset by PWMSYNC. If the +//! \e highEnable parameter is \b true, the PWMSYNC will be allowed to reset +//! the high comparator's digital filter latch. If it is false, the ability of +//! the PWMSYNC to reset the latch will be disabled. The \e lowEnable parameter +//! has the same effect on the low comparator's digital filter latch. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configLatchOnPWMSYNC(uint32_t base, bool highEnable, bool lowEnable); + +//***************************************************************************** +// +//! Configures the comparator subsystem's ramp generator. +//! +//! \param base is the base address of the comparator module. +//! \param maxRampVal is the ramp maximum reference value. +//! \param decrementVal value is the ramp decrement value. +//! \param delayVal is the ramp delay value. +//! \param pwmSyncSrc is the number of the PWMSYNC source. +//! \param useRampValShdw indicates if the max ramp shadow should be used. +//! +//! This function configures many of the main settings of the comparator +//! subsystem's ramp generator. The \e maxRampVal parameter should be passed +//! the ramp maximum reference value that will be loaded into the ramp +//! generator. The \e decrementVal parameter should be passed the decrement +//! value that will be subtracted from the ramp generator on each system clock +//! cycle. The \e delayVal parameter should be passed the 13-bit number of +//! system clock cycles the ramp generator should delay before beginning to +//! decrement the ramp generator after a PWMSYNC signal is received. +//! +//! These three values may be be set individually using the +//! CMPSS_setMaxRampValue(), CMPSS_setRampDecValue(), and +//! CMPSS_setRampDelayValue() APIs. +//! +//! The number of the PWMSYNC signal to be used to reset the ramp generator +//! should be specified by passing it into the \e pwmSyncSrc parameter. For +//! instance, passing a CMPSS_PWMSYNCx into \e pwmSyncSrc will select PWMSYNCx. +//! +//! To indicate whether the ramp generator should reset with the value from the +//! ramp max reference value shadow register or with the latched ramp max +//! reference value, use the \e useRampValShdw parameter. Passing it \b true +//! will result in the latched value being bypassed. The ramp generator will be +//! loaded right from the shadow register. A value of \b false will load the +//! ramp generator from the latched value. +//! +//! \return None. +// +//***************************************************************************** +extern void +CMPSS_configRamp(uint32_t base, uint16_t maxRampVal, uint16_t decrementVal, + uint16_t delayVal, uint16_t pwmSyncSrc, bool useRampValShdw); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CMPSS_H diff --git a/gpio_driverlib_cpu1/device/driverlib/cpu.h b/gpio_driverlib_cpu1/device/driverlib/cpu.h new file mode 100644 index 0000000..3e7385b --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cpu.h @@ -0,0 +1,172 @@ +//########################################################################### +// +// FILE: cpu.h +// +// TITLE: Useful C28x CPU defines. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef CPU_H +#define CPU_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#include "stdint.h" + +// +// External reference to the interrupt flag register (IFR) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IFR; +#endif + +// +// External reference to the interrupt enable register (IER) register +// +#ifndef __TMS320C28XX_CLA__ +extern __cregister volatile uint16_t IER; +#endif + +// +// Define to enable interrupts +// +#ifndef EINT +#define EINT __asm(" clrc INTM") +#endif + +// +// Define to disable interrupts +// +#ifndef DINT +#define DINT __asm(" setc INTM") +#endif + +// +// Define to enable debug events +// +#ifndef ERTM +#define ERTM __asm(" clrc DBGM") +#endif + +// +// Define to disable debug events +// +#ifndef DRTM +#define DRTM __asm(" setc DBGM") +#endif + +// +// Define to allow writes to protected registers +// +#ifndef EALLOW +#ifndef __TMS320C28XX_CLA__ +#define EALLOW __eallow() +#else +#define EALLOW __meallow() +#endif // __TMS320C28XX_CLA__ +#endif // EALLOW + +// +// Define to disable writes to protected registers +// +#ifndef EDIS +#ifndef __TMS320C28XX_CLA__ +#define EDIS __edis() +#else +#define EDIS __medis() +#endif // __TMS320C28XX_CLA__ +#endif // EDIS + +// +// Define for emulation stop +// +#ifndef ESTOP0 +#define ESTOP0 __asm(" ESTOP0") +#endif + +// +// Define for emulation stop +// +#ifndef ESTOP1 +#define ESTOP1 __asm(" ESTOP1") +#endif + +// +// Define for no operation +// +#ifndef NOP +#define NOP __asm(" NOP") +#endif + +// +// Define for putting processor into a low-power mode +// +#ifndef _DUAL_HEADERS +#ifndef IDLE +#define IDLE __asm(" IDLE") +#endif +#else +#define IDLE_ASM __asm(" IDLE"); +#endif + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// +//***************************************************************************** +extern void __eallow(void); +extern void __edis(void); + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // CPU_H diff --git a/gpio_driverlib_cpu1/device/driverlib/cputimer.c b/gpio_driverlib_cpu1/device/driverlib/cputimer.c new file mode 100644 index 0000000..5d12934 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cputimer.c @@ -0,0 +1,61 @@ +//############################################################################# +// +// FILE: cputimer.c +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "cputimer.h" + +//***************************************************************************** +// +// CPUTimer_setEmulationMode +// +//***************************************************************************** +void CPUTimer_setEmulationMode(uint32_t base, CPUTimer_EmulationMode mode) +{ + ASSERT(CPUTimer_isBaseValid(base)); + // + // Write to FREE_SOFT bits of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) = + (HWREGH(base + CPUTIMER_O_TCR) & + ~(CPUTIMER_TCR_FREE | CPUTIMER_TCR_SOFT)) | + (uint16_t)mode; +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/cputimer.h b/gpio_driverlib_cpu1/device/driverlib/cputimer.h new file mode 100644 index 0000000..71a7501 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/cputimer.h @@ -0,0 +1,509 @@ +//############################################################################# +// +// FILE: cputimer.h +// +// TITLE: C28x CPU timer Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef CPUTIMER_H +#define CPUTIMER_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup cputimer_api CPUTimer +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_cputimer.h" +#include "debug.h" +#include "sysctl.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +//! Values that can be passed to CPUTimer_setEmulationMode() as the +//! \e mode parameter. +// +//**************************************************************************** +typedef enum +{ + //! Denotes that the timer will stop after the next decrement + CPUTIMER_EMULATIONMODE_STOPAFTERNEXTDECREMENT = 0x0000, + //! Denotes that the timer will stop when it reaches zero + CPUTIMER_EMULATIONMODE_STOPATZERO = 0x0400, + //! Denotes that the timer will run free + CPUTIMER_EMULATIONMODE_RUNFREE = 0x0800 +}CPUTimer_EmulationMode; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e source parameter. +// +//***************************************************************************** +typedef enum +{ + //! System Clock Source + CPUTIMER_CLOCK_SOURCE_SYS = 0x0, + //! Internal Oscillator 1 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC1 = 0x1, + //! Internal Oscillator 2 Clock Source + CPUTIMER_CLOCK_SOURCE_INTOSC2 = 0x2, + //! External Clock Source + CPUTIMER_CLOCK_SOURCE_XTAL = 0x3, + //! Auxiliary PLL Clock Source + CPUTIMER_CLOCK_SOURCE_AUX = 0x6 +} CPUTimer_ClockSource; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! CPUTimer_selectClockSource() as the \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + CPUTIMER_CLOCK_PRESCALER_1 = 0, //!< Prescaler value of / 1 + CPUTIMER_CLOCK_PRESCALER_2 = 1, //!< Prescaler value of / 2 + CPUTIMER_CLOCK_PRESCALER_4 = 2, //!< Prescaler value of / 4 + CPUTIMER_CLOCK_PRESCALER_8 = 3, //!< Prescaler value of / 8 + CPUTIMER_CLOCK_PRESCALER_16 = 4 //!< Prescaler value of / 16 +} CPUTimer_Prescaler; + +//***************************************************************************** +// +//! \internal +//! Checks CPU timer base address. +//! +//! \param base specifies the Timer module base address. +//! +//! This function determines if a CPU timer module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool CPUTimer_isBaseValid(uint32_t base) +{ + return((base == CPUTIMER0_BASE) || (base == CPUTIMER1_BASE) || + (base == CPUTIMER2_BASE)); +} +#endif + +//***************************************************************************** +// +//! Clears CPU timer overflow flag. +//! +//! \param base is the base address of the timer module. +//! +//! This function clears the CPU timer overflow flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_clearOverflowFlag(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIF bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; +} + +//***************************************************************************** +// +//! Disables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function disables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_disableInterrupt(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TIE bit of TCR register + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Enables CPU timer interrupt. +//! +//! \param base is the base address of the timer module. +//! +//! This function enables the CPU timer interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_enableInterrupt(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TIE bit of TCR register + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TIE; +} + +//***************************************************************************** +// +//! Reloads CPU timer counter. +//! +//! \param base is the base address of the timer module. +//! +//! This function reloads the CPU timer counter with the values contained in +//! the CPU timer period register. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_reloadTimerCounter(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TRB bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; +} + +//***************************************************************************** +// +//! Stops CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function stops the CPU timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_stopTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Set TSS bit of register TCR + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function doesn't reset the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_resumeTimer(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Starts(restarts) CPU timer. +//! +//! \param base is the base address of the timer module. +//! +//! This function starts (restarts) the CPU timer. +//! +//! \b Note: This function reloads the timer counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_startTimer(uint32_t base) +{ + uint16_t tcrValue = 0; + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Reload the timer counter + // + tcrValue = HWREGH(base + CPUTIMER_O_TCR) & (~CPUTIMER_TCR_TIF); + HWREGH(base + CPUTIMER_O_TCR) = tcrValue | CPUTIMER_TCR_TRB; + + // + // Clear TSS bit of register TCR + // + HWREGH(base + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; +} + +//***************************************************************************** +// +//! Sets CPU timer period. +//! +//! \param base is the base address of the timer module. +//! \param periodCount is the CPU timer period count. +//! +//! This function sets the CPU timer period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Load the MSB period Count + // + HWREG(base + CPUTIMER_O_PRD) = periodCount; +} + +//***************************************************************************** +// +//! Returns the current CPU timer counter value. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the current CPU timer counter value. +//! +//! \return Returns the current CPU timer count value. +// +//***************************************************************************** +static inline uint32_t CPUTimer_getTimerCount(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Get the TIMH:TIM registers value + // + return(HWREG(base + CPUTIMER_O_TIM)); +} + +//***************************************************************************** +// +//! Set CPU timer pre-scaler value. +//! +//! \param base is the base address of the timer module. +//! \param prescaler is the CPU timer pre-scaler value. +//! +//! This function sets the pre-scaler value for the CPU timer. For every value +//! of (prescaler + 1), the CPU timer counter decrements by 1. +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_setPreScaler(uint32_t base, uint16_t prescaler) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Writes to TPR.TDDR and TPRH.TDDRH bits + // + HWREGH(base + CPUTIMER_O_TPRH) = prescaler >> 8U; + HWREGH(base + CPUTIMER_O_TPR) = (prescaler & CPUTIMER_TPR_TDDR_M) ; +} + +//***************************************************************************** +// +//! Return the CPU timer overflow status. +//! +//! \param base is the base address of the timer module. +//! +//! This function returns the CPU timer overflow status. +//! +//! \return Returns true if the CPU timer has overflowed, false if not. +// +//***************************************************************************** +static inline bool CPUTimer_getTimerOverflowStatus(uint32_t base) +{ + ASSERT(CPUTimer_isBaseValid(base)); + + // + // Check if TIF bits of register TCR are set + // + return(((HWREGH(base + CPUTIMER_O_TCR) & CPUTIMER_TCR_TIF) == + CPUTIMER_TCR_TIF) ? true : false); +} + +//***************************************************************************** +// +//! Select CPU Timer 2 Clock Source and Prescaler +//! +//! \param base is the base address of the timer module. +//! \param source is the clock source to use for CPU Timer 2 +//! \param prescaler is the value that configures the selected clock source +//! relative to the system clock +//! +//! This function selects the specified clock source and prescaler value +//! for the CPU timer (CPU timer 2 only). +//! +//! The \e source parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_SOURCE_SYS - System Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC1 - Internal Oscillator 1 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_INTOSC2 - Internal Oscillator 2 Clock +//! - \b CPUTIMER_CLOCK_SOURCE_XTAL - External Clock +//! - \b CPUTIMER_CLOCK_SOURCE_AUX - Auxiliary PLL Clock +//! +//! The \e prescaler parameter can be any one of the following: +//! - \b CPUTIMER_CLOCK_PRESCALER_1 - Prescaler value of / 1 +//! - \b CPUTIMER_CLOCK_PRESCALER_2 - Prescaler value of / 2 +//! - \b CPUTIMER_CLOCK_PRESCALER_4 - Prescaler value of / 4 +//! - \b CPUTIMER_CLOCK_PRESCALER_8 - Prescaler value of / 8 +//! - \b CPUTIMER_CLOCK_PRESCALER_16 - Prescaler value of / 16 +//! +//! \return None. +// +//***************************************************************************** +static inline void CPUTimer_selectClockSource(uint32_t base, + CPUTimer_ClockSource source, + CPUTimer_Prescaler prescaler) +{ + ASSERT(base == CPUTIMER2_BASE); + + // + // Set source and prescaler for CPU Timer 2 + // + if(base == CPUTIMER2_BASE) + { + EALLOW; + + // + // Set Clock Source + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | (uint16_t)source; + SYSCTL_REGWRITE_DELAY; + + // + // Set Clock Prescaler + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M) | + ((uint16_t)prescaler < 0.0F); + + // + // Get the sign-extended offset trim value + // + oldOffsetTrim = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + oldOffsetTrim = ((oldOffsetTrim & (uint16_t)DAC_REG_BYTE_MASK) ^ + (uint16_t)0x80) - (uint16_t)0x80; + + // + // Calculate new offset trim value if DAC is operating at a reference + // voltage other than 2.5v. + // + newOffsetTrim = ((float32_t)(2.5 / referenceVoltage) * + (int16_t)oldOffsetTrim); + + // + // Check if the new offset trim value is valid + // + ASSERT(((int16_t)newOffsetTrim > -129) && ((int16_t)newOffsetTrim < 128)); + + // + // Set the new offset trim value + // + EALLOW; + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | + (int16_t)newOffsetTrim; + + EDIS; + +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/dac.h b/gpio_driverlib_cpu1/device/driverlib/dac.h new file mode 100644 index 0000000..fcd866a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/dac.h @@ -0,0 +1,604 @@ +//########################################################################### +// +// FILE: dac.h +// +// TITLE: C28x DAC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DAC_H +#define DAC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dac_api DAC +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dac.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +// +// A 8-bit register mask +// +#define DAC_REG_BYTE_MASK (0xFFU) //!< Register Byte Mask + +// +// Lock Key +// +#define DAC_LOCK_KEY (0xA000U) //!< DAC Lock Key + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are defines for the reg parameter of the +// DAC_lockRegister() and DAC_isRegisterLocked() functions. +// +//***************************************************************************** +#define DAC_LOCK_CONTROL (0x1U) //!< Lock the control register +#define DAC_LOCK_SHADOW (0x2U) //!< Lock the shadow value register +#define DAC_LOCK_OUTPUT (0x4U) //!< Lock the output enable register + +#endif // DOXYGEN_PDF_IGNORE + +//***************************************************************************** +// +//! Values that can be passed to DAC_setReferenceVoltage() as the \e source +//! parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_REF_VDAC = 0, //!< VDAC reference voltage + DAC_REF_ADC_VREFHI = 1 //!< ADC VREFHI reference voltage +}DAC_ReferenceVoltage; + +//***************************************************************************** +// +//! Values that can be passed to DAC_setLoadMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + DAC_LOAD_SYSCLK = 0, //!< Load on next SYSCLK + DAC_LOAD_PWMSYNC = 4 //!< Load on next PWMSYNC specified by SYNCSEL +}DAC_LoadMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks DAC base address. +//! +//! \param base specifies the DAC module base address. +//! +//! This function determines if an DAC module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DAC_isBaseValid(uint32_t base) +{ + return( + (base == DACA_BASE) || + (base == DACB_BASE) || + (base == DACC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Get the DAC Revision value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC revision value. +//! +//! \return Returns the DAC revision value. +// +//***************************************************************************** +static inline uint16_t +DAC_getRevision(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the revision value. + // + return(HWREGH(base + DAC_O_REV) & DAC_REV_REV_M); +} + +//***************************************************************************** +// +//! Sets the DAC Reference Voltage +//! +//! \param base is the DAC module base address +//! \param source is the selected reference voltage +//! +//! This function sets the DAC reference voltage. +//! +//! The \e source parameter can have the following value: +//! - \b DAC_REF_VDAC - The VDAC reference voltage +//! - \b DAC_REF_ADC_VREFHI - The ADC VREFHI reference voltage +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setReferenceVoltage(uint32_t base, DAC_ReferenceVoltage source) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the reference voltage + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_DACREFSEL) | (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC Load Mode +//! +//! \param base is the DAC module base address +//! \param mode is the selected load mode +//! +//! This function sets the DAC load mode. +//! +//! The \e mode parameter can have one of two values: +//! - \b DAC_LOAD_SYSCLK - Load on next SYSCLK +//! - \b DAC_LOAD_PWMSYNC - Load on next PWMSYNC specified by SYNCSEL +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setLoadMode(uint32_t base, DAC_LoadMode mode) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Set the load mode + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_LOADMODE) | (uint16_t)mode; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DAC PWMSYNC Signal +//! +//! \param base is the DAC module base address +//! \param signal is the selected PWM signal +//! +//! This function sets the DAC PWMSYNC signal. +//! +//! The \e signal parameter must be set to a number that represents the PWM +//! signal that will be set. For instance, passing 2 into \e signal will +//! select PWM sync signal 2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setPWMSyncSignal(uint32_t base, uint16_t pwmSignal) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((pwmSignal > 0U) && (pwmSignal < 17U)); + + // + // Set the PWM sync signal + // + EALLOW; + + HWREGH(base + DAC_O_CTL) = (HWREGH(base + DAC_O_CTL) & + ~DAC_CTL_SYNCSEL_M) | + ((uint16_t)(pwmSignal - 1U) << + DAC_CTL_SYNCSEL_S); + + EDIS; +} + +//***************************************************************************** +// +//! Get the DAC Active Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC active output value. +//! +//! \return Returns the DAC active output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getActiveValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the active value + // + return(HWREGH(base + DAC_O_VALA) & DAC_VALA_DACVALA_M); +} + +//***************************************************************************** +// +//! Set the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! \param value is the 12-bit code to be loaded into the active value register +//! +//! This function sets the DAC shadow output value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setShadowValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT(value <= DAC_VALS_DACVALS_M); + + // + // Set the shadow value + // + HWREGH(base + DAC_O_VALS) = (HWREGH(base + DAC_O_VALS) & + ~DAC_VALS_DACVALS_M) | + (uint16_t)(value & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Get the DAC Shadow Output Value +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC shadow output value. +//! +//! \return Returns the DAC shadow output value. +// +//***************************************************************************** +static inline uint16_t +DAC_getShadowValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the shadow value + // + return(HWREGH(base + DAC_O_VALS) & DAC_VALS_DACVALS_M); +} + +//***************************************************************************** +// +//! Enable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function enables the DAC output. +//! +//! \note A delay is required after enabling the DAC. Further details +//! regarding the exact delay time length can be found in the device datasheet. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_enableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Enable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) |= DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the DAC Output +//! +//! \param base is the DAC module base address +//! +//! This function disables the DAC output. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_disableOutput(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Disable the output + // + EALLOW; + + HWREGH(base + DAC_O_OUTEN) &= ~DAC_OUTEN_DACOUTEN; + + EDIS; +} + +//***************************************************************************** +// +//! Set DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param offset is the specified value for the offset trim +//! +//! This function sets the DAC offset trim. The \e offset value should be a +//! signed number in the range of -128 to 127. +//! +//! \note The offset should not be modified unless specifically indicated by +//! TI Errata or other documentation. Modifying the offset value could cause +//! this module to operate outside of the datasheet specifications. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_setOffsetTrim(uint32_t base, int16_t offset) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((offset > -129) && (offset < 128)); + + // + // Set the offset trim value + // + EALLOW; + + HWREGH(base + DAC_O_TRIM) = (HWREGH(base + DAC_O_TRIM) & + ~DAC_TRIM_OFFSET_TRIM_M) | (int16_t)offset; + + EDIS; +} + +//***************************************************************************** +// +//! Get DAC Offset Trim +//! +//! \param base is the DAC module base address +//! +//! This function gets the DAC offset trim value. +//! +//! \return None. +// +//***************************************************************************** +static inline int16_t +DAC_getOffsetTrim(uint32_t base) +{ + uint16_t value; + + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + + // + // Get the sign-extended offset trim value + // + value = (HWREGH(base + DAC_O_TRIM) & DAC_TRIM_OFFSET_TRIM_M); + value = ((value & (uint16_t)DAC_REG_BYTE_MASK) ^ (uint16_t)0x80) - + (uint16_t)0x80; + + return((int16_t)value); +} + +//***************************************************************************** +// +//! Lock write-access to DAC Register +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC registers +//! +//! This function locks the write-access to the specified DAC register. Only a +//! system reset can unlock the register once locked. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return None. +// +//***************************************************************************** +static inline void +DAC_lockRegister(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Lock the specified registers + // + EALLOW; + + HWREGH(base + DAC_O_LOCK) |= (DAC_LOCK_KEY | reg); + + EDIS; +} + +//***************************************************************************** +// +//! Check if DAC Register is locked +//! +//! \param base is the DAC module base address +//! \param reg is the selected DAC register locks to check +//! +//! This function checks if write-access has been locked on the specified DAC +//! register. +//! +//! The \e reg parameter can be an ORed combination of any of the following +//! values: +//! - \b DAC_LOCK_CONTROL - Lock the DAC control register +//! - \b DAC_LOCK_SHADOW - Lock the DAC shadow value register +//! - \b DAC_LOCK_OUTPUT - Lock the DAC output enable/disable register +//! +//! \return Returns \b true if any of the registers specified are locked, and +//! \b false if all specified registers aren't locked. +// +//***************************************************************************** +static inline bool +DAC_isRegisterLocked(uint32_t base, uint16_t reg) +{ + // + // Check the arguments. + // + ASSERT(DAC_isBaseValid(base)); + ASSERT((reg & ~(DAC_LOCK_CONTROL | DAC_LOCK_SHADOW | + DAC_LOCK_OUTPUT)) == 0U); + + // + // Return the lock status on the specified registers + // + return((bool)((HWREGH(base + DAC_O_LOCK) & reg) != 0U)); +} + +//***************************************************************************** +// +//! Tune DAC Offset Trim +//! +//! \param base is the DAC module base address +//! \param referenceVoltage is the reference voltage the DAC +//! module is operating at. +//! +//! This function adjusts/tunes the DAC offset trim. The \e referenceVoltage +//! value should be a floating point number in the range specified in the +//! device data manual. +//! +//! \note Use this function to adjust the DAC offset trim if operating +//! at a reference voltage other than 2.5v. Since this function modifies +//! the DAC offset trim register, it should only be called once after +//! Device_cal. If it is called multiple times after Device_cal, the offset +//! value scaled would be the wrong value. +//! +//! \return None. +// +//***************************************************************************** +extern void +DAC_tuneOffsetTrim(uint32_t base, float32_t referenceVoltage); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DAC_H diff --git a/gpio_driverlib_cpu1/device/driverlib/dcsm.c b/gpio_driverlib_cpu1/device/driverlib/dcsm.c new file mode 100644 index 0000000..808027a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/dcsm.c @@ -0,0 +1,377 @@ +//############################################################################# +// +// FILE: dcsm.c +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#include "dcsm.h" + +//***************************************************************************** +// +// DCSM_unlockZone1CSM +// +//***************************************************************************** +void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z1OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z1OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z1_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z1_BASE + DCSM_O_Z1_CSMKEY3) = psCMDKey->csmKey3; + } +} + +//***************************************************************************** +// +// DCSM_unlockZone2CSM +// +//***************************************************************************** +void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey) +{ + uint32_t linkPointer; + uint32_t zsbBase = (DCSM_Z2OTP_BASE + 0x20U); // base address of the ZSB + int32_t bitPos = 28; // Bits [28:0] point to a ZSB (29-bit link pointer) + int32_t zeroFound = 0; + + // + // Check the arguments. + // + ASSERT(psCMDKey != NULL); + + linkPointer = HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTER); + + // + // Bits 31 and 30 as most-significant 0 are invalid LinkPointer options + // + linkPointer = linkPointer << 3; + + // + // Zone-Select Block (ZSB) selection using Link-Pointers + // and 0's bit position within the Link pointer + // + while((zeroFound == 0) && (bitPos > -1)) + { + // + // The most significant bit position in the resolved link pointer + // which is 0, defines the valid base address for the ZSB. + // + if((linkPointer & 0x80000000U) == 0U) + { + zeroFound = 1; + // + // Base address of the ZSB is calculated using + // 0x10 as the slope/step with which zsbBase expands with + // change in the bitPos and 3*0x10 is the offset + // + zsbBase = (DCSM_Z2OTP_BASE + (((uint32_t)bitPos + 3U) * 0x10U)); + } + else + { + // + // Move through the linkPointer to find the most significant + // bit position of 0 + // + bitPos--; + linkPointer = linkPointer << 1; + } + } + + // + // Perform dummy reads on the 128-bit password + // Using linkPointer because it is no longer needed + // + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD0); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD1); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD2); + linkPointer = HWREG(zsbBase + DCSM_O_Z2_CSMPSWD3); + + if(psCMDKey != NULL) + { + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY0) = psCMDKey->csmKey0; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY1) = psCMDKey->csmKey1; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY2) = psCMDKey->csmKey2; + HWREG(DCSM_Z2_BASE + DCSM_O_Z2_CSMKEY3) = psCMDKey->csmKey3; + } +} +//***************************************************************************** +// +// DCSM_getZone1FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t) + ((regValue >> (uint16_t)sector) & + 0x01U)); + } + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone1RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE1) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z1_BASE + DCSM_O_Z1_EXEONLYRAMR) >> + (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_getZone2FlashEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector) +{ + uint16_t regValue; + DCSM_EXEOnlyStatus status; + + // + // Check if sector belongs to this zone + // + if(DCSM_getFlashSectorZone(sector) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status register + // + regValue = HWREGH(DCSM_Z2_BASE + DCSM_O_Z2_EXEONLYSECTR); + // + // Get the EXE status of the Flash Sector + // + status = (DCSM_EXEOnlyStatus)((uint16_t)((regValue >> + (uint16_t)sector) & 0x01U)); + } + + return(status); +} + +//***************************************************************************** +// +// DCSM_getZone2RAMEXEStatus +// +//***************************************************************************** +DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module) +{ + ASSERT(module != DCSM_CLA); + uint32_t status; + + // + // Check if module belongs to this zone + // + if(DCSM_getRAMZone(module) != DCSM_MEMORY_ZONE2) + { + status = DCSM_INCORRECT_ZONE; + } + else + { + // + // Get the EXE status of the RAM Module + // + status = (uint16_t)((HWREGH(DCSM_Z2_BASE + + DCSM_O_Z2_EXEONLYRAMR) >> (uint16_t)module) & 0x01U); + } + return((DCSM_EXEOnlyStatus)status); +} + +//***************************************************************************** +// +// DCSM_claimZoneSemaphore +// +//***************************************************************************** +bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S) | + (uint16_t)zone; + EDIS; + + // + // If the calling function was unable to claim the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == (uint16_t)zone) ? + true : false); +} + +//***************************************************************************** +// +// DCSM_releaseZoneSemaphore +// +//***************************************************************************** +bool +DCSM_releaseZoneSemaphore(void) +{ + // + // FLSEM register address. + // + uint32_t regAddress = DCSMCOMMON_BASE + DCSM_O_FLSEM; + + EALLOW; + + // + // Write 0xA5 to the key and write the zone that is attempting to claim the + // Flash Pump Semaphore to the semaphore bits. + // + HWREGH(regAddress) = ((uint16_t)FLSEM_KEY << DCSM_FLSEM_KEY_S); + EDIS; + + // + // If the calling function was unable to release the zone semaphore, then + // return false + // + return(((HWREGH(regAddress) & DCSM_FLSEM_SEM_M) == 0x0U) ? true : false); +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/dcsm.h b/gpio_driverlib_cpu1/device/driverlib/dcsm.h new file mode 100644 index 0000000..d181fa7 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/dcsm.h @@ -0,0 +1,669 @@ +//############################################################################# +// +// FILE: dcsm.h +// +// TITLE: C28x Driver for the DCSM security module. +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef DCSM_H +#define DCSM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dcsm_api DCSM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dcsm.h" +#include "inc/hw_types.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the unlockZone1CSM() and unlockZone2CSM(). +// These are not parameters for any function. +// These are not intended for application code. +// +//***************************************************************************** + +#define DCSM_O_Z1_CSMPSWD0 0x08U //!< Z1 CSMPSWD0 offset +#define DCSM_O_Z1_CSMPSWD1 0x0AU //!< Z1 CSMPSWD1 offset +#define DCSM_O_Z1_CSMPSWD2 0x0CU //!< Z1 CSMPSWD2 offset +#define DCSM_O_Z1_CSMPSWD3 0x0EU //!< Z1 CSMPSWD3 offset +#define DCSM_O_Z2_CSMPSWD0 0x08U //!< Z2 CSMPSWD0 offset +#define DCSM_O_Z2_CSMPSWD1 0x0AU //!< Z2 CSMPSWD1 offset +#define DCSM_O_Z2_CSMPSWD2 0x0CU //!< Z2 CSMPSWD2 offset +#define DCSM_O_Z2_CSMPSWD3 0x0EU //!< Z2 CSMPSWD3 offset + +//***************************************************************************** +// +// Register key defines. +// +//***************************************************************************** +#define FLSEM_KEY 0xA5U //!< Zone semaphore key + +//***************************************************************************** +// +//! Data structures to hold password keys. +// +//***************************************************************************** +typedef struct +{ + uint32_t csmKey0; + uint32_t csmKey1; + uint32_t csmKey2; + uint32_t csmKey3; +} DCSM_CSMPasswordKey; + +//***************************************************************************** +// +//! Values to distinguish the status of RAM or FLASH sectors. These values +//! describe which zone the memory location belongs too. +//! These values can be returned from DCSM_getRAMZone(), +//! DCSM_getFlashSectorZone(). +// +//***************************************************************************** +typedef enum +{ + DCSM_MEMORY_INACCESSIBLE, //!< Inaccessible + DCSM_MEMORY_ZONE1, //!< Zone 1 + DCSM_MEMORY_ZONE2, //!< Zone 2 + DCSM_MEMORY_FULL_ACCESS //!< Full access +} DCSM_MemoryStatus; + +//***************************************************************************** +// +//! Values to pass to DCSM_claimZoneSemaphore(). These values are used +//! to describe the zone that can write to Flash Wrapper registers. +// +//***************************************************************************** +typedef enum +{ + DCSM_FLSEM_ZONE1 = 0x01U, //!< Flash semaphore Zone 1 + DCSM_FLSEM_ZONE2 = 0x02U //!< Flash semaphore Zone 2 +} DCSM_SemaphoreZone; + +//***************************************************************************** +// +//! Values to distinguish the security status of the zones. +//! These values can be returned from DCSM_getZone1CSMSecurityStatus(), +//! DCSM_getZone2CSMSecurityStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_STATUS_SECURE, //!< Secure + DCSM_STATUS_UNSECURE, //!< Unsecure + DCSM_STATUS_LOCKED, //!< Locked +} DCSM_SecurityStatus; + +//***************************************************************************** +// +// Values to distinguish the status of the Control Registers. These values +// describe can be used with the return values of +// DCSM_getZone1ControlStatus(), and DCSM_getZone2ControlStatus(). +// +//***************************************************************************** +#define DCSM_ALLZERO 0x08U //!< CSM Passwords all zeros +#define DCSM_ALLONE 0x10U //!< CSM Passwords all ones +#define DCSM_UNSECURE 0x20U //!< Zone is secure/unsecure +#define DCSM_ARMED 0x40U //!< CSM is armed + +//***************************************************************************** +// +//! Values to decribe the EXEONLY Status. +//! These values are returned from to DCSM_getZone1RAMEXEStatus(), +//! DCSM_getZone2RAMEXEStatus(), DCSM_getZone1FlashEXEStatus(), +//! DCSM_getZone2FlashEXEStatus(). +// +//***************************************************************************** +typedef enum +{ + DCSM_PROTECTED, //!< Protected + DCSM_UNPROTECTED, //!< Unprotected + DCSM_INCORRECT_ZONE //!< Incorrect Zone +}DCSM_EXEOnlyStatus; + +//***************************************************************************** +// +//! Values to distinguish RAM Module. +//! These values can be passed to DCSM_getZone1RAMEXEStatus() +//! DCSM_getZone2RAMEXEStatus(), DCSM_getRAMZone(). +// +//***************************************************************************** +typedef enum +{ + // + //C28x RAMs + // + DCSM_RAMLS0, //!< RAMLS0 + DCSM_RAMLS1, //!< RAMLS1 + DCSM_RAMLS2, //!< RAMLS2 + DCSM_RAMLS3, //!< RAMLS3 + DCSM_RAMLS4, //!< RAMLS4 + DCSM_RAMLS5, //!< RAMLS5 + DCSM_RAMD0, //!< RAMD0 + DCSM_RAMD1, //!< RAMD1 + DCSM_CLA = 14U //!> + shift) & 0x03U); + return((DCSM_MemoryStatus)ramStatus); +} + +//***************************************************************************** +// +//! Returns the security zone a flash sector belongs to +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function returns the security zone a flash sector belongs to. +//! +//! \return Returns DCSM_MEMORY_INACCESSIBLE if the section is inaccessible , +//! DCSM_MEMORY_ZONE1 if the section belongs to zone 1, DCSM_MEMORY_ZONE2 if +//! the section belongs to zone 2 and DCSM_MEMORY_FULL_ACCESS if the section +//! doesn't belong to any zone (or if the section is unsecure).. +// +//***************************************************************************** +static inline DCSM_MemoryStatus +DCSM_getFlashSectorZone(DCSM_Sector sector) +{ + uint32_t sectStat; + uint16_t shift; + + // + // Get the Sector status register for the specific bank + // + sectStat = HWREG(DCSMCOMMON_BASE + DCSM_O_SECTSTAT); + shift = (uint16_t)sector * 2U; + + // + //Read the SECTSTAT register for the specific Flash Sector. + // + return((DCSM_MemoryStatus)((uint16_t)((sectStat >> shift) & 0x3U))); +} + +//***************************************************************************** +// +//! Read Zone 1 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 1 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone1LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z1_BASE + DCSM_O_Z1_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Read Zone 2 Link Pointer Error +//! +//! A non-zero value indicates an error on the bit position that is set to 1. +//! +//! \return Returns the value of the Zone 2 Link Pointer error. +// +//***************************************************************************** +static inline uint32_t +DCSM_getZone2LinkPointerError(void) +{ + // + // Return the LinkPointer Error for specific bank + // + return(HWREG(DCSM_Z2_BASE + DCSM_O_Z2_LINKPOINTERERR)); +} + +//***************************************************************************** +// +//! Unlocks Zone 1 CSM. +//! +//! \param psCMDKey is a pointer to the DCSM_CSMPasswordKey struct that has the +//! CSM password for zone 1. +//! +//! This function unlocks the CSM password. It first reads the +//! four password locations in the User OTP. If any of the password values is +//! different from 0xFFFFFFFF, it unlocks the device by writing the provided +//! passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone1CSM(const DCSM_CSMPasswordKey * const psCMDKey); + +//***************************************************************************** +// +//! Unlocks Zone 2 CSM. +//! +//! \param psCMDKey is a pointer to the CSMPSWDKEY that has the CSM +//! password for zone 2. +//! +//! This function unlocks the CSM password. It first reads +//! the four password locations in the User OTP. If any of the password values +//! is different from 0xFFFFFFFF, it unlocks the device by writing the +//! provided passwords into CSM Key registers +//! +//! \return None. +//! +//! \note This function should not be called in an actual application, +//! should only be used for once to program the OTP memory. Ensure flash data +//! cache is disabled before calling this function(Flash_disableCache). +// +//***************************************************************************** +extern void +DCSM_unlockZone2CSM(const DCSM_CSMPasswordKey * const psCMDKey); +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 1 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone1RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a flash sector +//! +//! \param sector is the flash sector value. Use DCSM_Sector type. +//! +//! This function takes in a valid sector value and returns the status of EXE +//! ONLY security protection for the sector. +//! +//! \return Returns DCSM_PROTECTED if the sector is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the sector is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if sector does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2FlashEXEStatus(DCSM_Sector sector); + +//***************************************************************************** +// +//! Returns the EXE-ONLY status of zone 2 for a RAM module +//! +//! \param module is the RAM module value. Valid values are type DCSM_RAMModule +//! C28x RAMs : +//! - \b DCSM_RAMLS0 +//! - \b DCSM_RAMLS1 +//! - \b DCSM_RAMLS2 +//! - \b DCSM_RAMLS3 +//! - \b DCSM_RAMLS4 +//! - \b DCSM_RAMLS5 +//! - \b DCSM_RAMD0 +//! - \b DCSM_RAMD1 +//! +//! This function takes in a valid module value and returns the status of EXE +//! ONLY security protection for that module. DCSM_CLA is an invalid module +//! value. There is no EXE-ONLY available for DCSM_CLA. +//! +//! \return Returns DCSM_PROTECTED if the module is EXE-ONLY protected, +//! DCSM_UNPROTECTED if the module is not EXE-ONLY protected, +//! DCSM_INCORRECT_ZONE if module does not belong to this zone. +// +//***************************************************************************** +extern DCSM_EXEOnlyStatus +DCSM_getZone2RAMEXEStatus(DCSM_RAMModule module); + +//***************************************************************************** +// +//! Claims the zone semaphore which allows access to the Flash Wrapper register +//! for that zone. +//! +//! \param zone is the zone which is trying to claim the semaphore which allows +//! access to the Flash Wrapper registers. +//! +//! \return Returns true for a successful semaphore capture, false if it was +//! unable to capture the semaphore. +// +//***************************************************************************** +extern bool +DCSM_claimZoneSemaphore(DCSM_SemaphoreZone zone); + +//***************************************************************************** +// +//! Releases the zone semaphore. +//! +//! \return Returns true if it was successful in releasing the zone semaphore +//! and false if it was unsuccessful in releasing the zone semaphore. +//! +//! \note If the calling function is not in the right zone to be able +//! to access this register, it will return a false. +// +//***************************************************************************** +extern bool +DCSM_releaseZoneSemaphore(void); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DCSM_H diff --git a/gpio_driverlib_cpu1/device/driverlib/debug.h b/gpio_driverlib_cpu1/device/driverlib/debug.h new file mode 100644 index 0000000..5a2f93a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/debug.h @@ -0,0 +1,91 @@ +//########################################################################### +// +// FILE: debug.h +// +// TITLE: Assert definition macro for debug. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DEBUG_H +#define DEBUG_H + +//***************************************************************************** +// +// Prototype for the function that is called when an invalid argument is passed +// to an API. This is only used when doing a DEBUG build. It is the +// application's responsibility to define the __error__ function. +// +//***************************************************************************** +extern void __error__(const char *filename, uint32_t line); + +//***************************************************************************** +// +// The ASSERT macro, which does the actual assertion checking. Typically, this +// will be for procedure arguments. +// +//***************************************************************************** +#ifdef DEBUG +#ifdef __TMS320C28XX__ +// +// When called from C28x application +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __error__(__FILE__, __LINE__); \ + } \ + } \ + while((_Bool)0) +#else +// +// When called from CLA application. Update as needed. +// +#define ASSERT(expr) do \ + { \ + if(!(expr)) \ + { \ + __mdebugstop(); \ + } \ + } \ + while((_Bool)0) +#endif +#else +#define ASSERT(expr) +#endif + +#endif // DEBUG_H diff --git a/gpio_driverlib_cpu1/device/driverlib/dma.c b/gpio_driverlib_cpu1/device/driverlib/dma.c new file mode 100644 index 0000000..ea591b1 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/dma.c @@ -0,0 +1,370 @@ +//########################################################################### +// +// FILE: dma.c +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "dma.h" + +//***************************************************************************** +// +// DMA_configAddresses +// +//***************************************************************************** +void DMA_configAddresses(uint32_t base, const void *destAddr, + const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configBurst +// +//***************************************************************************** +void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((size >= 1U) && (size <= 32U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up BURST registers. + // + HWREGH(base + DMA_O_BURST_SIZE) = size - 1U; + HWREGH(base + DMA_O_SRC_BURST_STEP) = srcStep; + HWREGH(base + DMA_O_DST_BURST_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configTransfer +// +//***************************************************************************** +void DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(transferSize <= 0x10000U); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up TRANSFER registers. + // + HWREGH(base + DMA_O_TRANSFER_SIZE) = (uint16_t)(transferSize - 1U); + HWREGH(base + DMA_O_SRC_TRANSFER_STEP) = srcStep; + HWREGH(base + DMA_O_DST_TRANSFER_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configWrap +// +//***************************************************************************** +void DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT((srcWrapSize <= 0x10000U) || (destWrapSize <= 0x10000U)); + ASSERT(((srcStep >= -4096) && (srcStep <= 4095)) && + ((destStep >= -4096) && (destStep <= 4095))); + + EALLOW; + + // + // Set up WRAP registers. + // + HWREGH(base + DMA_O_SRC_WRAP_SIZE) = (uint16_t)(srcWrapSize - 1U); + HWREGH(base + DMA_O_SRC_WRAP_STEP) = srcStep; + + HWREGH(base + DMA_O_DST_WRAP_SIZE) = (uint16_t)(destWrapSize - 1U); + HWREGH(base + DMA_O_DST_WRAP_STEP) = destStep; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configMode +// +//***************************************************************************** +void DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up trigger selection in the CMA/CLA trigger source selection + // registers. These are considered part of system control. + // + switch(base) + { + case DMA_CH1_BASE: + // + // Channel 1 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH1_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH1_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH1_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH1_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 1U; + break; + + case DMA_CH2_BASE: + // + // Channel 2 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH2_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH2_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH2_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH2_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 2U; + break; + + case DMA_CH3_BASE: + // + // Channel 3 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH3_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH3_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH3_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH3_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 3U; + break; + + case DMA_CH4_BASE: + // + // Channel 4 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL1) & + ~((uint32_t)SYSCTL_DMACHSRCSEL1_CH4_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL1_CH4_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH4_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH4_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 4U; + break; + + case DMA_CH5_BASE: + // + // Channel 5 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH5_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH5_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH5_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH5_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 5U; + break; + + case DMA_CH6_BASE: + // + // Channel 6 + // + HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) = + (HWREG(DMACLASRCSEL_BASE + SYSCTL_O_DMACHSRCSEL2) & + ~((uint32_t)SYSCTL_DMACHSRCSEL2_CH6_M)) | + ((uint32_t)trigger << SYSCTL_DMACHSRCSEL2_CH6_S); + + // + // Set peripheral interrupt select bits to the channel number. + // + HWREGH(DMA_CH6_BASE + DMA_O_MODE) = + (HWREGH(DMA_CH6_BASE + DMA_O_MODE) & ~DMA_MODE_PERINTSEL_M) | 6U; + break; + + default: + // + // Invalid base. + // + break; + } + + // + // Write the configuration to the mode register. + // + HWREGH(base + DMA_O_MODE) &= ~(DMA_MODE_DATASIZE | DMA_MODE_CONTINUOUS | + DMA_MODE_ONESHOT); + HWREGH(base + DMA_O_MODE) |= config; + + EDIS; +} + +//***************************************************************************** +// +// DMA_configChannel +// +//***************************************************************************** +void DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + ASSERT(((transfParams->configSize == DMA_CFG_SIZE_16BIT) || + (transfParams->configSize == DMA_CFG_SIZE_32BIT)) && + ((transfParams->transferMode == DMA_CFG_ONESHOT_DISABLE) || + (transfParams->transferMode == DMA_CFG_ONESHOT_ENABLE)) && + ((transfParams->reinitMode == DMA_CFG_CONTINUOUS_DISABLE) || + (transfParams->reinitMode == DMA_CFG_CONTINUOUS_ENABLE))); + + // + // Configure DMA Channel + // + DMA_configAddresses(base, (const void *)transfParams->destAddr, + (const void *)transfParams->srcAddr); + + // + // Configure the size of each burst and the address step size + // + DMA_configBurst(base, transfParams->burstSize, transfParams->srcBurstStep, + transfParams->destBurstStep); + + // + // Configure the transfer size and the address step that is + // made after each burst. + // + DMA_configTransfer(base, transfParams->transferSize, + transfParams->srcTransferStep, + transfParams->destTransferStep); + + // + // Configure the DMA channel's wrap settings + // + DMA_configWrap(base, transfParams->srcWrapSize, transfParams->srcWrapStep, + transfParams->destWrapSize, transfParams->destWrapStep); + + // + // Configure the DMA channel's trigger and mode + // + DMA_configMode(base, transfParams->transferTrigger, + transfParams->transferMode | transfParams->reinitMode | + transfParams->configSize); + + // + // Enable the selected peripheral trigger to start a DMA transfer + // + DMA_enableTrigger(base); + + if(transfParams->enableInterrupt) + { + // + // Set the channel interrupt mode + // + DMA_setInterruptMode(base, transfParams->interruptMode); + + // + // Enable the indicated DMA channel interrupt source + // + DMA_enableInterrupt(base); + } + else + { + // + // Disable the indicated DMA channel interrupt source + // + DMA_disableInterrupt(base); + } +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/dma.h b/gpio_driverlib_cpu1/device/driverlib/dma.h new file mode 100644 index 0000000..ae57689 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/dma.h @@ -0,0 +1,1171 @@ +//########################################################################### +// +// FILE: dma.h +// +// TITLE: C28x DMA driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef DMA_H +#define DMA_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup dma_api DMA +//! \brief This module is used for DMA configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_dma.h" +#include "inc/hw_memmap.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to DMA_configMode() as the config parameter. +// +//***************************************************************************** +//! Only one burst transfer performed per trigger. +#define DMA_CFG_ONESHOT_DISABLE 0U +//! Burst transfers occur without additional event triggers after the first. +#define DMA_CFG_ONESHOT_ENABLE DMA_MODE_ONESHOT + +//! DMA channel will be disabled at the end of a transfer. +#define DMA_CFG_CONTINUOUS_DISABLE 0U +//! DMA reinitializes when the transfer count is zero and waits for a trigger. +#define DMA_CFG_CONTINUOUS_ENABLE DMA_MODE_CONTINUOUS + +//! DMA transfers 16 bits at a time. +#define DMA_CFG_SIZE_16BIT 0U +//! DMA transfers 32 bits at a time. +#define DMA_CFG_SIZE_32BIT DMA_MODE_DATASIZE + +//***************************************************************************** +// +//! Values that can be passed to DMA_configMode() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + DMA_TRIGGER_SOFTWARE = 0, + + DMA_TRIGGER_ADCA1 = 1, + DMA_TRIGGER_ADCA2 = 2, + DMA_TRIGGER_ADCA3 = 3, + DMA_TRIGGER_ADCA4 = 4, + DMA_TRIGGER_ADCAEVT = 5, + DMA_TRIGGER_ADCB1 = 6, + DMA_TRIGGER_ADCB2 = 7, + DMA_TRIGGER_ADCB3 = 8, + DMA_TRIGGER_ADCB4 = 9, + DMA_TRIGGER_ADCBEVT = 10, + DMA_TRIGGER_ADCC1 = 11, + DMA_TRIGGER_ADCC2 = 12, + DMA_TRIGGER_ADCC3 = 13, + DMA_TRIGGER_ADCC4 = 14, + DMA_TRIGGER_ADCCEVT = 15, + DMA_TRIGGER_ADCD1 = 16, + DMA_TRIGGER_ADCD2 = 17, + DMA_TRIGGER_ADCD3 = 18, + DMA_TRIGGER_ADCD4 = 19, + DMA_TRIGGER_ADCDEVT = 20, + + DMA_TRIGGER_XINT1 = 29, + DMA_TRIGGER_XINT2 = 30, + DMA_TRIGGER_XINT3 = 31, + DMA_TRIGGER_XINT4 = 32, + DMA_TRIGGER_XINT5 = 33, + + DMA_TRIGGER_EPWM1SOCA = 36, + DMA_TRIGGER_EPWM1SOCB = 37, + DMA_TRIGGER_EPWM2SOCA = 38, + DMA_TRIGGER_EPWM2SOCB = 39, + DMA_TRIGGER_EPWM3SOCA = 40, + DMA_TRIGGER_EPWM3SOCB = 41, + DMA_TRIGGER_EPWM4SOCA = 42, + DMA_TRIGGER_EPWM4SOCB = 43, + DMA_TRIGGER_EPWM5SOCA = 44, + DMA_TRIGGER_EPWM5SOCB = 45, + DMA_TRIGGER_EPWM6SOCA = 46, + DMA_TRIGGER_EPWM6SOCB = 47, + DMA_TRIGGER_EPWM7SOCA = 48, + DMA_TRIGGER_EPWM7SOCB = 49, + DMA_TRIGGER_EPWM8SOCA = 50, + DMA_TRIGGER_EPWM8SOCB = 51, + DMA_TRIGGER_EPWM9SOCA = 52, + DMA_TRIGGER_EPWM9SOCB = 53, + DMA_TRIGGER_EPWM10SOCA = 54, + DMA_TRIGGER_EPWM10SOCB = 55, + DMA_TRIGGER_EPWM11SOCA = 56, + DMA_TRIGGER_EPWM11SOCB = 57, + DMA_TRIGGER_EPWM12SOCA = 58, + DMA_TRIGGER_EPWM12SOCB = 59, + + DMA_TRIGGER_TINT0 = 68, + DMA_TRIGGER_TINT1 = 69, + DMA_TRIGGER_TINT2 = 70, + + DMA_TRIGGER_MCBSPAMXEVT = 71, + DMA_TRIGGER_MCBSPAMREVT = 72, + DMA_TRIGGER_MCBSPBMXEVT = 73, + DMA_TRIGGER_MCBSPBMREVT = 74, + + + DMA_TRIGGER_SDFM1FLT1 = 95, + DMA_TRIGGER_SDFM1FLT2 = 96, + DMA_TRIGGER_SDFM1FLT3 = 97, + DMA_TRIGGER_SDFM1FLT4 = 98, + + DMA_TRIGGER_SDFM2FLT1 = 99, + DMA_TRIGGER_SDFM2FLT2 = 100, + DMA_TRIGGER_SDFM2FLT3 = 101, + DMA_TRIGGER_SDFM2FLT4 = 102, + + + DMA_TRIGGER_SPIATX = 109, + DMA_TRIGGER_SPIARX = 110, + DMA_TRIGGER_SPIBTX = 111, + DMA_TRIGGER_SPIBRX = 112, + DMA_TRIGGER_SPICTX = 113, + DMA_TRIGGER_SPICRX = 114, + + DMA_TRIGGER_CLB1INT = 127, + DMA_TRIGGER_CLB2INT = 128, + DMA_TRIGGER_CLB3INT = 129, + DMA_TRIGGER_CLB4INT = 130, + +} DMA_Trigger; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setInterruptMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! DMA interrupt is generated at the beginning of a transfer + DMA_INT_AT_BEGINNING, + //! DMA interrupt is generated at the end of a transfer + DMA_INT_AT_END +} DMA_InterruptMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after current read-write access is completed + DMA_EMULATION_STOP, + //! Continue DMA operation regardless of emulation suspend + DMA_EMULATION_FREE_RUN +} DMA_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to DMA_configChannel() as the +//! configure parameter. +// +//***************************************************************************** +typedef struct +{ + DMA_Trigger transferTrigger; //DMA transfer triggers + DMA_InterruptMode interruptMode; //Channel interrupt mode + //! enableInterrupt can have a value 1(Enable) or 0(Disable) + bool enableInterrupt; //Enable/Disable interrupt mode + //! configSize can have a value DMA_CFG_SIZE_16BIT/32BIT + uint32_t configSize; //Data bus width (16 or 32 bits) + //! transferMode can have a value DMA_CFG_ONESHOT_DISABLE/ENABLE + uint32_t transferMode; //Burst transfer mode + //! reinitMode can have a value DMA_CFG_CONTINUOUS_DISABLE/ENABLE + uint32_t reinitMode; //DMA reinitialization mode + //! burstSize value range from 1 word to 32 sixteen-bit words. + uint32_t burstSize; //Number of words transferred per burst + //! transferSize value range from 1 to 65536 + uint32_t transferSize; //Number of bursts per transfer + //! Number of bursts to be transferred before a wrap of the source address + //! occurs. srcWrapSize value range from 1 to 65536 + uint32_t srcWrapSize; + //! Number of bursts to be transferred before a wrap of the destination + //! address occurs. destWrapSize value range from 1 to 65536 + uint32_t destWrapSize; + uint32_t destAddr; //destination address + uint32_t srcAddr; //source address + //! Amount to inc or dec the source address after each word of a burst. + //! srcBurstStep can have only signed values from -4096 to 4095 + int16_t srcBurstStep; + //! Amount to inc or dec the destination address after each word of a burst. + //! destBurstStep can have only signed values from -4096 to 4095 + int16_t destBurstStep; + //! Amount to inc or dec the source address after each burst of a transfer. + //! srcTransferStep can have only signed values from -4096 to 4095 + int16_t srcTransferStep; + //! Amount to inc or dec the destination address after each burst of a + //! transfer. destTransferStep can have only signed values from -4096 to 4095 + int16_t destTransferStep; + //! Amount to inc or dec the source address when the wrap occurs. + //! srcWrapStep can have only signed values from -4096 to 4095 + int16_t srcWrapStep; + //! Amount to inc or dec the destination address when the wrap occurs. + //! destWrapStep can have only signed values from -4096 to 4095 + int16_t destWrapStep; + +} DMA_ConfigParams; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an DMA channel base address. +//! +//! \param base specifies the DMA channel base address. +//! +//! This function determines if a DMA channel base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +DMA_isBaseValid(uint32_t base) +{ + return((base == DMA_CH1_BASE) || (base == DMA_CH2_BASE) || + (base == DMA_CH3_BASE) || (base == DMA_CH4_BASE) || + (base == DMA_CH5_BASE) || (base == DMA_CH6_BASE)); +} +#endif + +//***************************************************************************** +// +//! Initializes the DMA controller to a known state. +//! +//! This function configures does a hard reset of the DMA controller in order +//! to put it into a known state. The function also sets the DMA to run free +//! during an emulation suspend (see the field DEBUGCTRL.FREE for more info). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_initController(void) +{ + EALLOW; + + // + // Set the hard reset bit. One NOP is required after HARDRESET. + // + HWREGH(DMA_BASE + DMA_O_CTRL) |= DMA_CTRL_HARDRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Channel Soft Reset +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function does a soft reset to place the channel into its default state +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_triggerSoftReset(uint32_t base) +{ + EALLOW; + + // + // Set the soft reset bit. One NOP is required after SOFTRESET. + // + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_SOFTRESET; + NOP; + + EDIS; +} + +//***************************************************************************** +// +//! Sets DMA emulation mode. +//! +//! \param mode is the emulation mode to be selected. +//! +//! This function sets the behavior of the DMA operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b DMA_EMULATION_STOP - DMA runs until the current read-write access is +//! completed. +//! - \b DMA_EMULATION_FREE_RUN - DMA operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setEmulationMode(DMA_EmulationMode mode) +{ + EALLOW; + + // + // Set emulation mode + // + if(mode == DMA_EMULATION_STOP) + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) &= ~DMA_DEBUGCTRL_FREE; + } + else + { + HWREGH(DMA_BASE + DMA_O_DEBUGCTRL) |= DMA_DEBUGCTRL_FREE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables peripherals to trigger a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the selected peripheral trigger to start a DMA +//! transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables peripherals from triggering a DMA transfer. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the selected peripheral trigger from starting a DMA +//! transfer on the specified channel. This also disables the use of the +//! software force using the DMA_forceTrigger() API. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Clear the peripheral interrupt trigger enable bit. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_PERINTE; + EDIS; +} + +//***************************************************************************** +// +//! Force a peripheral trigger to a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function sets the peripheral trigger flag and if triggering a DMA +//! burst is enabled (see DMA_enableTrigger()), a DMA burst transfer will be +//! forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_forceTrigger(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the peripheral interrupt trigger force bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTFRC; + EDIS; +} + +//***************************************************************************** +// +//! Clears a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears the peripheral trigger flag. Normally, you would use +//! this function when initializing the DMA for the first time. The flag is +//! cleared automatically when the DMA starts the first burst of a transfer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearTriggerFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write a one to the clear bit to clear the peripheral trigger flag. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_PERINTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Transfer Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Transfer Status Flag is set, which +//! means a DMA transfer has begun. +//! This flag is cleared when TRANSFER_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Transfer Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTransferStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Transfer Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_TRANSFERSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Burst Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Burst Status Flag is set, which +//! means a DMA burst has begun. +//! This flag is cleared when BURST_COUNT reaches zero, or when the +//! HARDRESET or SOFTRESET bit is set. +//! +//! \return Returns \b true if the Burst Status Flag is set. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getBurstStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Burst Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_BURSTSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Run Status Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Run Status Flag is set, which +//! means the DMA channel is enabled. +//! This flag is cleared when a transfer completes (TRANSFER_COUNT = 0) and +//! continuous mode is disabled, or when the HARDRESET, SOFTRESET, or HALT bit +//! is set. +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getRunStatusFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Run Status Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_RUNSTS) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's Overflow Flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if the Overflow Flag is set, which +//! means peripheral event trigger was received while Peripheral Event Trigger +//! Flag was already set. +//! This flag can be cleared by writing to ERRCLR bit, using the function +//! DMA_clearErrorFlag(). +//! +//! \return Returns \b true if the channel is enabled. Returns \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +DMA_getOverflowFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the Overflow Flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_OVRFLG) != 0U); +} + +//***************************************************************************** +// +//! Gets the status of a DMA channel's peripheral trigger flag. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function returns \b true if a peripheral trigger event has occurred +//! The flag is automatically cleared when the first burst transfer begins, but +//! if needed, it can be cleared using DMA_clearTriggerFlag(). +//! +//! \return Returns \b true if a peripheral trigger event has occurred and its +//! flag is set. Returns \b false otherwise. +// +//***************************************************************************** +static inline bool +DMA_getTriggerFlagStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Read the peripheral trigger flag and return appropriately. + // + return((HWREGH(base + DMA_O_CONTROL) & DMA_CONTROL_PERINTFLG) != 0U); +} + +//***************************************************************************** +// +//! Starts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function starts the DMA running, typically after you have configured +//! it. It will wait for the first trigger event to start operation. To halt +//! the channel use DMA_stopChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_startChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the run bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_RUN; + EDIS; +} + +//***************************************************************************** +// +//! Halts a DMA channel. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function halts the DMA at its current state and any current read-write +//! access is completed. To start the channel again use DMA_startChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_stopChannel(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Set the halt bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_HALT; + EDIS; +} + +//***************************************************************************** +// +//! Enables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables a DMA channel interrupt source. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel interrupt source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTE; + EDIS; +} + +//***************************************************************************** +// +//! Enables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function enables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. An overrun is when a peripheral +//! event trigger is received by the DMA before a previous trigger on that +//! channel had been serviced and its flag had been cleared. +//! +//! Note that this is the same interrupt signal as the interrupt that gets +//! generated at the beginning/end of a transfer. That interrupt must first be +//! enabled using DMA_enableInterrupt() in order for the overrun interrupt to +//! be generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_enableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Enable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) |= DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the DMA channel overrun interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function disables the indicated DMA channel's ability to generate an +//! interrupt upon the detection of an overrun. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_disableOverrunInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Disable the specified DMA channel interrupt. + // + EALLOW; + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_OVRINTE; + EDIS; +} + +//***************************************************************************** +// +//! Clears the DMA channel error flags. +//! +//! \param base is the base address of the DMA channel control registers. +//! +//! This function clears both the DMA channel's sync error flag and its +//! overrun error flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_clearErrorFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + // + // Write to the error clear bit. + // + EALLOW; + HWREGH(base + DMA_O_CONTROL) |= DMA_CONTROL_ERRCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the interrupt generation mode of a DMA channel interrupt. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param mode is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e mode parameter +//! is \b DMA_INT_AT_END, the DMA channel interrupt will be generated at the +//! end of the transfer. If \b DMA_INT_AT_BEGINNING, the interrupt will be +//! generated at the beginning of a new transfer. Generating at the beginning +//! of a new transfer is the default behavior. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setInterruptMode(uint32_t base, DMA_InterruptMode mode) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Write the selected interrupt generation mode to the register. + // + if(mode == DMA_INT_AT_END) + { + HWREGH(base + DMA_O_MODE) |= DMA_MODE_CHINTMODE; + } + else + { + HWREGH(base + DMA_O_MODE) &= ~DMA_MODE_CHINTMODE; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the DMA channel priority mode. +//! +//! \param ch1IsHighPri is a flag to indicate the channel interrupt mode. +//! +//! This function sets the channel interrupt mode. When the \e ch1IsHighPri +//! parameter is \b false, the DMA channels are serviced in round-robin mode. +//! This is the default behavior. +//! +//! If \b true, channel 1 will be given higher priority than the other +//! channels. This means that if a channel 1 trigger occurs, the current word +//! transfer on any other channel is completed and channel 1 is serviced for +//! the complete burst count. The lower-priority channel's interrupted transfer +//! will then resume. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_setPriorityMode(bool ch1IsHighPri) +{ + EALLOW; + + // + // Write the selected priority mode to the register. + // + if(ch1IsHighPri) + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) |= + DMA_PRIORITYCTRL1_CH1PRIORITY; + } + else + { + HWREGH(DMA_BASE + DMA_O_PRIORITYCTRL1) &= + ~DMA_PRIORITYCTRL1_CH1PRIORITY; + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the source address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *srcAddr is a source address. +//! +//! This function configures the source address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configSourceAddress(uint32_t base, const void *srcAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up SOURCE address. + // + HWREG(base + DMA_O_SRC_BEG_ADDR_SHADOW) = (uint32_t)srcAddr; + HWREG(base + DMA_O_SRC_ADDR_SHADOW) = (uint32_t)srcAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the destination address for the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! +//! This function configures the destinaton address of a DMA +//! channel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +DMA_configDestAddress(uint32_t base, const void *destAddr) +{ + // + // Check the arguments. + // + ASSERT(DMA_isBaseValid(base)); + + EALLOW; + + // + // Set up DESTINATION address. + // + HWREG(base + DMA_O_DST_BEG_ADDR_SHADOW) = (uint32_t)destAddr; + HWREG(base + DMA_O_DST_ADDR_SHADOW) = (uint32_t)destAddr; + + EDIS; +} + +//***************************************************************************** +// +//! Setup DMA to transfer data on the specified channel. +//! +//! \param base is Base address of the DMA channel control register +//! \param *transfParams configuration parameter +//! Refer struct #DMA_ConfigParams +//! +//! This function configures the DMA transfer on the specified channel. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configChannel(uint32_t base, const DMA_ConfigParams *transfParams); + +//***************************************************************************** +// +//! Configures the DMA channel +//! +//! \param base is the base address of the DMA channel control registers. +//! \param *destAddr is the destination address. +//! \param *srcAddr is a source address. +//! +//! This function configures the source and destination addresses of a DMA +//! channel. The parameters are pointers to the data to be transferred. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configAddresses(uint32_t base, const void *destAddr, const void *srcAddr); + +//***************************************************************************** +// +//! Configures the DMA channel's burst settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param size is the number of words transferred per burst. +//! \param srcStep is the amount to increment or decrement the source address +//! after each word of a burst. +//! \param destStep is the amount to increment or decrement the destination +//! address after each word of a burst. +//! +//! This function configures the size of each burst and the address step size. +//! +//! The \e size parameter is the number of words that will be transferred +//! during a single burst. Possible amounts range from 1 word to 32 words. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred word of a burst. Only signed values from -4096 to 4095 are +//! valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void DMA_configBurst(uint32_t base, uint16_t size, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's transfer settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param transferSize is the number of bursts per transfer. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the transfer size and the address step that is +//! made after each burst. +//! +//! The \e transferSize parameter is the number of bursts per transfer. If DMA +//! channel interrupts are enabled, they will occur after this number of bursts +//! have completed. The maximum number of bursts is 65536. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses after each +//! transferred burst of a transfer. Only signed values from -4096 to 4095 are +//! valid. If a wrap occurs, these step values will be ignored. Wrapping is +//! configured with DMA_configWrap(). +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configTransfer(uint32_t base, uint32_t transferSize, int16_t srcStep, + int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel's wrap settings. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param srcWrapSize is the number of bursts to be transferred before a wrap +//! of the source address occurs. +//! \param srcStep is the amount to increment or decrement the source address +//! after each burst of a transfer unless a wrap occurs. +//! \param destWrapSize is the number of bursts to be transferred before a wrap +//! of the destination address occurs. +//! \param destStep is the amount to increment or decrement the destination +//! address after each burst of a transfer unless a wrap occurs. +//! +//! This function configures the DMA channel's wrap settings. +//! +//! The \e srcWrapSize and \e destWrapSize parameters are the number of bursts +//! that are to be transferred before their respective addresses are wrapped. +//! The maximum wrap size is 65536 bursts. +//! +//! The \e srcStep and \e destStep parameters specify the address step that +//! should be added to the source and destination addresses when the wrap +//! occurs. Only signed values from -4096 to 4095 are valid. +//! +//! \note Note that regardless of what data size (configured by +//! DMA_configMode()) is used, parameters are in terms of 16-bits words. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configWrap(uint32_t base, uint32_t srcWrapSize, int16_t srcStep, + uint32_t destWrapSize, int16_t destStep); + +//***************************************************************************** +// +//! Configures the DMA channel trigger and mode. +//! +//! \param base is the base address of the DMA channel control registers. +//! \param trigger is the interrupt source that triggers a DMA transfer. +//! \param config is a bit field of several configuration selections. +//! +//! This function configures the DMA channel's trigger and mode. +//! +//! The \e trigger parameter is the interrupt source that will trigger the +//! start of a DMA transfer. +//! +//! The \e config parameter is the logical OR of the following values: +//! - \b DMA_CFG_ONESHOT_DISABLE or \b DMA_CFG_ONESHOT_ENABLE. If enabled, +//! the subsequent burst transfers occur without additional event triggers +//! after the first event trigger. If disabled, only one burst transfer is +//! performed per event trigger. +//! - \b DMA_CFG_CONTINUOUS_DISABLE or \b DMA_CFG_CONTINUOUS_ENABLE. If enabled +//! the DMA reinitializes when the transfer count is zero and waits for the +//! next interrupt event trigger. If disabled, the DMA stops and clears the +//! run status bit. +//! - \b DMA_CFG_SIZE_16BIT or \b DMA_CFG_SIZE_32BIT. This setting selects +//! whether the databus width is 16 or 32 bits. +//! +//! \return None. +// +//***************************************************************************** +extern void +DMA_configMode(uint32_t base, DMA_Trigger trigger, uint32_t config); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // DMA_H diff --git a/gpio_driverlib_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h b/gpio_driverlib_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h new file mode 100644 index 0000000..00e9ac6 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/driver_inclusive_terminology_mapping.h @@ -0,0 +1,109 @@ +#ifndef DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ +#define DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ + + +//***************************************************************************** +// CLB +//***************************************************************************** +#define CLB_LOCAL_IN_MUX_SPISIMO_SLAVE CLB_LOCAL_IN_MUX_SPIPICO_PERIPHERAL +#define CLB_LOCAL_IN_MUX_SPISIMO_MASTER CLB_LOCAL_IN_MUX_SPIPICO_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI1_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI1_SPISTE CLB_GLOBAL_IN_MUX_SPI1_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI2_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI2_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI2_SPISTE CLB_GLOBAL_IN_MUX_SPI2_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI3_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI3_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI3_SPISTE CLB_GLOBAL_IN_MUX_SPI3_SPIPTE +#define CLB_GLOBAL_IN_MUX_SPI4_SPISOMI_MASTER CLB_GLOBAL_IN_MUX_SPI4_SPIPOCI_CONTROLLER +#define CLB_GLOBAL_IN_MUX_SPI4_SPISTE CLB_GLOBAL_IN_MUX_SPI4_SPIPTE + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_MODE_SLAVE SPI_MODE_PERIPHERAL +#define SPI_MODE_MASTER SPI_MODE_CONTROLLER +#define SPI_MODE_SLAVE_OD SPI_MODE_PERIPHERAL_OD +#define SPI_MODE_MASTER_OD SPI_MODE_CONTROLLER_OD + +#define SPI_STE_ACTIVE_LOW SPI_PTE_ACTIVE_LOW +#define SPI_STE_ACTIVE_HIGH SPI_PTE_ACTIVE_HIGH + +#define SPI_setSTESignalPolarity SPI_setPTESignalPolarity + + +//***************************************************************************** +// Interrupt +//***************************************************************************** +#define Interrupt_enableMaster Interrupt_enableGlobal +#define Interrupt_disableMaster Interrupt_disableGlobal + + +//***************************************************************************** +// SysCtrl +//***************************************************************************** +#define SysCtl_AccessMaster SysCtl_AccessController +#define SYSCTL_SEC_MASTER_CLA SYSCTL_SEC_CONTROLLER_CLA +#define SYSCTL_SEC_MASTER_DMA SYSCTL_SEC_CONTROLLER_DMA +#define SysCtl_selectSecMaster SysCtl_selectSecController + + +//***************************************************************************** +// GPIO +//***************************************************************************** +#define GPIO_setMasterCore GPIO_setControllerCore + + + +//***************************************************************************** +// Memcfg +//***************************************************************************** +#define MemCfg_LSRAMMMasterSel MemCfg_LSRAMMControllerSel +#define MEMCFG_LSRAMMASTER_CPU_ONLY MEMCFG_LSRAMCONTROLLER_CPU_ONLY +#define MEMCFG_LSRAMMASTER_CPU_CLA1 MEMCFG_LSRAMCONTROLLER_CPU_CLA1 +#define MemCfg_setLSRAMMasterSel MemCfg_setLSRAMControllerSel + +#define MemCfg_GSRAMMasterSel MemCfg_GSRAMControllerSel +#define MEMCFG_GSRAMMASTER_CPU1 MEMCFG_GSRAMCONTROLLER_CPU1 +#define MEMCFG_GSRAMMASTER_CPU2 MEMCFG_GSRAMCONTROLLER_CPU2 +#define MemCfg_setGSRAMMasterSel MemCfg_setGSRAMControllerSel + +//***************************************************************************** +// EMIF +//***************************************************************************** +#define EMIF_MasterSelect EMIF_ControllerSelect +#define EMIF_selectMaster EMIF_selectController +#define EMIF_MASTER_CPU1_NG EMIF_CONTROLLER_CPU1_NG +#define EMIF_MASTER_CPU1_G EMIF_CONTROLLER_CPU1_G +#define EMIF_MASTER_CPU2_G EMIF_CONTROLLER_CPU2_G +#define EMIF_MASTER_CPU1_NG2 EMIF_CONTROLLER_CPU1_NG2 + + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_MASTER_SEND_MODE I2C_CONTROLLER_SEND_MODE +#define I2C_MASTER_RECEIVE_MODE I2C_CONTROLLER_RECEIVE_MODE +#define I2C_SLAVE_SEND_MODE I2C_TARGET_SEND_MODE +#define I2C_SLAVE_RECEIVE_MODE I2C_TARGET_RECEIVE_MODE +#define I2C_INT_ADDR_SLAVE I2C_INT_ADDR_TARGET +#define I2C_STS_ADDR_SLAVE I2C_STS_ADDR_TARGET +#define I2C_STS_SLAVE_DIR I2C_STS_TARGET_DIR +#define I2C_INTSRC_ADDR_SLAVE I2C_INTSRC_ADDR_TARGET + +#define I2C_initMaster I2C_initController +#define I2C_setSlaveAddress I2C_setTargetAddress +#define I2C_setOwnSlaveAddress I2C_setOwnAddress + + +//***************************************************************************** +// SDFM +//***************************************************************************** +#define SDFM_enableMasterInterrupt SDFM_enableMainInterrupt +#define SDFM_disableMasterInterrupt SDFM_disableMainInterrupt +#define SDFM_enableMasterFilter SDFM_enableMainFilter +#define SDFM_disableMasterFilter SDFM_disableMainFilter + +#define SDFM_MASTER_INTERRUPT_FLAG SDFM_MAIN_INTERRUPT_FLAG + +#endif /* DRIVER_INCLUSIVE_TERMINOLOGY_MAPPING_H_ */ diff --git a/gpio_driverlib_cpu1/device/driverlib/ecap.c b/gpio_driverlib_cpu1/device/driverlib/ecap.c new file mode 100644 index 0000000..4a48441 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/ecap.c @@ -0,0 +1,61 @@ +//########################################################################### +// +// FILE: ecap.c +// +// TITLE: C28x ECAP driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ecap.h" + +//***************************************************************************** +// +// ECAP_setEmulationMode +// +//***************************************************************************** +void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to FREE/SOFT bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_FREE_SOFT_M)) | + ((uint16_t)mode << ECAP_ECCTL1_FREE_SOFT_S)); +} diff --git a/gpio_driverlib_cpu1/device/driverlib/ecap.h b/gpio_driverlib_cpu1/device/driverlib/ecap.h new file mode 100644 index 0000000..577d7a8 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/ecap.h @@ -0,0 +1,1164 @@ +//########################################################################### +// +// FILE: ecap.h +// +// TITLE: C28x ECAP driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef ECAP_H +#define ECAP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ecap_api eCAP +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// Includes +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ecap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// eCAP minimum and maximum values +// +//***************************************************************************** +#define ECAP_MAX_PRESCALER_VALUE 32U // Maximum Pre-scaler value + +//***************************************************************************** +// +// Values that can be passed to ECAP_enableInterrupt(), +// ECAP_disableInterrupt(), ECAP_clearInterrupt() and ECAP_forceInterrupt() as +// the intFlags parameter and returned by ECAP_getInterruptSource(). +// +//***************************************************************************** +//! Event 1 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_1 0x2U +//! Event 2 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_2 0x4U +//! Event 3 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_3 0x8U +//! Event 4 ISR source +//! +#define ECAP_ISR_SOURCE_CAPTURE_EVENT_4 0x10U +//! Counter overflow ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_OVERFLOW 0x20U +//! Counter equals period ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_PERIOD 0x40U +//! Counter equals compare ISR source +//! +#define ECAP_ISR_SOURCE_COUNTER_COMPARE 0x80U + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEmulationMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! TSCTR is stopped on emulation suspension + ECAP_EMULATION_STOP = 0x0U, + //! TSCTR runs until 0 before stopping on emulation suspension + ECAP_EMULATION_RUN_TO_ZERO = 0x1U, + //! TSCTR is not affected by emulation suspension + ECAP_EMULATION_FREE_RUN = 0x2U +}ECAP_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setCaptureMode() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! eCAP operates in continuous capture mode + ECAP_CONTINUOUS_CAPTURE_MODE = 0U, + //! eCAP operates in one shot capture mode + ECAP_ONE_SHOT_CAPTURE_MODE = 1U +}ECAP_CaptureMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity(),ECAP_setCaptureMode(), +//! ECAP_enableCounterResetOnEvent(),ECAP_disableCounterResetOnEvent(), +//! ECAP_getEventTimeStamp(),ECAP_setDMASource() as the \e event parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVENT_1 = 0U, //!< eCAP event 1 + ECAP_EVENT_2 = 1U, //!< eCAP event 2 + ECAP_EVENT_3 = 2U, //!< eCAP event 3 + ECAP_EVENT_4 = 3U //!< eCAP event 4 +}ECAP_Events; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setSyncOutMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! sync out on the sync in signal and software force + ECAP_SYNC_OUT_SYNCI = 0x00U, + //! sync out on counter equals period + ECAP_SYNC_OUT_COUNTER_PRD = 0x40U, + //! Disable sync out signal + ECAP_SYNC_OUT_DISABLED = 0x80U +}ECAP_SyncOutMode; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setAPWMPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_APWM_ACTIVE_HIGH = 0x000, //!< APWM is active high + ECAP_APWM_ACTIVE_LOW = 0x400 //!< APWM is active low +}ECAP_APWMPolarity; + +//***************************************************************************** +// +//! Values that can be passed to ECAP_setEventPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + ECAP_EVNT_RISING_EDGE = 0U, //!< Rising edge polarity + ECAP_EVNT_FALLING_EDGE = 1U //!< Falling edge polarity +}ECAP_EventPolarity; + +//***************************************************************************** +// +//! \internal +//! Checks eCAP base address. +//! +//! \param base specifies the eCAP module base address. +//! +//! This function determines if an eCAP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool ECAP_isBaseValid(uint32_t base) +{ + return( + (base == ECAP1_BASE) || + (base == ECAP2_BASE) || + (base == ECAP3_BASE) || + (base == ECAP4_BASE) || + (base == ECAP5_BASE) || + (base == ECAP6_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the input prescaler. +//! +//! \param base is the base address of the ECAP module. +//! \param preScalerValue is the pre scaler value for ECAP input +//! +//! This function divides the ECAP input scaler. The pre scale value is +//! doubled inside the module. For example a preScalerValue of 5 will divide +//! the scaler by 10. Use a value of 1 to divide the pre scaler by 1. +//! The \e preScalerValue should be less than \b ECAP_MAX_PRESCALER_VALUE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPrescaler(uint32_t base, + uint16_t preScalerValue) +{ + ASSERT(ECAP_isBaseValid(base)); + + ASSERT(preScalerValue < ECAP_MAX_PRESCALER_VALUE); + + + // + // Write to PRESCALE bit + // + HWREGH(base + ECAP_O_ECCTL1) = + ((HWREGH(base + ECAP_O_ECCTL1) & (~ECAP_ECCTL1_PRESCALE_M)) | + (preScalerValue << ECAP_ECCTL1_PRESCALE_S)); +} + +//***************************************************************************** +// +//! Sets the Capture event polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! \param polarity is the polarity of the event. +//! +//! This function sets the polarity of a given event. The value of event +//! is between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 inclusive corresponding to +//! the four available events.For each event the polarity value determines the +//! edge on which the capture is activated. For a rising edge use a polarity +//! value of \b ECAP_EVNT_RISING_EDGE and for a falling edge use a polarity of +//! \b ECAP_EVNT_FALLING_EDGE. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setEventPolarity(uint32_t base, + ECAP_Events event, + ECAP_EventPolarity polarity) +{ + + uint16_t shift; + + ASSERT(ECAP_isBaseValid(base)); + + shift = ((uint16_t)event) << 1U; + + + // + // Write to CAP1POL, CAP2POL, CAP3POL or CAP4POL + // + HWREGH(base + ECAP_O_ECCTL1) = + (HWREGH(base + ECAP_O_ECCTL1) & ~(1U << shift)) | + ((uint16_t)polarity << shift); +} + +//***************************************************************************** +// +//! Sets the capture mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the capture mode. +//! \param event is the event number at which the counter stops or wraps. +//! +//! This function sets the eCAP module to a continuous or one-shot mode. +//! The value of mode should be either \b ECAP_CONTINUOUS_CAPTURE_MODE or +//! \b ECAP_ONE_SHOT_CAPTURE_MODE corresponding to continuous or one-shot mode +//! respectively. +//! +//! The value of event determines the event number at which the counter stops +//! (in one-shot mode) or the counter wraps (in continuous mode). The value of +//! event should be between \b ECAP_EVENT_1 and \b ECAP_EVENT_4 corresponding +//! to the valid event numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setCaptureMode(uint32_t base, + ECAP_CaptureMode mode, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to CONT/ONESHT + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_CONT_ONESHT)) | + (uint16_t)mode); + + // + // Write to STOP_WRAP + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_STOP_WRAP_M)) | + (((uint16_t)event) << ECAP_ECCTL2_STOP_WRAP_S )); +} + +//***************************************************************************** +// +//! Re-arms the eCAP module. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function re-arms the eCAP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_reArm(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to RE-ARM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_REARM; +} + +//***************************************************************************** +// +//! Enables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be enabled. +//! +//! This function sets and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + + // + // Set bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source to be disabled. +//! +//! This function clears and disables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableInterrupt(uint32_t base, + uint16_t intFlags) +{ + + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Clear bits in ECEINT register + // + HWREGH(base + ECAP_O_ECEINT) &= ~intFlags; +} + +//***************************************************************************** +// +//! Returns the interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP interrupt flag. The following are valid +//! interrupt sources corresponding to the eCAP interrupt flag. +//! +//! \return Returns the eCAP interrupt that has occurred. The following are +//! valid return values. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \note - User can check if a combination of various interrupts have occurred +//! by ORing the above return values. +// +//***************************************************************************** +static inline uint16_t ECAP_getInterruptSource(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of ECFLG register + // + return(HWREGH(base + ECAP_O_ECFLG) & 0xFEU); +} + +//***************************************************************************** +// +//! Returns the Global interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the eCAP Global interrupt flag. +//! +//! \return Returns true if there is a global eCAP interrupt, false otherwise. +// +//***************************************************************************** +static inline bool ECAP_getGlobalInterruptStatus(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Return contents of Global interrupt bit + // + return((HWREGH(base + ECAP_O_ECFLG) & 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Clears interrupt flag. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function clears eCAP interrupt flags. The following are valid +//! interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + // + // Write to ECCLR register + // + HWREGH(base + ECAP_O_ECCLR) = intFlags; +} + +//***************************************************************************** +// +//! Clears global interrupt flag +//! +//! \param base is the base address of the ECAP module. +//! +//! This function clears the global interrupt bit. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_clearGlobalInterrupt(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to INT bit + // + HWREGH(base + ECAP_O_ECCLR) = ECAP_ECCLR_INT; +} + +//***************************************************************************** +// +//! Forces interrupt source. +//! +//! \param base is the base address of the ECAP module. +//! \param intFlags is the interrupt source. +//! +//! This function forces and enables eCAP interrupt source. The following are +//! valid interrupt sources. +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_1 - Event 1 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_2 - Event 2 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_3 - Event 3 generates interrupt +//! - ECAP_ISR_SOURCE_CAPTURE_EVENT_4 - Event 4 generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_OVERFLOW - Counter overflow generates interrupt +//! - ECAP_ISR_SOURCE_COUNTER_PERIOD - Counter equal period generates +//! interrupt +//! - ECAP_ISR_SOURCE_COUNTER_COMPARE - Counter equal compare generates +//! interrupt +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_forceInterrupt(uint32_t base, + uint16_t intFlags) +{ + ASSERT(ECAP_isBaseValid(base)); + ASSERT((intFlags & ~(ECAP_ISR_SOURCE_CAPTURE_EVENT_1 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_2 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_3 | + ECAP_ISR_SOURCE_CAPTURE_EVENT_4 | + ECAP_ISR_SOURCE_COUNTER_OVERFLOW | + ECAP_ISR_SOURCE_COUNTER_PERIOD | + ECAP_ISR_SOURCE_COUNTER_COMPARE)) == 0U); + + + // + // Write to ECFRC register + // + HWREGH(base + ECAP_O_ECFRC) = intFlags; +} + +//***************************************************************************** +// +//! Sets eCAP in Capture mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCaptureMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Sets eCAP in APWM mode. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function sets the eCAP module to operate in APWM mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableAPWMMode(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAP/APWM bit + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_CAP_APWM; +} + +//***************************************************************************** +// +//! Enables counter reset on an event. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function enables the base timer, TSCTR, to be reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) |= 1U << ((2U * (uint16_t)event) + 1U); +} + +//***************************************************************************** +// +//! Disables counter reset on events. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number the time base gets reset. +//! +//! This function disables the base timer, TSCTR, from being reset on capture +//! event provided by the variable event. Valid inputs for event are +//! \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableCounterResetOnEvent(uint32_t base, + ECAP_Events event) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CTRRST1,CTRRST2,CTRRST3 or CTRRST4 bits + // + HWREGH(base + ECAP_O_ECCTL1) &= ~(1U << ((2U * (uint16_t)event) + 1U)); +} + +//***************************************************************************** +// +//! Enables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) |= ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Disables time stamp capture. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables time stamp count to be captured +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableTimeStampCapture(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear CAPLDEN bit + // + HWREGH(base + ECAP_O_ECCTL1) &= ~ECAP_ECCTL1_CAPLDEN; +} + +//***************************************************************************** +// +//! Sets a phase shift value count. +//! +//! \param base is the base address of the ECAP module. +//! \param shiftCount is the phase shift value. +//! +//! This function writes a phase shift value to be loaded into the main time +//! stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setPhaseShiftCount(uint32_t base, uint32_t shiftCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CTRPHS + // + HWREG(base + ECAP_O_CTRPHS) = shiftCount; +} + +//***************************************************************************** +// +//! Enable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function enables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_enableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Disable counter loading with phase shift value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function disables loading of the counter with the value present in the +//! phase shift counter as defined by the ECAP_setPhaseShiftCount() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_disableLoadCounter(uint32_t base) +{ + + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCI_EN + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_SYNCI_EN; +} + +//***************************************************************************** +// +//! Load time stamp counter +//! +//! \param base is the base address of the ECAP module. +//! +//! This function forces the value in the phase shift counter register to be +//! loaded into Time stamp counter register. +//! Make sure to enable loading of Time stamp counter by calling +//! ECAP_enableLoadCounter() function before calling this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_loadCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SWSYNC + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_SWSYNC; +} + +//***************************************************************************** +// +//! Configures Sync out signal mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the sync out mode. +//! +//! This function sets the sync out mode. Valid parameters for mode are: +//! - ECAP_SYNC_OUT_SYNCI - Trigger sync out on sync-in event. +//! - ECAP_SYNC_OUT_COUNTER_PRD - Trigger sync out when counter equals period. +//! - ECAP_SYNC_OUT_DISABLED - Disable sync out. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setSyncOutMode(uint32_t base, + ECAP_SyncOutMode mode) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Write to SYNCO_SEL + // + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & (~ECAP_ECCTL2_SYNCO_SEL_M)) | + (uint16_t)mode); +} + +//***************************************************************************** +// +//! Stops Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function stops the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_stopCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Clear TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) &= ~ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Starts Time stamp counter. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function starts the time stamp counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_startCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + + // + // Set TSCTR + // + HWREGH(base + ECAP_O_ECCTL2) |= ECAP_ECCTL2_TSCTRSTOP; +} + +//***************************************************************************** +// +//! Set eCAP APWM polarity. +//! +//! \param base is the base address of the ECAP module. +//! \param polarity is the polarity of APWM +//! +//! This function sets the polarity of the eCAP in APWM mode. Valid inputs for +//! polarity are: +//! - ECAP_APWM_ACTIVE_HIGH - For active high. +//! - ECAP_APWM_ACTIVE_LOW - For active low. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPolarity(uint32_t base, + ECAP_APWMPolarity polarity) +{ + ASSERT(ECAP_isBaseValid(base)); + + HWREGH(base + ECAP_O_ECCTL2) = + ((HWREGH(base + ECAP_O_ECCTL2) & ~ECAP_ECCTL2_APWMPOL) | + (uint16_t)polarity); +} + +//***************************************************************************** +// +//! Set eCAP APWM period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the period count for APWM. +//! +//! This function sets the period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMPeriod(uint32_t base, uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP1 + // + HWREG(base + ECAP_O_CAP1) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the on or off time count of the APWM waveform depending +//! on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity(), is active high then compareCount determines the on +//! time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMCompare(uint32_t base, uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP2 + // + HWREG(base + ECAP_O_CAP2) = compareCount; +} + +//***************************************************************************** +// +//! Load eCAP APWM shadow period. +//! +//! \param base is the base address of the ECAP module. +//! \param periodCount is the shadow period count for APWM. +//! +//! This function sets the shadow period count of the APWM waveform. +//! periodCount takes the actual count which is written to the register. The +//! user is responsible for converting the desired frequency or time into +//! the period count. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowPeriod(uint32_t base, + uint32_t periodCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP3 + // + HWREG(base + ECAP_O_CAP3) = periodCount; +} + +//***************************************************************************** +// +//! Set eCAP APWM shadow on or off time count. +//! +//! \param base is the base address of the ECAP module. +//! \param compareCount is the on or off count for APWM. +//! +//! This function sets the shadow on or off time count of the APWM waveform +//! depending on the polarity of the output. If the output , as set by +//! ECAP_setAPWMPolarity() , is active high then compareCount determines the +//! on time. If the output is active low then compareCount determines the off +//! time. compareCount takes the actual count which is written to the register. +//! The user is responsible for converting the desired frequency or time into +//! the appropriate count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void ECAP_setAPWMShadowCompare(uint32_t base, + uint32_t compareCount) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Write to CAP4 + // + HWREG(base + ECAP_O_CAP4) = compareCount; +} + +//***************************************************************************** +// +//! Returns the time base counter value. +//! +//! \param base is the base address of the ECAP module. +//! +//! This function returns the time base counter value. +//! +//! \return Returns the time base counter value. +// +//***************************************************************************** +static inline uint32_t ECAP_getTimeBaseCounter(uint32_t base) +{ + ASSERT(ECAP_isBaseValid(base)); + + // + // Read the Time base counter value + // + return(HWREG(base + ECAP_O_TSCTR)); +} + +//***************************************************************************** +// +//! Returns event time stamp. +//! +//! \param base is the base address of the ECAP module. +//! \param event is the event number. +//! +//! This function returns the current time stamp count of the given event. +//! Valid values for event are \b ECAP_EVENT_1 to \b ECAP_EVENT_4. +//! +//! \return Event time stamp value or 0 if \e event is invalid. +// +//***************************************************************************** +static inline uint32_t ECAP_getEventTimeStamp(uint32_t base, ECAP_Events event) +{ + uint32_t count; + + ASSERT(ECAP_isBaseValid(base)); + + + switch(event) + { + case ECAP_EVENT_1: + + // + // Read CAP1 register + // + count = HWREG(base + ECAP_O_CAP1); + break; + + case ECAP_EVENT_2: + // + // Read CAP2 register + // + count = HWREG(base + ECAP_O_CAP2); + break; + + case ECAP_EVENT_3: + + // + // Read CAP3 register + // + count = HWREG(base + ECAP_O_CAP3); + break; + + case ECAP_EVENT_4: + + // + // Read CAP4 register + // + count = HWREG(base + ECAP_O_CAP4); + break; + + default: + + // + // Invalid event parameter + // + count = 0U; + break; + } + + return(count); +} + +//***************************************************************************** +// +//! Configures emulation mode. +//! +//! \param base is the base address of the ECAP module. +//! \param mode is the emulation mode. +//! +//! This function configures the eCAP counter, TSCTR, to the desired emulation +//! mode when emulation suspension occurs. Valid inputs for mode are: +//! - ECAP_EMULATION_STOP - Counter is stopped immediately. +//! - ECAP_EMULATION_RUN_TO_ZERO - Counter runs till it reaches 0. +//! - ECAP_EMULATION_FREE_RUN - Counter is not affected. +//! +//! \return None. +// +//***************************************************************************** +extern void ECAP_setEmulationMode(uint32_t base, ECAP_EmulationMode mode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // ECAP_H diff --git a/gpio_driverlib_cpu1/device/driverlib/emif.c b/gpio_driverlib_cpu1/device/driverlib/emif.c new file mode 100644 index 0000000..a862104 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/emif.c @@ -0,0 +1,46 @@ +//########################################################################### +// +// FILE: emif.c +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "emif.h" + diff --git a/gpio_driverlib_cpu1/device/driverlib/emif.h b/gpio_driverlib_cpu1/device/driverlib/emif.h new file mode 100644 index 0000000..7177421 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/emif.h @@ -0,0 +1,1369 @@ +//########################################################################### +// +// FILE: emif.h +// +// TITLE: C28x EMIF driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EMIF_H +#define EMIF_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup emif_api EMIF +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_emif.h" +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines to specify access protection to EMIF_setAccessProtection(). +// +//***************************************************************************** +//! This flag is used to specify whether CPU fetches are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_FETCHPROT MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 + +//! This flag is used to specify whether CPU writes are allowed/blocked +//! for EMIF. +#define EMIF_ACCPROT0_CPUWRPROT MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 + +//! This flag is used to specify whether DMA writes are allowed/blocked +//! for EMIF. It is valid only for EMIF1 instance. +#define EMIF_ACCPROT0_DMAWRPROT MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF1ACCPROT0 register that aren't +// associated with EMIF1 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF1 \ + ((uint16_t)MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 |\ + (uint16_t)MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1) + +//***************************************************************************** +// +// Define to mask out the bits in the EMIF2ACCPROT0 register that aren't +// associated with EMIF2 access protection. +// +//***************************************************************************** +#define EMIF_ACCPROT0_MASK_EMIF2 \ + ((uint16_t)MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 |\ + (uint16_t)MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2) + +//***************************************************************************** +// +// Define to mask out the bits in the ASYNC_CSx_CR register that +// aren't associated with async configuration. +// +//***************************************************************************** +#define EMIF_ASYNC_CS_CR_MASK ((uint32_t)EMIF_ASYNC_CS2_CR_R_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_R_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_HOLD_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_STROBE_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_W_SETUP_M | \ + (uint32_t)EMIF_ASYNC_CS2_CR_TA_M) + +//***************************************************************************** +// +// Define to mask out the bits in the INT_MSK register that aren't associated +// with interrupts. +// +//***************************************************************************** +#define EMIF_ASYNC_INT_MASK ((uint16_t)EMIF_INT_MSK_SET_AT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_LT_MASK_SET | \ + (uint16_t)EMIF_INT_MSK_SET_WR_MASK_SET_M) + +//***************************************************************************** +// +// Defines to specify interrupt sources to EMIF_enableAsyncInterrupt() and +// EMIF_disableAsyncInterrupt().Three interrupts are available for asynchronous +// memory interface: Masked Asyncronous Timeout(AT) to indicate EMxWAIT signal +// remains active even after maximum wait cycles are reached. Masked Line Trap +// (LT) to indicate illegal memory access or invalid cache line size. +// Masked Wait Rise(WR) to indicate rising edge on EMxWAIT is detected. +// +//***************************************************************************** +//! This flag is used to allow/block EMIF to generate Masked Asynchronous +//! Timeout interrupt. +#define EMIF_ASYNC_INT_AT EMIF_INT_MSK_SET_AT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Line Trap +//! interrupt. +#define EMIF_ASYNC_INT_LT EMIF_INT_MSK_SET_LT_MASK_SET + +//! This flag is used to allow/block EMIF to generate Masked Wait Rise +//! interrupt. +#define EMIF_ASYNC_INT_WR EMIF_INT_MSK_SET_WR_MASK_SET_M + +//***************************************************************************** +// +// Define for key for EMIF1MSEL register that enables the register write. +// +//***************************************************************************** +#define EMIF_MSEL_KEY 0x93A5CE70U + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_CR register that aren't +// associated with SDRAM configuration parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_CR_MASK ((uint32_t)EMIF_SDRAM_CR_PAGESIGE_M | \ + (uint32_t)EMIF_SDRAM_CR_IBANK_M | \ + (uint32_t)EMIF_SDRAM_CR_BIT_11_9_LOCK | \ + (uint32_t)EMIF_SDRAM_CR_CL_M | \ + (uint32_t)EMIF_SDRAM_CR_NM | \ + (uint32_t)EMIF_SDRAM_CR_SR) + +//***************************************************************************** +// +// Define to mask out the bits in the SDRAM_TR register that aren't +// associated with SDRAM timings parameters. +// +//***************************************************************************** +#define EMIF_SYNC_SDRAM_TR_MASK ((uint32_t)EMIF_SDRAM_TR_T_RRD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RC_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RAS_M | \ + (uint32_t)EMIF_SDRAM_TR_T_WR_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RCD_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RP_M | \ + (uint32_t)EMIF_SDRAM_TR_T_RFC_M) + +//***************************************************************************** +// +//! Values that can be passed to EMIF_setAsyncMode(), +//! EMIF_setAsyncTimingParams(), EMIF_setAsyncDataBusWidth(), +//! EMIF_enableAsyncExtendedWait() and EMIF_disableAsyncExtendedWait() +//! as the \e offset parameter. Three chip selects are available in +//! asynchronous memory interface so there are three configuration registers +//! available for each EMIF instance. All the three chip select offsets are +//! valid for EMIF1 while only EMIF_ASYNC_CS2_OFFSET is valid for EMIF2. +// +//***************************************************************************** +typedef enum +{ + EMIF_ASYNC_CS2_OFFSET = EMIF_O_ASYNC_CS2_CR, //! It is valid only for EMIF1 instance and not for EMIF2 instance. +//! Valid value for configBase parameter is EMIF1CONFIG_BASE. Valid +//! values for select parameter can be \e EMIF_CONTROLLER_CPU1_NG, +//! \e EMIF_CONTROLLER_CPU1_G, \e EMIF_CONTROLLER_CPU2_G or +//! \e EMIF_CONTROLLER_CPU1_NG2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_selectController(uint32_t configBase, EMIF_ControllerSelect select) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase)); + + // + // Sets the bits that enables EMIF1 controller selection. + // + EALLOW; + HWREG(configBase + MEMCFG_O_EMIF1MSEL) = (EMIF_MSEL_KEY | (uint32_t)select); + EDIS; +} + +//***************************************************************************** +// +//! Sets the access protection. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! \param access is the required access protection configuration. +//! +//! This function sets the access protection for an EMIF instance from CPU +//! and DMA. The \e access parameter can be any of \b EMIF_ACCPROT0_FETCHPROT, +//! \b EMIF_ACCPROT0_CPUWRPROT \b EMIF_ACCPROT0_DMAWRPROT values or their +//! combination. EMIF_ACCPROT0_DMAWRPROT value is valid as access parameter +//! for EMIF1 instance only . +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAccessProtection(uint32_t configBase, uint16_t access) +{ + uint16_t temp; + // + // Check the arguments. + // + + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + if(configBase == EMIF1CONFIG_BASE) + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF1); + temp = EMIF_ACCPROT0_MASK_EMIF1; + } + else + { + ASSERT(access <= EMIF_ACCPROT0_MASK_EMIF2); + temp = EMIF_ACCPROT0_MASK_EMIF2; + } + + // + // Sets the bits that enables access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) = + (HWREGH(configBase + MEMCFG_O_EMIF1ACCPROT0) & ~(temp)) | access; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function commits the access protection for an EMIF instance from +//! CPU & DMA. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_commitAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that commits access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1COMMIT) |= + MEMCFG_EMIF1COMMIT_COMMIT_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Locks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function locks the write to access configuration fields i.e +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_lockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that locks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) |= MEMCFG_EMIF1LOCK_LOCK_EMIF1; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the write to access configuration fields. +//! +//! \param configBase is the configuration address of the EMIF instance used. +//! +//! This function unlocks the write to access configuration fields such as +//! ACCPROT0 & Mselect fields, for an EMIF instance. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_unlockAccessConfig(uint32_t configBase) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isEMIF1ConfigBaseValid(configBase) || + EMIF_isEMIF2ConfigBaseValid(configBase)); + + // + // Sets the bits that unlocks access protection config. + // + EALLOW; + HWREGH(configBase + MEMCFG_O_EMIF1LOCK) &= + ~((uint16_t)MEMCFG_EMIF1LOCK_LOCK_EMIF1); + EDIS; +} + +//***************************************************************************** +// +// Prototypes for Asynchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Selects the asynchronous mode of operation. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param mode is the desired mode of operation for external memory. +//! +//! +//! This function sets the mode of operation for asynchronous memory +//! between Normal or Strobe mode. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values for param \e mode can be \e EMIF_ASYNC_STROBE_MODE or +//! \e EMIF_ASYNC_NORMAL_MODE. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMode(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncMode mode) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async mode of operation. + // + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) + & ~((uint32_t)EMIF_ASYNC_CS2_CR_SS)) + | (uint32_t)mode; +} + +//***************************************************************************** +// +//! Enables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of the +//! EMIF instance +//! +//! This function enables the extended wait mode for an asynchronous +//! external memory.Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that enables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) | + EMIF_ASYNC_CS2_CR_EW; +} + +//***************************************************************************** +// +//! Disables the Extended Wait Mode. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! This function disables the extended wait mode for an asynchronous external +//! memory.Valid values for param \e offset can be \e EMIF_ASYNC_CS2_OFFSET, +//! \e EMIF_ASYNC_CS3_OFFSET & \e EMIF_ASYNC_C43_OFFSET for EMIF1 and +//! \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncExtendedWait(uint32_t base, EMIF_AsyncCSOffset offset) + { + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the bit that disables extended wait mode. + // + HWREG(base + (uint32_t)offset) = HWREG(base + (uint32_t)offset) & + ~((uint32_t)EMIF_ASYNC_CS2_CR_EW); +} + +//***************************************************************************** +// +//! Sets the wait polarity. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param polarity is desired wait polarity. +//! +//! This function sets the wait polarity for an asynchronous external memory. +//! Valid values for param \e polarity can be \e EMIF_ASYNC_WAIT_POLARITY_LOW +//! or \e EMIF_ASYNC_WAIT_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncWaitPolarity(uint32_t base, EMIF_AsyncWaitPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the polarity for async extended wait mode. + // + HWREG(base + EMIF_O_ASYNC_WCCR) = (HWREG(base + EMIF_O_ASYNC_WCCR) + & ~((uint32_t)EMIF_ASYNC_WCCR_WP0)) + | (uint32_t)polarity; +} + +//***************************************************************************** +// +//! Sets the Maximum Wait Cycles. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param value is the desired maximum wait cycles. +//! +//! This function sets the maximum wait cycles for extended asynchronous cycle. +//! Valid values for parameter \e value lies b/w 0x0U-0xFFU or 0-255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncMaximumWaitCycles(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(value <= (EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)); + + // + // Sets the bit that enables extended wait mode. + // + HWREGH(base + EMIF_O_ASYNC_WCCR) = (HWREGH(base + EMIF_O_ASYNC_WCCR) + & ~((uint16_t)EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M)) + | value; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Memory Timing Characteristics. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param tParam is the desired timing parameters. +//! +//! This function sets timing characteristics for an external asynchronous +//! memory to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET and +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 & EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncTimingParams(uint32_t base, EMIF_AsyncCSOffset offset, + const EMIF_AsyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory timing parameters. + // + temp = (tParam->turnArnd << EMIF_ASYNC_CS2_CR_TA_S) | + (tParam->rHold << EMIF_ASYNC_CS2_CR_R_HOLD_S) | + (tParam->rStrobe << EMIF_ASYNC_CS2_CR_R_STROBE_S) | + (tParam->rSetup << EMIF_ASYNC_CS2_CR_R_SETUP_S) | + (tParam->wHold << EMIF_ASYNC_CS2_CR_W_HOLD_S) | + (tParam->wStrobe << EMIF_ASYNC_CS2_CR_W_STROBE_S) | + (tParam->wSetup << EMIF_ASYNC_CS2_CR_W_SETUP_S); + + HWREG(base + (uint32_t)offset) = (HWREG(base + (uint32_t)offset) & + ~EMIF_ASYNC_CS_CR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the Asynchronous Data Bus Width. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param offset is the offset of asynchronous chip select of EMIF instance. +//! +//! \param width is the data bus width of the memory. +//! +//! This function sets the data bus size for an external asynchronous memory +//! to be interfaced. Valid values for param \e offset can be +//! \e EMIF_ASYNC_CS2_OFFSET, \e EMIF_ASYNC_CS3_OFFSET & +//! \e EMIF_ASYNC_C43_OFFSET for EMIF1 and \e EMIF_ASYNC_CS2_OFFSET for EMIF2. +//! Valid values of param \e width can be \e EMIF_ASYNC_DATA_WIDTH_8, +//! \e EMIF_ASYNC_DATA_WIDTH_16 or \e EMIF_ASYNC_DATA_WIDTH_32. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setAsyncDataBusWidth(uint32_t base, EMIF_AsyncCSOffset offset, + EMIF_AsyncDataWidth width) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + if(base == EMIF2_BASE) + { + ASSERT(offset == EMIF_ASYNC_CS2_OFFSET); + } + + // + // Sets the async memory data bus width. + // + HWREGH(base + (uint32_t)offset) = (HWREGH(base + (uint32_t)offset) + & ~((uint16_t)EMIF_ASYNC_CS2_CR_ASIZE_M)) + | (uint32_t)width; +} + +//***************************************************************************** +// +// Prototypes for Interrupt Handling +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for desired interrupts. +//! +//! This function enables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or their +//! combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that enables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_SET) = intFlags; +} + +//***************************************************************************** +// +//! Disables the Asynchronous Memory Interrupts. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for interrupts to be disabled. +//! +//! This function disables the desired interrupts for an external asynchronous +//! memory interface. Valid values for param \e intFlags can be +//! \b EMIF_ASYNC_INT_AT, \b EMIF_ASYNC_INT_LT, \b EMIF_ASYNC_INT_WR or +//! their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableAsyncInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bits that disables async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK_CLR) = intFlags; + +} + +//***************************************************************************** +// +//! Gets the interrupt status. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function gets the interrupt status for an EMIF instance. +//! +//! \return Returns the current interrupt status. +// +//***************************************************************************** +static inline uint16_t +EMIF_getAsyncInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets the async memory interrupt status. + // + return(HWREGH(base + EMIF_O_INT_MSK) & EMIF_ASYNC_INT_MASK); +} + +//***************************************************************************** +// +//! Clears the interrupt status for an EMIF instance. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param intFlags is the mask for the interrupt status to be cleared. +//! +//! This function clears the interrupt status for an EMIF instance. +//! The \e intFlags parameter can be any of \b EMIF_INT_MSK_SET_AT_MASK_SET, +//! \b EMIF_INT_MSK_SET_LT_MASK_SET, or \b EMIF_INT_MSK_SET_WR_MASK_SET_M +//! values or their combination. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_clearAsyncInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(intFlags <= EMIF_ASYNC_INT_MASK); + + // + // Sets the bit that clears desired async memory interrupts. + // + HWREGH(base + EMIF_O_INT_MSK) = intFlags; +} + +//***************************************************************************** +// +// Prototypes for Synchronous Memory Interface +// +//***************************************************************************** +//***************************************************************************** +// +//! Sets the Synchronous Memory Timing Parameters. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tParam is parameters from memory datasheet in \e ns. +//! +//! This function sets the timing characteristics for an external +//! synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncTimingParams(uint32_t base, const EMIF_SyncTimingParams *tParam) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets sync memory timing parameters. + // + temp = ((tParam->tRrd << EMIF_SDRAM_TR_T_RRD_S) + & EMIF_SDRAM_TR_T_RRD_M) + | ((tParam->tRc << EMIF_SDRAM_TR_T_RC_S) + & EMIF_SDRAM_TR_T_RC_M) + | ((tParam->tRas << EMIF_SDRAM_TR_T_RAS_S) + & EMIF_SDRAM_TR_T_RAS_M) + | ((tParam->tWr << EMIF_SDRAM_TR_T_WR_S) + & EMIF_SDRAM_TR_T_WR_M) + | ((tParam->tRcd << EMIF_SDRAM_TR_T_RCD_S) + & EMIF_SDRAM_TR_T_RCD_M) + | ((tParam->tRp << EMIF_SDRAM_TR_T_RP_S) + & EMIF_SDRAM_TR_T_RP_M) + | ((tParam->tRfc << EMIF_SDRAM_TR_T_RFC_S) + & EMIF_SDRAM_TR_T_RFC_M); + + HWREG(base + EMIF_O_SDRAM_TR) = (HWREG(base + EMIF_O_SDRAM_TR) & + ~EMIF_SYNC_SDRAM_TR_MASK) | temp; +} + +//***************************************************************************** +// +//! Sets the SDRAM Self Refresh Exit Timing. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param tXs is the desired timing value. +//! +//! This function sets the self refresh exit timing for an external +//! synchronous memory to be interfaced. tXs values must lie between +//! 0x0U-0x1FU or 0-31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncSelfRefreshExitTmng(uint32_t base, uint16_t tXs) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(tXs <= EMIF_SDR_EXT_TMNG_T_XS_M); + + // + // Sets the self refresh exit timing for sync memory. + // + HWREGH(base + EMIF_O_SDR_EXT_TMNG) = (HWREGH(base + EMIF_O_SDR_EXT_TMNG) + & ~((uint16_t)EMIF_SDR_EXT_TMNG_T_XS_M)) + | tXs; +} + +//***************************************************************************** +// +//! Sets the SDR Refresh Rate. +//! +//! \param base is the base address of an EMIF instance. +//! +//! \param refRate is the refresh rate. +//! +//! This function sets the refresh rate for an external synchronous memory +//! to be interfaced. Valid values for refRate lies b/w 0x0U-0x1FFFU or +//! 0-8191. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncRefreshRate(uint32_t base, uint16_t refRate) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + ASSERT(refRate <= EMIF_SDRAM_RCR_REFRESH_RATE_M); + + // + // Sets the sync memory refresh rate. + // + HWREGH(base + EMIF_O_SDRAM_RCR) = (HWREGH(base + EMIF_O_SDRAM_RCR) + & (~(uint16_t)EMIF_SDRAM_RCR_REFRESH_RATE_M)) + | refRate; +} + +//***************************************************************************** +// +//! Sets the Synchronous Memory configuration parameters. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! \param config is the desired configuration parameters. +//! +//! This function sets configuration parameters like CL, NM, IBANK +//! and PAGESIZE for an external synchronous memory to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_setSyncMemoryConfig(uint32_t base, const EMIF_SyncConfig *config) +{ + uint32_t temp; + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the sync memory configuration bits. + // + temp = ((uint32_t)config->casLatency | (uint32_t)config->iBank | + (uint32_t)config->narrowMode | (uint32_t)config->pageSize); + + HWREG(base + EMIF_O_SDRAM_CR) = (HWREG(base + EMIF_O_SDRAM_CR) & + ~EMIF_SYNC_SDRAM_CR_MASK) | temp; +} + +//***************************************************************************** +// +// Prototypes for EMIF Low Power Modes +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_SR; +} + +//***************************************************************************** +// +//! Disables Self Refresh. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Self Refresh Mode for EMIF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncSelfRefresh(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory self refresh mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_SR); +} + +//***************************************************************************** +// +//! Enables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function Enables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PD; +} + +//***************************************************************************** +// +//! Disables Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables sync memory power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PD); +} + +//***************************************************************************** +// +//! Enables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function enables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_enableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that enables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) |= EMIF_SDRAM_CR_PDWR; +} + +//***************************************************************************** +// +//! Disables Refresh in Power Down. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function disables Refresh in Power Down Mode for synchronous memory +//! to be interfaced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EMIF_disableSyncRefreshInPowerDown(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Sets the bits that disables refresh in power down mode. + // + HWREG(base + EMIF_O_SDRAM_CR) &= ~((uint32_t)EMIF_SDRAM_CR_PDWR); +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of SDRAM accesses +//! from a controller(CPUx/CPUx.DMA). +//! +//! \return \e Returns total number of accesses to SDRAM. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_AR)); + +} + +//***************************************************************************** +// +//! Gets total number of SDRAM accesses which require activate command. +//! +//! \param base is the base address of the EMIF instance used. +//! +//! This function returns total number of accesses to SDRAM which +//! require activate command. +//! +//!\return \e Returns total number of accesses to SDRAM which require activate. +// +//***************************************************************************** +static inline uint32_t +EMIF_getSyncTotalActivateAccesses(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EMIF_isBaseValid(base)); + + // + // Gets total accesses to sync memory which requires activate command. + // + return(HWREG(base + EMIF_O_TOTAL_SDRAM_ACTR)); +} + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EMIF_H diff --git a/gpio_driverlib_cpu1/device/driverlib/epwm.c b/gpio_driverlib_cpu1/device/driverlib/epwm.c new file mode 100644 index 0000000..76e09bb --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/epwm.c @@ -0,0 +1,363 @@ +//########################################################################### +// +// FILE: epwm.c +// +// TITLE: C28x EPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "epwm.h" + +//***************************************************************************** +// +// EPWM_setEmulationMode +// +//***************************************************************************** +void EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode) +{ + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to FREE_SOFT bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & (~EPWM_TBCTL_FREE_SOFT_M)) | + ((uint16_t)emulationMode << EPWM_TBCTL_FREE_SOFT_S)); +} + +//***************************************************************************** +// +// EPWM_configureSignal +// +//***************************************************************************** +void EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams) +{ + float32_t tbClkInHz = 0.0F; + uint16_t tbPrdVal = 0U, cmpAVal = 0U, cmpBVal = 0U; + + // + // Check the arguments. + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Valid values in the function for TBCTR Mode are UP, DOWN + // and UP-DOWN count. + // + ASSERT((uint16_t)signalParams->tbCtrMode <= 2U); + + // + // Configure EPWM clock Divider + // + SysCtl_setEPWMClockDivider(signalParams->epwmClkDiv); + + // + // Configure Time Base counter Clock + // + EPWM_setClockPrescaler(base, signalParams->tbClkDiv, + signalParams->tbHSClkDiv); + + // + // Configure Time Base Counter Mode + // + EPWM_setTimeBaseCounterMode(base, signalParams->tbCtrMode); + + // + // Calculate TBCLK, TBPRD and CMPx values to be configured for + // achieving desired signal + // + tbClkInHz = ((float32_t)signalParams->sysClkInHz / + (float32_t)(1U << ((uint16_t)signalParams->epwmClkDiv + + (uint16_t)signalParams->tbClkDiv))); + + if(signalParams->tbHSClkDiv <= EPWM_HSCLOCK_DIVIDER_4) + { + tbClkInHz /= (float32_t)(1U << (uint16_t)signalParams->tbHSClkDiv); + } + else + { + tbClkInHz /= (float32_t)(2U * (uint16_t)signalParams->tbHSClkDiv); + } + + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)(signalParams->dutyValA * + (float32_t)(tbPrdVal + 1U)); + cmpBVal = (uint16_t)(signalParams->dutyValB * + (float32_t)(tbPrdVal + 1U)); + } + else if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN) + { + tbPrdVal = (uint16_t)((tbClkInHz / signalParams->freqInHz) - 1.0f); + cmpAVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValA * (float32_t)(tbPrdVal + 1U))); + cmpBVal = (uint16_t)((float32_t)(tbPrdVal + 1U) - + (signalParams->dutyValB * (float32_t)(tbPrdVal + 1U))); + } + else + { + tbPrdVal = (uint16_t)(tbClkInHz / (2.0f * signalParams->freqInHz)); + cmpAVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValA * + (float32_t)tbPrdVal))) + 0.5f); + cmpBVal = (uint16_t)(((float32_t)tbPrdVal - + ((signalParams->dutyValB * + (float32_t)tbPrdVal))) + 0.5f); + } + + // + // Configure TBPRD value + // + EPWM_setTimeBasePeriod(base, tbPrdVal); + + // + // Default Configurations. + // + EPWM_disablePhaseShiftLoad(base); + EPWM_setPhaseShift(base, 0U); + EPWM_setTimeBaseCounter(base, 0U); + + // + // Setup shadow register load on ZERO + // + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_A, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + EPWM_setCounterCompareShadowLoadMode(base, + EPWM_COUNTER_COMPARE_B, + EPWM_COMP_LOAD_ON_CNTR_ZERO); + // + // Set Compare values + // + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_A, + cmpAVal); + EPWM_setCounterCompareValue(base, EPWM_COUNTER_COMPARE_B, + cmpBVal); + + // + // Set actions for ePWMxA & ePWMxB + // + if(signalParams->tbCtrMode == EPWM_COUNTER_MODE_UP) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + + } + } + else if((signalParams->tbCtrMode == EPWM_COUNTER_MODE_DOWN)) + { + // + // Set PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } + else + { + // + // Clear PWMxA on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxA on event A, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA); + + // + // Clear PWMxA on event A, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_A, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA); + + if(signalParams->invertSignalB == true) + { + // + // Set PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Clear PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Set PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + else + { + // + // Clear PWMxB on Zero + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO); + + // + // Set PWMxB on event B, up count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_HIGH, + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB); + // + // Clear PWMxB on event B, down count + // + EPWM_setActionQualifierAction(base, + EPWM_AQ_OUTPUT_B, + EPWM_AQ_OUTPUT_LOW, + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB); + } + } +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/epwm.h b/gpio_driverlib_cpu1/device/driverlib/epwm.h new file mode 100644 index 0000000..ada9b80 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/epwm.h @@ -0,0 +1,7496 @@ +//############################################################################# +// +// FILE: epwm.h +// +// TITLE: C28x EPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef EPWM_H +#define EPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup epwm_api ePWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_epwm.h" +#include "cpu.h" +#include "debug.h" +#include "sysctl.h" + + +// +// Time Base Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setEmulationMode() as the +//! \e emulationMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Stop after next Time Base counter increment or decrement + EPWM_EMULATION_STOP_AFTER_NEXT_TB = 0, + //! Stop when counter completes whole cycle + EPWM_EMULATION_STOP_AFTER_FULL_CYCLE = 1, + //! Free run + EPWM_EMULATION_FREE_RUN = 2 +} EPWM_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCountModeAfterSync() as the +//! \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNT_MODE_DOWN_AFTER_SYNC = 0, //!< Count down after sync event + EPWM_COUNT_MODE_UP_AFTER_SYNC = 1 //!< Count up after sync event +} EPWM_SyncCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e prescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_CLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_CLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_CLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_CLOCK_DIVIDER_8 = 3, //!< Divide clock by 8 + EPWM_CLOCK_DIVIDER_16 = 4, //!< Divide clock by 16 + EPWM_CLOCK_DIVIDER_32 = 5, //!< Divide clock by 32 + EPWM_CLOCK_DIVIDER_64 = 6, //!< Divide clock by 64 + EPWM_CLOCK_DIVIDER_128 = 7 //!< Divide clock by 128 +} EPWM_ClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setClockPrescaler() as the +//! \e highSpeedPrescaler parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_HSCLOCK_DIVIDER_1 = 0, //!< Divide clock by 1 + EPWM_HSCLOCK_DIVIDER_2 = 1, //!< Divide clock by 2 + EPWM_HSCLOCK_DIVIDER_4 = 2, //!< Divide clock by 4 + EPWM_HSCLOCK_DIVIDER_6 = 3, //!< Divide clock by 6 + EPWM_HSCLOCK_DIVIDER_8 = 4, //!< Divide clock by 8 + EPWM_HSCLOCK_DIVIDER_10 = 5, //!< Divide clock by 10 + EPWM_HSCLOCK_DIVIDER_12 = 6, //!< Divide clock by 12 + EPWM_HSCLOCK_DIVIDER_14 = 7 //!< Divide clock by 14 +} EPWM_HSClockDivider; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setSyncOutPulseMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Sync pulse is generated by software + EPWM_SYNC_OUT_PULSE_ON_SOFTWARE = 0, + //! Sync pulse is passed from EPWMxSYNCIN + EPWM_SYNC_OUT_PULSE_ON_EPWMxSYNCIN = 0, + //! Sync pulse is generated when time base counter equals zero + EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO = 1, + //! Sync pulse is generated when time base counter equals compare B value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B = 2, + //! Sync pulse is disabled + EPWM_SYNC_OUT_PULSE_DISABLED = 4, + //! Sync pulse is generated when time base counter equals compare C value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C = 5, + //! Sync pulse is generated when time base counter equals compare D value + EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D = 6 +} EPWM_SyncOutPulseMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setPeriodLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! PWM Period register access is through shadow register + EPWM_PERIOD_SHADOW_LOAD = 0, + //! PWM Period register access is directly + EPWM_PERIOD_DIRECT_LOAD = 1 +} EPWM_PeriodLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTimeBaseCounterMode() as the +//! \e counterMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_MODE_UP = 0, //!< Up - count mode + EPWM_COUNTER_MODE_DOWN = 1, //!< Down - count mode + EPWM_COUNTER_MODE_UP_DOWN = 2, //!< Up - down - count mode + EPWM_COUNTER_MODE_STOP_FREEZE = 3 //!< Stop - Freeze counter +} EPWM_TimeBaseCountMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectPeriodLoadEvent() as the +//! \e shadowLoadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow to active load occurs when time base counter reaches 0 + EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO = 0, + //! Shadow to active load occurs when time base counter reaches 0 and a + //! SYNC occurs + EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC = 1, + //! Shadow to active load occurs only when a SYNC occurs + EPWM_SHADOW_LOAD_MODE_SYNC = 2 +} EPWM_PeriodShadowLoadMode; + +//***************************************************************************** +// +// Values that can be returned by the EPWM_getTimeBaseCounterDirection() +// +//***************************************************************************** +//! Time base counter is counting up +//! +#define EPWM_TIME_BASE_STATUS_COUNT_UP 1U +//! Time base counter is counting down +//! +#define EPWM_TIME_BASE_STATUS_COUNT_DOWN 0U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e epwmLink +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_WITH_EPWM_1 = 0, //!< link current ePWM with ePWM1 + EPWM_LINK_WITH_EPWM_2 = 1, //!< link current ePWM with ePWM2 + EPWM_LINK_WITH_EPWM_3 = 2, //!< link current ePWM with ePWM3 + EPWM_LINK_WITH_EPWM_4 = 3, //!< link current ePWM with ePWM4 + EPWM_LINK_WITH_EPWM_5 = 4, //!< link current ePWM with ePWM5 + EPWM_LINK_WITH_EPWM_6 = 5, //!< link current ePWM with ePWM6 + EPWM_LINK_WITH_EPWM_7 = 6, //!< link current ePWM with ePWM7 + EPWM_LINK_WITH_EPWM_8 = 7, //!< link current ePWM with ePWM8 + EPWM_LINK_WITH_EPWM_9 = 8, //!< link current ePWM with ePWM9 + EPWM_LINK_WITH_EPWM_10 = 9, //!< link current ePWM with ePWM10 + EPWM_LINK_WITH_EPWM_11 = 10, //!< link current ePWM with ePWM11 + EPWM_LINK_WITH_EPWM_12 = 11 //!< link current ePWM with ePWM12 +} EPWM_CurrentLink; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setupEPWMLinks() as the \e linkComp +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_LINK_TBPRD = 0U, //!< link TBPRD registers + EPWM_LINK_COMP_A = 4U, //!< link COMPA registers + EPWM_LINK_COMP_B = 8U, //!< link COMPB registers + EPWM_LINK_COMP_C = 12U, //!< link COMPC registers + EPWM_LINK_COMP_D = 16U, //!< link COMPD registers + EPWM_LINK_GLDCTL2 = 28U //!< link GLDCTL2 registers +} EPWM_LinkComponent; + +// +// Counter Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to the EPWM_getCounterCompareShadowStatus(), +//! EPWM_setCounterCompareValue(), EPWM_setCounterCompareShadowLoadMode(), +//! EPWM_disableCounterCompareShadowLoadMode() +//! as the \e compModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_COUNTER_COMPARE_A = 0, //!< Counter compare A + EPWM_COUNTER_COMPARE_B = 2, //!< Counter compare B + EPWM_COUNTER_COMPARE_C = 5, //!< Counter compare C + EPWM_COUNTER_COMPARE_D = 7 //!< Counter compare D +} EPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setCounterCompareShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_COMP_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_COMP_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_COMP_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_COMP_LOAD_ON_SYNC_ONLY = 8 +} EPWM_CounterCompareLoadMode; + +// +// Action Qualifier Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() and +//! EPWM_disableActionQualifierShadowLoadMode() as the \e aqModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_ACTION_QUALIFIER_A = 0, //!< Action Qualifier A + EPWM_ACTION_QUALIFIER_B = 2 //!< Action Qualifier B +} EPWM_ActionQualifierModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierShadowLoadMode() as the +//! \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_AQ_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_AQ_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_AQ_LOAD_FREEZE = 3, + //! Load on sync or when counter equals zero + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO = 4, + //! Load on sync or when counter equals period + EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD = 5, + //! Load on sync or when counter equals zero or period + EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD = 6, + //! Load on sync only + EPWM_AQ_LOAD_ON_SYNC_ONLY = 8 +} EPWM_ActionQualifierLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierT1TriggerSource() and +//! EPWM_setActionQualifierT2TriggerSource() as the \e trigger parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 = 0, //!< Digital compare event A 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 = 1, //!< Digital compare event A 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 = 2, //!< Digital compare event B 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 = 3, //!< Digital compare event B 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 = 4, //!< Trip zone 1 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 = 5, //!< Trip zone 2 + EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 = 6, //!< Trip zone 3 + EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN = 7 //!< ePWM sync +} EPWM_ActionQualifierTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierAction() as the \e +//! event parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero + EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO = 0, + //! Time base counter equals period + EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD = 2, + //! Time base counter up equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA = 4, + //! Time base counter down equals COMPA + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA = 6, + //! Time base counter up equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB = 8, + //! Time base counter down equals COMPB + EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB = 10, + //! T1 event on count up + EPWM_AQ_OUTPUT_ON_T1_COUNT_UP = 1, + //! T1 event on count down + EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN = 3, + //! T2 event on count up + EPWM_AQ_OUTPUT_ON_T2_COUNT_UP = 5, + //! T2 event on count down + EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN = 7 +} EPWM_ActionQualifierOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierSWAction(), +//! EPWM_setActionQualifierAction() as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_NO_CHANGE = 0, //!< No change in the output pins + EPWM_AQ_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_OUTPUT_HIGH = 2, //!< Set output pins to High + EPWM_AQ_OUTPUT_TOGGLE = 3 //!< Toggle the output pins +} EPWM_ActionQualifierOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceAction() +//! as the \e outPut parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_SW_DISABLED = 0, //!< Software forcing disabled + EPWM_AQ_SW_OUTPUT_LOW = 1, //!< Set output pins to low + EPWM_AQ_SW_OUTPUT_HIGH = 2 //!< Set output pins to High +} EPWM_ActionQualifierSWOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierActionComplete() +//! as the \e action parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals zero and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_ZERO = 0x0, + //! Time base counter equals zero and set output pins to low + EPWM_AQ_OUTPUT_LOW_ZERO = 0x1, + //! Time base counter equals zero and set output pins to high + EPWM_AQ_OUTPUT_HIGH_ZERO = 0x2, + //! Time base counter equals zero and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_ZERO = 0x3, + //! Time base counter equals period and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD = 0x0, + //! Time base counter equals period and set output pins to low + EPWM_AQ_OUTPUT_LOW_PERIOD = 0x4, + //! Time base counter equals period and set output pins to high + EPWM_AQ_OUTPUT_HIGH_PERIOD = 0x8, + //! Time base counter equals period and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_PERIOD = 0xC, + //! Time base counter up equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA = 0x00, + //! Time base counter up equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPA = 0x10, + //! Time base counter up equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPA = 0x20, + //! Time base counter up equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA = 0x30, + //! Time base counter down equals COMPA and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA = 0x00, + //! Time base counter down equals COMPA and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPA = 0x40, + //! Time base counter down equals COMPA and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA = 0x80, + //! Time base counter down equals COMPA and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA = 0xC0, + //! Time base counter up equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB = 0x000, + //! Time base counter up equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_CMPB = 0x100, + //! Time base counter up equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_CMPB = 0x200, + //! Time base counter up equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB = 0x300, + //! Time base counter down equals COMPB and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB = 0x000, + //! Time base counter down equals COMPB and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_CMPB = 0x400, + //! Time base counter down equals COMPB and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB = 0x800, + //! Time base counter down equals COMPB and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB = 0xC00 +} EPWM_ActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to +//! EPWM_setAdditionalActionQualifierActionComplete() as the \e action +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! T1 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 = 0x0, + //! T1 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T1 = 0x1, + //! T1 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T1 = 0x2, + //! T1 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T1 = 0x3, + //! T1 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1 = 0x0, + //! T1 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T1 = 0x4, + //! T1 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T1 = 0x8, + //! T1 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 = 0xC, + //! T2 event on count up and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 = 0x00, + //! T2 event on count up and set output pins to low + EPWM_AQ_OUTPUT_LOW_UP_T2 = 0x10, + //! T2 event on count up and set output pins to high + EPWM_AQ_OUTPUT_HIGH_UP_T2 = 0x20, + //! T2 event on count up and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_UP_T2 = 0x30, + //! T2 event on count down and no change in the output pins + EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 = 0x00, + //! T2 event on count down and set output pins to low + EPWM_AQ_OUTPUT_LOW_DOWN_T2 = 0x40, + //! T2 event on count down and set output pins to high + EPWM_AQ_OUTPUT_HIGH_DOWN_T2 = 0x80, + //! T2 event on count down and toggle the output pins + EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 = 0xC0 +} EPWM_AdditionalActionQualifierEventAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_forceActionQualifierSWAction(), +//! EPWM_setActionQualifierSWAction(), EPWM_setActionQualifierAction() +//! EPWM_setActionQualifierContSWForceAction() as the \e epwmOutput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_AQ_OUTPUT_A = 0, //!< ePWMxA output + EPWM_AQ_OUTPUT_B = 2 //!< ePWMxB output +} EPWM_ActionQualifierOutputModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setActionQualifierContSWForceShadowMode() +//! as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Shadow mode load when counter equals zero + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO = 0, + //! Shadow mode load when counter equals period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD = 1, + //! Shadow mode load when counter equals zero or period + EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! No shadow load mode. Immediate mode only. + EPWM_AQ_SW_IMMEDIATE_LOAD = 3 +} EPWM_ActionQualifierContForce; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandOutputSwapMode() +//! as the \e output parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_OUTPUT_A = 1, //!< DB output is ePWMA + EPWM_DB_OUTPUT_B = 0 //!< DB output is ePWMB +} EPWM_DeadBandOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity(), +//! EPWM_setDeadBandDelayMode() as the \e delayMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_RED = 1, //!< DB RED (Rising Edge Delay) mode + EPWM_DB_FED = 0 //!< DB FED (Falling Edge Delay) mode +} EPWM_DeadBandDelayMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandDelayPolarity as the +//! \e polarity parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DB_POLARITY_ACTIVE_HIGH = 0, //!< DB polarity is not inverted + EPWM_DB_POLARITY_ACTIVE_LOW = 1 //!< DB polarity is inverted +} EPWM_DeadBandPolarity; + +//***************************************************************************** +// +// Values that can be passed to EPWM_setRisingEdgeDeadBandDelayInput(), +// EPWM_setFallingEdgeDeadBandDelayInput() as the input parameter. +// +//***************************************************************************** +//! Input signal is ePWMA +//! +#define EPWM_DB_INPUT_EPWMA 0U +//! Input signal is ePWMB +//! +#define EPWM_DB_INPUT_EPWMB 1U +//! Input signal is the output of Rising Edge delay +//! +#define EPWM_DB_INPUT_DB_RED 2U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandControlShadowLoadMode() as +//! the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_DB_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_DB_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_DB_LOAD_FREEZE = 3 +} EPWM_DeadBandControlLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setRisingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_RED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_RED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_RED_LOAD_FREEZE = 3 +} EPWM_RisingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setFallingEdgeDelayCountShadowLoadMode() +//! as the \e loadMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter equals zero + EPWM_FED_LOAD_ON_CNTR_ZERO = 0, + //! Load when counter equals period + EPWM_FED_LOAD_ON_CNTR_PERIOD = 1, + //! Load when counter equals zero or period + EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD = 2, + //! Freeze shadow to active load + EPWM_FED_LOAD_FREEZE = 3 +} EPWM_FallingEdgeDelayLoadMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDeadBandCounterClock() as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Dead band counter runs at TBCLK rate + EPWM_DB_COUNTER_CLOCK_FULL_CYCLE = 0, + //! Dead band counter runs at 2*TBCLK rate + EPWM_DB_COUNTER_CLOCK_HALF_CYCLE = 1 +} EPWM_DeadBandClockMode; + +// +// Trip Zone +// +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneSignals() and +// EPWM_disableTripZoneSignals() as the tzSignal parameter. +// +//***************************************************************************** +//! TZ1 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC1 0x1U +//! TZ2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC2 0x2U +//! TZ3 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC3 0x4U +//! TZ4 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC4 0x8U +//! TZ5 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC5 0x10U +//! TZ6 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_CBC6 0x20U +//! DCAEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCAEVT2 0x40U +//! DCBEVT2 Cycle By Cycle +//! +#define EPWM_TZ_SIGNAL_DCBEVT2 0x80U +//! One-shot TZ1 +//! +#define EPWM_TZ_SIGNAL_OSHT1 0x100U +//! One-shot TZ2 +//! +#define EPWM_TZ_SIGNAL_OSHT2 0x200U +//! One-shot TZ3 +//! +#define EPWM_TZ_SIGNAL_OSHT3 0x400U +//! One-shot TZ4 +//! +#define EPWM_TZ_SIGNAL_OSHT4 0x800U +//! One-shot TZ5 +//! +#define EPWM_TZ_SIGNAL_OSHT5 0x1000U +//! One-shot TZ6 +//! +#define EPWM_TZ_SIGNAL_OSHT6 0x2000U +//! One-shot DCAEVT1 +//! +#define EPWM_TZ_SIGNAL_DCAEVT1 0x4000U +//! One-shot DCBEVT1 +//! +#define EPWM_TZ_SIGNAL_DCBEVT1 0x8000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcType parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_DC_OUTPUT_A1 = 0, //!< Digital Compare output 1 A + EPWM_TZ_DC_OUTPUT_A2 = 3, //!< Digital Compare output 2 A + EPWM_TZ_DC_OUTPUT_B1 = 6, //!< Digital Compare output 1 B + EPWM_TZ_DC_OUTPUT_B2 = 9 //!< Digital Compare output 2 B +} EPWM_TripZoneDigitalCompareOutput; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneDigitalCompareEventCondition() +//! as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_EVENT_DC_DISABLED = 0, //!< Event is disabled + EPWM_TZ_EVENT_DCXH_LOW = 1, //!< Event when DCxH low + EPWM_TZ_EVENT_DCXH_HIGH = 2, //!< Event when DCxH high + EPWM_TZ_EVENT_DCXL_LOW = 3, //!< Event when DCxL low + EPWM_TZ_EVENT_DCXL_HIGH = 4, //!< Event when DCxL high + EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW = 5 //!< Event when DCxL high DCxH low +} EPWM_TripZoneDigitalCompareOutputEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the \e tzEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_EVENT_TZA = 0, //!< TZ1 - TZ6, DCAEVT2, DCAEVT1 + EPWM_TZ_ACTION_EVENT_TZB = 2, //!< TZ1 - TZ6, DCBEVT2, DCBEVT1 + EPWM_TZ_ACTION_EVENT_DCAEVT1 = 4, //!< DCAEVT1 (Digital Compare A event 1) + EPWM_TZ_ACTION_EVENT_DCAEVT2 = 6, //!< DCAEVT2 (Digital Compare A event 2) + EPWM_TZ_ACTION_EVENT_DCBEVT1 = 8, //!< DCBEVT1 (Digital Compare B event 1) + EPWM_TZ_ACTION_EVENT_DCBEVT2 = 10 //!< DCBEVT2 (Digital Compare B event 2) +} EPWM_TripZoneEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAction() as the +//! \e tzAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ACTION_DISABLE = 3 //!< Disable action +} EPWM_TripZoneAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvAction() as the +//! \e tzAdvEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZB_D = 9, + //! TZ1 - TZ6, DCBEVT2, DCBEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZB_U = 6, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_TZA_D = 3, + //! TZ1 - TZ6, DCAEVT2, DCAEVT1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_TZA_U = 0 +} EPWM_TripZoneAdvancedEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA(), +//! EPWM_setTripZoneAdvDigitalCompareActionB(),EPWM_setTripZoneAdvAction() +//! as the \e tzAdvDCAction parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_TZ_ADV_ACTION_HIGH_Z = 0, //!< High impedance output + EPWM_TZ_ADV_ACTION_HIGH = 1, //!< High voltage state + EPWM_TZ_ADV_ACTION_LOW = 2, //!< Low voltage state + EPWM_TZ_ADV_ACTION_TOGGLE = 3, //!< Toggle the output + EPWM_TZ_ADV_ACTION_DISABLE = 7 //!< Disable action +} EPWM_TripZoneAdvancedAction; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setTripZoneAdvDigitalCompareActionA() and +//! EPWM_setTripZoneAdvDigitalCompareActionB() as the \e tzAdvDCEvent +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital Compare event A/B 1 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U = 0, + //! Digital Compare event A/B 1 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D = 3, + //! Digital Compare event A/B 2 while counting up + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U = 6, + //! Digital Compare event A/B 2 while counting down + EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D = 9 +} EPWM_TripZoneAdvDigitalCompareEvent; + + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableTripZoneInterrupt()and +// EPWM_disableTripZoneInterrupt() as the tzInterrupt parameter . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle interrupt +//! +#define EPWM_TZ_INTERRUPT_CBC 0x2U +//! Trip Zones One Shot interrupt +//! +#define EPWM_TZ_INTERRUPT_OST 0x4U +//! Digital Compare A Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT1 0x8U +//! Digital Compare A Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCAEVT2 0x10U +//! Digital Compare B Event 1 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT1 0x20U +//! Digital Compare B Event 2 interrupt +//! +#define EPWM_TZ_INTERRUPT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be returned by EPWM_getTripZoneFlagStatus() . +// +//***************************************************************************** +//! Trip Zones Cycle By Cycle flag +//! +#define EPWM_TZ_FLAG_CBC 0x2U +//! Trip Zones One Shot flag +//! +#define EPWM_TZ_FLAG_OST 0x4U +//! Digital Compare A Event 1 flag +//! +#define EPWM_TZ_FLAG_DCAEVT1 0x8U +//! Digital Compare A Event 2 flag +//! +#define EPWM_TZ_FLAG_DCAEVT2 0x10U +//! Digital Compare B Event 1 flag +//! +#define EPWM_TZ_FLAG_DCBEVT1 0x20U +//! Digital Compare B Event 2 flag +//! +#define EPWM_TZ_FLAG_DCBEVT2 0x40U + +//***************************************************************************** +// +// Value can be passed to EPWM_clearTripZoneFlag() as the +// tzInterrupt parameter and returned by EPWM_getTripZoneFlagStatus(). +// +//***************************************************************************** +//! Trip Zone interrupt +//! +#define EPWM_TZ_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearCycleByCycleTripZoneFlag() +// as the tzCbcFlag parameter and returned by +// EPWM_getCycleByCycleTripZoneFlagStatus(). +// +//***************************************************************************** +//! CBC flag 1 +//! +#define EPWM_TZ_CBC_FLAG_1 0x1U +//! CBC flag 2 +//! +#define EPWM_TZ_CBC_FLAG_2 0x2U +//! CBC flag 3 +//! +#define EPWM_TZ_CBC_FLAG_3 0x4U +//! CBC flag 4 +//! +#define EPWM_TZ_CBC_FLAG_4 0x8U +//! CBC flag 5 +//! +#define EPWM_TZ_CBC_FLAG_5 0x10U +//! CBC flag 6 +//! +#define EPWM_TZ_CBC_FLAG_6 0x20U +//! CBC flag Digital compare event A2 +//! +#define EPWM_TZ_CBC_FLAG_DCAEVT2 0x40U +//! CBC flag Digital compare event B2 +//! +#define EPWM_TZ_CBC_FLAG_DCBEVT2 0x80U + +//***************************************************************************** +// +// Values that can be passed to EPWM_clearOneShotTripZoneFlag() as +// the tzCbcFlag parameter and returned by the +// EPWM_getOneShotTripZoneFlagStatus() . +// +//***************************************************************************** +//! OST flag OST1 +//! +#define EPWM_TZ_OST_FLAG_OST1 0x1U +//! OST flag OST2 +//! +#define EPWM_TZ_OST_FLAG_OST2 0x2U +//! OST flag OST3 +//! +#define EPWM_TZ_OST_FLAG_OST3 0x4U +//! OST flag OST4 +//! +#define EPWM_TZ_OST_FLAG_OST4 0x8U +//! OST flag OST5 +//! +#define EPWM_TZ_OST_FLAG_OST5 0x10U +//! OST flag OST6 +//! +#define EPWM_TZ_OST_FLAG_OST6 0x20U +//! OST flag Digital compare event A1 +//! +#define EPWM_TZ_OST_FLAG_DCAEVT1 0x40U +//! OST flag Digital compare event B1 +//! +#define EPWM_TZ_OST_FLAG_DCBEVT1 0x80U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectCycleByCycleTripZoneClearEvent() as +//! the \e clearMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Clear CBC pulse when counter equals zero + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO = 0, + //! Clear CBC pulse when counter equals period + EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD = 1, + //! Clear CBC pulse when counter equals zero or period + EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD = 2 +} EPWM_CycleByCycleTripZoneClearMode; + +//***************************************************************************** +// +// Values that can be passed to EPWM_forceTripZoneEvent() as the +// tzForceEvent parameter. +// +//***************************************************************************** +//! Force Cycle By Cycle trip event +//! +#define EPWM_TZ_FORCE_EVENT_CBC 0x2U +//! Force a One-Shot Trip Event +//! +#define EPWM_TZ_FORCE_EVENT_OST 0x4U +//! Force Digital Compare Output A Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT1 0x8U +//! Force Digital Compare Output A Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCAEVT2 0x10U +//! Force Digital Compare Output B Event 1 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT1 0x20U +//! Force Digital Compare Output B Event 2 +//! +#define EPWM_TZ_FORCE_EVENT_DCBEVT2 0x40U + +//***************************************************************************** +// +// Values that can be passed to EPWM_setInterruptSource() as the +// interruptSource parameter. +// +//***************************************************************************** +//! Time-base counter is disabled +//! +#define EPWM_INT_TBCTR_DISABLED 0U +//! Time-base counter equal to zero +//! +#define EPWM_INT_TBCTR_ZERO 1U +//! Time-base counter equal to period +//! +#define EPWM_INT_TBCTR_PERIOD 2U +//! Time-base counter equal to zero or period +//! +#define EPWM_INT_TBCTR_ZERO_OR_PERIOD 3U +//! time-base counter equal to CMPA when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPA 4U +//! time-base counter equal to CMPC when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPC 8U +//! time-base counter equal to CMPA when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPA 5U +//! time-base counter equal to CMPC when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPC 10U +//! time-base counter equal to CMPB when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPB 6U +//! time-base counter equal to CMPD when the timer is incrementing +//! +#define EPWM_INT_TBCTR_U_CMPD 12U +//! time-base counter equal to CMPB when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPB 7U +//! time-base counter equal to CMPD when the timer is decrementing +//! +#define EPWM_INT_TBCTR_D_CMPD 14U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_enableADCTrigger(), +//! EPWM_disableADCTrigger(),EPWM_setADCTriggerSource(), +//! EPWM_setADCTriggerEventPrescale(),EPWM_getADCTriggerFlagStatus(), +//! EPWM_clearADCTriggerFlag(),EPWM_enableADCTriggerEventCountInit(), +//! EPWM_disableADCTriggerEventCountInit(),EPWM_forceADCTriggerEventCountInit(), +//! EPWM_setADCTriggerEventCountInitValue(),EPWM_getADCTriggerEventCount(), +//! EPWM_forceADCTrigger() as the \e adcSOCType parameter +// +//***************************************************************************** +typedef enum +{ + EPWM_SOC_A = 0, //!< SOC A + EPWM_SOC_B = 1 //!< SOC B +} EPWM_ADCStartOfConversionType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setADCTriggerSource() as the +//! \e socSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Event is based on DCxEVT1 + EPWM_SOC_DCxEVT1 = 0, + //! Time-base counter equal to zero + EPWM_SOC_TBCTR_ZERO = 1, + //! Time-base counter equal to period + EPWM_SOC_TBCTR_PERIOD = 2, + //! Time-base counter equal to zero or period + EPWM_SOC_TBCTR_ZERO_OR_PERIOD = 3, + //! Time-base counter equal to CMPA when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPA = 4, + //! Time-base counter equal to CMPC when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPC = 8, + //! Time-base counter equal to CMPA when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPA = 5, + //! Time-base counter equal to CMPC when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPC = 10, + //! Time-base counter equal to CMPB when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPB = 6, + //! Time-base counter equal to CMPD when the timer is incrementing + EPWM_SOC_TBCTR_U_CMPD = 12, + //! Time-base counter equal to CMPB when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPB = 7, + //! Time-base counter equal to CMPD when the timer is decrementing + EPWM_SOC_TBCTR_D_CMPD = 14 +} EPWM_ADCStartOfConversionSource; + +// +// Digital Compare Module +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput(), +//! EPWM_enableDigitalCompareTripCombinationInput(), +//! EPWM_disableDigitalCompareTripCombinationInput() as the \e dcType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TYPE_DCAH = 0, //!< Digital Compare A High + EPWM_DC_TYPE_DCAL = 1, //!< Digital Compare A Low + EPWM_DC_TYPE_DCBH = 2, //!< Digital Compare B High + EPWM_DC_TYPE_DCBL = 3 //!< Digital Compare B Low +} EPWM_DigitalCompareType; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_selectDigitalCompareTripInput() +//! as the \e tripSource parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_TRIP_TRIPIN1 = 0, //!< Trip 1 + EPWM_DC_TRIP_TRIPIN2 = 1, //!< Trip 2 + EPWM_DC_TRIP_TRIPIN3 = 2, //!< Trip 3 + EPWM_DC_TRIP_TRIPIN4 = 3, //!< Trip 4 + EPWM_DC_TRIP_TRIPIN5 = 4, //!< Trip 5 + EPWM_DC_TRIP_TRIPIN6 = 5, //!< Trip 6 + EPWM_DC_TRIP_TRIPIN7 = 6, //!< Trip 7 + EPWM_DC_TRIP_TRIPIN8 = 7, //!< Trip 8 + EPWM_DC_TRIP_TRIPIN9 = 8, //!< Trip 9 + EPWM_DC_TRIP_TRIPIN10 = 9, //!< Trip 10 + EPWM_DC_TRIP_TRIPIN11 = 10, //!< Trip 11 + EPWM_DC_TRIP_TRIPIN12 = 11, //!< Trip 12 + EPWM_DC_TRIP_TRIPIN14 = 13, //!< Trip 14 + EPWM_DC_TRIP_TRIPIN15 = 14, //!< Trip 15 + EPWM_DC_TRIP_COMBINATION = 15 //!< All Trips (Trip1 - Trip 15) are selected +} EPWM_DigitalCompareTripInput; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableDigitalCompareTripCombinationInput(), +// EPWM_disableDigitalCompareTripCombinationInput() as the tripInput +// parameter. +// +//***************************************************************************** +//! Combinational Trip 1 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN1 0x1U +//! Combinational Trip 2 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN2 0x2U +//! Combinational Trip 3 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN3 0x4U +//! Combinational Trip 4 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN4 0x8U +//! Combinational Trip 5 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN5 0x10U +//! Combinational Trip 6 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN6 0x20U +//! Combinational Trip 7 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN7 0x40U +//! Combinational Trip 8 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN8 0x80U +//! Combinational Trip 9 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN9 0x100U +//! Combinational Trip 10 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN10 0x200U +//! Combinational Trip 11 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN11 0x400U +//! Combinational Trip 12 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN12 0x800U +//! Combinational Trip 14 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN14 0x2000U +//! Combinational Trip 15 input +//! +#define EPWM_DC_COMBINATIONAL_TRIPIN15 0x4000U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareBlankingEvent() as the +//! the \e blankingPulse parameter. +// +//***************************************************************************** +typedef enum +{ + //! Time base counter equals period + EPWM_DC_WINDOW_START_TBCTR_PERIOD = 0, + //! Time base counter equals zero + EPWM_DC_WINDOW_START_TBCTR_ZERO = 1, + //! Time base counter equals zero or period + EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD = 2 +} EPWM_DigitalCompareBlankingPulse; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareFilterInput() +//! as the \e filterInput parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_WINDOW_SOURCE_DCAEVT1 = 0, //!< DC filter signal source is DCAEVT1 + EPWM_DC_WINDOW_SOURCE_DCAEVT2 = 1, //!< DC filter signal source is DCAEVT2 + EPWM_DC_WINDOW_SOURCE_DCBEVT1 = 2, //!< DC filter signal source is DCBEVT1 + EPWM_DC_WINDOW_SOURCE_DCBEVT2 = 3 //!< DC filter signal source is DCBEVT2 +} EPWM_DigitalCompareFilterInput; + +//***************************************************************************** +// +//! Values that can be assigned to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode(),EPWM_enableDigitalCompareSyncEvent() +//! EPWM_enableDigitalCompareADCTrigger(),EPWM_disableDigitalCompareSyncEvent() +//! EPWM_disableDigitalCompareADCTrigger() as the \e dcModule parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_MODULE_A = 0, //!< Digital Compare Module A + EPWM_DC_MODULE_B = 1 //!< Digital Compare Module B +} EPWM_DigitalCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource(), +//! EPWM_setDigitalCompareEventSyncMode as the \e dcEvent parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EVENT_1 = 0, //!< Digital Compare Event number 1 + EPWM_DC_EVENT_2 = 1 //!< Digital Compare Event number 2 +} EPWM_DigitalCompareEvent; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSource() as the +//! \e dcEventSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Signal source is unfiltered (DCAEVT1/2) + EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL = 0, + //! Signal source is filtered (DCEVTFILT) + EPWM_DC_EVENT_SOURCE_FILT_SIGNAL = 1 +} EPWM_DigitalCompareEventSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEventSyncMode() as the +//! \e syncMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! DC input signal is synced with TBCLK + EPWM_DC_EVENT_INPUT_SYNCED = 0, + //! DC input signal is not synced with TBCLK + EPWM_DC_EVENT_INPUT_NOT_SYNCED = 1 +} EPWM_DigitalCompareSyncMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setGlobalLoadTrigger() as the +//! \e loadTrigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Load when counter is equal to zero + EPWM_GL_LOAD_PULSE_CNTR_ZERO = 0x0, + //! Load when counter is equal to period + EPWM_GL_LOAD_PULSE_CNTR_PERIOD = 0x1, + //! Load when counter is equal to zero or period + EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD = 0x2, + //! Load on sync event + EPWM_GL_LOAD_PULSE_SYNC = 0x3, + //! Load on sync event or when counter is equal to zero + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO = 0x4, + //! Load on sync event or when counter is equal to period + EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD = 0x5, + //! Load on sync event or when counter is equal to period or zero + EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD = 0x6, + //! Load on global force + EPWM_GL_LOAD_PULSE_GLOBAL_FORCE = 0xF +} EPWM_GlobalLoadTrigger; + +//***************************************************************************** +// +// Values that can be passed to EPWM_enableGlobalLoadRegisters(), +// EPWM_disableGlobalLoadRegisters() as theloadRegister parameter. +// +//***************************************************************************** +//! Global load TBPRD:TBPRDHR +//! +#define EPWM_GL_REGISTER_TBPRD_TBPRDHR 0x1U +//! Global load CMPA:CMPAHR +//! +#define EPWM_GL_REGISTER_CMPA_CMPAHR 0x2U +//! Global load CMPB:CMPBHR +//! +#define EPWM_GL_REGISTER_CMPB_CMPBHR 0x4U +//! Global load CMPC +//! +#define EPWM_GL_REGISTER_CMPC 0x8U +//! Global load CMPD +//! +#define EPWM_GL_REGISTER_CMPD 0x10U +//! Global load DBRED:DBREDHR +//! +#define EPWM_GL_REGISTER_DBRED_DBREDHR 0x20U +//! Global load DBFED:DBFEDHR +//! +#define EPWM_GL_REGISTER_DBFED_DBFEDHR 0x40U +//! Global load DBCTL +//! +#define EPWM_GL_REGISTER_DBCTL 0x80U +//! Global load AQCTLA/A2 +//! +#define EPWM_GL_REGISTER_AQCTLA_AQCTLA2 0x100U +//! Global load AQCTLB/B2 +//! +#define EPWM_GL_REGISTER_AQCTLB_AQCTLB2 0x200U +//! Global load AQCSFRC +//! +#define EPWM_GL_REGISTER_AQCSFRC 0x400U + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyTriggerSource() as the \e +//! trigger parameter. +// +//***************************************************************************** +typedef enum +{ + //! Valley capture trigged by software + EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE = 0U, + //! Valley capture trigged by when counter is equal to zero + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO = 1U, + //! Valley capture trigged by when counter is equal period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_PERIOD = 2U, + //! Valley capture trigged when counter is equal to zero or period + EPWM_VALLEY_TRIGGER_EVENT_CNTR_ZERO_PERIOD = 3U, + //! Valley capture trigged by DCAEVT1 (Digital Compare A event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT1 = 4U, + //! Valley capture trigged by DCAEVT2 (Digital Compare A event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCAEVT2 = 5U, + //! Valley capture trigged by DCBEVT1 (Digital Compare B event 1) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT1 = 6U, + //! Valley capture trigged by DCBEVT2 (Digital Compare B event 2) + EPWM_VALLEY_TRIGGER_EVENT_DCBEVT2 = 7U +} EPWM_ValleyTriggerSource; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_getValleyCountEdgeStatus() as the \e edge +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_VALLEY_COUNT_START_EDGE = 0, //!< Valley count start edge + EPWM_VALLEY_COUNT_STOP_EDGE = 1 //!< Valley count stop edge +} EPWM_ValleyCounterEdge; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setValleyDelayValue() as the \e delayMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Delay value equals the offset value defines by software + EPWM_VALLEY_DELAY_MODE_SW_DELAY = 0U, + //! Delay value equals the sum of the Hardware counter value and the offset + //! value defines by software + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SW_DELAY = 1U, + //! Delay value equals the the Hardware counter shifted by + //! (1 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_1_SW_DELAY = 2U, + //! Delay value equals the the Hardware counter shifted by + //! (2 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_2_SW_DELAY = 3U, + //! Delay value equals the the Hardware counter shifted by + //! (4 + the offset value defines by software) + EPWM_VALLEY_DELAY_MODE_VCNT_DELAY_SHIFT_4_SW_DELAY = 4U +} EPWM_ValleyDelayMode; + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterMode() +//! as the \e edgeMode parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_MODE_RISING = 0, //!< Digital Compare Edge filter low + //!< to high edge mode + EPWM_DC_EDGEFILT_MODE_FALLING = 1, //!< Digital Compare Edge filter high + //!< to low edge mode + EPWM_DC_EDGEFILT_MODE_BOTH = 2 //!< Digital Compare Edge filter both + //!< edges mode +} EPWM_DigitalCompareEdgeFilterMode; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_setDigitalCompareEdgeFilterEdgeCount() +//! as the \e edgeCount parameter. +// +//***************************************************************************** +typedef enum +{ + EPWM_DC_EDGEFILT_EDGECNT_0 = 0, //!< Digital Compare Edge filter edge + //!< count = 0 + EPWM_DC_EDGEFILT_EDGECNT_1 = 1, //!< Digital Compare Edge filter edge + //!< count = 1 + EPWM_DC_EDGEFILT_EDGECNT_2 = 2, //!< Digital Compare Edge filter edge + //!< count = 2 + EPWM_DC_EDGEFILT_EDGECNT_3 = 3, //!< Digital Compare Edge filter edge + //!< count = 3 + EPWM_DC_EDGEFILT_EDGECNT_4 = 4, //!< Digital Compare Edge filter edge + //!< count = 4 + EPWM_DC_EDGEFILT_EDGECNT_5 = 5, //!< Digital Compare Edge filter edge + //!< count = 5 + EPWM_DC_EDGEFILT_EDGECNT_6 = 6, //!< Digital Compare Edge filter edge + //!< count = 6 + EPWM_DC_EDGEFILT_EDGECNT_7 = 7 //!< Digital Compare Edge filter edge + //!< count = 7 +} EPWM_DigitalCompareEdgeFilterEdgeCount; + +//***************************************************************************** +// +//! Values that can be passed to EPWM_configureSignal() as the +//! \e signalParams parameter. +// +//***************************************************************************** +typedef struct +{ + float32_t freqInHz; //!< Desired Signal Frequency(in Hz) + float32_t dutyValA; //!< Desired ePWMxA Signal Duty + float32_t dutyValB; //!< Desired ePWMxB Signal Duty + bool invertSignalB; //!< Invert ePWMxB Signal if true + float32_t sysClkInHz; //!< SYSCLK Frequency(in Hz) + SysCtl_EPWMCLKDivider epwmClkDiv; //!< EPWM Clock Divider + EPWM_TimeBaseCountMode tbCtrMode; //!< Time Base Counter Mode + EPWM_ClockDivider tbClkDiv; //!< Time Base Counter Clock Divider + EPWM_HSClockDivider tbHSClkDiv; //!< Time Base Counter HS Clock Divider +} EPWM_SignalParams; + +//***************************************************************************** +// +// Functions APIs shared with HRPWM module +// +//***************************************************************************** + +// +// Period Control related API +// +#define EPWM_setSyncPulseSource HRPWM_setSyncPulseSource + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks ePWM base address. +//! +//! \param base specifies the ePWM module base address. +//! +//! This function determines if an ePWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool EPWM_isBaseValid(uint32_t base) +{ + return( + (base == EPWM1_BASE) || + (base == EPWM2_BASE) || + (base == EPWM3_BASE) || + (base == EPWM4_BASE) || + (base == EPWM5_BASE) || + (base == EPWM6_BASE) || + (base == EPWM7_BASE) || + (base == EPWM8_BASE) || + (base == EPWM9_BASE) || + (base == EPWM10_BASE) || + (base == EPWM11_BASE) || + (base == EPWM12_BASE) + ); +} +#endif + +// +// Time Base Sub Module related APIs +// +//***************************************************************************** +// +//! Set the time base count +//! +//! \param base is the base address of the EPWM module. +//! \param count is the time base count value. +//! +//! This function sets the 16 bit counter value of the time base counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounter(uint32_t base, uint16_t count) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBCTR register + // + HWREGH(base + EPWM_O_TBCTR) = count; +} + +//***************************************************************************** +// +//! Set count mode after phase shift sync +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the count mode. +//! +//! This function sets the time base count to count up or down after a new +//! phase value set by the EPWM_setPhaseShift(). The count direction is +//! determined by the variable mode. Valid inputs for mode are: +//! - EPWM_COUNT_MODE_UP_AFTER_SYNC - Count up after sync +//! - EPWM_COUNT_MODE_DOWN_AFTER_SYNC - Count down after sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCountModeAfterSync(uint32_t base, EPWM_SyncCountMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(mode == EPWM_COUNT_MODE_UP_AFTER_SYNC) + { + // + // Set PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSDIR; + } + else + { + // + // Clear PHSDIR bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSDIR; + } +} + +//***************************************************************************** +// +//! Set the time base clock and the high speed time base clock count pre-scaler +//! +//! \param base is the base address of the EPWM module. +//! \param prescaler is the time base count pre scale value. +//! \param highSpeedPrescaler is the high speed time base count pre scale +//! value. +//! +//! This function sets the pre scaler(divider)value for the time base clock +//! counter and the high speed time base clock counter. +//! Valid values for pre-scaler and highSpeedPrescaler are EPWM_CLOCK_DIVIDER_X, +//! where X is 1,2,4,8,16, 32,64 or 128. +//! The actual numerical values for these macros represent values 0,1...7. +//! The equation for the output clock is: +//! TBCLK = EPWMCLK/(highSpeedPrescaler * pre-scaler) +//! +//! \b Note: EPWMCLK is a scaled version of SYSCLK. At reset EPWMCLK is half +//! SYSCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setClockPrescaler(uint32_t base, EPWM_ClockDivider prescaler, + EPWM_HSClockDivider highSpeedPrescaler) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CLKDIV and HSPCLKDIV bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & + ~(EPWM_TBCTL_CLKDIV_M | EPWM_TBCTL_HSPCLKDIV_M)) | + (((uint16_t)prescaler << EPWM_TBCTL_CLKDIV_S) | + ((uint16_t)highSpeedPrescaler << EPWM_TBCTL_HSPCLKDIV_S))); +} + +//***************************************************************************** +// +//! Force a software sync pulse +//! +//! \param base is the base address of the EPWM module. +//! +//! This function causes a single software initiated sync pulse. Make sure the +//! appropriate mode is selected using EPWM_setupSyncOutputMode() before using +//! this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceSyncPulse(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SWFSYNC bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_SWFSYNC; +} + +//***************************************************************************** +// +//! Set up the sync out pulse event +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the sync out mode. +//! +//! This function set the sync out pulse mode. +//! Valid values for mode are: +//! - EPWM_SYNC_OUT_PULSE_ON_SOFTWARE - sync pulse is generated by software +//! when EPWM_forceSyncPulse() +//! function is called or by EPWMxSYNCI +//! signal. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_ZERO - sync pulse is generated when +//! time base counter equals zero. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_B - sync pulse is generated when +//! time base counter equals compare +//! B value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_C - sync pulse is generated when +//! time base counter equals compare +//! C value. +//! - EPWM_SYNC_OUT_PULSE_ON_COUNTER_COMPARE_D - sync pulse is generated when +//! time base counter equals compare +//! D value. +//! - EPWM_SYNC_OUT_PULSE_DISABLED - sync pulse is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setSyncOutPulseMode(uint32_t base, EPWM_SyncOutPulseMode mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // No extended mode support + // + if(mode < EPWM_SYNC_OUT_PULSE_DISABLED) + { + // + // Write to SYNCOSEL bits + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_SYNCOSEL_M)) | + ((uint16_t)mode << EPWM_TBCTL_SYNCOSEL_S)); + } + // + // Extended modes and sync out disable mode + // + else + { + // + // Write 0x3 to SYNCOSEL to enable selection from SYNCOSELX + // + HWREGH(base + EPWM_O_TBCTL) = HWREGH(base + EPWM_O_TBCTL) | + EPWM_TBCTL_SYNCOSEL_M; + + // + // Write to SYNCOSELX bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_SYNCOSELX_M)) | + (((uint16_t)mode & 0x3U) << EPWM_TBCTL2_SYNCOSELX_S)); + } +} + +//***************************************************************************** +// +//! Set PWM period load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the PWM period load mode. +//! +//! This function sets the load mode for the PWM period. If loadMode is set to +//! EPWM_PERIOD_SHADOW_LOAD, a write or read to the TBPRD (PWM Period count +//! register) accesses the shadow register. If loadMode is set to +//! EPWM_PERIOD_DIRECT_LOAD, a write or read to the TBPRD register accesses the +//! register directly. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPeriodLoadMode(uint32_t base, EPWM_PeriodLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(loadMode == EPWM_PERIOD_SHADOW_LOAD) + { + // + // Clear PRDLD + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PRDLD; + } + else + { + // + // Set PRDLD + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PRDLD; + } +} + +//***************************************************************************** +// +//! Enable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of phase shift when the appropriate sync +//! event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) |= EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Disable phase shift load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of phase shift. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear PHSEN bit + // + HWREGH(base + EPWM_O_TBCTL) &= ~EPWM_TBCTL_PHSEN; +} + +//***************************************************************************** +// +//! Set time base counter mode +//! +//! \param base is the base address of the EPWM module. +//! \param counterMode is the time base counter mode. +//! +//! This function sets up the time base counter mode. +//! Valid values for counterMode are: +//! - EPWM_COUNTER_MODE_UP - Up - count mode. +//! - EPWM_COUNTER_MODE_DOWN - Down - count mode. +//! - EPWM_COUNTER_MODE_UP_DOWN - Up - down - count mode. +//! - EPWM_COUNTER_MODE_STOP_FREEZE - Stop - Freeze counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBaseCounterMode(uint32_t base, EPWM_TimeBaseCountMode counterMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to CTRMODE bit + // + HWREGH(base + EPWM_O_TBCTL) = + ((HWREGH(base + EPWM_O_TBCTL) & ~(EPWM_TBCTL_CTRMODE_M)) | + ((uint16_t)counterMode)); +} + +//***************************************************************************** +// +//! Set shadow to active period load on sync mode +//! +//! \param base is the base address of the EPWM module. +//! \param shadowLoadMode is the shadow to active load mode. +//! +//! This function sets up the shadow to active Period register load mode with +//! respect to a sync event. Valid values for shadowLoadMode are: +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_ZERO - shadow to active load occurs when +//! time base counter reaches 0. +//! - EPWM_SHADOW_LOAD_MODE_COUNTER_SYNC - shadow to active load occurs when +//! time base counter reaches 0 and a +//! SYNC occurs. +//! - EPWM_SHADOW_LOAD_MODE_SYNC - shadow to active load occurs only +//! when a SYNC occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_selectPeriodLoadEvent(uint32_t base, + EPWM_PeriodShadowLoadMode shadowLoadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to PRDLDSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) = + ((HWREGH(base + EPWM_O_TBCTL2) & ~(EPWM_TBCTL2_PRDLDSYNC_M)) | + ((uint16_t)shadowLoadMode << EPWM_TBCTL2_PRDLDSYNC_S)); +} +//***************************************************************************** +// +//! Enable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Disable one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables one shot sync mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear OSHTSYNCMODE bit + // + HWREGH(base + EPWM_O_TBCTL2) &= ~EPWM_TBCTL2_OSHTSYNCMODE; +} + +//***************************************************************************** +// +//! Start one shot sync mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function propagates a one shot sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startOneShotSync(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set OSHTSYNC bit + // + HWREGH(base + EPWM_O_TBCTL2) |= EPWM_TBCTL2_OSHTSYNC; +} + +//***************************************************************************** +// +//! Returns time base counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the current value of the time base counter. +//! +//! \return returns time base counter value +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterValue(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Returns TBCTR value + // + return(HWREGH(base + EPWM_O_TBCTR)); +} + +//***************************************************************************** +// +//! Return time base counter maximum status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the status of the time base max counter. +//! +//! \return Returns true if the counter has reached 0xFFFF. +//! Returns false if the counter hasn't reached 0xFFFF. +// +//***************************************************************************** +static inline bool +EPWM_getTimeBaseCounterOverflowStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if CTRMAX bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRMAX) == + EPWM_TBSTS_CTRMAX) ? true : false); +} + +//***************************************************************************** +// +//! Clear max time base counter event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the max time base counter latch event. The latch event +//! occurs when the time base counter reaches its maximum value of 0xFFFF. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearTimeBaseCounterOverflowEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CTRMAX bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_CTRMAX; +} + +//***************************************************************************** +// +//! Return external sync signal status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the external sync signal status. +//! +//! \return Returns true if if an external sync signal event +//! Returns false if there is no event. +// +//***************************************************************************** +static inline bool +EPWM_getSyncStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return true if SYNCI bit is set, false otherwise + // + return(((HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_SYNCI) == + EPWM_TBSTS_SYNCI) ? true : false); +} + +//***************************************************************************** +// +//! Clear external sync signal event. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the external sync signal latch event. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_clearSyncEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SYNCI bit + // + HWREGH(base + EPWM_O_TBSTS) = EPWM_TBSTS_SYNCI; +} + +//***************************************************************************** +// +//! Return time base counter direction. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the direction of the time base counter. +//! +//! \return returns EPWM_TIME_BASE_STATUS_COUNT_UP if the counter is counting +//! up or EPWM_TIME_BASE_STATUS_COUNT_DOWN if the counter is +//! counting down. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBaseCounterDirection(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return CTRDIR bit + // + return(HWREGH(base + EPWM_O_TBSTS) & EPWM_TBSTS_CTRDIR); +} + +//***************************************************************************** +// +//! Sets the phase shift offset counter value. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the phase shift count value. +//! +//! This function sets the 16 bit time-base counter phase of the ePWM relative +//! to the time-base that is supplying the synchronization input signal. Call +//! the EPWM_enablePhaseShiftLoad() function to enable loading of the +//! phaseCount phase shift value when a sync event occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setPhaseShift(uint32_t base, uint16_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPHS bit + // + HWREG(base + EPWM_O_TBPHS) = + ((HWREG(base + EPWM_O_TBPHS) & + ~((uint32_t)EPWM_TBPHS_TBPHS_M)) | + ((uint32_t)phaseCount << EPWM_TBPHS_TBPHS_S)); +} + +//***************************************************************************** +// +//! Sets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is period count value. +//! +//! This function sets the period of the PWM count. The value of periodCount is +//! the value written to the register. User should map the desired period or +//! frequency of the waveform into the correct periodCount. +//! Invoke the function EPWM_selectPeriodLoadEvent() with the appropriate +//! parameter to set the load mode of the Period count. periodCount has a +//! maximum valid value of 0xFFFF +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTimeBasePeriod(uint32_t base, uint16_t periodCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TBPRD bit + // + HWREGH(base + EPWM_O_TBPRD) = periodCount; +} + +//***************************************************************************** +// +//! Gets the PWM period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the period of the PWM count. +//! +//! \return The period count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read from TBPRD bit + // + return(HWREGH(base + EPWM_O_TBPRD)); +} + +//***************************************************************************** +// +//! Sets the EPWM links. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmLink is the ePWM instance to link with. +//! \param linkComp is the ePWM component to link. +//! +//! This function links the component defined in linkComp in the current ePWM +//! instance with the linkComp component of the ePWM instance defined by +//! epwmLink. A change (a write) in the value of linkComp component of epwmLink +//! instance, causes a change in the current ePWM linkComp component. +//! For example if the current ePWM is ePWM3 and the values of epwmLink and +//! linkComp are EPWM_LINK_WITH_EPWM_1 and EPWM_LINK_COMP_C respectively, +//! then a write to COMPC register in ePWM1, will result in a simultaneous +//! write to COMPC register in ePWM3. +//! Valid values for epwmLink are: +//! - EPWM_LINK_WITH_EPWM_1 - link current ePWM with ePWM1 +//! - EPWM_LINK_WITH_EPWM_2 - link current ePWM with ePWM2 +//! - EPWM_LINK_WITH_EPWM_3 - link current ePWM with ePWM3 +//! - EPWM_LINK_WITH_EPWM_4 - link current ePWM with ePWM4 +//! - EPWM_LINK_WITH_EPWM_5 - link current ePWM with ePWM5 +//! - EPWM_LINK_WITH_EPWM_6 - link current ePWM with ePWM6 +//! - EPWM_LINK_WITH_EPWM_7 - link current ePWM with ePWM7 +//! - EPWM_LINK_WITH_EPWM_8 - link current ePWM with ePWM8 +//! - EPWM_LINK_WITH_EPWM_9 - link current ePWM with ePWM9 +//! - EPWM_LINK_WITH_EPWM_10 - link current ePWM with ePWM10 +//! - EPWM_LINK_WITH_EPWM_11 - link current ePWM with ePWM11 +//! - EPWM_LINK_WITH_EPWM_12 - link current ePWM with ePWM12 +//! +//! Valid values for linkComp are: +//! - EPWM_LINK_TBPRD - link TBPRD:TBPRDHR registers +//! - EPWM_LINK_COMP_A - link COMPA registers +//! - EPWM_LINK_COMP_B - link COMPB registers +//! - EPWM_LINK_COMP_C - link COMPC registers +//! - EPWM_LINK_COMP_D - link COMPD registers +//! - EPWM_LINK_GLDCTL2 - link GLDCTL2 registers +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setupEPWMLinks(uint32_t base, EPWM_CurrentLink epwmLink, + EPWM_LinkComponent linkComp) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + uint32_t registerOffset; + registerOffset = base + EPWM_O_XLINK; + + // + // Configure EPWM links + // + HWREG(registerOffset) = + ((HWREG(registerOffset) & ~((uint32_t)EPWM_XLINK_TBPRDLINK_M << (uint32_t)linkComp)) | + ((uint32_t)epwmLink << (uint32_t)linkComp)); +} + + +//***************************************************************************** +// +//! Sets up the Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets up the counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! - loadMode +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_COMP_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO - load when counter equals zero +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_PERIOD -load when counter equals period +//! - EPWM_COMP_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_COMP_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule, + EPWM_CounterCompareLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t loadModeOffset; + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + syncModeOffset = 10U; + loadModeOffset = 0U; + shadowModeOffset = 4U; + } + else + { + syncModeOffset = 12U; + loadModeOffset = 2U; + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(registerOffset) = ((HWREGH(registerOffset) & + ~((0x3U << syncModeOffset) | // Clear sync mode + (0x3U << loadModeOffset) | // Clear load mode + (0x1U << shadowModeOffset))) | // shadow mode + ((((uint16_t)loadMode >> 2U) << syncModeOffset) | + (((uint16_t)loadMode & 0x3U) << loadModeOffset))); +} + +//***************************************************************************** +// +//! Disable Counter Compare shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the counter compare module. +//! +//! This function disables counter compare shadow load mode. +//! Valid values for the variables are: +//! - compModule +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableCounterCompareShadowLoadMode(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + uint16_t shadowModeOffset; + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_C)) + { + shadowModeOffset = 4U; + } + else + { + shadowModeOffset = 6U; + } + + // + // Get the register offset. EPWM_O_CMPCTL for A&B or + // EPWM_O_CMPCTL2 for C&D + // + registerOffset = base + EPWM_O_CMPCTL + ((uint32_t)compModule & 0x1U); + + // + // Disable shadow load mode. + // + HWREGH(registerOffset) = (HWREGH(registerOffset) | + (0x1U << shadowModeOffset)); +} + +//***************************************************************************** +// +//! Set counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! \param compCount is the counter compare count value. +//! +//! This function sets the counter compare value for counter compare registers. +//! The maximum value for compCount is 0xFFFF. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule, + uint16_t compCount) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Write to the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Write to COMPA or COMPB bits + // + HWREGH(base + registerOffset + 0x1U) = compCount; + } + else + { + // + // Write to COMPC or COMPD bits + // + HWREGH(base + registerOffset) = compCount; + } +} + +//***************************************************************************** +// +//! Get counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function gets the counter compare value for counter compare registers. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! - EPWM_COUNTER_COMPARE_C - counter compare C. +//! - EPWM_COUNTER_COMPARE_D - counter compare D. +//! +//! \return The counter compare count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getCounterCompareValue(uint32_t base, EPWM_CounterCompareModule compModule) +{ + uint32_t registerOffset; + uint16_t compCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset for the Counter compare + // + registerOffset = EPWM_O_CMPA + (uint32_t)compModule; + + // + // Read from the counter compare registers. + // + if((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)) + { + // + // Read COMPA or COMPB bits + // + compCount = (uint16_t)((HWREG(base + registerOffset) & + 0xFFFF0000UL) >> 16U); + } + else + { + // + // Read COMPC or COMPD bits + // + compCount = HWREGH(base + registerOffset); + } + return(compCount); +} + +//***************************************************************************** +// +//! Return the counter compare shadow register full status. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare value module. +//! +//! This function returns the counter Compare shadow register full status flag. +//! Valid values for compModule are: +//! - EPWM_COUNTER_COMPARE_A - counter compare A. +//! - EPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return Returns true if the shadow register is full. +//! Returns false if the shadow register is not full. +// +//***************************************************************************** +static inline bool +EPWM_getCounterCompareShadowStatus(uint32_t base, + EPWM_CounterCompareModule compModule) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Check the validity of input. + // COMPA and COMPB are valid input arguments. + // + ASSERT((compModule == EPWM_COUNTER_COMPARE_A) || + (compModule == EPWM_COUNTER_COMPARE_B)); + + // + // Read the value of SHDWAFULL or SHDWBFULL bit + // + return((((HWREG(base + EPWM_O_CMPCTL) >> + ((((uint16_t)compModule >> 1U) & 0x1U) + 8U)) & + 0x1U) == 0x1U) ? true:false); +} + +// +// Action Qualifier module related APIs +// +//***************************************************************************** +// +//! Sets the Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! - loadMode +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - EPWM_AQ_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - EPWM_AQ_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals +//! zero or period +//! - EPWM_AQ_LOAD_FREEZE - Freeze shadow to active load +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO - load on sync or when counter +//! equals zero +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_PERIOD - load on sync or when counter +//! equals period +//! - EPWM_AQ_LOAD_ON_SYNC_CNTR_ZERO_PERIOD - load on sync or when +//! counter equals zero or period +//! - EPWM_AQ_LOAD_ON_SYNC_ONLY - load on sync only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule, + EPWM_ActionQualifierLoadMode loadMode) +{ + uint16_t syncModeOffset; + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + syncModeOffset = 8U + (uint16_t)aqModule; + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Set the appropriate sync and load mode bits and also enable shadow + // load mode. Shadow to active load can also be frozen. + // + HWREGH(base + EPWM_O_AQCTL) = ((HWREGH(base + EPWM_O_AQCTL) & + (~((0x3U << (uint16_t)aqModule) | + (0x3U << (uint16_t)syncModeOffset))) | + (0x1U << shadowModeOffset)) | + ((((uint16_t)loadMode >> 2U) << + syncModeOffset) | (((uint16_t)loadMode & + 0x3U) << (uint16_t)aqModule))); +} + +//***************************************************************************** +// +//! Disable Action Qualifier shadow load mode +//! +//! \param base is the base address of the EPWM module. +//! \param aqModule is the Action Qualifier module value. +//! +//! This function disables the Action Qualifier shadow load mode. +//! Valid values for the variables are: +//! - aqModule +//! - EPWM_ACTION_QUALIFIER_A - Action Qualifier A. +//! - EPWM_ACTION_QUALIFIER_B - Action Qualifier B. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableActionQualifierShadowLoadMode(uint32_t base, + EPWM_ActionQualifierModule aqModule) +{ + uint16_t shadowModeOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shadowModeOffset = 4U + (uint16_t)aqModule; + + // + // Disable shadow load mode. Action qualifier is loaded on + // immediate mode only. + // + HWREGH(base + EPWM_O_AQCTL) &= ~(1U << shadowModeOffset); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T1 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T1. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT1TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T1 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T1SEL_M)) | + ((uint16_t)trigger)); +} + +//***************************************************************************** +// +//! Set up Action qualifier trigger source for event T2 +//! +//! \param base is the base address of the EPWM module. +//! \param trigger sources for Action Qualifier triggers. +//! +//! This function sets up the sources for Action Qualifier event T2. +//! Valid values for trigger are: +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_1 - Digital compare event A 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCA_2 - Digital compare event A 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_1 - Digital compare event B 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_DCB_2 - Digital compare event B 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_1 - Trip zone 1 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_2 - Trip zone 2 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_TZ_3 - Trip zone 3 +//! - EPWM_AQ_TRIGGER_EVENT_TRIG_EPWM_SYNCIN - ePWM sync +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierT2TriggerSource(uint32_t base, + EPWM_ActionQualifierTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set T2 trigger source + // + HWREGH(base + EPWM_O_AQTSRCSEL) = + ((HWREGH(base + EPWM_O_AQTSRCSEL) & (~EPWM_AQTSRCSEL_T2SEL_M)) | + ((uint16_t)trigger << EPWM_AQTSRCSEL_T2SEL_S)); +} + +//***************************************************************************** +// +//! Set up Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! \param event is the event that causes a change in output. +//! +//! This function sets up the Action Qualifier output on ePWM A or ePWMB, +//! depending on the value of epwmOutput, to a value specified by outPut based +//! on the input events - specified by event. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! - event +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_ZERO - Time base counter equals +//! zero +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_PERIOD - Time base counter equals +//! period +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPA - Time base counter up equals +//! COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPA - Time base counter down +//! equals COMPA +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_UP_CMPB - Time base counter up equals +//! COMPB +//! - EPWM_AQ_OUTPUT_ON_TIMEBASE_DOWN_CMPB - Time base counter down +//! equals COMPB +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_UP - T1 event on count up +//! - EPWM_AQ_OUTPUT_ON_T1_COUNT_DOWN - T1 event on count down +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_UP - T2 event on count up +//! - EPWM_AQ_OUTPUT_ON_T2_COUNT_DOWN - T2 event on count down +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output, + EPWM_ActionQualifierOutputEvent event) +{ + uint32_t registerOffset; + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // If the event occurs on T1 or T2 events + // + if(((uint16_t)event & 0x1U) == 1U) + { + // + // Write to T1U,T1D,T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = + ((HWREGH(base + registerTOffset) & ~(3U << ((uint16_t)event - 1U))) | + ((uint16_t)output << ((uint16_t)event - 1U))); + } + else + { + // + // Write to ZRO,PRD,CAU,CAD,CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~(3U << (uint16_t)event)) | + ((uint16_t)output << (uint16_t)event)); + } +} + +//***************************************************************************** +// +//! Set up Action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Action Qualifier output on ePWMA or ePWMB, +//! depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different time base counter scenarios +//! should be OR'd together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! - action +//! - When time base counter equals zero +//! - EPWM_AQ_OUTPUT_NO_CHANGE_ZERO - Time base counter equals zero +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_ZERO - Time base counter equals zero +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_ZERO - Time base counter equals zero +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_ZERO - Time base counter equals zero +//! and toggle the output pins +//! - When time base counter equals period +//! - EPWM_AQ_OUTPUT_NO_CHANGE_PERIOD - Time base counter equals period +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_PERIOD - Time base counter equals period +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_PERIOD - Time base counter equals period +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_PERIOD - Time base counter equals period +//! and toggle the output pins +//! - When time base counter equals CMPA during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPA - Time base counter up equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPA - Time base counter up equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPA - Time base counter up equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPA - Time base counter up equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPA during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPA - Time base counter down equals +//! COMPA and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPA - Time base counter down equals +//! COMPA and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPA - Time base counter down equals +//! COMPA and toggle output pins +//! - When time base counter equals CMPB during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_CMPB - Time base counter up equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_CMPB - Time base counter up equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_UP_CMPB - Time base counter up equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_CMPB - Time base counter up equals +//! COMPB and toggle output pins +//! - When time base counter equals CMPB during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_CMPB- Time base counter down equals +//! COMPB and no change in the +//! output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_CMPB - Time base counter down equals +//! COMPB and set output pins high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_CMPB - Time base counter down equals +//! COMPB and toggle output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each time base +//! counter scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerOffset = EPWM_O_AQCTLA + (uint32_t)epwmOutput; + + // + // Write to ZRO, PRD, CAU, CAD, CBU or CBD bits of AQCTLA register + // + HWREGH(base + registerOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Set up Additional action qualifier event outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param action is the desired action when the specified event occurs +//! +//! This function sets up the Additional Action Qualifier output on ePWMA or +//! ePWMB depending on the value of epwmOutput, to a value specified by action. +//! Valid action param values from different event scenarios should be OR'd +//! together to configure complete action for a pwm output. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - action +//! - When T1 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T1 - T1 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T1 - T1 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T1 - T1 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T1 - T1 event on count up +//! and toggle the output pins +//! - When T1 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T1- T1 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T1 - T1 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T1 - T1 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T1 - T1 event on count down +//! and toggle the output pins +//! - When T2 event occurs during up-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_UP_T2 - T2 event on count up +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_UP_T2 - T2 event on count up +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_UP_T2 - T2 event on count up +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_UP_T2 - T2 event on count up +//! and toggle the output pins +//! - When T2 event occurs during down-count +//! - EPWM_AQ_OUTPUT_NO_CHANGE_DOWN_T2 - T2 event on count down +//! and no change in output pins +//! - EPWM_AQ_OUTPUT_LOW_DOWN_T2 - T2 event on count down +//! and set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH_DOWN_T2 - T2 event on count down +//! and set output pins to high +//! - EPWM_AQ_OUTPUT_TOGGLE_DOWN_T2 - T2 event on count down +//! and toggle the output pins +//! +//! \b note: A logical OR of the valid values should be passed as the action +//! parameter. Single action should be configured for each event +//! scenario. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setAdditionalActionQualifierActionComplete(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + uint16_t action) +{ + uint32_t registerTOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the register offset + // + registerTOffset = EPWM_O_AQCTLA2 + (uint32_t)epwmOutput; + + // + // Write to T1U, T1D, T2U or T2D of AQCTLA2 register + // + HWREGH(base + registerTOffset) = (uint16_t)action; +} + +//***************************************************************************** +// +//! Sets up Action qualifier continuous software load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param mode is the mode for shadow to active load mode. +//! +//! This function sets up the AQCFRSC register load mode for continuous +//! software force reload mode. The software force actions are determined by +//! the EPWM_setActionQualifierContSWForceAction() function. +//! Valid values for mode are: +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO - shadow mode load when counter +//! equals zero +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_PERIOD - shadow mode load when counter +//! equals period +//! - EPWM_AQ_SW_SH_LOAD_ON_CNTR_ZERO_PERIOD - shadow mode load when counter +//! equals zero or period +//! - EPWM_AQ_SW_IMMEDIATE_LOAD - immediate mode load only +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceShadowMode(uint32_t base, + EPWM_ActionQualifierContForce mode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action qualifier software action reload mode. + // Write to RLDCSF bit + // + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_RLDCSF_M) | + ((uint16_t)mode << EPWM_AQSFRC_RLDCSF_S)); +} + +//***************************************************************************** +// +//! Triggers a continuous software forced event. +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function triggers a continuous software forced Action Qualifier output +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for the parameters are: +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_SW_DISABLED - Software forcing disabled. +//! - EPWM_AQ_SW_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_SW_OUTPUT_HIGH - Set output pins to High +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierContSWForceAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierSWOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a continuous software forced output + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQCSFRC) = + ((HWREGH(base + EPWM_O_AQCSFRC) & ~EPWM_AQCSFRC_CSFB_M) | + ((uint16_t)output << EPWM_AQCSFRC_CSFB_S)) ; + } +} + +//***************************************************************************** +// +//! Set up one time software forced Action qualifier outputs +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! \param output is the Action Qualifier output. +//! +//! This function sets up the one time software forced Action Qualifier output +//! on ePWM A or ePWMB, depending on the value of epwmOutput to a value +//! specified by outPut. +//! The following are valid values for the parameters. +//! - epwmOutput +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! - output +//! - EPWM_AQ_OUTPUT_NO_CHANGE - No change in the output pins +//! - EPWM_AQ_OUTPUT_LOW - Set output pins to low +//! - EPWM_AQ_OUTPUT_HIGH - Set output pins to High +//! - EPWM_AQ_OUTPUT_TOGGLE - Toggle the output pins +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput, + EPWM_ActionQualifierOutput output) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the one time software forced action + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFA_M) | + ((uint16_t)output)); + } + else + { + HWREGH(base + EPWM_O_AQSFRC) = + ((HWREGH(base + EPWM_O_AQSFRC) & ~EPWM_AQSFRC_ACTSFB_M) | + ((uint16_t)output << EPWM_AQSFRC_ACTSFB_S)); + } +} + +//***************************************************************************** +// +//! Triggers a one time software forced event on Action qualifier +//! +//! \param base is the base address of the EPWM module. +//! \param epwmOutput is the ePWM pin type. +//! +//! This function triggers a one time software forced Action Qualifier event +//! on ePWM A or B based on the value of epwmOutput. +//! Valid values for epwmOutput are: +//! - EPWM_AQ_OUTPUT_A - ePWMxA output +//! - EPWM_AQ_OUTPUT_B - ePWMxB output +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceActionQualifierSWAction(uint32_t base, + EPWM_ActionQualifierOutputModule epwmOutput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Initiate a software forced event + // + if(epwmOutput == EPWM_AQ_OUTPUT_A) + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFA; + } + else + { + HWREGH(base + EPWM_O_AQSFRC) |= EPWM_AQSFRC_OTSFB; + } +} + +// +// Dead Band Module related APIs +// +//***************************************************************************** +// +//! Sets Dead Band signal output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param output is the ePWM Dead Band output. +//! \param enableSwapMode is the output swap mode. +//! +//! This function sets up the output signal swap mode. For example if the +//! output variable is set to EPWM_DB_OUTPUT_A and enableSwapMode is true, then +//! the ePWM A output gets its signal from the ePWM B signal path. Valid values +//! for the input variables are: +//! - output +//! - EPWM_DB_OUTPUT_A - ePWM output A +//! - EPWM_DB_OUTPUT_B - ePWM output B +//! - enableSwapMode +//! - true - the output is swapped +//! - false - the output and the signal path are the same. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandOutputSwapMode(uint32_t base, EPWM_DeadBandOutput output, + bool enableSwapMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)output + EPWM_DBCTL_OUTSWAP_S); + + if(enableSwapMode) + { + // + // Set the appropriate outswap bit to swap output + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band signal output mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param enableDelayMode is the dead band delay mode. +//! +//! This function sets up the dead band delay mode. The delayMode variable +//! determines if the applied delay is Rising Edge or Falling Edge. The +//! enableDelayMode determines if a dead band delay should be applied. +//! Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - enableDelayMode +//! - true - Falling edge or Rising edge delay is applied. +//! - false - Dead Band delay is bypassed. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayMode(uint32_t base, EPWM_DeadBandDelayMode delayMode, + bool enableDelayMode) +{ + uint16_t mask; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + mask = (uint16_t)1U << ((uint16_t)delayMode + EPWM_DBCTL_OUT_MODE_S); + + if(enableDelayMode) + { + // + // Set the appropriate outmode bit to enable Dead Band delay + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) | mask); + } + else + { + // + // Clear the appropriate outswap bit to disable output swap + // + HWREGH(base + EPWM_O_DBCTL) = (HWREGH(base + EPWM_O_DBCTL) & ~ mask); + } +} + +//***************************************************************************** +// +//! Sets Dead Band delay polarity. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Dead Band delay type. +//! \param polarity is the polarity of the delayed signal. +//! +//! This function sets up the polarity as determined by the variable polarity +//! of the Falling Edge or Rising Edge delay depending on the value of +//! delayMode. Valid values for the variables are: +//! - delayMode +//! - EPWM_DB_RED - Rising Edge delay +//! - EPWM_DB_FED - Falling Edge delay +//! - polarity +//! - EPWM_DB_POLARITY_ACTIVE_HIGH - polarity is not inverted. +//! - EPWM_DB_POLARITY_ACTIVE_LOW - polarity is inverted. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandDelayPolarity(uint32_t base, + EPWM_DeadBandDelayMode delayMode, + EPWM_DeadBandPolarity polarity) +{ + uint16_t shift; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + shift = (((uint16_t)delayMode ^ 0x1U) + EPWM_DBCTL_POLSEL_S); + + // + // Set the appropriate polsel bits for dead band polarity + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~ (1U << shift)) | + ((uint16_t)polarity << shift)); +} + +//***************************************************************************** +// +//! Sets Rising Edge Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA( Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB( Valid for both Falling +//! Edge and Rising Edge) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB)); + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S))) | + (input << EPWM_DBCTL_IN_MODE_S)); +} + +//***************************************************************************** +// +//! Sets Dead Band delay input. +//! +//! \param base is the base address of the EPWM module. +//! \param input is the input signal to the dead band. +//! +//! This function sets up the rising Edge delay input signal. +//! Valid values for input are: +//! - EPWM_DB_INPUT_EPWMA - Input signal is ePWMA(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_EPWMB - Input signal is ePWMB(Valid for both Falling +//! Edge and Rising Edge) +//! - EPWM_DB_INPUT_DB_RED - Input signal is the output of Rising +//! Edge delay. +//! (Valid only for Falling Edge delay) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDeadBandDelayInput(uint32_t base, uint16_t input) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((input == EPWM_DB_INPUT_EPWMA) || + (input == EPWM_DB_INPUT_EPWMB) || + (input == EPWM_DB_INPUT_DB_RED)); + + if(input == EPWM_DB_INPUT_DB_RED) + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) |= EPWM_DBCTL_DEDB_MODE; + } + else + { + // + // Set the Falling Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) &= ~EPWM_DBCTL_DEDB_MODE; + + // + // Set the Rising Edge Delay input + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~(1U << (EPWM_DBCTL_IN_MODE_S + 1U))) | + (input << (EPWM_DBCTL_IN_MODE_S + 1U))); + } +} + +//***************************************************************************** +// +//! Set the Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load mode. +//! +//! This function enables and sets the Dead Band control register shadow +//! load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_DB_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_DB_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_DB_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_DB_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandControlShadowLoadMode(uint32_t base, + EPWM_DeadBandControlLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode and setup the load event + // + HWREGH(base + EPWM_O_DBCTL2) = + ((HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_LOADDBCTLMODE_M) | + (EPWM_DBCTL2_SHDWDBCTLMODE | (uint16_t)loadMode)); +} + +//***************************************************************************** +// +//! Disable Dead Band control shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Dead Band control register shadow +//! load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDeadBandControlShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow load mode. Only immediate load mode only. + // + HWREGH(base + EPWM_O_DBCTL2) = + (HWREGH(base + EPWM_O_DBCTL2) & ~EPWM_DBCTL2_SHDWDBCTLMODE); +} + +//***************************************************************************** +// +//! Set the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function sets the Rising Edge Delay register shadow load mode. +//! Valid values for the \e loadMode parameter are: +//! - EPWM_RED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_RED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_RED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_RED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_RisingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Set-up the load mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADREDMODE_M) | + ((uint16_t)EPWM_DBCTL_SHDWDBREDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADREDMODE_S))); + +} + +//***************************************************************************** +// +//! Disable the RED (Rising Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Rising Edge Delay register shadow load mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableRisingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBREDMODE); + +} + +//***************************************************************************** +// +//! Set the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadMode is the shadow to active load event. +//! +//! This function enables and sets the Falling Edge Delay register shadow load +//! mode. Valid values for the \e loadMode parameters are: +//! - EPWM_FED_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - EPWM_FED_LOAD_ON_CNTR_PERIOD - load when counter equals period. +//! - EPWM_FED_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period. +//! - EPWM_FED_LOAD_FREEZE - Freeze shadow to active load. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCountShadowLoadMode(uint32_t base, + EPWM_FallingEdgeDelayLoadMode loadMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable the shadow mode. Setup the load mode. + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_LOADFEDMODE_M) | + (EPWM_DBCTL_SHDWDBFEDMODE | + ((uint16_t)loadMode << EPWM_DBCTL_LOADFEDMODE_S))); + +} + +//***************************************************************************** +// +//! Disables the FED (Falling Edge Delay) shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Falling Edge Delay register shadow load mode. +//! Valid values for the parameters are: +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableFallingEdgeDelayCountShadowLoadMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable the shadow mode. + // + HWREGH(base + EPWM_O_DBCTL) = + (HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_SHDWDBFEDMODE); +} + +//***************************************************************************** +// +//! Sets Dead Band Counter clock rate. +//! +//! \param base is the base address of the EPWM module. +//! \param clockMode is the Dead Band counter clock mode. +//! +//! This function sets up the Dead Band counter clock rate with respect to +//! TBCLK (ePWM time base counter). +//! Valid values for clockMode are: +//! - EPWM_DB_COUNTER_CLOCK_FULL_CYCLE -Dead band counter runs at TBCLK +//! (ePWM Time Base Counter) rate. +//! - EPWM_DB_COUNTER_CLOCK_HALF_CYCLE -Dead band counter runs at 2*TBCLK +//! (twice ePWM Time Base Counter)rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDeadBandCounterClock(uint32_t base, + EPWM_DeadBandClockMode clockMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DB clock mode + // + HWREGH(base + EPWM_O_DBCTL) = + ((HWREGH(base + EPWM_O_DBCTL) & ~EPWM_DBCTL_HALFCYCLE) | + ((uint16_t)clockMode << 15U)); +} + +//***************************************************************************** +// +//! Set ePWM RED count +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the RED(Rising Edge Delay) count. +//! +//! This function sets the RED (Rising Edge Delay) count value. +//! The value of redCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setRisingEdgeDelayCount(uint32_t base, uint16_t redCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(redCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBRED) = redCount; +} + +//***************************************************************************** +// +//! Set ePWM FED count +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the FED(Falling Edge Delay) count. +//! +//! This function sets the FED (Falling Edge Delay) count value. +//! The value of fedCount should be less than 0x4000U. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setFallingEdgeDelayCount(uint32_t base, uint16_t fedCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(fedCount < 0x4000U); + + // + // Set the RED (Rising Edge Delay) count + // + HWREGH(base + EPWM_O_DBFED) = fedCount; +} + +// +// Chopper module related APIs +// +//***************************************************************************** +// +//! Enable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set CHPEN bit. Enable Chopper + // + HWREGH(base + EPWM_O_PCCTL) |= EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Disable chopper mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables ePWM chopper module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableChopper(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear CHPEN bit. Disable Chopper + // + HWREGH(base + EPWM_O_PCCTL) &= ~EPWM_PCCTL_CHPEN; +} + +//***************************************************************************** +// +//! Set chopper duty cycle. +//! +//! \param base is the base address of the EPWM module. +//! \param dutyCycleCount is the chopping clock duty cycle count. +//! +//! This function sets the chopping clock duty cycle. The value of +//! dutyCycleCount should be less than 7. The dutyCycleCount value is converted +//! to the actual chopper duty cycle value base on the following equation: +//! chopper duty cycle = (dutyCycleCount + 1) / 8 +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperDutyCycle(uint32_t base, uint16_t dutyCycleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(dutyCycleCount < 7U); + + // + // Set the chopper duty cycle + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & ~EPWM_PCCTL_CHPDUTY_M) | + (dutyCycleCount << EPWM_PCCTL_CHPDUTY_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param freqDiv is the chopping clock frequency divider. +//! +//! This function sets the scaler for the chopping clock frequency. The value +//! of freqDiv should be less than 8. The chopping clock frequency is altered +//! based on the following equation. +//! chopper clock frequency = SYSCLKOUT / ( 1 + freqDiv) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFreq(uint32_t base, uint16_t freqDiv) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(freqDiv < 8U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_CHPFREQ_M) | + (freqDiv << EPWM_PCCTL_CHPFREQ_S)); +} + +//***************************************************************************** +// +//! Set chopper clock frequency scaler. +//! +//! \param base is the base address of the EPWM module. +//! \param firstPulseWidth is the width of the first pulse. +//! +//! This function sets the first pulse width of chopper output waveform. The +//! value of firstPulseWidth should be less than 0x10. The value of the first +//! pulse width in seconds is given using the following equation: +//! first pulse width = 1 / (((firstPulseWidth + 1) * SYSCLKOUT)/8) +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setChopperFirstPulseWidth(uint32_t base, uint16_t firstPulseWidth) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(firstPulseWidth < 16U); + + // + // Set the chopper clock + // + HWREGH(base + EPWM_O_PCCTL) = + ((HWREGH(base + EPWM_O_PCCTL) & + ~(uint16_t)EPWM_PCCTL_OSHTWTH_M) | + (firstPulseWidth << EPWM_PCCTL_OSHTWTH_S)); +} + +// +// Trip Zone module related APIs +// +//***************************************************************************** +// +//! Enables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function enables the Trip Zone signals specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) |= tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Disables Trip Zone signal. +//! +//! \param base is the base address of the EPWM module. +//! \param tzSignal is the Trip Zone signal. +//! +//! This function disables the Trip Zone signal specified by tzSignal as a +//! source for the Trip Zone module. +//! Valid values for tzSignal are: +//! - EPWM_TZ_SIGNAL_CBC1 - TZ1 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC2 - TZ2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC3 - TZ3 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC4 - TZ4 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC5 - TZ5 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_CBC6 - TZ6 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCAEVT2 - DCAEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_DCBEVT2 - DCBEVT2 Cycle By Cycle +//! - EPWM_TZ_SIGNAL_OSHT1 - One-shot TZ1 +//! - EPWM_TZ_SIGNAL_OSHT2 - One-shot TZ2 +//! - EPWM_TZ_SIGNAL_OSHT3 - One-shot TZ3 +//! - EPWM_TZ_SIGNAL_OSHT4 - One-shot TZ4 +//! - EPWM_TZ_SIGNAL_OSHT5 - One-shot TZ5 +//! - EPWM_TZ_SIGNAL_OSHT6 - One-shot TZ6 +//! - EPWM_TZ_SIGNAL_DCAEVT1 - One-shot DCAEVT1 +//! - EPWM_TZ_SIGNAL_DCBEVT1 - One-shot DCBEVT1 +//! +//! \b note: A logical OR of the valid values can be passed as the tzSignal +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneSignals(uint32_t base, uint16_t tzSignal) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear the trip zone bits + // + EALLOW; + HWREGH(base + EPWM_O_TZSEL) &= ~tzSignal; + EDIS; +} + +//***************************************************************************** +// +//! Set Digital compare conditions that cause Trip Zone event. +//! +//! \param base is the base address of the EPWM module. +//! \param dcType is the Digital compare output type. +//! \param dcEvent is the Digital Compare output event. +//! +//! This function sets up the Digital Compare output Trip Zone event sources. +//! The dcType variable specifies the event source to be whether Digital +//! Compare output A or Digital Compare output B. The dcEvent parameter +//! specifies the event that causes Trip Zone. +//! Valid values for the parameters are: +//! - dcType +//! - EPWM_TZ_DC_OUTPUT_A1 - Digital Compare output 1 A +//! - EPWM_TZ_DC_OUTPUT_A2 - Digital Compare output 2 A +//! - EPWM_TZ_DC_OUTPUT_B1 - Digital Compare output 1 B +//! - EPWM_TZ_DC_OUTPUT_B2 - Digital Compare output 2 B +//! - dcEvent +//! - EPWM_TZ_EVENT_DC_DISABLED - Event Trigger is disabled +//! - EPWM_TZ_EVENT_DCXH_LOW - Trigger event when DCxH low +//! - EPWM_TZ_EVENT_DCXH_HIGH - Trigger event when DCxH high +//! - EPWM_TZ_EVENT_DCXL_LOW - Trigger event when DCxL low +//! - EPWM_TZ_EVENT_DCXL_HIGH - Trigger event when DCxL high +//! - EPWM_TZ_EVENT_DCXL_HIGH_DCXH_LOW - Trigger event when DCxL high +//! DCxH low +//! +//! \note x in DCxH/DCxL represents DCAH/DCAL or DCBH/DCBL +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneDigitalCompareEventCondition(uint32_t base, + EPWM_TripZoneDigitalCompareOutput dcType, + EPWM_TripZoneDigitalCompareOutputEvent dcEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set Digital Compare Events conditions that cause a Digital Compare trip + // + EALLOW; + HWREGH(base + EPWM_O_TZDCSEL) = + ((HWREGH(base + EPWM_O_TZDCSEL) & ~(0x7U << (uint16_t)dcType)) | + ((uint16_t)dcEvent << (uint16_t)dcType)); + EDIS; +} + +//***************************************************************************** +// +//! Enable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the advanced actions of the Trip Zone events. The +//! advanced features combine the trip zone events with the direction of the +//! counter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Advanced feature. Set ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Disable advanced Trip Zone event Action. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the advanced actions of the Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableTripZoneAdvAction(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Advanced feature. clear ETZE bit + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) &= ~EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzEvent is the Trip Zone event type. +//! \param tzAction is the Trip zone Action. +//! +//! This function sets the Trip Zone Action to be taken when a Trip Zone event +//! occurs. +//! Valid values for the parameters are: +//! - tzEvent +//! - EPWM_TZ_ACTION_EVENT_DCBEVT2 - DCBEVT2 (Digital Compare B event 2) +//! - EPWM_TZ_ACTION_EVENT_DCBEVT1 - DCBEVT1 (Digital Compare B event 1) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT2 - DCAEVT2 (Digital Compare A event 2) +//! - EPWM_TZ_ACTION_EVENT_DCAEVT1 - DCAEVT1 (Digital Compare A event 1) +//! - EPWM_TZ_ACTION_EVENT_TZB - TZ1 - TZ6, DCBEVT2, DCBEVT1 +//! - EPWM_TZ_ACTION_EVENT_TZA - TZ1 - TZ6, DCAEVT2, DCAEVT1 +//! - tzAction +//! - EPWM_TZ_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ACTION_HIGH - high output +//! - EPWM_TZ_ACTION_LOW - low low +//! - EPWM_TZ_ACTION_DISABLE - disable action +//! +//! \note Disable the advanced Trip Zone event using +//! EPWM_disableTripZoneAdvAction() before calling this function. +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzEvent parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAction(uint32_t base, EPWM_TripZoneEvent tzEvent, + EPWM_TripZoneAction tzAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL) = + ((HWREGH(base + EPWM_O_TZCTL) & ~(0x3U << (uint16_t)tzEvent)) | + ((uint16_t)tzAction << (uint16_t)tzEvent)) ; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Trip Zone Action. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvEvent is the Trip Zone event type. +//! \param tzAdvAction is the Trip zone Action. +//! +//! This function sets the Advanced Trip Zone Action to be taken when an +//! advanced Trip Zone event occurs. +//! +//! Valid values for the parameters are: +//! - tzAdvEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_D - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZB_U - TZ1 - TZ6, DCBEVT2, DCBEVT1 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_D - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_TZA_U - TZ1 - TZ6, DCAEVT2, DCAEVT1 while +//! counting up +//! - tzAdvAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note This function operates on both ePWMA and ePWMB depending on the +//! tzAdvEvent parameter. +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvAction(uint32_t base, EPWM_TripZoneAdvancedEvent tzAdvEvent, + EPWM_TripZoneAdvancedAction tzAdvAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTL2) = + ((HWREGH(base + EPWM_O_TZCTL2) & ~(0x7U << (uint16_t)tzAdvEvent)) | + ((uint16_t)tzAdvAction << (uint16_t)tzAdvEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMA. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMA when an advanced Digital Compare Trip Zone A event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event A2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event A2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event A1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event A1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setTripZoneAdvDigitalCompareActionA(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCA) = + ((HWREGH(base + EPWM_O_TZCTLDCA) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Set Advanced Digital Compare Trip Zone Action on ePWMB. +//! +//! \param base is the base address of the EPWM module. +//! \param tzAdvDCEvent is the Digital Compare Trip Zone event type. +//! \param tzAdvDCAction is the Digital Compare Trip zone Action. +//! +//! This function sets the Digital Compare (DC) Advanced Trip Zone Action to be +//! taken on ePWMB when an advanced Digital Compare Trip Zone B event occurs. +//! Valid values for the parameters are: +//! - tzAdvDCEvent +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_D - Digital Compare event B2 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT2_U - Digital Compare event B2 while +//! counting up +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_D - Digital Compare event B1 while +//! counting down +//! - EPWM_TZ_ADV_ACTION_EVENT_DCxEVT1_U - Digital Compare event B1 while +//! counting up +//! - tzAdvDCAction +//! - EPWM_TZ_ADV_ACTION_HIGH_Z - high impedance output +//! - EPWM_TZ_ADV_ACTION_HIGH - high voltage state +//! - EPWM_TZ_ADV_ACTION_LOW - low voltage state +//! - EPWM_TZ_ADV_ACTION_TOGGLE - Toggle output +//! - EPWM_TZ_ADV_ACTION_DISABLE - disable action +//! +//! \note This function enables the advanced Trip Zone event. +//! +//! \note Advanced Trip Zone events take into consideration the direction of +//! the counter in addition to Digital Compare Trip Zone events. +//! +//! \return None. +// +//***************************************************************************** +static inline void EPWM_setTripZoneAdvDigitalCompareActionB(uint32_t base, + EPWM_TripZoneAdvDigitalCompareEvent tzAdvDCEvent, + EPWM_TripZoneAdvancedAction tzAdvDCAction) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Advanced Action for Trip Zone events + // + EALLOW; + HWREGH(base + EPWM_O_TZCTLDCB) = + ((HWREGH(base + EPWM_O_TZCTLDCB) & ~(0x7U << (uint16_t)tzAdvDCEvent)) | + ((uint16_t)tzAdvDCAction << (uint16_t)tzAdvDCEvent)); + + HWREGH(base + EPWM_O_TZCTL2) |= EPWM_TZCTL2_ETZE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function enables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Enable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) |= tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Disable Trip Zone interrupts. +//! +//! \param base is the base address of the EPWM module. +//! \param tzInterrupt is the Trip Zone interrupt. +//! +//! This function disables the Trip Zone interrupts. +//! Valid values for tzInterrupt are: +//! - EPWM_TZ_INTERRUPT_CBC - Trip Zones Cycle By Cycle interrupt +//! - EPWM_TZ_INTERRUPT_OST - Trip Zones One Shot interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT1 - Digital Compare A Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCAEVT2 - Digital Compare A Event 2 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT1 - Digital Compare B Event 1 interrupt +//! - EPWM_TZ_INTERRUPT_DCBEVT2 - Digital Compare B Event 2 interrupt +//! +//! \b note: A logical OR of the valid values can be passed as the tzInterrupt +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_disableTripZoneInterrupt(uint32_t base, uint16_t tzInterrupt) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzInterrupt > 0U) && (tzInterrupt <= 0x80U)); + + // + // Disable Trip zone interrupts + // + EALLOW; + HWREGH(base + EPWM_O_TZEINT) &= ~tzInterrupt; + EDIS; +} + +//***************************************************************************** +// +//! Gets the Trip Zone status flag +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the Trip Zone status flag. +//! +//! \return The function returns the following or the bitwise OR value +//! of the following values. +//! - EPWM_TZ_INTERRUPT - Trip Zone interrupt was generated +//! due to the following TZ events. +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle event status flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot event status flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 status flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 status flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 status flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 status flag +// +//*************************************************************************** +static inline uint16_t +EPWM_getTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZFLG) & 0x7FU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone Cycle by Cycle flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific Cycle by Cycle Trip Zone flag +//! status. +//! +//! \return The function returns the following values. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 status flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 status flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 status flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 status flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 status flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 status flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC status flag for Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC status flag for Digital compare +//! event B2 +// +//*************************************************************************** +static inline uint16_t +EPWM_getCycleByCycleTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Cycle By Cycle Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZCBCFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Gets the Trip Zone One Shot flag status +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the specific One Shot Trip Zone flag status. +//! +//! \return The function returns the bitwise OR of the following flags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST status flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST status flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST status flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST status flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST status flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST status flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST status flag for Digital +//! compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST status flag for Digital +//! compare event B1 +// +//*************************************************************************** +static inline uint16_t +EPWM_getOneShotTripZoneFlagStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the One Shot Trip zone flag status + // + return(HWREGH(base + EPWM_O_TZOSTFLG) & 0xFFU); +} + +//***************************************************************************** +// +//! Set the Trip Zone CBC pulse clear event. +//! +//! \param base is the base address of the EPWM module. +//! \param clearEvent is the CBC trip zone clear event. +//! +//! This function set the event which automatically clears the +//! CBC (Cycle by Cycle) latch. +//! Valid values for clearEvent are: +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO - Clear CBC pulse when counter +//! equals zero +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_PERIOD - Clear CBC pulse when counter +//! equals period +//! - EPWM_TZ_CBC_PULSE_CLR_CNTR_ZERO_PERIOD - Clear CBC pulse when counter +//! equals zero or period +//! +//! \return None. +// +//************************************************************************** +static inline void +EPWM_selectCycleByCycleTripZoneClearEvent(uint32_t base, + EPWM_CycleByCycleTripZoneClearMode clearEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Cycle by Cycle Trip Latch mode + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) = + ((HWREGH(base + EPWM_O_TZCLR) & ~EPWM_TZCLR_CBCPULSE_M) | + ((uint16_t)clearEvent << EPWM_TZCLR_CBCPULSE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Clear Trip Zone flag +//! +//! \param base is the base address of the EPWM module. +//! \param tzFlags is the Trip Zone flags. +//! +//! This function clears the Trip Zone flags +//! Valid values for tzFlags are: +//! - EPWM_TZ_INTERRUPT - Global Trip Zone interrupt flag +//! - EPWM_TZ_FLAG_CBC - Trip Zones Cycle By Cycle flag +//! - EPWM_TZ_FLAG_OST - Trip Zones One Shot flag +//! - EPWM_TZ_FLAG_DCAEVT1 - Digital Compare A Event 1 flag +//! - EPWM_TZ_FLAG_DCAEVT2 - Digital Compare A Event 2 flag +//! - EPWM_TZ_FLAG_DCBEVT1 - Digital Compare B Event 1 flag +//! - EPWM_TZ_FLAG_DCBEVT2 - Digital Compare B Event 2 flag +//! +//! \b note: A bitwise OR of the valid values can be passed as the tzFlags +//! parameter. +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearTripZoneFlag(uint32_t base, uint16_t tzFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzFlags <= 0x80U); + + // + // Clear Trip zone event flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCLR) |= tzFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone Cycle by Cycle flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzCBCFlags is the CBC flag to be cleared. +//! +//! This function clears the specific Cycle by Cycle Trip Zone flag. +//! The following are valid values for tzCBCFlags. +//! - EPWM_TZ_CBC_FLAG_1 - CBC 1 flag +//! - EPWM_TZ_CBC_FLAG_2 - CBC 2 flag +//! - EPWM_TZ_CBC_FLAG_3 - CBC 3 flag +//! - EPWM_TZ_CBC_FLAG_4 - CBC 4 flag +//! - EPWM_TZ_CBC_FLAG_5 - CBC 5 flag +//! - EPWM_TZ_CBC_FLAG_6 - CBC 6 flag +//! - EPWM_TZ_CBC_FLAG_DCAEVT2 - CBC flag Digital compare +//! event A2 +//! - EPWM_TZ_CBC_FLAG_DCBEVT2 - CBC flag Digital compare +//! event B2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearCycleByCycleTripZoneFlag(uint32_t base, uint16_t tzCBCFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzCBCFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZCBCCLR) |= tzCBCFlags; + EDIS; +} + +//***************************************************************************** +// +//! Clear the Trip Zone One Shot flag. +//! +//! \param base is the base address of the EPWM module. +//! \param tzOSTFlags is the OST flags to be cleared. +//! +//! This function clears the specific One Shot (OST) Trip Zone flag. +//! The following are valid values for tzOSTFlags. +//! - EPWM_TZ_OST_FLAG_OST1 - OST flag for OST1 +//! - EPWM_TZ_OST_FLAG_OST2 - OST flag for OST2 +//! - EPWM_TZ_OST_FLAG_OST3 - OST flag for OST3 +//! - EPWM_TZ_OST_FLAG_OST4 - OST flag for OST4 +//! - EPWM_TZ_OST_FLAG_OST5 - OST flag for OST5 +//! - EPWM_TZ_OST_FLAG_OST6 - OST flag for OST6 +//! - EPWM_TZ_OST_FLAG_DCAEVT1 - OST flag for Digital compare event A1 +//! - EPWM_TZ_OST_FLAG_DCBEVT1 - OST flag for Digital compare event B1 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_clearOneShotTripZoneFlag(uint32_t base, uint16_t tzOSTFlags) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(tzOSTFlags < 0x800U); + + // + // Clear the Cycle By Cycle Trip zone flag + // + EALLOW; + HWREGH(base + EPWM_O_TZOSTCLR) |= tzOSTFlags; + EDIS; +} + +//***************************************************************************** +// +//! Force Trip Zone events. +//! +//! \param base is the base address of the EPWM module. +//! \param tzForceEvent is the forced Trip Zone event. +//! +//! This function forces a Trip Zone event. +//! Valid values for tzForceEvent are: +//! - EPWM_TZ_FORCE_EVENT_CBC - Force Trip Zones Cycle By Cycle event +//! - EPWM_TZ_FORCE_EVENT_OST - Force Trip Zones One Shot Event +//! - EPWM_TZ_FORCE_EVENT_DCAEVT1 - Force Digital Compare A Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCAEVT2 - Force Digital Compare A Event 2 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT1 - Force Digital Compare B Event 1 +//! - EPWM_TZ_FORCE_EVENT_DCBEVT2 - Force Digital Compare B Event 2 +//! +//! \return None. +// +//*************************************************************************** +static inline void +EPWM_forceTripZoneEvent(uint32_t base, uint16_t tzForceEvent) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((tzForceEvent & 0xFF81U)== 0U); + + // + // Force a Trip Zone event + // + EALLOW; + HWREGH(base + EPWM_O_TZFRC) |= tzForceEvent; + EDIS; +} + +// +// Event Trigger related APIs +// +//***************************************************************************** +// +//! Enable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! disable ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable ePWM interrupt + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTEN; +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt source. +//! +//! \param base is the base address of the EPWM module. +//! \param interruptSource is the ePWM interrupt source. +//! +//! This function sets the ePWM interrupt source. +//! Valid values for interruptSource are: +//! - EPWM_INT_TBCTR_DISABLED - Time-base counter is disabled +//! - EPWM_INT_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_INT_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_INT_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is incrementing +//! - EPWM_INT_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD (depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptSource(uint32_t base, uint16_t interruptSource) +{ + uint16_t intSource; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(((interruptSource > 0U) && (interruptSource < 9U)) || + (interruptSource == 10U) || (interruptSource == 12U) || + (interruptSource == 14U)); + + if((interruptSource == EPWM_INT_TBCTR_U_CMPC) || + (interruptSource == EPWM_INT_TBCTR_U_CMPD) || + (interruptSource == EPWM_INT_TBCTR_D_CMPC) || + (interruptSource == EPWM_INT_TBCTR_D_CMPD)) + { + // + // Shift the interrupt source by 1 + // + intSource = interruptSource >> 1U; + + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_INTSELCMP; + } + else if((interruptSource == EPWM_INT_TBCTR_U_CMPA) || + (interruptSource == EPWM_INT_TBCTR_U_CMPB) || + (interruptSource == EPWM_INT_TBCTR_D_CMPA) || + (interruptSource == EPWM_INT_TBCTR_D_CMPB)) + { + intSource = interruptSource; + + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_INTSELCMP; + } + else + { + intSource = interruptSource; + } + + // + // Set the interrupt source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_INTSEL_M) | intSource); +} + +//***************************************************************************** +// +//! Sets the ePWM interrupt event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the event count for interrupt scale +//! +//! This function sets the interrupt event count that determines the number of +//! events that have to occur before an interrupt is issued. +//! Maximum value for eventCount is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCount(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Enable advanced feature of interrupt every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_INTPSSEL; + HWREGH(base + EPWM_O_ETINTPS) = + ((HWREGH(base + EPWM_O_ETINTPS) & ~EPWM_ETINTPS_INTPRD2_M) | + eventCount); +} + +//***************************************************************************** +// +//! Return the interrupt status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt status. +//! \b Note This function doesn't return the Trip Zone status. +//! +//! \return Returns true if ePWM interrupt was generated. +//! Returns false if no interrupt was generated +// +//***************************************************************************** +static inline bool +EPWM_getEventTriggerInterruptStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return INT bit of ETFLG register + // + return(((HWREGH(base + EPWM_O_ETFLG) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear interrupt flag. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function clears the ePWM interrupt flag. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearEventTriggerInterruptFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear INT bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= EPWM_ETCLR_INT; +} + +//***************************************************************************** +// +//! Enable Pre-interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the ePWM interrupt counter to be pre-interrupt loaded +//! with a count value. +//! +//! \note This is valid only for advanced/expanded interrupt mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Disable interrupt count load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the ePWM interrupt counter from being loaded with +//! pre-interrupt count value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable interrupt event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= ~EPWM_ETCNTINITCTL_INTINITEN; +} + +//***************************************************************************** +// +//! Force a software pre interrupt event counter load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces the ePWM interrupt counter to be loaded with the +//! contents set by EPWM_setPreInterruptEventCount(). +//! +//! \note make sure the EPWM_enablePreInterruptEventCountLoad() function is +//! is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceInterruptEventCountInit(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= EPWM_ETCNTINITCTL_INTINITFRC; +} + +//***************************************************************************** +// +//! Set interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM interrupt count. eventCount is the value of the +//! pre-interrupt value that is to be loaded. The maximum value of eventCount +//! is 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setInterruptEventCountInitValue(uint32_t base, uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the Pre-interrupt event count + // + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_INTINIT_M) | + (uint16_t)(eventCount & 0xFU)); +} + +//***************************************************************************** +// +//! Get the interrupt count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the ePWM interrupt event count. +//! +//! \return The interrupt event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getInterruptEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the interrupt event count + // + return(((HWREGH(base + EPWM_O_ETINTPS) & EPWM_ETINTPS_INTCNT2_M) >> + EPWM_ETINTPS_INTCNT2_S)); +} + +//***************************************************************************** +// +//! Force ePWM interrupt. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces an ePWM interrupt. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceEventTriggerInterrupt(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set INT bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= EPWM_ETFRC_INT; +} + +// +// ADC SOC configuration related APIs +// +//***************************************************************************** +// +//! Enable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM module to trigger an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Disable ADC SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM module from triggering an ADC SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable an SOC + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCAEN; + } + else + { + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBEN; + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC source. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param socSource is the SOC source. +//! +//! This function sets the ePWM ADC SOC source. +//! Valid values for socSource are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - socSource +//! - EPWM_SOC_DCxEVT1 - Event is based on DCxEVT1 +//! - EPWM_SOC_TBCTR_ZERO - Time-base counter equal to zero +//! - EPWM_SOC_TBCTR_PERIOD - Time-base counter equal to period +//! - EPWM_SOC_TBCTR_ZERO_OR_PERIOD - Time-base counter equal to zero or +//! period +//! - EPWM_SOC_TBCTR_U_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is incrementing +//! - EPWM_SOC_TBCTR_D_CMPx - Where x is A,B,C or D +//! Time-base counter equal to CMPA, CMPB, +//! CMPC or CMPD(depending the value of x) +//! when the timer is decrementing +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerSource(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + EPWM_ADCStartOfConversionSource socSource) +{ + uint16_t source; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + source = (uint16_t)socSource >> 1U; + } + else + { + source = (uint16_t)socSource; + } + + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the SOC source + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCASEL_M) | + (source << EPWM_ETSEL_SOCASEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCASELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCASELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } + else + { + // + // Enable the comparator selection + // + HWREGH(base + EPWM_O_ETSEL) = + ((HWREGH(base + EPWM_O_ETSEL) & ~EPWM_ETSEL_SOCBSEL_M) | + (source << EPWM_ETSEL_SOCBSEL_S)); + + // + // Enable the comparator selection + // + if((socSource == EPWM_SOC_TBCTR_U_CMPA) || + (socSource == EPWM_SOC_TBCTR_U_CMPB) || + (socSource == EPWM_SOC_TBCTR_D_CMPA) || + (socSource == EPWM_SOC_TBCTR_D_CMPB)) + { + // + // Enable events based on comp A or comp B + // + HWREGH(base + EPWM_O_ETSEL) &= ~EPWM_ETSEL_SOCBSELCMP; + } + else if((socSource == EPWM_SOC_TBCTR_U_CMPC) || + (socSource == EPWM_SOC_TBCTR_U_CMPD) || + (socSource == EPWM_SOC_TBCTR_D_CMPC) || + (socSource == EPWM_SOC_TBCTR_D_CMPD)) + { + // + // Enable events based on comp C or comp D + // + HWREGH(base + EPWM_O_ETSEL) |= EPWM_ETSEL_SOCBSELCMP; + } + else + { + // + // No action required for the other socSource options + // + } + } +} + +//***************************************************************************** +// +//! Sets the ePWM SOC event counts. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param preScaleCount is the event count number. +//! +//! This function sets the SOC event count that determines the number of +//! events that have to occur before an SOC is issued. +//! Valid values for the parameters are: +//! - adcSOCType +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! - preScaleCount +//! - [1 - 15] - Generate SOC pulse every preScaleCount +//! up to 15 events. +//! +//! \note A preScaleCount value of 0 disables the prescale. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventPrescale(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t preScaleCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(preScaleCount < 16U); + + // + // Enable advanced feature of SOC every up to 15 events + // + HWREGH(base + EPWM_O_ETPS) |= EPWM_ETPS_SOCPSSEL; + if(adcSOCType == EPWM_SOC_A) + { + // + // Set the count for SOC A + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCAPRD2_M) | + preScaleCount); + } + else + { + // + // Set the count for SOC B + // + HWREGH(base + EPWM_O_ETSOCPS) = + ((HWREGH(base + EPWM_O_ETSOCPS) & ~EPWM_ETSOCPS_SOCBPRD2_M) | + (preScaleCount << EPWM_ETSOCPS_SOCBPRD2_S)); + } +} + +//***************************************************************************** +// +//! Return the SOC event status. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC status. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return Returns true if the selected adcSOCType SOC was generated. +//! Returns false if the selected adcSOCType SOC was not generated. +// +//***************************************************************************** +static inline bool +EPWM_getADCTriggerFlagStatus(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC A/ B status + // + return((((HWREGH(base + EPWM_O_ETFLG) >> + ((uint16_t)adcSOCType + 2U)) & 0x1U) == 0x1U) ? true : false); +} + +//***************************************************************************** +// +//! Clear SOC flag. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function clears the ePWM SOC flag. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_clearADCTriggerFlag(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear SOC A/B bit of ETCLR register + // + HWREGH(base + EPWM_O_ETCLR) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +//***************************************************************************** +// +//! Enable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function enables the ePWM SOC event counter which is set by the +//! EPWM_setADCTriggerEventCountInitValue() function to be loaded before +//! an SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 14U); +} + +//***************************************************************************** +// +//! Disable Pre-SOC event count load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function disables the ePWM SOC event counter from being loaded before +//! an SOC event (only an SOC event causes an increment of the counter value). +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \note This is valid only for advanced/expanded SOC mode +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable SOC event count initializing/loading + // + HWREGH(base + EPWM_O_ETCNTINITCTL) &= + ~(1U << ((uint16_t)adcSOCType + 14U)); +} + +//***************************************************************************** +// +//! Force a software pre SOC event counter load. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type +//! +//! This function forces the ePWM SOC counter to be loaded with the +//! contents set by EPWM_setPreADCStartOfConversionEventCount(). +//! +//! \note make sure the EPWM_enableADCTriggerEventCountInit() +//! function is called before invoking this function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceADCTriggerEventCountInit(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Load the Interrupt Event counter value + // + HWREGH(base + EPWM_O_ETCNTINITCTL) |= 1U << ((uint16_t)adcSOCType + 11U); +} + +//***************************************************************************** +// +//! Set ADC Trigger count values. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! \param eventCount is the ePWM interrupt count value. +//! +//! This function sets the ePWM ADC Trigger count values. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! The eventCount has a maximum value of 15. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setADCTriggerEventCountInitValue(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType, + uint16_t eventCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(eventCount < 16U); + + // + // Set the ADC Trigger event count + // + if(adcSOCType == EPWM_SOC_A) + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCAINIT_M) | + (uint16_t)(eventCount << EPWM_ETCNTINIT_SOCAINIT_S)); + } + else + { + HWREGH(base + EPWM_O_ETCNTINIT) = + ((HWREGH(base + EPWM_O_ETCNTINIT) & ~EPWM_ETCNTINIT_SOCBINIT_M) | + (eventCount << EPWM_ETCNTINIT_SOCBINIT_S)); + } +} + +//***************************************************************************** +// +//! Get the SOC event count. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function returns the ePWM SOC event count. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return The SOC event counts that have occurred. +// +//***************************************************************************** +static inline uint16_t +EPWM_getADCTriggerEventCount(uint32_t base, + EPWM_ADCStartOfConversionType adcSOCType) +{ + uint16_t eventCount; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the SOC event count + // + if(adcSOCType == EPWM_SOC_A) + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCACNT2_S) & 0xFU; + } + else + { + eventCount = (HWREGH(base + EPWM_O_ETSOCPS) >> + EPWM_ETSOCPS_SOCBCNT2_S) & 0xFU; + } + return(eventCount); +} + +//***************************************************************************** +// +//! Force SOC event. +//! +//! \param base is the base address of the EPWM module. +//! \param adcSOCType is the ADC SOC type. +//! +//! This function forces an ePWM SOC event. +//! Valid values for adcSOCType are: +//! - EPWM_SOC_A - SOC A +//! - EPWM_SOC_B - SOC B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_forceADCTrigger(uint32_t base, EPWM_ADCStartOfConversionType adcSOCType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set SOC A/B bit of ETFRC register + // + HWREGH(base + EPWM_O_ETFRC) |= 1U << ((uint16_t)adcSOCType + 2U); +} + +// +// Digital Compare module related APIs +// +//***************************************************************************** +// +//! Set the DC trip input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripSource is the tripSource. +//! \param dcType is the Digital Compare type. +//! +//! This function sets the trip input to the Digital Compare (DC). For a given +//! dcType the function sets the tripSource to be the input to the DC. +//! Valid values for the parameter are: +//! - tripSource +//! - EPWM_DC_TRIP_TRIPINx - Trip x,where x ranges from 1 to 15 excluding 13 +//! - EPWM_DC_TRIP_COMBINATION - selects all the Trip signals whose input +//! is enabled by the following function +//! EPWM_enableDigitalCompareTripCombinationInput() +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_selectDigitalCompareTripInput(uint32_t base, + EPWM_DigitalCompareTripInput tripSource, + EPWM_DigitalCompareType dcType) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + EPWM_O_DCTRIPSEL) = + ((HWREGH(base + EPWM_O_DCTRIPSEL) & ~(0xFU << ((uint16_t)dcType << 2U))) | + ((uint16_t)tripSource << ((uint16_t)dcType << 2U))); + EDIS; +} + +// +// DCFILT +// +//***************************************************************************** +// +//! Enable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Disable DC filter blanking window. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the DC filter blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareBlankingWindow(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC filter blanking window + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKE; + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Window inverse mode. This will +//! invert the blanking window. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Window inverse mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Window inverse mode. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareWindowInverseMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC window inverse mode. + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_BLANKINV; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare filter blanking pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param blankingPulse is Pulse that starts blanking window. +//! +//! This function sets the input pulse that starts the Digital Compare blanking +//! window. +//! Valid values for blankingPulse are: +//! - EPWM_DC_WINDOW_START_TBCTR_PERIOD - Time base counter equals period +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO - Time base counter equals zero +//! - EPWM_DC_WINDOW_START_TBCTR_ZERO_PERIOD - Time base counter equals zero +//! or period. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareBlankingEvent(uint32_t base, + EPWM_DigitalCompareBlankingPulse blankingPulse) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC blanking event + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_PULSESEL_M) | + ((uint16_t)((uint32_t)blankingPulse << EPWM_DCFCTL_PULSESEL_S))); + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter input. +//! +//! \param base is the base address of the EPWM module. +//! \param filterInput is Digital Compare signal source. +//! +//! This function sets the signal input source that will be filtered by the +//! Digital Compare module. +//! Valid values for filterInput are: +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT1 - DC filter signal source is DCAEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCAEVT2 - DC filter signal source is DCAEVT2 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT1 - DC filter signal source is DCBEVT1 +//! - EPWM_DC_WINDOW_SOURCE_DCBEVT2 - DC filter signal source is DCBEVT2 +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareFilterInput(uint32_t base, + EPWM_DigitalCompareFilterInput filterInput) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the signal source that will be filtered + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + ((HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_SRCSEL_M) | + ((uint16_t)filterInput)); + EDIS; +} + +// +// DC Edge Filter +// +//***************************************************************************** +// +//! Enable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the Digital Compare Edge filter to generate event +//! after configured number of edges. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) |= EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare Edge Filter. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the Digital Compare Edge filter. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareEdgeFilter(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable DC Edge Filter + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) &= ~EPWM_DCFCTL_EDGEFILTSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Mode. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeMode is Digital Compare Edge filter mode. +//! +//! This function sets the Digital Compare Event filter mode. Valid values +//! for edgeMode are: +//! - EPWM_DC_EDGEFILT_MODE_RISING - DC edge filter mode is rising edge +//! - EPWM_DC_EDGEFILT_MODE_FALLING - DC edge filter mode is falling edge +//! - EPWM_DC_EDGEFILT_MODE_BOTH - DC edge filter mode is both edges +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterMode(uint32_t base, + EPWM_DigitalCompareEdgeFilterMode edgeMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter mode + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = + (HWREGH(base + EPWM_O_DCFCTL) & ~EPWM_DCFCTL_EDGEMODE_M) | + ((uint16_t)edgeMode << EPWM_DCFCTL_EDGEMODE_S); + EDIS; +} + +//***************************************************************************** +// +//! Set the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! \param edgeCount is Digital Compare event filter count +//! +//! This function sets the Digital Compare Event filter Edge Count to generate +//! events. Valid values for edgeCount can be: +//! - EPWM_DC_EDGEFILT_EDGECNT_0 - No edge is required to generate event +//! - EPWM_DC_EDGEFILT_EDGECNT_1 - 1 edge is required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_2 - 2 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_3 - 3 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_4 - 4 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_5 - 5 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_6 - 6 edges are required for event generation +//! - EPWM_DC_EDGEFILT_EDGECNT_7 - 7 edges are required for event generation +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEdgeFilterEdgeCount(uint32_t base, uint16_t edgeCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set DC Edge filter edge count + // + EALLOW; + HWREGH(base + EPWM_O_DCFCTL) = (HWREGH(base + EPWM_O_DCFCTL) & + ~EPWM_DCFCTL_EDGECOUNT_M) | + (edgeCount << EPWM_DCFCTL_EDGECOUNT_S); + EDIS; +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge Filter Edge Count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the configured Digital Compare Edge filter edge +//! count required to generate events. It can return values from 0-7. +//! +//! \return Returns the configured DigitalCompare Edge filter edge count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return configured DC edge filter edge count + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGECOUNT_M) >> + EPWM_DCFCTL_EDGECOUNT_S); +} + +//***************************************************************************** +// +//! Returns the Digital Compare Edge filter captured edge count status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the count of edges captured by Digital Compare Edge +//! filter. It can return values from 0-7. +//! +//! \return Returns the count of captured edges +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareEdgeFilterEdgeStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return captured edge count by DC Edge filter + // + return((HWREGH(base + EPWM_O_DCFCTL) & EPWM_DCFCTL_EDGESTATUS_M) >> + EPWM_DCFCTL_EDGESTATUS_S); +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window offset +//! +//! \param base is the base address of the EPWM module. +//! \param windowOffsetCount is blanking window offset length. +//! +//! This function sets the offset between window start pulse and blanking +//! window in TBCLK count. +//! The function take a 16bit count value for the offset value. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowOffset(uint32_t base, uint16_t windowOffsetCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window offset in TBCLK counts + // + HWREGH(base + EPWM_O_DCFOFFSET) = windowOffsetCount; +} + +//***************************************************************************** +// +//! Set up the Digital Compare filter window length +//! +//! \param base is the base address of the EPWM module. +//! \param windowLengthCount is blanking window length. +//! +//! This function sets up the Digital Compare filter blanking window length in +//! TBCLK count.The function takes a 16bit count value for the window length. +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareWindowLength(uint32_t base, uint16_t windowLengthCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the blanking window length in TBCLK counts + // + HWREGH(base + EPWM_O_DCFWINDOW) = windowLengthCount; +} + +//***************************************************************************** +// +//! Return DC filter blanking window offset count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window offset count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowOffsetCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Offset count + // + return(HWREGH(base + EPWM_O_DCFOFFSETCNT)); +} + +//***************************************************************************** +// +//! Return DC filter blanking window length count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns DC filter blanking window length count. +//! +//! \return None +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareBlankingWindowLengthCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the Blanking Window Length count + // + return(HWREGH(base + EPWM_O_DCFWINDOWCNT)); +} + +//***************************************************************************** +// +//! Set up the Digital Compare Event source. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param dcEventSource is the - Digital Compare Event source. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - dcEventSource +//! - EPWM_DC_EVENT_SOURCE_FILT_SIGNAL - signal source is filtered +//! \note The signal source for this option is DCxEVTy, where the +//! value of x is dependent on dcModule and the value of y is +//! dependent on dcEvent. Possible signal sources are DCAEVT1, +//! DCBEVT1, DCAEVT2 or DCBEVT2 depending on the value of both +//! dcModule and dcEvent. +//! - EPWM_DC_EVENT_SOURCE_ORIG_SIGNAL - signal source is unfiltered +//! The signal source for this option is DCxEVTy. +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSource(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareEventSource dcEventSource) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event 1 source source + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SRCSEL) | + (uint16_t)dcEventSource); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2SRCSEL) | + ((uint16_t)dcEventSource << 8U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Set up the Digital Compare input sync mode. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! \param dcEvent is the Digital Compare Event number. +//! \param syncMode is the Digital Compare Event sync mode. +//! +//! This function sets up the Digital Compare module Event sources. +//! The following are valid values for the parameters. +//! - dcModule +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! - dcEvent +//! - EPWM_DC_EVENT_1 - Digital Compare Event number 1 +//! - EPWM_DC_EVENT_2 - Digital Compare Event number 2 +//! - syncMode +//! - EPWM_DC_EVENT_INPUT_SYNCED - DC input signal is synced with +//! TBCLK +//! - EPWM_DC_EVENT_INPUT_NOT SYNCED - DC input signal is not synced with +//! TBCLK +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareEventSyncMode(uint32_t base, + EPWM_DigitalCompareModule dcModule, + EPWM_DigitalCompareEvent dcEvent, + EPWM_DigitalCompareSyncMode syncMode) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Set the DC event sync mode + // + EALLOW; + if(dcEvent == EPWM_DC_EVENT_1) + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1FRCSYNCSEL) | + ((uint16_t)syncMode << 1U)); + } + else + { + HWREGH(base + registerOffset) = + ((HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT2FRCSYNCSEL) | + ((uint16_t)syncMode << 9U)); + } + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating Start of +//! Conversion. +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareADCTrigger(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare start of conversion generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SOCE); + EDIS; +} + +//***************************************************************************** +// +//! Enable Digital Compare to generate sync out pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function enables the Digital Compare Event 1 to generate sync out +//! pulse +//! The following are valid values for the \e dcModule parameter. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Enable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +//***************************************************************************** +// +//! Disable Digital Compare from generating Start of Conversion. +//! +//! \param base is the base address of the EPWM module. +//! \param dcModule is the Digital Compare module. +//! +//! This function disables the Digital Compare Event 1 from generating synch +//! out pulse. +//! The following are valid values for the \e dcModule parameters. +//! - EPWM_DC_MODULE_A - Digital Compare Module A +//! - EPWM_DC_MODULE_B - Digital Compare Module B +//! +//! \return None +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareSyncEvent(uint32_t base, + EPWM_DigitalCompareModule dcModule) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + registerOffset = EPWM_O_DCACTL + (uint32_t)dcModule; + + // + // Disable Digital Compare sync out pulse generation + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~EPWM_DCACTL_EVT1SYNCE); + EDIS; +} + +// +// DC capture mode +// +//***************************************************************************** +// +//! Enables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disables the Time Base Counter Capture controller. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disable the time Base Counter Capture. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareCounterCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Disable Time base counter capture + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPE; + EDIS; +} + +//***************************************************************************** +// +//! Set the Time Base Counter Capture mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableShadowMode is the shadow read mode flag. +//! +//! This function sets the mode the Time Base Counter value is read from. If +//! enableShadowMode is true, CPU reads of the DCCAP register will return the +//! shadow register contents.If enableShadowMode is false, CPU reads of the +//! DCCAP register will return the active register contents. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setDigitalCompareCounterShadowMode(uint32_t base, bool enableShadowMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(enableShadowMode) + { + // + // Enable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_SHDWMODE; + } + else + { + // + // Disable DC counter shadow mode + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_SHDWMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Capture event status. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC capture event status. +//! +//! \return Returns true if a DC capture event has occurs. +//! Returns false if no DC Capture event has occurred. +//! +//! \return None. +// +//***************************************************************************** +static inline bool +EPWM_getDigitalCompareCaptureStatus(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC compare status + // + return((HWREGH(base + EPWM_O_DCCAPCTL) & EPWM_DCCAPCTL_CAPSTS) == + EPWM_DCCAPCTL_CAPSTS); +} + +//***************************************************************************** +// +//! Clears DC capture latched status flag +//! +//! \param base is the base address of the EPWM module. +//! This function is used to clear the CAPSTS (set) condition. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_clearDigitalCompareCaptureStatusFlag(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear digital compare capture status flag + // + EALLOW; + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPCLR; + EDIS; +} + +//***************************************************************************** +// +//! Configures DC capture operating mode +//! +//! \param base is the base address of the EPWM module. +//! \param disableClearMode is the clear mode bit. +//! +//! This function is used to configure the DC capture operating mode. If +//! \e disableClearMode is false, the TBCNT value is captured in active register +//! on occurance of DCEVTFILT event. The trip events are ignored until next +//! PRD or ZRO event re-triggers the capture mechanism. +//! If \e disableClearMode is true, the TBCNT value is captured, CAPSTS flag is +//! set and further trips are ignored until CAPSTS bit is cleared. +//! +//! \return None. +//***************************************************************************** +static inline void +EPWM_configureDigitalCompareCounterCaptureMode(uint32_t base, + bool disableClearMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + EALLOW; + if(disableClearMode) + { + // + // Disable DC counter auto-clear on PULSESEL event + // + HWREGH(base + EPWM_O_DCCAPCTL) |= EPWM_DCCAPCTL_CAPMODE; + } + else + { + // + // Enable DC counter clear on PULSESEL events + // + HWREGH(base + EPWM_O_DCCAPCTL) &= ~EPWM_DCCAPCTL_CAPMODE; + } + EDIS; +} + +//***************************************************************************** +// +//! Return the DC Time Base Counter capture value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the DC Time Base Counter capture value. The value +//! read is determined by the mode as set in the +//! EPWM_setTimeBaseCounterReadMode() function. +//! +//! \return Returns the DC Time Base Counter Capture count value. +// +//***************************************************************************** +static inline uint16_t +EPWM_getDigitalCompareCaptureCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the DC Time Base Counter Capture count value + // + return(HWREGH(base + EPWM_O_DCCAP)); +} + +//***************************************************************************** +// +//! Enable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function enables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) | tripInput); + + // + // Enable the combination input + // + HWREGH(base + EPWM_O_DCTRIPSEL) = + (HWREGH(base + EPWM_O_DCTRIPSEL) | (0xFU << ((uint16_t)dcType << 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Disable DC TRIP combinational input. +//! +//! \param base is the base address of the EPWM module. +//! \param tripInput is the Trip number. +//! \param dcType is the Digital Compare module. +//! +//! This function disables the specified Trip input. +//! Valid values for the parameters are: +//! - tripInput +//! - EPWM_DC_COMBINATIONAL_TRIPINx, where x is 1,2,...12,14,15 +//! - dcType +//! - EPWM_DC_TYPE_DCAH - Digital Compare A High +//! - EPWM_DC_TYPE_DCAL - Digital Compare A Low +//! - EPWM_DC_TYPE_DCBH - Digital Compare B High +//! - EPWM_DC_TYPE_DCBL - Digital Compare B Low +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableDigitalCompareTripCombinationInput(uint32_t base, + uint16_t tripInput, + EPWM_DigitalCompareType dcType) +{ + uint32_t registerOffset; + + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Get the DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL register + // offset with respect to DCAHTRIPSEL + // + registerOffset = EPWM_O_DCAHTRIPSEL + (uint32_t)dcType; + + // + // Set the DC trip input + // + EALLOW; + HWREGH(base + registerOffset) = + (HWREGH(base + registerOffset) & ~tripInput); + EDIS; +} + +// +// Valley switching +// +//***************************************************************************** +// +//! Enable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley Capture mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear VCAPE bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_VCAPE; + EDIS; +} + +//***************************************************************************** +// +//! Start valley capture mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function starts Valley Capture sequence. +//! +//! \b Make sure you invoke EPWM_setValleyTriggerSource with the trigger +//! variable set to EPWM_VALLEY_TRIGGER_EVENT_SOFTWARE before calling this +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_startValleyCapture(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set VCAPSTART bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_VCAPSTART; + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger. +//! +//! \param base is the base address of the EPWM module. +//! \param trigger is the Valley counter trigger. +//! +//! This function sets the trigger value that initiates Valley Capture sequence +//! +//! \b Set the number of Trigger source events for starting and stopping the +//! valley capture using EPWM_setValleyTriggerEdgeCounts(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerSource(uint32_t base, EPWM_ValleyTriggerSource trigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to TRIGSEL bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_TRIGSEL_M) | + ((uint16_t)trigger << 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Set valley capture trigger source count. +//! +//! \param base is the base address of the EPWM module. +//! \param startCount +//! \param stopCount +//! +//! This function sets the number of trigger events required to start and stop +//! the valley capture count. +//! Maximum values for both startCount and stopCount is 15 corresponding to the +//! 15th edge of the trigger event. +//! +//! \b Note: +//! A startCount value of 0 prevents starting the valley counter. +//! A stopCount value of 0 prevents the valley counter from stopping. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyTriggerEdgeCounts(uint32_t base, uint16_t startCount, + uint16_t stopCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((startCount < 16U) && (stopCount < 16U)); + + // + // Write to STARTEDGE and STOPEDGE bits + // + EALLOW; + HWREGH(base + EPWM_O_VCNTCFG) = + ((HWREGH(base + EPWM_O_VCNTCFG) & + ~(EPWM_VCNTCFG_STARTEDGE_M | EPWM_VCNTCFG_STOPEDGE_M)) | + (startCount | (stopCount << 8U))); + EDIS; +} + +//***************************************************************************** +// +//! Enable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) |= EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Disable valley switching delay. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Valley switching delay. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Clear EDGEFILTDLYSEL bit + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) &= ~EPWM_VCAPCTL_EDGEFILTDLYSEL; + EDIS; +} + +//***************************************************************************** +// +//! Set Valley delay values. +//! +//! \param base is the base address of the EPWM module. +//! \param delayOffsetValue is the software defined delay offset value. +//! +//! This function sets the Valley delay value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleySWDelayValue(uint32_t base, uint16_t delayOffsetValue) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to SWVDELVAL bits + // + HWREGH(base + EPWM_O_SWVDELVAL) = delayOffsetValue; +} + +//***************************************************************************** +// +//! Set Valley delay mode. +//! +//! \param base is the base address of the EPWM module. +//! \param delayMode is the Valley delay mode. +//! +//! This function sets the Valley delay mode values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setValleyDelayDivider(uint32_t base, EPWM_ValleyDelayMode delayMode) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Write to VDELAYDIV bits + // + EALLOW; + HWREGH(base + EPWM_O_VCAPCTL) = + ((HWREGH(base + EPWM_O_VCAPCTL) & ~EPWM_VCAPCTL_VDELAYDIV_M) | + ((uint16_t)delayMode << 7U)); + EDIS; +} + +//***************************************************************************** +// +//! Get the valley edge status bit. +//! +//! \param base is the base address of the EPWM module. +//! \param edge is the start or stop edge. +//! +//! This function returns the status of the start or stop valley status +//! depending on the value of edge. +//! If a start or stop edge has occurred, the function returns true, if not it +//! returns false. +//! +//! \return Returns true if the specified edge has occurred, +//! Returns false if the specified edge has not occurred. +// +//***************************************************************************** +static inline bool +EPWM_getValleyEdgeStatus(uint32_t base, EPWM_ValleyCounterEdge edge) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + if(edge == EPWM_VALLEY_COUNT_START_EDGE) + { + // + // Returns STARTEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STARTEDGESTS) == + EPWM_VCNTCFG_STARTEDGESTS ) ? true : false); + } + else + { + // + // Returns STOPEDGESTS status + // + return(((HWREGH(base + EPWM_O_VCNTCFG) & EPWM_VCNTCFG_STOPEDGESTS) == + EPWM_VCNTCFG_STOPEDGESTS) ? true : false); + } +} + +//***************************************************************************** +// +//! Get the Valley Counter value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the valley time base count value which is captured +//! upon occurrence of the stop edge condition selected by +//! EPWM_setValleyTriggerSource() and by the stopCount variable of the +//! EPWM_setValleyTriggerEdgeCounts() function. +//! +//! \return Returns the valley base time count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read VCNTVAL register + // + return(HWREGH(base + EPWM_O_VCNTVAL)); +} + +//***************************************************************************** +// +//! Get the Valley delay value. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the hardware valley delay count. +//! +//! \return Returns the valley delay count. +// +//***************************************************************************** +static inline uint16_t +EPWM_getValleyHWDelay(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Read HWVDELVAL register + // + return(HWREGH(base + EPWM_O_HWVDELVAL)); +} + +//***************************************************************************** +// +//! Enable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables Global shadow to active load mode of registers. +//! The trigger source for loading shadow to active is determined by +//! EPWM_setGlobalLoadTrigger() function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Disable Global shadow load mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables Global shadow to active load mode of registers. +//! Loading shadow to active is determined individually. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Shadow to active load is controlled individually + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_GLD; + EDIS; +} + +//***************************************************************************** +// +//! Set the Global shadow load pulse. +//! +//! \param base is the base address of the EPWM module. +//! \param loadTrigger is the pulse that causes global shadow load. +//! +//! This function sets the pulse that causes Global shadow to active load. +//! Valid values for the loadTrigger parameter are: +//! +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO - load when counter is equal +//! to zero +//! - EPWM_GL_LOAD_PULSE_CNTR_PERIOD - load when counter is equal +//! to period +//! - EPWM_GL_LOAD_PULSE_CNTR_ZERO_PERIOD - load when counter is equal +//! to zero or period +//! - EPWM_GL_LOAD_PULSE_SYNC - load on sync event +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_ZERO - load on sync event or when +//! counter is equal to zero +//! - EPWM_GL_LOAD_PULSE_SYNC_OR_CNTR_PERIOD - load on sync event or when +//! counter is equal to period +//! - EPWM_GL_LOAD_PULSE_SYNC_CNTR_ZERO_PERIOD - load on sync event or when +//! counter is equal to period +//! or zero +//! - EPWM_GL_LOAD_PULSE_GLOBAL_FORCE - load on global force +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadTrigger(uint32_t base, EPWM_GlobalLoadTrigger loadTrigger) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set the Global shadow to active load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDMODE_M) | + ((uint16_t)loadTrigger << EPWM_GLDCTL_GLDMODE_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! \param prescalePulseCount is the pulse event counts. +//! +//! This function sets the number of Global Load pulse events that have to +//! occurred before a global load pulse is issued. Valid values for +//! prescaleCount range from 0 to 7. 0 being no event (disables counter), and 7 +//! representing 7 events. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadEventPrescale(uint32_t base, uint16_t prescalePulseCount) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT(prescalePulseCount < 8U); + + // + // Set the number of counts that have to occur before + // a load strobe is issued + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) = + ((HWREGH(base + EPWM_O_GLDCTL) & ~EPWM_GLDCTL_GLDPRD_M) | + (prescalePulseCount << EPWM_GLDCTL_GLDPRD_S)); + EDIS; +} + +//***************************************************************************** +// +//! Return the number of Global load pulse event counts +//! +//! \param base is the base address of the EPWM module. +//! +//! This function returns the number of Global Load pulse events that have +//! occurred. These pulse events are set by the EPWM_setGlobalLoadTrigger() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +EPWM_getGlobalLoadEventCount(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Return the number of events that have occurred + // + return((HWREGH(base + EPWM_O_GLDCTL) >> EPWM_GLDCTL_GLDCNT_S) & 0x7U); +} + +//***************************************************************************** +// +//! Enable continuous global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables global continuous shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) &= ~EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Enable One shot global shadow to active load. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables a one time global shadow to active load. Register +//! load happens every time the event set by the +//! EPWM_setGlobalLoadTrigger() occurs. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadOneShotMode(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Enable global continuous shadow to active load + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL) |= EPWM_GLDCTL_OSHTMODE; + EDIS; +} + +//***************************************************************************** +// +//! Set One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function sets a one time global shadow to active load pulse. The pulse +//! propagates to generate a load signal if any of the events set by +//! EPWM_setGlobalLoadTrigger() occur. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_setGlobalLoadOneShotLatch(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Set a one shot Global shadow load pulse. + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_OSHTLD; + EDIS; +} + +//***************************************************************************** +// +//! Force a software One shot global shadow to active load pulse. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function forces a software a one time global shadow to active load +//! pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_forceGlobalLoadOneShotEvent(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + + // + // Force a Software Global shadow load pulse + // + EALLOW; + HWREGH(base + EPWM_O_GLDCTL2) |= EPWM_GLDCTL2_GFRCLD; + EDIS; +} + +//***************************************************************************** +// +//! Enable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function enables the register specified by loadRegister to be globally +//! loaded. +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_enableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded globally + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) |= loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Disable a register to be loaded Globally. +//! +//! \param base is the base address of the EPWM module. +//! \param loadRegister is the register. +//! +//! This function disables the register specified by loadRegister from being +//! loaded globally. The shadow to active load happens as specified by the +//! register control +//! Valid values for loadRegister are: +//! - EPWM_GL_REGISTER_TBPRD_TBPRDHR - Register TBPRD:TBPRDHR +//! - EPWM_GL_REGISTER_CMPA_CMPAHR - Register CMPA:CMPAHR +//! - EPWM_GL_REGISTER_CMPB_CMPBHR - Register CMPB:CMPBHR +//! - EPWM_GL_REGISTER_CMPC - Register CMPC +//! - EPWM_GL_REGISTER_CMPD - Register CMPD +//! - EPWM_GL_REGISTER_DBRED_DBREDHR - Register DBRED:DBREDHR +//! - EPWM_GL_REGISTER_DBFED_DBFEDHR - Register DBFED:DBFEDHR +//! - EPWM_GL_REGISTER_DBCTL - Register DBCTL +//! - EPWM_GL_REGISTER_AQCTLA_AQCTLA2 - Register AQCTLA/A2 +//! - EPWM_GL_REGISTER_AQCTLB_AQCTLB2 - Register AQCTLB/B2 +//! - EPWM_GL_REGISTER_AQCSFRC - Register AQCSFRC +//! +//! \return None. +// +//***************************************************************************** +static inline void +EPWM_disableGlobalLoadRegisters(uint32_t base, uint16_t loadRegister) +{ + // + // Check the arguments + // + ASSERT(EPWM_isBaseValid(base)); + ASSERT((loadRegister > 0x0000U) && (loadRegister < 0x0800U)); + + // + // The register specified by loadRegister is loaded by individual + // register configuration setting + // + EALLOW; + HWREGH(base + EPWM_O_GLDCFG) &= ~loadRegister; + EDIS; +} + +//***************************************************************************** +// +//! Set emulation mode +//! +//! \param base is the base address of the EPWM module. +//! \param emulationMode is the emulation mode. +//! +//! This function sets the emulation behaviours of the time base counter. Valid +//! values for emulationMode are: +//! - EPWM_EMULATION_STOP_AFTER_NEXT_TB - Stop after next Time Base counter +//! increment or decrement. +//! - EPWM_EMULATION_STOP_AFTER_FULL_CYCLE - Stop when counter completes whole +//! cycle. +//! - EPWM_EMULATION_FREE_RUN - Free run. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_setEmulationMode(uint32_t base, EPWM_EmulationMode emulationMode); + +//***************************************************************************** +// +//! Configures ePWM signal with desired frequency & duty +//! +//! \param base is the base address of the EPWM module. +//! \param signalParams is the desired signal parameters. +//! +//! This function configures the ePWM module to generate a signal with +//! desired frequency & duty. +//! +//! \return None. +// +//***************************************************************************** +extern void +EPWM_configureSignal(uint32_t base, const EPWM_SignalParams *signalParams); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EPWM_H diff --git a/gpio_driverlib_cpu1/device/driverlib/eqep.c b/gpio_driverlib_cpu1/device/driverlib/eqep.c new file mode 100644 index 0000000..64caf47 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/eqep.c @@ -0,0 +1,149 @@ +//########################################################################### +// +// FILE: eqep.c +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "eqep.h" + +//***************************************************************************** +// +// EQEP_setCompareConfig +// +//***************************************************************************** +void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles) +{ + uint16_t regValue; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the compare match value + // + HWREG(base + EQEP_O_QPOSCMP) = compareValue; + + // + // Set the shadow register settings and pulse width. + // + regValue = (config & (uint16_t)(EQEP_QPOSCTL_PCSHDW | + EQEP_QPOSCTL_PCLOAD)) | (cycles - 1U); + + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(EQEP_QPOSCTL_PCSPW_M | + EQEP_QPOSCTL_PCLOAD | + EQEP_QPOSCTL_PCSHDW)) | regValue; + + // + // Set position compare sync-output mode. + // + regValue = config & (uint16_t)(EQEP_QDECCTL_SOEN | EQEP_QDECCTL_SPSEL); + + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SOEN | + EQEP_QDECCTL_SPSEL)) | regValue; +} + +//***************************************************************************** +// +// EQEP_setInputPolarity +// +//***************************************************************************** +void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Configure QEPA signal + // + if(invertQEPA) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QAP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QAP; + } + + // + // Configure QEPB signal + // + if(invertQEPB) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QBP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QBP; + } + + // + // Configure index signal + // + if(invertIndex) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QIP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QIP; + } + + // + // Configure strobe signal + // + if(invertStrobe) + { + HWREGH(base + EQEP_O_QDECCTL) |= EQEP_QDECCTL_QSP; + } + else + { + HWREGH(base + EQEP_O_QDECCTL) &= ~EQEP_QDECCTL_QSP; + } +} diff --git a/gpio_driverlib_cpu1/device/driverlib/eqep.h b/gpio_driverlib_cpu1/device/driverlib/eqep.h new file mode 100644 index 0000000..4f1eaa2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/eqep.h @@ -0,0 +1,1691 @@ +//########################################################################### +// +// FILE: eqep.h +// +// TITLE: C28x eQEP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef EQEP_H +#define EQEP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup eqep_api eQEP +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_eqep.h" +#include "inc/hw_types.h" +#include "debug.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to EQEP_setDecoderConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Operation Mode +// +#define EQEP_CONFIG_QUADRATURE 0x0000U //!< Quadrature-clock mode +#define EQEP_CONFIG_CLOCK_DIR 0x4000U //!< Direction-count mode +#define EQEP_CONFIG_UP_COUNT 0x8000U //!< Up-count mode, QDIR = 1 +#define EQEP_CONFIG_DOWN_COUNT 0xC000U //!< Down-count mode, QDIR = 0 + +// +// Resolution +// +#define EQEP_CONFIG_2X_RESOLUTION 0x0000U //!< Count rising and falling edge +#define EQEP_CONFIG_1X_RESOLUTION 0x0800U //!< Count rising edge only + +// +// Swap QEPA and QEPB +// +#define EQEP_CONFIG_NO_SWAP 0x0000U //!< Do not swap QEPA and QEPB +#define EQEP_CONFIG_SWAP 0x0400U //!< Swap QEPA and QEPB + +// +// Index pulse gating option +// +#define EQEP_CONFIG_IGATE_DISABLE 0x0000U //!< Disable gating of Index pulse +#define EQEP_CONFIG_IGATE_ENABLE 0x0200U //!< Gate the index pin with strobe + +//***************************************************************************** + +// +// Values that can be passed to EQEP_setCompareConfig() as the config +// parameter. +// +//***************************************************************************** + +// +// Sync pulse pin +// +#define EQEP_COMPARE_NO_SYNC_OUT 0x0000U //!< Disable sync output +#define EQEP_COMPARE_IDX_SYNC_OUT 0x2000U //!< Sync output on index pin +#define EQEP_COMPARE_STROBE_SYNC_OUT 0x3000U //!< Sync output on strobe pin + +// +// Shadow register use +// +#define EQEP_COMPARE_NO_SHADOW 0x0000U //!< Disable shadow of QPOSCMP +#define EQEP_COMPARE_LOAD_ON_ZERO 0x8000U //!< Load on QPOSCNT = 0 +#define EQEP_COMPARE_LOAD_ON_MATCH 0xC000U //!< Load on QPOSCNT = QPOSCMP + +//***************************************************************************** +// +// Values that can be passed to EQEP_enableInterrupt(), +// EQEP_disableInterrupt(), and EQEP_clearInterruptStatus() as the +// intFlags parameter and returned by EQEP_clearInterruptStatus(). +// +//***************************************************************************** +#define EQEP_INT_GLOBAL 0x0001U //!< Global interrupt flag +#define EQEP_INT_POS_CNT_ERROR 0x0002U //!< Position counter error +#define EQEP_INT_PHASE_ERROR 0x0004U //!< Quadrature phase error +#define EQEP_INT_DIR_CHANGE 0x0008U //!< Quadrature direction change +#define EQEP_INT_WATCHDOG 0x0010U //!< Watchdog time-out +#define EQEP_INT_UNDERFLOW 0x0020U //!< Position counter underflow +#define EQEP_INT_OVERFLOW 0x0040U //!< Position counter overflow +#define EQEP_INT_POS_COMP_READY 0x0080U //!< Position-compare ready +#define EQEP_INT_POS_COMP_MATCH 0x0100U //!< Position-compare match +#define EQEP_INT_STROBE_EVNT_LATCH 0x0200U //!< Strobe event latch +#define EQEP_INT_INDEX_EVNT_LATCH 0x0400U //!< Index event latch +#define EQEP_INT_UNIT_TIME_OUT 0x0800U //!< Unit time-out + +//***************************************************************************** +// +// Values that can be returned by EQEP_getStatus(). +// +//***************************************************************************** +//! Unit position event detected +#define EQEP_STS_UNIT_POS_EVNT 0x0080U +//! Direction was clockwise on first index event +#define EQEP_STS_DIR_ON_1ST_IDX 0x0040U +//! Direction is CW (forward) +#define EQEP_STS_DIR_FLAG 0x0020U +//! Direction was CW on index +#define EQEP_STS_DIR_LATCH 0x0010U +//! Capture timer overflow +#define EQEP_STS_CAP_OVRFLW_ERROR 0x0008U +//! Direction changed between position capture events +#define EQEP_STS_CAP_DIR_ERROR 0x0004U +//! First index pulse occurred +#define EQEP_STS_1ST_IDX_FLAG 0x0002U +//! Position counter error +#define EQEP_STS_POS_CNT_ERROR 0x0001U + +//***************************************************************************** +// +// Values that can be passed to EQEP_setLatchMode() as the latchMode parameter. +// +//***************************************************************************** + +// +// Position counter latch event +// +#define EQEP_LATCH_CNT_READ_BY_CPU 0x0000U //!< On position counter read +#define EQEP_LATCH_UNIT_TIME_OUT 0x0004U //!< On unit time-out event + +// +// Strobe position counter latch event +// +//! On rising edge of strobe +#define EQEP_LATCH_RISING_STROBE 0x0000U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_LATCH_EDGE_DIR_STROBE 0x0040U + +// +// Index position counter latch event +// +#define EQEP_LATCH_RISING_INDEX 0x0010U //!< On rising edge of index +#define EQEP_LATCH_FALLING_INDEX 0x0020U //!< On falling edge of index + +#define EQEP_LATCH_SW_INDEX_MARKER 0x0030U //!< On software index marker + +//***************************************************************************** +// +// Values that can be passed to EQEP_setPositionInitMode() as the initMode +// parameter. +// +//***************************************************************************** +#define EQEP_INIT_DO_NOTHING 0x0000U //!< Action is disabled + +// +// Strobe events +// +//! On rising edge of strobe +#define EQEP_INIT_RISING_STROBE 0x0800U +//! On rising edge when clockwise, on falling when counter clockwise +#define EQEP_INIT_EDGE_DIR_STROBE 0x0C00U + +// +// Index events +// +#define EQEP_INIT_RISING_INDEX 0x0200U //!< On rising edge of index +#define EQEP_INIT_FALLING_INDEX 0x0300U //!< On falling edge of index +#endif + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setPositionCounterConfig() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Reset position on index pulse + EQEP_POSITION_RESET_IDX = 0x0000, + //! Reset position on maximum position + EQEP_POSITION_RESET_MAX_POS = 0x1000, + //! Reset position on the first index pulse + EQEP_POSITION_RESET_1ST_IDX = 0x2000, + //! Reset position on a unit time event + EQEP_POSITION_RESET_UNIT_TIME_OUT = 0x3000 +} EQEP_PositionResetMode; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e capPrescale +//! parameter. CAPCLK is the capture timer clock frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_CAPTURE_CLK_DIV_1 = 0x00, //!< CAPCLK = SYSCLKOUT/1 + EQEP_CAPTURE_CLK_DIV_2 = 0x10, //!< CAPCLK = SYSCLKOUT/2 + EQEP_CAPTURE_CLK_DIV_4 = 0x20, //!< CAPCLK = SYSCLKOUT/4 + EQEP_CAPTURE_CLK_DIV_8 = 0x30, //!< CAPCLK = SYSCLKOUT/8 + EQEP_CAPTURE_CLK_DIV_16 = 0x40, //!< CAPCLK = SYSCLKOUT/16 + EQEP_CAPTURE_CLK_DIV_32 = 0x50, //!< CAPCLK = SYSCLKOUT/32 + EQEP_CAPTURE_CLK_DIV_64 = 0x60, //!< CAPCLK = SYSCLKOUT/64 + EQEP_CAPTURE_CLK_DIV_128 = 0x70 //!< CAPCLK = SYSCLKOUT/128 +} EQEP_CAPCLKPrescale; + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setCaptureConfig() as the \e evntPrescale +//! parameter. UPEVNT is the unit position event frequency. +// +//***************************************************************************** +typedef enum +{ + EQEP_UNIT_POS_EVNT_DIV_1, //!< UPEVNT = QCLK/1 + EQEP_UNIT_POS_EVNT_DIV_2, //!< UPEVNT = QCLK/2 + EQEP_UNIT_POS_EVNT_DIV_4, //!< UPEVNT = QCLK/4 + EQEP_UNIT_POS_EVNT_DIV_8, //!< UPEVNT = QCLK/8 + EQEP_UNIT_POS_EVNT_DIV_16, //!< UPEVNT = QCLK/16 + EQEP_UNIT_POS_EVNT_DIV_32, //!< UPEVNT = QCLK/32 + EQEP_UNIT_POS_EVNT_DIV_64, //!< UPEVNT = QCLK/64 + EQEP_UNIT_POS_EVNT_DIV_128, //!< UPEVNT = QCLK/128 + EQEP_UNIT_POS_EVNT_DIV_256, //!< UPEVNT = QCLK/256 + EQEP_UNIT_POS_EVNT_DIV_512, //!< UPEVNT = QCLK/512 + EQEP_UNIT_POS_EVNT_DIV_1024, //!< UPEVNT = QCLK/1024 + EQEP_UNIT_POS_EVNT_DIV_2048 //!< UPEVNT = QCLK/2048 +} EQEP_UPEVNTPrescale; + + +//***************************************************************************** +// +//! Values that can be passed to EQEP_setEmulationMode() as the \e emuMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + EQEP_EMULATIONMODE_STOPIMMEDIATELY, //!< Counters stop immediately + EQEP_EMULATIONMODE_STOPATROLLOVER, //!< Counters stop at period rollover + EQEP_EMULATIONMODE_RUNFREE //!< Counter unaffected by suspend +}EQEP_EmulationMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an eQEP base address. +//! +//! \param base specifies the eQEP module base address. +//! +//! This function determines if a eQEP module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +EQEP_isBaseValid(uint32_t base) +{ + return( + (base == EQEP1_BASE) || + (base == EQEP2_BASE) || + (base == EQEP3_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the enhanced quadrature encoder pulse +//! (eQEP) module. The module must be configured before it is enabled. +//! +//! \sa EQEP_setConfig() +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_QPEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module. +//! +//! \param base is the base address of the enhanced quadrature encoder pulse +//! (eQEP) module +//! +//! This function disables operation of the eQEP module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the eQEP module. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_QPEN); +} + +//***************************************************************************** +// +//! Configures eQEP module's quadrature decoder unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module decoder unit. +//! +//! This function configures the operation of the eQEP module's quadrature +//! decoder unit. The \e config parameter provides the configuration +//! of the decoder and is the logical OR of several values: +//! +//! - \b EQEP_CONFIG_2X_RESOLUTION or \b EQEP_CONFIG_1X_RESOLUTION specify +//! if both rising and falling edges should be counted or just rising edges. +//! - \b EQEP_CONFIG_QUADRATURE, \b EQEP_CONFIG_CLOCK_DIR, +//! \b EQEP_CONFIG_UP_COUNT, or \b EQEP_CONFIG_DOWN_COUNT specify if +//! quadrature signals are being provided on QEPA and QEPB, if a direction +//! signal and a clock are being provided, or if the direction should be +//! hard-wired for a single direction with QEPA used for input. +//! - \b EQEP_CONFIG_NO_SWAP or \b EQEP_CONFIG_SWAP to specify if the +//! signals provided on QEPA and QEPB should be swapped before being +//! processed. +//! - \b EQEP_CONFIG_IGATE_DISABLE or \b EQEP_CONFIG_IGATE_ENABLE to specify +//! if the gating of the index pulse should be enabled or disabled +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setDecoderConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the new decoder configuration to the hardware. + // + HWREGH(base + EQEP_O_QDECCTL) = (HWREGH(base + EQEP_O_QDECCTL) & + ~(EQEP_QDECCTL_SWAP | + EQEP_QDECCTL_XCR | + EQEP_QDECCTL_QSRC_M | + EQEP_QDECCTL_IGATE)) | config; +} + +//***************************************************************************** +// +//! Configures eQEP module position counter unit. +//! +//! \param base is the base address of the eQEP module. +//! \param mode is the configuration for the eQEP module position counter. +//! \param maxPosition specifies the maximum position value. +//! +//! This function configures the operation of the eQEP module position +//! counter. The \e mode parameter determines the event on which the position +//! counter gets reset. It should be passed one of the following values: +//! \b EQEP_POSITION_RESET_IDX, \b EQEP_POSITION_RESET_MAX_POS, +//! \b EQEP_POSITION_RESET_1ST_IDX, or \b EQEP_POSITION_RESET_UNIT_TIME_OUT. +//! +//! \e maxPosition is the maximum value of the position counter and is +//! the value used to reset the position capture when moving in the reverse +//! (negative) direction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionCounterConfig(uint32_t base, EQEP_PositionResetMode mode, + uint32_t maxPosition) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the position counter reset configuration to the hardware. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~EQEP_QEPCTL_PCRM_M) | (uint16_t)mode; + + // + // Set the maximum position. + // + HWREG(base + EQEP_O_QPOSMAX) = maxPosition; +} + +//***************************************************************************** +// +//! Gets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current position of the encoder. Depending upon +//! the configuration of the encoder, and the incident of an index pulse, this +//! value may or may not contain the expected data (that is, if in reset on +//! index mode, if an index pulse has not been encountered, the position +//! counter is not yet aligned with the index pulse). +//! +//! \return The current position of the encoder. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPosition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSCNT)); +} + +//***************************************************************************** +// +//! Sets the current encoder position. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the new position for the encoder. +//! +//! This function sets the current position of the encoder; the encoder +//! position is then measured relative to this value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the position counter. + // + HWREG(base + EQEP_O_QPOSCNT) = position; +} + +//***************************************************************************** +// +//! Gets the current direction of rotation. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the current direction of rotation. In this case, +//! current means the most recently detected direction of the encoder; it may +//! not be presently moving but this is the direction it last moved before it +//! stopped. +//! +//! \return Returns 1 if moving in the forward direction or -1 if moving in the +//! reverse direction. +// +//***************************************************************************** +static inline int16_t +EQEP_getDirection(uint32_t base) +{ + int16_t direction; + + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the direction of rotation. + // + if((HWREGH(base + EQEP_O_QEPSTS) & EQEP_QEPSTS_QDF) != 0U) + { + direction = 1; + } + else + { + direction = -1; + } + + return(direction); +} + +//***************************************************************************** +// +//! Enables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) |= intFlags; +} + +//***************************************************************************** +// +//! Disables individual eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables eQEP module interrupt sources. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + HWREGH(base + EQEP_O_QEINT) &= ~(intFlags); +} + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the interrupt status for the eQEP module +//! module. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! the following values: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +// +//***************************************************************************** +static inline uint16_t +EQEP_getInterruptStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + return(HWREGH(base + EQEP_O_QFLG)); +} + +//***************************************************************************** +// +//! Clears eQEP module interrupt sources. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_GLOBAL - Global interrupt flag +//! - \b EQEP_INT_POS_CNT_ERROR - Position counter error +//! - \b EQEP_INT_PHASE_ERROR - Quadrature phase error +//! - \b EQEP_INT_DIR_CHANGE - Quadrature direction change +//! - \b EQEP_INT_WATCHDOG - Watchdog time-out +//! - \b EQEP_INT_UNDERFLOW - Position counter underflow +//! - \b EQEP_INT_OVERFLOW - Position counter overflow +//! - \b EQEP_INT_POS_COMP_READY - Position-compare ready +//! - \b EQEP_INT_POS_COMP_MATCH - Position-compare match +//! - \b EQEP_INT_STROBE_EVNT_LATCH - Strobe event latch +//! - \b EQEP_INT_INDEX_EVNT_LATCH - Index event latch +//! - \b EQEP_INT_UNIT_TIME_OUT - Unit time-out +//! +//! Note that the \b EQEP_INT_GLOBAL value is the global interrupt flag. In +//! order to get any further eQEP interrupts, this flag must be cleared. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearInterruptStatus(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QCLR) = intFlags; +} + +//***************************************************************************** +// +//! Forces individual eQEP module interrupts. +//! +//! \param base is the base address of the eQEP module. +//! \param intFlags is a bit mask of the interrupt sources to be forced. +//! +//! This function forces eQEP module interrupt flags. The \e intFlags +//! parameter can be any of the following values OR'd together: +//! - \b EQEP_INT_POS_CNT_ERROR +//! - \b EQEP_INT_PHASE_ERROR +//! - \b EQEP_INT_DIR_CHANGE +//! - \b EQEP_INT_WATCHDOG +//! - \b EQEP_INT_UNDERFLOW +//! - \b EQEP_INT_OVERFLOW +//! - \b EQEP_INT_POS_COMP_READY +//! - \b EQEP_INT_POS_COMP_MATCH +//! - \b EQEP_INT_STROBE_EVNT_LATCH +//! - \b EQEP_INT_INDEX_EVNT_LATCH +//! - \b EQEP_INT_UNIT_TIME_OUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_forceInterrupt(uint32_t base, uint16_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Force the specified interrupts. + // + HWREGH(base + EQEP_O_QFRC) |= intFlags; +} + +//***************************************************************************** +// +//! Gets the encoder error indicator. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the error indicator for the eQEP module. It is an +//! error for both of the signals of the quadrature input to change at the same +//! time. +//! +//! \return Returns \b true if an error has occurred and \b false otherwise. +// +//***************************************************************************** +static inline bool +EQEP_getError(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the error indicator. + // + return((HWREGH(base + EQEP_O_QFLG) & EQEP_QFLG_PHE) != 0U); +} + +//***************************************************************************** +// +//! Returns content of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the contents of the status register. The value it +//! returns is an OR of the following values: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_DIR_ON_1ST_IDX - If set, clockwise rotation (forward +//! movement) occurred on the first index event +//! - \b EQEP_STS_DIR_FLAG - If set, movement is clockwise rotation +//! - \b EQEP_STS_DIR_LATCH - If set, clockwise rotation occurred on last +//! index event marker +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! - \b EQEP_STS_POS_CNT_ERROR - Position counter error occurred +//! +//! \return Returns the value of the QEP status register. +// +//***************************************************************************** +static inline uint16_t +EQEP_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the status register. + // + return(HWREGH(base + EQEP_O_QEPSTS) & 0x00FFU); +} + +//***************************************************************************** +// +//! Clears selected fields of the eQEP module status register +//! +//! \param base is the base address of the eQEP module. +//! \param statusFlags is the bit mask of the status flags to be cleared. +//! +//! This function clears the status register fields indicated by +//! \e statusFlags. The \e statusFlags parameter is the logical OR of any of +//! the following: +//! +//! - \b EQEP_STS_UNIT_POS_EVNT - Unit position event detected +//! - \b EQEP_STS_CAP_OVRFLW_ERROR - Overflow occurred in eQEP capture timer +//! - \b EQEP_STS_CAP_DIR_ERROR - Direction change occurred between position +//! capture events +//! - \b EQEP_STS_1ST_IDX_FLAG - Set by the occurrence of the first index +//! pulse +//! +//! \note Only the above status fields can be cleared. All others are +//! read-only, non-sticky fields. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_clearStatus(uint32_t base, uint16_t statusFlags) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + HWREGH(base + EQEP_O_QEPSTS) = statusFlags; +} + +//***************************************************************************** +// +//! Configures eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! \param capPrescale is the prescaler setting of the eQEP capture timer clk. +//! \param evntPrescale is the prescaler setting of the unit position event +//! frequency. +//! +//! This function configures the operation of the eQEP module edge-capture +//! unit. The \e capPrescale parameter provides the configuration of the eQEP +//! capture timer clock rate. It determines by which power of 2 between 1 and +//! 128 inclusive SYSCLKOUT is divided. The macros for this parameter are in +//! the format of EQEP_CAPTURE_CLK_DIV_X, where X is the divide value. For +//! example, \b EQEP_CAPTURE_CLK_DIV_32 will give a capture timer clock +//! frequency that is SYSCLKOUT/32. +//! +//! The \e evntPrescale parameter determines how frequently a unit position +//! event occurs. The macro that can be passed this parameter is in the format +//! EQEP_UNIT_POS_EVNT_DIV_X, where X is the number of quadrature clock +//! periods between unit position events. For example, +//! \b EQEP_UNIT_POS_EVNT_DIV_16 will result in a unit position event +//! frequency of QCLK/16. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setCaptureConfig(uint32_t base, EQEP_CAPCLKPrescale capPrescale, + EQEP_UPEVNTPrescale evntPrescale) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write new prescaler configurations to the appropriate registers. + // + HWREGH(base + EQEP_O_QCAPCTL) = + (HWREGH(base + EQEP_O_QCAPCTL) & + ~(EQEP_QCAPCTL_UPPS_M | EQEP_QCAPCTL_CCPS_M)) | + ((uint16_t)evntPrescale | (uint16_t)capPrescale); +} + +//***************************************************************************** +// +//! Enables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) |= EQEP_QCAPCTL_CEN; +} + +//***************************************************************************** +// +//! Disables the eQEP module edge-capture unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's edge-capture unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCapture(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable edge capture. + // + HWREGH(base + EQEP_O_QCAPCTL) &= ~(EQEP_QCAPCTL_CEN); +} + +//***************************************************************************** +// +//! Gets the encoder capture period. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the period count value between the last successive +//! eQEP position events. +//! +//! \return The period count value between the last successive position events. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriod(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture period. + // + return(HWREGH(base + EQEP_O_QCPRD)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the time base for the edge capture unit. +//! +//! \return The capture timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the capture timer value. + // + return(HWREGH(base + EQEP_O_QCTMR)); +} + +//***************************************************************************** +// +//! Enables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function enables operation of the eQEP module's position-compare unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Enable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) |= EQEP_QPOSCTL_PCE; +} + +//***************************************************************************** +// +//! Disables the eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's position-compare +//! unit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableCompare(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable position compare. + // + HWREGH(base + EQEP_O_QPOSCTL) &= ~(EQEP_QPOSCTL_PCE); +} + +//***************************************************************************** +// +//! Configures the position-compare unit's sync output pulse width. +//! +//! \param base is the base address of the eQEP module. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the width of the sync output pulse. The width of +//! the pulse will be \e cycles * 4 * the width of a SYSCLKOUT cycle. The +//! maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setComparePulseWidth(uint32_t base, uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + ASSERT(cycles <= (EQEP_QPOSCTL_PCSPW_M + 1U)); + + // + // Set the pulse width. + // + HWREGH(base + EQEP_O_QPOSCTL) = (HWREGH(base + EQEP_O_QPOSCTL) & + ~(uint16_t)EQEP_QPOSCTL_PCSPW_M) | + (cycles - 1U); +} + +//***************************************************************************** +// +//! Loads the eQEP module unit timer period as number of SYSCLK cycles. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function sets the unit time-out interrupt when it matches the value +//! specified by \e period +//! The unit timer is clocked by SYSCLKOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_loadUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; +} + +//***************************************************************************** +// +//! Enables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is period value at which a unit time-out interrupt is set. +//! +//! This function enables operation of the eQEP module's peripheral unit timer. +//! The unit timer is clocked by SYSCLKOUT and will set the unit time-out +//! interrupt when it matches the value specified by \e period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableUnitTimer(uint32_t base, uint32_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the period of the unit timer. + // + HWREG(base + EQEP_O_QUPRD) = period; + + // + // Enable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_UTE; +} + +//***************************************************************************** +// +//! Disables the eQEP module unit timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral +//! unit timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableUnitTimer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral unit timer. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_UTE); +} + +//***************************************************************************** +// +//! Enables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! \param period is watchdog period value at which a time-out will occur if +//! no quadrature-clock event is detected. +//! +//! This function enables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \note When selecting \e period, note that the watchdog timer is clocked +//! from SYSCLKOUT/64. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_enableWatchdog(uint32_t base, uint16_t period) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the timeout count for the eQEP peripheral watchdog timer. + // + HWREGH(base + EQEP_O_QWDPRD) = period; + + // + // Enable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_WDE; +} + +//***************************************************************************** +// +//! Disables the eQEP module watchdog timer. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function disables operation of the eQEP module's peripheral watchdog +//! timer. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_disableWatchdog(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Disable peripheral watchdog. + // + HWREGH(base + EQEP_O_QEPCTL) &= ~(EQEP_QEPCTL_WDE); +} + +//***************************************************************************** +// +//! Sets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! \param value is the value to be written to the watchdog timer. +//! +//! This function sets the eQEP module's watchdog timer value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setWatchdogTimerValue(uint32_t base, uint16_t value) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the value to the watchdog timer register. + // + HWREGH(base + EQEP_O_QWDTMR) = value; +} + +//***************************************************************************** +// +//! Gets the eQEP module watchdog timer value. +//! +//! \param base is the base address of the eQEP module. +//! +//! \return Returns the current watchdog timer value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getWatchdogTimerValue(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Read the value from the watchdog timer register. + // + return(HWREGH(base + EQEP_O_QWDTMR)); +} + +//***************************************************************************** +// +//! Configures the mode in which the position counter is initialized. +//! +//! \param base is the base address of the eQEP module. +//! \param initMode is the configuration for initializing the position count. +//! See below for a description of this parameter. +//! +//! This function configures the events on which the position count can be +//! initialized. The \e initMode parameter provides the mode as either +//! \b EQEP_INIT_DO_NOTHING (no action configured) or one of the following +//! strobe events, index events, or a logical OR of both a strobe event and an +//! index event. +//! +//! - \b EQEP_INIT_RISING_STROBE or \b EQEP_INIT_EDGE_DIR_STROBE specify +//! which strobe event will initialize the position counter. +//! - \b EQEP_INIT_RISING_INDEX or \b EQEP_INIT_FALLING_INDEX specify +//! which index event will initialize the position counter. +//! +//! Use EQEP_setSWPositionInit() to cause a software initialization and +//! EQEP_setInitialPosition() to set the value that gets loaded into the +//! position counter upon initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setPositionInitMode(uint32_t base, uint16_t initMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the init mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_IEI_M | EQEP_QEPCTL_SEI_M)) | + initMode; +} + +//***************************************************************************** +// +//! Sets the software initialization of the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param initialize is a flag to specify if software initialization of the +//! position counter is enabled. +//! +//! This function does a software initialization of the position counter when +//! the \e initialize parameter is \b true. When \b false, the QEPCTL[SWI] bit +//! is cleared and no action is taken. +//! +//! The init value to be loaded into the position counter can be set with +//! EQEP_setInitialPosition(). Additional initialization causes can be +//! configured with EQEP_setPositionInitMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setSWPositionInit(uint32_t base, bool initialize) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set or clear the software initialization bit. + // + if(initialize) + { + HWREGH(base + EQEP_O_QEPCTL) |= EQEP_QEPCTL_SWI; + } + else + { + HWREGH(base + EQEP_O_QEPCTL) &= ~EQEP_QEPCTL_SWI; + } +} + +//***************************************************************************** +// +//! Sets the init value for the encoder position counter. +//! +//! \param base is the base address of the eQEP module. +//! \param position is the value to be written to the position counter upon. +//! initialization. +//! +//! This function sets the init value for position of the encoder. See +//! EQEP_setPositionInitMode() to set the initialization cause or +//! EQEP_setSWPositionInit() to cause a software initialization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setInitialPosition(uint32_t base, uint32_t position) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write position to position counter init register + // + HWREG(base + EQEP_O_QPOSINIT) = position; +} + +//***************************************************************************** +// +//! Configures the quadrature modes in which the position count can be latched. +//! +//! \param base is the base address of the eQEP module. +//! \param latchMode is the configuration for latching of the position count +//! and several other registers. See below for a description of this +//! parameter. +//! +//! This function configures the events on which the position count and several +//! other registers can be latched. The \e latchMode parameter provides the +//! mode as the logical OR of several values. +//! +//! - \b EQEP_LATCH_CNT_READ_BY_CPU or \b EQEP_LATCH_UNIT_TIME_OUT specify +//! the event that latches the position counter. This latch register can be +//! read using EQEP_getPositionLatch(). The capture timer and capture +//! period are also latched based on this setting, and can be read using +//! EQEP_getCaptureTimerLatch() and EQEP_getCapturePeriodLatch(). +//! - \b EQEP_LATCH_RISING_STROBE or \b EQEP_LATCH_EDGE_DIR_STROBE +//! specify which strobe event will latch the position counter into the +//! strobe position latch register. This register can be read with +//! EQEP_getStrobePositionLatch(). +//! - \b EQEP_LATCH_RISING_INDEX, \b EQEP_LATCH_FALLING_INDEX, or +//! \b EQEP_LATCH_SW_INDEX_MARKER specify which index event will latch the +//! position counter into the index position latch register. This register +//! can be read with EQEP_getIndexPositionLatch(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setLatchMode(uint32_t base, uint32_t latchMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Set the latch mode in the QEP Control register. + // + HWREGH(base + EQEP_O_QEPCTL) = (HWREGH(base + EQEP_O_QEPCTL) & + ~(EQEP_QEPCTL_QCLM | EQEP_QEPCTL_IEL_M | + EQEP_QEPCTL_SEL)) | latchMode; +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on an index event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the index position latch register. The +//! position counter is latched into this register on either a rising index +//! edge, a falling index edge, or a software index marker. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on an index event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getIndexPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSILAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a strobe event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the strobe position latch register. The +//! position counter can be configured to be latched into this register on +//! rising strobe edges only or on rising strobe edges while moving clockwise +//! and falling strobe edges while moving counter-clockwise. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The position count latched on a strobe event. +// +//***************************************************************************** +static inline uint32_t +EQEP_getStrobePositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder position that was latched on a unit time-out event. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the position latch register. The +//! position counter is latched into this register either on a unit time-out +//! event. +//! +//! \return The position count latch register value. +// +//***************************************************************************** +static inline uint32_t +EQEP_getPositionLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREG(base + EQEP_O_QPOSLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture timer latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture timer latch register. The +//! capture timer value is latched into this register either on a unit time-out +//! event or upon the CPU reading the eQEP position counter. This is configured +//! using EQEP_setLatchMode(). +//! +//! \return The edge-capture timer latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCaptureTimerLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCTMRLAT)); +} + +//***************************************************************************** +// +//! Gets the encoder capture period latch. +//! +//! \param base is the base address of the eQEP module. +//! +//! This function returns the value in the capture period latch register. The +//! capture period value is latched into this register either on a unit +//! time-out event or upon the CPU reading the eQEP position counter. This is +//! configured using EQEP_setLatchMode(). +//! +//! \return The edge-capture period latch value. +// +//***************************************************************************** +static inline uint16_t +EQEP_getCapturePeriodLatch(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Return the current position counter. + // + return(HWREGH(base + EQEP_O_QCPRDLAT)); +} + +//***************************************************************************** +// +//! Set the emulation mode of the eQEP module. +//! +//! \param base is the base address of the eQEP module. +//! \param emuMode is the mode operation upon an emulation suspend. +//! +//! This function sets the eQEP module's emulation mode. This mode determines +//! how the timers are affected by an emulation suspend. Valid values for the +//! \e emuMode parameter are the following: +//! +//! - \b EQEP_EMULATIONMODE_STOPIMMEDIATELY - The position counter, watchdog +//! counter, unit timer, and capture timer all stop immediately. +//! - \b EQEP_EMULATIONMODE_STOPATROLLOVER - The position counter, watchdog +//! counter, unit timer all count until period rollover. The capture timer +//! counts until the next unit period event. +//! - \b EQEP_EMULATIONMODE_RUNFREE - The position counter, watchdog counter, +//! unit timer, and capture timer are all unaffected by an emulation suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +EQEP_setEmulationMode(uint32_t base, EQEP_EmulationMode emuMode) +{ + // + // Check the arguments. + // + ASSERT(EQEP_isBaseValid(base)); + + // + // Write the emulation mode to the FREE_SOFT bits. + // + HWREGH(base + EQEP_O_QEPCTL) = + (HWREGH(base + EQEP_O_QEPCTL) & ~EQEP_QEPCTL_FREE_SOFT_M) | + ((uint16_t)emuMode << EQEP_QEPCTL_FREE_SOFT_S); +} + +//***************************************************************************** +// +//! Configures eQEP module position-compare unit. +//! +//! \param base is the base address of the eQEP module. +//! \param config is the configuration for the eQEP module +//! position-compare unit. See below for a description of this parameter. +//! \param compareValue is the value to which the position count value is +//! compared for a position-compare event. +//! \param cycles is the width of the pulse that can be generated on a +//! position-compare event. It is in units of 4 SYSCLKOUT cycles. +//! +//! This function configures the operation of the eQEP module position-compare +//! unit. The \e config parameter provides the configuration of the +//! position-compare unit and is the logical OR of several values: +//! +//! - \b EQEP_COMPARE_NO_SYNC_OUT, \b EQEP_COMPARE_IDX_SYNC_OUT, or +//! \b EQEP_COMPARE_STROBE_SYNC_OUT specify if there is a sync output pulse +//! and which pin should be used. +//! - \b EQEP_COMPARE_NO_SHADOW, \b EQEP_COMPARE_LOAD_ON_ZERO, or +//! \b EQEP_COMPARE_LOAD_ON_MATCH specify if a shadow is enabled and when +//! should the load should occur--QPOSCNT = 0 or QPOSCNT = QPOSCOMP. +//! +//! The \e cycles is used to select the width of the sync output pulse. The +//! width of the resulting pulse will be \e cycles * 4 * the width of a +//! SYSCLKOUT cycle. The maximum width is 4096 * 4 * SYSCLKOUT cycles. +//! +//! \note You can set the sync pulse width independently using the +//! EQEP_setComparePulseWidth() function. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setCompareConfig(uint32_t base, uint16_t config, uint32_t compareValue, + uint16_t cycles); + +//***************************************************************************** +// +//! Sets the polarity of the eQEP module's input signals. +//! +//! \param base is the base address of the eQEP module. +//! \param invertQEPA is the flag to negate the QEPA input. +//! \param invertQEPB is the flag to negate the QEPA input. +//! \param invertIndex is the flag to negate the index input. +//! \param invertStrobe is the flag to negate the strobe input. +//! +//! This function configures the polarity of the inputs to the eQEP module. To +//! negate the polarity of any of the input signals, pass \b true into its +//! corresponding parameter in this function. Pass \b false to leave it as-is. +//! +//! \return None. +// +//***************************************************************************** +extern void +EQEP_setInputPolarity(uint32_t base, bool invertQEPA, bool invertQEPB, + bool invertIndex, bool invertStrobe); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // EQEP_H diff --git a/gpio_driverlib_cpu1/device/driverlib/flash.c b/gpio_driverlib_cpu1/device/driverlib/flash.c new file mode 100644 index 0000000..372b77b --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/flash.c @@ -0,0 +1,175 @@ +//########################################################################### +// +// FILE: flash.c +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "flash.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_initModule, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_powerDown, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_wakeFromLPM, ".TI.ramfunc"); +#endif + +//***************************************************************************** +// +// Flash_initModule +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT(waitstates <= 0xFU); + + // + // Set the bank power up delay so that the bank will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Set the bank fallback power mode to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Power up flash bank and pump and this also sets the fall back mode of + // flash and pump as active + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); + + // + // Disable cache and prefetch mechanism before changing wait states + // + Flash_disableCache(ctrlBase); + Flash_disablePrefetch(ctrlBase); + + // + // Set waitstates according to frequency. + // + Flash_setWaitstates(ctrlBase, waitstates); + + + // + // Enable cache and prefetch mechanism to improve performance of code + // executed from flash. + // + Flash_enableCache(ctrlBase); + Flash_enablePrefetch(ctrlBase); + + // + // At reset, ECC is enabled. If it is disabled by application software and + // if application again wants to enable ECC. + // + Flash_enableECC(eccBase); + + // + // Force a pipeline flush to ensure that the write to the last register + // configured occurs before returning. + // + + FLASH_DELAY_CONFIG; +} + +//***************************************************************************** +// +// Flash_powerDown +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_powerDown(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank power up delay so that it will power up properly. + // + Flash_setBankPowerUpDelay(ctrlBase, 0x14); + + // + // Power down the flash bank. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_SLEEP); + + // + // Power down the flash pump. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_SLEEP); +} + +//***************************************************************************** +// +// Flash_wakeFromLPM +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +void +Flash_wakeFromLPM(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // Set the bank fallback power modes to active. + // + Flash_setBankPowerMode(ctrlBase, FLASH_BANK, FLASH_BANK_PWR_ACTIVE); + + // + // Set the flash pump power mode to active. + // + Flash_setPumpPowerMode(ctrlBase, FLASH_PUMP_PWR_ACTIVE); +} diff --git a/gpio_driverlib_cpu1/device/driverlib/flash.h b/gpio_driverlib_cpu1/device/driverlib/flash.h new file mode 100644 index 0000000..a60a2f2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/flash.h @@ -0,0 +1,1671 @@ +//########################################################################### +// +// FILE: flash.h +// +// TITLE: C28x Flash driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef FLASH_H +#define FLASH_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif +#ifndef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +//! \addtogroup flash_api Flash +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_flash.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +#ifndef __cplusplus +#pragma CODE_SECTION(Flash_setBankPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setPumpPowerMode, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_disablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_setWaitstates, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableCache, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enablePrefetch, ".TI.ramfunc"); +#pragma CODE_SECTION(Flash_enableECC, ".TI.ramfunc"); +#endif + + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the bank parameter +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK = 0x0 //!< Bank +} Flash_BankNumber; + +//***************************************************************************** +// +//! Values that can be passed to Flash_claimPumpSemaphore() in order to claim +//! the pump semaphore. +// +//***************************************************************************** +typedef enum +{ + FLASH_CPU1_WRAPPER = 0x2, //!< CPU1 Wrapper + FLASH_CPU2_WRAPPER = 0x1 //!< CPU2 Wrapper +}Flash_PumpOwnership; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setBankPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_BANK_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_BANK_PWR_STANDBY = 0x1, //!< Standby fallback mode + FLASH_BANK_PWR_ACTIVE = 0x3 //!< Active fallback mode +} Flash_BankPowerMode; + +//***************************************************************************** +// +//! Values that can be passed to Flash_setPumpPowerMode() as the powerMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + FLASH_PUMP_PWR_SLEEP = 0x0, //!< Sleep fallback mode + FLASH_PUMP_PWR_ACTIVE = 0x1 //!< Active fallback mode +} Flash_PumpPowerMode; + +//***************************************************************************** +// +//! Type that correspond to values returned from Flash_getLowErrorStatus() and +//! Flash_getHighErrorStatus() determining the error status code. +// +//***************************************************************************** +typedef enum +{ + FLASH_NO_ERR = 0x0, //!< No error + FLASH_FAIL_0 = 0x1, //!< Fail on 0 + FLASH_FAIL_1 = 0x2, //!< Fail on 1 + FLASH_UNC_ERR = 0x4 //!< Uncorrectable error +} Flash_ErrorStatus; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getLowErrorType() and +//! Flash_getHighErrorType() determining the error type. +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_ERR = 0x0, //!< Data error + FLASH_ECC_ERR = 0x1 //!< ECC error +} Flash_ErrorType; + +//***************************************************************************** +// +//! Values that can be returned from Flash_getECCTestSingleBitErrorType(). +// +//***************************************************************************** +typedef enum +{ + FLASH_DATA_BITS = 0x0, //!< Data bits + FLASH_CHECK_BITS = 0x1 //!< ECC bits +} Flash_SingleBitErrorIndicator; + +//***************************************************************************** +// +// Values that can be passed to Flash_clearLowErrorStatus and +// Flash_clearHighErrorStatus. +// +//***************************************************************************** +#define FLASH_FAIL_0_CLR 0x1 //!< Fail-0 clear +#define FLASH_FAIL_1_CLR 0x2 //!< Fail-1 clear +#define FLASH_UNC_ERR_CLR 0x4 //!< Uncorrectable error Clear + +//***************************************************************************** +// +// Values that can be returned from Flash_getInterruptFlag and +// Flash_getECCTestStatus. +// +//***************************************************************************** +#define FLASH_NO_ERROR 0x0 //!< No error +#define FLASH_SINGLE_ERROR 0x1 //!< Single bit error +#define FLASH_UNC_ERROR 0x2 //!< Uncorrectable error + +//***************************************************************************** +// +// Delay instruction that allows for register configuration to complete. +// +//***************************************************************************** +#define FLASH_DELAY_CONFIG __asm(" RPT #7 || NOP") + +//***************************************************************************** +// +// Key value for claiming the pump semaphore. +// +//***************************************************************************** +#define FLASH_PUMP_KEY 0x5A5A0000UL //!< Pump semaphore key + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function determines if a flash wrapper control base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isCtrlBaseValid(uint32_t ctrlBase) +{ + return((ctrlBase == FLASH0CTRL_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash wrapper base address for the ECC registers. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function determines if a flash wrapper ECC base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isECCBaseValid(uint32_t eccBase) +{ + return((eccBase == FLASH0ECC_BASE)); +} +#endif + +//***************************************************************************** +// +//! \internal +//! Checks a flash pump semaphore base address. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! This function determines if a flash pump semaphore base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +Flash_isPumpSemBaseValid(uint32_t pumpSemBase) +{ + return((pumpSemBase == FLASHPUMPSEMAPHORE_BASE)); +} +#endif + +//***************************************************************************** +// +//! Sets the random read wait state amount. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param waitstates is the wait-state value. +//! +//! This function sets the number of wait states for a flash read access. The +//! \e waitstates parameter is a number between 0 and 15. It is \b important +//! to look at your device's datasheet for information about what the required +//! minimum flash wait-state is for your selected SYSCLK frequency. +//! +//! By default the wait state amount is configured to the maximum 15. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setWaitstates(uint32_t ctrlBase, uint16_t waitstates) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // waitstates is 4 bits wide. + // + ASSERT(waitstates <= 0xFU); + + EALLOW; + // + // Write flash read wait-state amount to appropriate register. + // + HWREG(ctrlBase + FLASH_O_FRDCNTL) = + (HWREG(ctrlBase + FLASH_O_FRDCNTL) & + ~(uint32_t)FLASH_FRDCNTL_RWAIT_M) | + ((uint32_t)waitstates << FLASH_FRDCNTL_RWAIT_S); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of a flash bank. +//! +//! \param ctrlBase is the base address of the flash wrapper registers. +//! \param bank is the flash bank that is being configured. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode of the flash bank specified by +//! them \e bank parameter. The power mode is specified by the \e powerMode +//! parameter with one of the following values: +//! +//! - \b FLASH_BANK_PWR_SLEEP - Sense amplifiers and sense reference disabled. +//! - \b FLASH_BANK_PWR_STANDBY - Sense amplifiers disabled but sense reference +//! enabled. +//! - \b FLASH_BANK_PWR_ACTIVE - Sense amplifiers and sense reference enabled. +//! +//! +//! Note: There is only one Flash_BankNumber value on this device (FLASH_BANK). +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setBankPowerMode(uint32_t ctrlBase, Flash_BankNumber bank, + Flash_BankPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FBFALLBACK) = + (HWREG(ctrlBase + FLASH_O_FBFALLBACK) & + ~((FLASH_FBFALLBACK_BNKPWR0_M) << ((uint32_t)bank * 2U))) | + ((uint32_t)powerMode << ((uint32_t)bank * 2U)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the fallback power mode of the charge pump. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param powerMode is the power mode to be entered. +//! +//! This function sets the fallback power mode flash charge pump. +//! +//! - \b FLASH_PUMP_PWR_SLEEP - All circuits disabled. +//! - \b FLASH_PUMP_PWR_ACTIVE - All pump circuits active. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_setPumpPowerMode(uint32_t ctrlBase, Flash_PumpPowerMode powerMode) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Write the power mode to the appropriate register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PMPPWR) | (uint32_t)powerMode; + EDIS; +} + +//***************************************************************************** +// +//! Enables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables prefetch mechanism. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disablePrefetch(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the prefetch enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_PREFETCH_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Set the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) |= + FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables data cache. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_disableCache(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + EALLOW; + + // + // Clear the data cache enable bit. + // + HWREG(ctrlBase + FLASH_O_FRD_INTF_CTRL) &= + ~(uint32_t)FLASH_FRD_INTF_CTRL_DATA_CACHE_EN; + EDIS; +} + +//***************************************************************************** +// +//! Enables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +#ifdef __cplusplus +#pragma CODE_SECTION(".TI.ramfunc"); +#endif +static inline void +Flash_enableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Write the key value 0xA to ECC_ENABLE register. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0xAU; + EDIS; +} + +//***************************************************************************** +// +//! Disables flash error correction code (ECC) protection. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECC(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + + // + // Clear ECC enable field with the one's complement of the key. + // + HWREG(eccBase + FLASH_O_ECC_ENABLE) = + (HWREG(eccBase + FLASH_O_ECC_ENABLE) & + ~(uint32_t)FLASH_ECC_ENABLE_ENABLE_M) | 0x5U; + EDIS; +} + + +//***************************************************************************** +// +//! Sets the bank power up delay. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param delay is the number of HCLK cycles. +//! +//! This function sets the VREADST delay to ensure that the requisite delay is +//! introduced for the flash pump/bank to come out of low-power mode, so that +//! the flash/OTP is ready for CPU access. +//! +//! Note: Refer to TRM before configuring VREADST. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setBankPowerUpDelay(uint32_t ctrlBase, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + ASSERT(delay <= 0xFF); + + EALLOW; + + // + // Write period to the BAGP of the FBAC register. + // + HWREG(ctrlBase + FLASH_O_FBAC) = (HWREG(ctrlBase + FLASH_O_FBAC) & + ~(uint32_t)FLASH_FBAC_VREADST_M) | delay; + EDIS; +} + +//***************************************************************************** +// +//! Sets the pump wake up time. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param sysclkCycles is the number of SYSCLK cycles it takes for the pump +//! to wakeup. +//! +//! This function sets the wakeup time with \e sysclkCycles parameter. +//! The \e sysclkCycles is a value between 0 and 8190. When the charge pump +//! exits sleep power mode, it will take sysclkCycles to wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setPumpWakeupTime(uint32_t ctrlBase, uint16_t sysclkCycles) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + // + // PSLEEP = sysclkCycles/2. PSLEEP maximum value is 4095(12 bits wide) + // + ASSERT( sysclkCycles <= 8190U ); + + EALLOW; + + // + // Write sysclkCycles/2 to PSLEEP of the FPAC1 register. + // + HWREG(ctrlBase + FLASH_O_FPAC1) = + (HWREG(ctrlBase + FLASH_O_FPAC1) & + ~(uint32_t)FLASH_FPAC1_PSLEEP_M) | + (((uint32_t)sysclkCycles / (uint32_t)2) << + (uint32_t)FLASH_FPAC1_PSLEEP_S); + EDIS; +} + +//***************************************************************************** +// +//! Reads the bank active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param bank is the flash bank that is being used. +//! +//! \return Returns \b true if the Bank is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isBankReady(uint32_t ctrlBase, Flash_BankNumber bank) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + uint32_t bitMask = (uint32_t)FLASH_FBPRDY_BANKRDY << (uint32_t)bank; + // + // Return the BANKXRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & bitMask) == bitMask) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + +//***************************************************************************** +// +//! Reads the pump active power state. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! \return Returns \b true if the Pump is in Active power state and \b false +//! otherwise. +// +//***************************************************************************** +static inline bool +Flash_isPumpReady(uint32_t ctrlBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isCtrlBaseValid(ctrlBase)); + + bool ready; + + // + // Return the PUMPRDY bit in FBPRDY. + // + if((HWREG(ctrlBase + FLASH_O_FBPRDY) & + (uint32_t)FLASH_FBPRDY_PUMPRDY) == FLASH_FBPRDY_PUMPRDY) + { + ready = true; + } + else + { + ready = false; + } + return(ready); +} + + +//***************************************************************************** +// +//! Gets the single error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the single error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the single bit error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where a single bit +//! error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getSingleBitErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_SINGLE_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address low. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the lower 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_LOW)); +} + +//***************************************************************************** +// +//! Gets the uncorrectable error address high. +//! +//! \param eccBase is the base address of the flash wrapper ECC base. +//! +//! This function returns the 32-bit address of the uncorrectable error that +//! occurred in the upper 64-bits of a 128-bit memory-aligned data. The +//! returned address is to that 64-bit aligned data. +//! +//! \return Returns the 32 bits of a 64-bit aligned address where an +//! uncorrectable error occurred. +// +//***************************************************************************** +static inline uint32_t +Flash_getUncorrectableErrorAddressHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_UNC_ERR_ADDR_HIGH)); +} + +//***************************************************************************** +// +//! Gets the error status of the Lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the lower 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the low error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getLowErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the Low Error Status bits + // + errorStatus = (HWREG(eccBase + FLASH_O_ERR_STATUS) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error status of the Upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error status of the upper 64-bits of a 128-bit +//! aligned address. +//! +//! \return Returns value of the high error status bits which can be used with +//! Flash_ErrorStatus type. +// +//***************************************************************************** +static inline Flash_ErrorStatus +Flash_getHighErrorStatus(uint32_t eccBase) +{ + uint32_t errorStatus; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Get the High Error Status bits + // + errorStatus = ((HWREG(eccBase + FLASH_O_ERR_STATUS) >> 16U) & 0x7UL); + return((Flash_ErrorStatus)errorStatus); +} + +//***************************************************************************** +// +//! Gets the error position of the lower 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the lower 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the lower error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getLowErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_L_M) >> + FLASH_ERR_POS_ERR_POS_L_S); +} + +//***************************************************************************** +// +//! Gets the error position of the upper 64-bits for a single bit error. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error position of the upper 64-bits. If the +//! error type is FLASH_ECC_ERR, the position ranges from 0-7 else it ranges +//! from 0-63 for FLASH_DATA_ERR. +//! +//! \return Returns the position of the upper error bit. +// +//***************************************************************************** +static inline uint32_t +Flash_getHighErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return((HWREG(eccBase + FLASH_O_ERR_POS) & + (uint32_t)FLASH_ERR_POS_ERR_POS_H_M) >> + FLASH_ERR_POS_ERR_POS_H_S); +} + +//***************************************************************************** +// +//! Gets the error type of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the lower 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the lower 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getLowErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_L) + == FLASH_ERR_POS_ERR_TYPE_L) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} + +//***************************************************************************** +// +//! Gets the error type of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the error type of the upper 64-bits. The error type +//! can be FLASH_ECC_ERR or FLASH_DATA_ERR. +//! +//! \return Returns the type of the upper 64-bit error. +// +//***************************************************************************** +static inline Flash_ErrorType +Flash_getHighErrorType(uint32_t eccBase) +{ + Flash_ErrorType errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Check which error type. + // If bit is 1 then ECC error, else it is a Data error. + // + if((HWREG(eccBase + FLASH_O_ERR_POS) & FLASH_ERR_POS_ERR_TYPE_H) + == FLASH_ERR_POS_ERR_TYPE_H) + { + errorType = FLASH_ECC_ERR; + } + else + { + errorType = FLASH_DATA_ERR; + } + + return(errorType); +} +//***************************************************************************** +// +//! Clears the errors status of the lower 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearLowErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus); + EDIS; +} + +//***************************************************************************** +// +//! Clears the errors status of the upper 64-bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param errorStatus is the error status to clear. errorStatus is a uint16_t. +//! errorStatus is a bitwise OR of the following value: +//! +//! - \b FLASH_FAIL_0_CLR +//! - \b FLASH_FAIL_1_CLR +//! - \b FLASH_UNC_ERR_CLR +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearHighErrorStatus(uint32_t eccBase, uint16_t errorStatus) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + ASSERT( errorStatus <= 7U ); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_STATUS_CLR) |= ((uint32_t)errorStatus << 16U); + EDIS; +} + +//***************************************************************************** +// +//! Gets the single bit error count. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error count. +// +//***************************************************************************** +static inline uint32_t +Flash_getErrorCount(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_ERR_CNT) & + (uint32_t)FLASH_ERR_CNT_ERR_CNT_M); +} + +//***************************************************************************** +// +//! Sets the single bit error threshold. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param threshold is the single bit error threshold. Valid ranges are from +//! 0-65535. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setErrorThreshold(uint32_t eccBase, uint16_t threshold) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_THRESHOLD) = ((uint32_t)threshold & + (uint32_t)FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M); + EDIS; +} + +//***************************************************************************** +// +//! Gets the error interrupt. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the type of error interrupt that occurred. The +//! values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the interrupt flag. +// +//***************************************************************************** +static inline uint32_t +Flash_getInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_ERR_INTFLG) & (uint32_t)0x3U)); +} + +//***************************************************************************** +// +//! Clears the single error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearSingleErrorInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Clears the uncorrectable error interrupt flag. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_clearUncorrectableInterruptFlag(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_ERR_INTCLR) |= + FLASH_ERR_INTCLR_UNC_ERR_INTCLR; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data Low Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the low double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataLowECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAL_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the Data High Test register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param data is a 32-bit value that is the high double word of selected +//! 64-bit data +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setDataHighECCTest(uint32_t eccBase, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FDATAH_TEST) = data; + EDIS; +} + +//***************************************************************************** +// +//! Sets the test address register for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param address is a 32-bit value containing an address. Bits 21-3 will be +//! used as the flash word (128-bit) address. +//! +//! This function left shifts the address 1 bit to convert it to a byte address +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestAddress(uint32_t eccBase, uint32_t address) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Left shift the address 1 bit to make it byte-addressable + // + uint32_t byteAddress = address << 1; + + EALLOW; + + // + // Write bits 21-3 to the register. + // + HWREG(eccBase + FLASH_O_FADDR_TEST) = byteAddress; + + EDIS; + +} + +//***************************************************************************** +// +//! Sets the ECC test bits for ECC testing. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param ecc is a 32-bit value. The least significant 8 bits are used as +//! the ECC Control Bits in the ECC Test. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_setECCTestECCBits(uint32_t eccBase, uint16_t ecc) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + ASSERT( ecc <= 255U ); + EALLOW; + + // + // Write the 8 ECC Control Bits. + // + HWREG(eccBase + FLASH_O_FECC_TEST) = + ((uint32_t)ecc & (uint32_t)FLASH_FECC_TEST_ECC_M); + EDIS; +} + +//***************************************************************************** +// +//! Enables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_enableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Disables ECC Test mode. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_disableECCTestMode(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_TEST_EN; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [63:0] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectLowECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) &= + ~(uint32_t)FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Selects the ECC block on bits [127:64] of bank data. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_selectHighECCBlock(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_ECC_SELECT; + EDIS; +} + +//***************************************************************************** +// +//! Performs the ECC calculation on the test block. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_performECCCalculation(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + EALLOW; + HWREG(eccBase + FLASH_O_FECC_CTRL) |= FLASH_FECC_CTRL_DO_ECC_CALC; + EDIS; +} + +//***************************************************************************** +// +//! Gets the ECC Test data out high 63:32 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC TEst data out High. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutHigh(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTH_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test data out low 31:0 bits. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test data out Low. +// +//***************************************************************************** +static inline uint32_t +Flash_getTestDataOutLow(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + return(HWREG(eccBase + FLASH_O_FOUTL_TEST)); +} + +//***************************************************************************** +// +//! Gets the ECC Test status. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! This function returns the ECC test status. The values can be used with +//! - \b FLASH_NO_ERROR +//! - \b FLASH_SINGLE_ERROR +//! - \b FLASH_UNC_ERROR +//! +//! \return Returns the ECC test status. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestStatus(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read which type of error occurred. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS)) & (uint32_t)0x3U); +} + +//***************************************************************************** +// +//! Gets the ECC Test single bit error position. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the ECC Test single bit error position. If the error type +//! is check bits than the position can range from 0 to 7. If the error type +//! is data bits than the position can range from 0 to 63. +// +//***************************************************************************** +static inline uint32_t +Flash_getECCTestErrorPosition(uint32_t eccBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the position bits and shift it to the right. + // + return((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_DATA_ERR_POS_M) >> + FLASH_FECC_STATUS_DATA_ERR_POS_S); +} + +//***************************************************************************** +// +//! Gets the single bit error type. +//! +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! +//! \return Returns the single bit error type as a +//! Flash_SingleBitErrorIndicator. FLASH_DATA_BITS and FLASH_CHECK_BITS +//! indicate where the single bit error occurred. +// +//***************************************************************************** +static inline Flash_SingleBitErrorIndicator +Flash_getECCTestSingleBitErrorType(uint32_t eccBase) +{ + uint32_t errorType; + // + // Check the arguments. + // + ASSERT(Flash_isECCBaseValid(eccBase)); + + // + // Read the ERR_TYPE bit to see where the single bit error was. + // + errorType = ((HWREG(eccBase + FLASH_O_FECC_STATUS) & + (uint32_t)FLASH_FECC_STATUS_ERR_TYPE) >> 8U); + return((Flash_SingleBitErrorIndicator)errorType); +} + +//***************************************************************************** +// +//! Claim the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! \param wrapper is the Flash_PumpOwnership wrapper claiming the pump +//! semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_claimPumpSemaphore(uint32_t pumpSemBase, Flash_PumpOwnership wrapper) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Block until the pump semaphore is claimed. + // + EALLOW; + while((HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) + & FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M) != wrapper) + { + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = + FLASH_PUMP_KEY | (uint32_t)wrapper; + } + EDIS; +} + +//***************************************************************************** +// +//! Release the flash pump semaphore. +//! +//! \param pumpSemBase is the base address of the flash pump semaphore. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Flash_releasePumpSemaphore(uint32_t pumpSemBase) +{ + // + // Check the arguments. + // + ASSERT(Flash_isPumpSemBaseValid(pumpSemBase)); + + // + // Relinquish the pump semaphore. + // + EALLOW; + HWREG(pumpSemBase + FLASH_O_PUMPREQUEST) = FLASH_PUMP_KEY; + EDIS; +} + +//***************************************************************************** +// +//! Initializes the flash control registers. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! \param eccBase is the base address of the flash wrapper ECC registers. +//! \param waitstates is the wait-state value. +//! +//! This function initializes the flash control registers. At reset bank and +//! pump are in sleep. A flash access will power up the bank and pump +//! automatically. This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! This function also sets the number of wait-states for a flash access +//! (see Flash_setWaitstates() for more details), and enables cache, the +//! prefetch mechanism, and ECC. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_initModule(uint32_t ctrlBase, uint32_t eccBase, uint16_t waitstates); + + +//***************************************************************************** +// +//! Powers down the flash. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function powers down the flash bank(s) and the flash pump. +//! +//! Note: For this device, you must claim the flash pump semaphore before +//! calling this function and powering down the pump. Afterwards, you may want +//! to relinquish the flash pump. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_powerDown(uint32_t ctrlBase); + +//***************************************************************************** +// +//! Wakes the flash from low power mode. +//! +//! \param ctrlBase is the base address of the flash wrapper control registers. +//! +//! This function will power up Flash bank and pump and set the +//! fallback mode of flash and pump as active. +//! +//! \return None. +// +//***************************************************************************** +extern void +Flash_wakeFromLPM(uint32_t ctrlBase); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** +#endif // #ifdef __TMS320C28XX_CLA__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // FLASH_H diff --git a/gpio_driverlib_cpu1/device/driverlib/gpio.c b/gpio_driverlib_cpu1/device/driverlib/gpio.c new file mode 100644 index 0000000..be20285 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/gpio.c @@ -0,0 +1,489 @@ +//########################################################################### +// +// FILE: gpio.c +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "gpio.h" + +//***************************************************************************** +// +// GPIO_setDirectionMode +// +//***************************************************************************** +void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Set the data direction + // + if(pinIO == GPIO_DIR_MODE_OUT) + { + // + // Output + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] |= pinMask; + } + else + { + // + // Input + // + gpioBaseAddr[GPIO_GPxDIR_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getDirectionMode +// +//***************************************************************************** +GPIO_Direction +GPIO_getDirectionMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + return((GPIO_Direction)((uint32_t)((gpioBaseAddr[GPIO_GPxDIR_INDEX] >> + (pin % 32U)) & 1U))); + +} + +//***************************************************************************** +// +// GPIO_setInterruptPin +// +//***************************************************************************** +void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum) +{ + XBAR_InputNum input; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + // + // Pick the X-BAR input that corresponds to the requested XINT. + // + switch(extIntNum) + { + case GPIO_INT_XINT1: + input = XBAR_INPUT4; + break; + + case GPIO_INT_XINT2: + input = XBAR_INPUT5; + break; + + case GPIO_INT_XINT3: + input = XBAR_INPUT6; + break; + + case GPIO_INT_XINT4: + input = XBAR_INPUT13; + break; + + case GPIO_INT_XINT5: + input = XBAR_INPUT14; + break; + + default: + // + // Invalid interrupt. Shouldn't happen if enum value is used. + // XBAR_INPUT1 isn't tied to an XINT, so we'll use it to check for + // a bad value. + // + input = XBAR_INPUT1; + break; + } + + if(input != XBAR_INPUT1) + { + XBAR_setInputPin(input, (uint16_t)pin); + } +} + +//***************************************************************************** +// +// GPIO_setPadConfig +// +//***************************************************************************** +void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + EALLOW; + + // + // Enable open drain if necessary + // + if((pinType & GPIO_PIN_TYPE_OD) != 0U) + { + gpioBaseAddr[GPIO_GPxODR_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxODR_INDEX] &= ~pinMask; + } + + // + // Enable pull-up if necessary + // + if((pinType & GPIO_PIN_TYPE_PULLUP) != 0U) + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] &= ~pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxPUD_INDEX] |= pinMask; + } + + // + // Invert polarity if necessary + // + if((pinType & GPIO_PIN_TYPE_INVERT) != 0U) + { + gpioBaseAddr[GPIO_GPxINV_INDEX] |= pinMask; + } + else + { + gpioBaseAddr[GPIO_GPxINV_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getPadConfig +// +//***************************************************************************** +uint32_t +GPIO_getPadConfig(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + uint32_t pinTypeRes; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + pinMask = (uint32_t)1U << (pin % 32U); + + pinTypeRes = GPIO_PIN_TYPE_STD; + + // + // Get open drain value + // + if((gpioBaseAddr[GPIO_GPxODR_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_OD; + } + + // + // Get pull-up value + // + if((gpioBaseAddr[GPIO_GPxPUD_INDEX] & pinMask) == 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_PULLUP; + } + + // + // Get polarity value + // + if((gpioBaseAddr[GPIO_GPxINV_INDEX] & pinMask) != 0U) + { + pinTypeRes |= GPIO_PIN_TYPE_INVERT; + } + + return(pinTypeRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationMode +// +//***************************************************************************** +void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Write the input qualification mode to the register. + // + EALLOW; + + gpioBaseAddr[qSelIndex] &= ~((uint32_t)GPIO_GPAQSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[qSelIndex] |= (uint32_t)qualification << shiftAmt; + + EDIS; +} + +//***************************************************************************** +// +// GPIO_getQualificationMode +// +//***************************************************************************** +GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t qSelIndex; + uint32_t qualRes; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPAQSEL1_GPIO1_S * (pin % 16U); + qSelIndex = GPIO_GPxQSEL_INDEX + ((pin % 32U) / 16U); + + // + // Read the qualification mode register and shift and mask to get the + // value for the specified pin. + // + qualRes = (gpioBaseAddr[qSelIndex] >> shiftAmt) & + (uint32_t)GPIO_GPAQSEL1_GPIO0_M; + return((GPIO_QualificationMode)qualRes); +} + +//***************************************************************************** +// +// GPIO_setQualificationPeriod +// +//***************************************************************************** +void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask, regVal, shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + ASSERT((divider >= 1U) && (divider <= 510U)); + + shiftAmt = (pin % 32U) & ~((uint32_t)0x7U); + pinMask = (uint32_t)0xFFU << shiftAmt; + + // + // Divide divider by two to get the value that needs to go into the field. + // Then shift it into the right place. + // + regVal = (divider / 2U) << shiftAmt; + + // + // Write the divider parameter into the register. + // + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] &= ~pinMask; + gpioBaseAddr[GPIO_GPxCTRL_INDEX] |= regVal; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setControllerCore +// +//***************************************************************************** +void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t cSelIndex; + uint32_t shiftAmt; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + shiftAmt = (uint32_t)GPIO_GPACSEL1_GPIO1_S * (pin % 8U); + cSelIndex = GPIO_GPxCSEL_INDEX + ((pin % 32U) / 8U); + + // + // Write the core parameter into the register. + // + EALLOW; + gpioBaseAddr[cSelIndex] &= ~((uint32_t)GPIO_GPACSEL1_GPIO0_M << shiftAmt); + gpioBaseAddr[cSelIndex] |= (uint32_t)core << shiftAmt; + EDIS; +} + +//***************************************************************************** +// +// GPIO_setAnalogMode +// +//***************************************************************************** +void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode) +{ + volatile uint32_t *gpioBaseAddr; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT((pin == 42U) || (pin == 43U)); + + pinMask = (uint32_t)1U << (pin % 32U); + gpioBaseAddr = (uint32_t *)GPIOCTRL_BASE + + ((pin / 32U) * GPIO_CTRL_REGS_STEP); + + EALLOW; + + // + // Set the analog mode selection. + // + if(mode == GPIO_ANALOG_ENABLED) + { + // + // Enable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] |= pinMask; + } + else + { + // + // Disable analog mode + // + gpioBaseAddr[GPIO_GPxAMSEL_INDEX] &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +// GPIO_setPinConfig +// +//***************************************************************************** +void +GPIO_setPinConfig(uint32_t pinConfig) +{ + uint32_t muxRegAddr; + uint32_t pinMask, shiftAmt; + + muxRegAddr = (uint32_t)GPIOCTRL_BASE + (pinConfig >> 16); + shiftAmt = ((pinConfig >> 8) & (uint32_t)0xFFU); + pinMask = (uint32_t)0x3U << shiftAmt; + + EALLOW; + + // + // Clear fields in MUX register first to avoid glitches + // + HWREG(muxRegAddr) &= ~pinMask; + + // + // Write value into GMUX register + // + HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) = + (HWREG(muxRegAddr + GPIO_MUX_TO_GMUX) & ~pinMask) | + (((pinConfig >> 2) & (uint32_t)0x3U) << shiftAmt); + + // + // Write value into MUX register + // + HWREG(muxRegAddr) |= ((pinConfig & (uint32_t)0x3U) << shiftAmt); + EDIS; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/gpio.h b/gpio_driverlib_cpu1/device/driverlib/gpio.h new file mode 100644 index 0000000..05ae80a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/gpio.h @@ -0,0 +1,1047 @@ +//########################################################################### +// +// FILE: gpio.h +// +// TITLE: C28x GPIO driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef GPIO_H +#define GPIO_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup gpio_api GPIO +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_gpio.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_xint.h" +#include "cpu.h" +#include "xbar.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions to access gpio registers. +// Not intended for use by application code. +// +// Divide by 2 is for C28x which has word access +// +//***************************************************************************** +#define GPIO_CTRL_REGS_STEP ((GPIO_O_GPBCTRL - GPIO_O_GPACTRL) / 2U) +#define GPIO_DATA_REGS_STEP ((GPIO_O_GPBDAT - GPIO_O_GPADAT) / 2U) + +#define GPIO_GPxCTRL_INDEX (GPIO_O_GPACTRL / 2U) +#define GPIO_GPxQSEL_INDEX (GPIO_O_GPAQSEL1 / 2U) +#define GPIO_GPxMUX_INDEX (GPIO_O_GPAMUX1 / 2U) +#define GPIO_GPxDIR_INDEX (GPIO_O_GPADIR / 2U) +#define GPIO_GPxAMSEL_INDEX (0x00000014U / 2U) // Address rsvd for GPAAMSEL +#define GPIO_GPxPUD_INDEX (GPIO_O_GPAPUD / 2U) +#define GPIO_GPxINV_INDEX (GPIO_O_GPAINV / 2U) +#define GPIO_GPxODR_INDEX (GPIO_O_GPAODR / 2U) +#define GPIO_GPxGMUX_INDEX (GPIO_O_GPAGMUX1 / 2U) +#define GPIO_GPxCSEL_INDEX (GPIO_O_GPACSEL1 / 2U) +#define GPIO_GPxLOCK_INDEX (GPIO_O_GPALOCK / 2U) +#define GPIO_GPxCR_INDEX (GPIO_O_GPACR / 2U) + +#define GPIO_GPxDAT_INDEX (GPIO_O_GPADAT / 2U) +#define GPIO_GPxSET_INDEX (GPIO_O_GPASET / 2U) +#define GPIO_GPxCLEAR_INDEX (GPIO_O_GPACLEAR / 2U) +#define GPIO_GPxTOGGLE_INDEX (GPIO_O_GPATOGGLE / 2U) + +#define GPIO_MUX_TO_GMUX (GPIO_O_GPAGMUX1 - GPIO_O_GPAMUX1) + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to GPIO_setPadConfig() as the pinType parameter +// and returned by GPIO_getPadConfig(). +// +//***************************************************************************** +#define GPIO_PIN_TYPE_STD 0x0000U //!< Push-pull output or floating input +#define GPIO_PIN_TYPE_PULLUP 0x0001U //!< Pull-up enable for input +#define GPIO_PIN_TYPE_INVERT 0x0002U //!< Invert polarity on input +#define GPIO_PIN_TYPE_OD 0x0004U //!< Open-drain on output +#endif + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setDirectionMode() as the \e pinIO +//! parameter and returned from GPIO_getDirectionMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_DIR_MODE_IN, //!< Pin is a GPIO input + GPIO_DIR_MODE_OUT //!< Pin is a GPIO output +} GPIO_Direction; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptType() as the \e intType +//! parameter and returned from GPIO_getInterruptType(). +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_TYPE_FALLING_EDGE = 0x00, //!< Interrupt on falling edge + GPIO_INT_TYPE_RISING_EDGE = 0x04, //!< Interrupt on rising edge + GPIO_INT_TYPE_BOTH_EDGES = 0x0C //!< Interrupt on both edges +} GPIO_IntType; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setQualificationMode() as the +//! \e qualification parameter and returned by GPIO_getQualificationMode(). +// +//***************************************************************************** +typedef enum +{ + GPIO_QUAL_SYNC, //!< Synchronization to SYSCLK + GPIO_QUAL_3SAMPLE, //!< Qualified with 3 samples + GPIO_QUAL_6SAMPLE, //!< Qualified with 6 samples + GPIO_QUAL_ASYNC //!< No synchronization +} GPIO_QualificationMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setAnalogMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_ANALOG_DISABLED, //!< Pin is in digital mode + GPIO_ANALOG_ENABLED //!< Pin is in analog mode +} GPIO_AnalogMode; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setControllerCore() as the \e core +//! parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_CORE_CPU1, //!< CPU1 selected as controller core + GPIO_CORE_CPU1_CLA1, //!< CPU1's CLA1 selected as controller core + GPIO_CORE_CPU2, //!< CPU2 selected as controller core + GPIO_CORE_CPU2_CLA1 //!< CPU2's CLA1 selected as controller core +} GPIO_CoreSelect; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_readPortData(), GPIO_setPortPins(), +//! GPIO_clearPortPins(), and GPIO_togglePortPins() as the \e port parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_PORT_A = 0, //!< GPIO port A + GPIO_PORT_B = 1, //!< GPIO port B + GPIO_PORT_C = 2, //!< GPIO port C + GPIO_PORT_D = 3, //!< GPIO port D + GPIO_PORT_E = 4, //!< GPIO port E + GPIO_PORT_F = 5 //!< GPIO port F +} GPIO_Port; + +//***************************************************************************** +// +//! Values that can be passed to GPIO_setInterruptPin(), +//! GPIO_setInterruptType(), GPIO_getInterruptType(), GPIO_enableInterrupt(), +//! GPIO_disableInterrupt(), as the \e extIntNum parameter. +// +//***************************************************************************** +typedef enum +{ + GPIO_INT_XINT1, //!< External Interrupt 1 + GPIO_INT_XINT2, //!< External Interrupt 2 + GPIO_INT_XINT3, //!< External Interrupt 3 + GPIO_INT_XINT4, //!< External Interrupt 4 + GPIO_INT_XINT5 //!< External Interrupt 5 +} GPIO_ExternalIntNum; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks that a pin number is valid for a device. +//! +//! Note that this function reflects the highest possible GPIO number of a +//! device on its biggest package. Check the datasheet to see what the actual +//! range of valid pin numbers is for a specific package. +//! +//! \return None. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +GPIO_isPinValid(uint32_t pin) +{ + return(pin <= 168U); +} +#endif + +//***************************************************************************** +// +//! Sets the interrupt type for the specified pin. +//! +//! \param extIntNum specifies the external interrupt. +//! \param intType specifies the type of interrupt trigger mechanism. +//! +//! This function sets up the various interrupt trigger mechanisms for the +//! specified pin on the selected GPIO port. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! One of the following flags can be used to define the \e intType +//! parameter: +//! +//! - \b GPIO_INT_TYPE_FALLING_EDGE sets detection to edge and trigger to +//! falling +//! - \b GPIO_INT_TYPE_RISING_EDGE sets detection to edge and trigger to rising +//! - \b GPIO_INT_TYPE_BOTH_EDGES sets detection to both edges +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setInterruptType(GPIO_ExternalIntNum extIntNum, GPIO_IntType intType) +{ + // + // Write the selected polarity to the appropriate register. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) = + (HWREGH(XINT_BASE + (uint16_t)extIntNum) & ~XINT_1CR_POLARITY_M) | + (uint16_t)intType; +} + +//***************************************************************************** +// +//! Gets the interrupt type for a pin. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function gets the interrupt type for a interrupt. The interrupt can be +//! configured as a falling-edge, rising-edge, or both-edges detected +//! interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return Returns one of the flags described for GPIO_setInterruptType(). +// +//***************************************************************************** +static inline GPIO_IntType +GPIO_getInterruptType(GPIO_ExternalIntNum extIntNum) +{ + // + // Read the selected polarity from the appropriate register. + // + return((GPIO_IntType)((uint16_t)(HWREGH(XINT_BASE + (uint16_t)extIntNum) & + XINT_1CR_POLARITY_M))); +} + +//***************************************************************************** +// +//! Enables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function enables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_enableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Set the enable bit for the specified interrupt. + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) |= XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Disables the specified external interrupt. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! This function disables the indicated external interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_disableInterrupt(GPIO_ExternalIntNum extIntNum) +{ + // + // Clear the enable bit for the specified interrupt + // + HWREGH(XINT_BASE + (uint16_t)extIntNum) &= ~XINT_1CR_ENABLE; +} + +//***************************************************************************** +// +//! Gets the value of the external interrupt counter. +//! +//! \param extIntNum specifies the external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns external interrupt counter value. +// +//***************************************************************************** +static inline uint16_t +GPIO_getInterruptCounter(GPIO_ExternalIntNum extIntNum) +{ + ASSERT(extIntNum <= GPIO_INT_XINT3); + + // + // Read the counter value from the appropriate register. + // + return((HWREGH(XINT_BASE + XINT_O_1CTR + (uint16_t)extIntNum))); +} + +//***************************************************************************** +// +//! Reads the value present on the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! The value at the specified pin are read, as specified by \e pin. The value +//! is returned for both input and output pins. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return Returns the value in the data register for the specified pin. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + return((gpioDataReg[GPIO_GPxDAT_INDEX] >> (pin % 32U)) & (uint32_t)0x1U); +} + + +//***************************************************************************** +// +//! Writes a value to the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param outVal is the value to write to the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePin(uint32_t pin, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + pinMask = (uint32_t)1U << (pin % 32U); + + if(outVal == 0U) + { + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; + } + else + { + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; + } +} + +//***************************************************************************** +// +//! Toggles the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! Writes the corresponding bit values to the output pin specified by +//! \e pin. Writing to a pin configured as an input pin has no effect. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePin(uint32_t pin) +{ + volatile uint32_t *gpioDataReg; + + // + // Check the arguments. + // + ASSERT(GPIO_isPinValid(pin)); + + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((pin / 32U) * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = (uint32_t)1U << (pin % 32U); +} + +//***************************************************************************** +// +//! Reads the data on the specified port. +//! +//! \param port is the GPIO port being accessed in the form of \b GPIO_PORT_X +//! where X is the port letter. +//! +//! \return Returns the value available on pin for the specified port. Each +//! bit of the the return value represents a pin on the port, where bit 0 +//! represents GPIO port pin 0, bit 1 represents GPIO port pin 1, and so on. +// +//***************************************************************************** +static inline uint32_t +GPIO_readPortData(GPIO_Port port) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and return DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + return(gpioDataReg[GPIO_GPxDAT_INDEX]); +} + + +//***************************************************************************** +// +//! Writes a value to the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param outVal is the value to write to the port. +//! +//! This function writes the value \e outVal to the port specified by the +//! \e port parameter which takes a value in the form of \b GPIO_PORT_X where X +//! is the port letter. For example, use \b GPIO_PORT_A to affect port A +//! (GPIOs 0-31). +//! +//! The \e outVal is a bit-packed value, where each bit represents a bit on a +//! GPIO port. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO port +//! pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_writePortData(GPIO_Port port, uint32_t outVal) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to DATA. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxDAT_INDEX] = outVal; +} + +//***************************************************************************** +// +//! Sets all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function sets all of the pins specified by the \e pinMask parameter on +//! the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be set. Bit 0 represents GPIO port pin 0, bit 1 represents GPIO +//! port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_setPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to SET. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxSET_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Clears all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function clears all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is \b set +//! identifies the pin to be cleared. Bit 0 represents GPIO port pin 0, bit 1 +//! represents GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_clearPortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to CLEAR. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxCLEAR_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Toggles all of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function toggles all of the pins specified by the \e pinMask parameter +//! on the port specified by the \e port parameter which takes a value in the +//! form of \b GPIO_PORT_X where X is the port letter. For example, use +//! \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be toggled. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_togglePortPins(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to TOGGLE. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIODATA_BASE) + + ((uint32_t)port * GPIO_DATA_REGS_STEP); + + gpioDataReg[GPIO_GPxTOGGLE_INDEX] = pinMask; +} + +//***************************************************************************** +// +//! Locks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function locks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that this function is for locking the configuration of a pin such as +//! the pin muxing, direction, open drain mode, and other settings. It does not +//! affect the ability to change the value of the pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_lockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Unlocks the configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function unlocks the configuration registers of the pins specified by +//! the \e pinMask parameter on the port specified by the \e port parameter +//! which takes a value in the form of \b GPIO_PORT_X where X is the port +//! letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be unlocked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_unlockPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxLOCK_INDEX] &= ~pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Commits the lock configuration of the specified pins on the specified port. +//! +//! \param port is the GPIO port being accessed. +//! \param pinMask is a mask of which of the 32 pins on the port are affected. +//! +//! This function commits the lock configuration registers of the pins +//! specified by the \e pinMask parameter on the port specified by the \e port +//! parameter which takes a value in the form of \b GPIO_PORT_X where X is the +//! port letter. For example, use \b GPIO_PORT_A to affect port A (GPIOs 0-31). +//! +//! The \e pinMask is a bit-packed value, where each bit that is set identifies +//! the pin to be locked. Bit 0 represents GPIO port pin 0, bit 1 represents +//! GPIO port pin 1, 0xFFFFFFFF represents all pins on that port, and so on. +//! +//! Note that once this function is called, GPIO_lockPortConfig() and +//! GPIO_unlockPortConfig() will no longer have any effect on the specified +//! pins. +//! +//! \return None. +// +//***************************************************************************** +static inline void +GPIO_commitPortConfig(GPIO_Port port, uint32_t pinMask) +{ + volatile uint32_t *gpioDataReg; + + // + // Get the starting address of the port's registers and write to the lock. + // + gpioDataReg = (uint32_t *)((uintptr_t)GPIOCTRL_BASE) + + ((uint32_t)port * GPIO_CTRL_REGS_STEP); + + EALLOW; + gpioDataReg[GPIO_GPxCR_INDEX] |= pinMask; + EDIS; +} + +//***************************************************************************** +// +//! Sets the direction and mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinIO is the pin direction mode. +//! +//! This function configures the specified pin on the selected GPIO port as +//! either input or output. +//! +//! The parameter \e pinIO is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_DIR_MODE_IN +//! - \b GPIO_DIR_MODE_OUT +//! +//! where \b GPIO_DIR_MODE_IN specifies that the pin is programmed as an input +//! and \b GPIO_DIR_MODE_OUT specifies that the pin is programmed as an output. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setDirectionMode(uint32_t pin, GPIO_Direction pinIO); + +//***************************************************************************** +// +//! Gets the direction mode of a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function gets the direction mode for a specified pin. The pin can be +//! configured as either an input or output The type of direction is returned +//! as an enumerated data type. +//! +//! \return Returns one of the enumerated data types described for +//! GPIO_setDirectionMode(). +// +//***************************************************************************** +extern GPIO_Direction +GPIO_getDirectionMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the pin for the specified external interrupt. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param extIntNum specifies the external interrupt. +//! +//! This function sets which pin triggers the selected external interrupt. +//! +//! The following defines can be used to specify the external interrupt for the +//! \e extIntNum parameter: +//! +//! - \b GPIO_INT_XINT1 +//! - \b GPIO_INT_XINT2 +//! - \b GPIO_INT_XINT3 +//! - \b GPIO_INT_XINT4 +//! - \b GPIO_INT_XINT5 +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \sa XBAR_setInputPin() +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setInterruptPin(uint32_t pin, GPIO_ExternalIntNum extIntNum); + +//***************************************************************************** +// +//! Sets the pad configuration for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param pinType specifies the pin type. +//! +//! This function sets the pin type for the specified pin. The parameter +//! \e pinType can be the following values: +//! +//! - \b GPIO_PIN_TYPE_STD specifies a push-pull output or a floating input +//! - \b GPIO_PIN_TYPE_PULLUP specifies the pull-up is enabled for an input +//! - \b GPIO_PIN_TYPE_OD specifies an open-drain output pin +//! - \b GPIO_PIN_TYPE_INVERT specifies inverted polarity on an input +//! +//! \b GPIO_PIN_TYPE_INVERT may be OR-ed with \b GPIO_PIN_TYPE_STD or +//! \b GPIO_PIN_TYPE_PULLUP. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPadConfig(uint32_t pin, uint32_t pinType); + +//***************************************************************************** +// +//! Gets the pad configuration for a pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! This function returns the pin type for the specified pin. The value +//! returned corresponds to the values used in GPIO_setPadConfig(). +//! +//! \return Returns a bit field of the values \b GPIO_PIN_TYPE_STD, +//! \b GPIO_PIN_TYPE_PULLUP, \b GPIO_PIN_TYPE_OD, and \b GPIO_PIN_TYPE_INVERT. +// +//***************************************************************************** +extern uint32_t +GPIO_getPadConfig(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification mode for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param qualification specifies the qualification mode of the pin. +//! +//! This function sets the qualification mode for the specified pin. The +//! parameter \e qualification can be one of the following values: +//! - \b GPIO_QUAL_SYNC +//! - \b GPIO_QUAL_3SAMPLE +//! - \b GPIO_QUAL_6SAMPLE +//! - \b GPIO_QUAL_ASYNC +//! +//! To set the qualification sampling period, use +//! GPIO_setQualificationPeriod(). +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationMode(uint32_t pin, GPIO_QualificationMode qualification); + +//***************************************************************************** +// +//! Gets the qualification type for the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! +//! \return Returns the qualification mode in the form of one of the values +//! \b GPIO_QUAL_SYNC, \b GPIO_QUAL_3SAMPLE, \b GPIO_QUAL_6SAMPLE, or +//! \b GPIO_QUAL_ASYNC. +// +//***************************************************************************** +extern GPIO_QualificationMode +GPIO_getQualificationMode(uint32_t pin); + +//***************************************************************************** +// +//! Sets the qualification period for a set of pins +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param divider specifies the output drive strength. +//! +//! This function sets the qualification period for a set of \b 8 \b pins, +//! specified by the \e pin parameter. For instance, passing in 3 as the value +//! of \e pin will set the qualification period for GPIO0 through GPIO7, and a +//! value of 98 will set the qualification period for GPIO96 through GPIO103. +//! This is because the register field that configures the divider is shared. +//! +//! To think of this in terms of an equation, configuring \e pin as \b n will +//! configure GPIO (n & ~(7)) through GPIO ((n & ~(7)) + 7). +//! +//! \e divider is the value by which the frequency of SYSCLKOUT is divided. It +//! can be 1 or an even value between 2 and 510 inclusive. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setQualificationPeriod(uint32_t pin, uint32_t divider); + +//***************************************************************************** +// +//! Selects the controller core of a specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param core is the core that is controller of the specified pin. +//! +//! This function configures which core owns the specified pin's data registers +//! (DATA, SET, CLEAR, and TOGGLE). The \e core parameter is an enumerated data +//! type that specifies the core, such as \b GPIO_CORE_CPU1_CLA1 to make CPU1's +//! CLA1 controller of the pin. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setControllerCore(uint32_t pin, GPIO_CoreSelect core); + +//***************************************************************************** +// +//! Sets the analog mode of the specified pin. +//! +//! \param pin is the identifying GPIO number of the pin. +//! \param mode is the selected analog mode. +//! +//! This function configures the specified pin for either analog or digital +//! mode. Not all GPIO pins have the ability to be switched to analog mode, +//! so refer to the technical reference manual for details. This setting should +//! be thought of as another level of muxing. +//! +//! The parameter \e mode is an enumerated data type that can be one of the +//! following values: +//! +//! - \b GPIO_ANALOG_DISABLED - Pin is in digital mode +//! - \b GPIO_ANALOG_ENABLED - Pin is in analog mode +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \b Note: The pin parameter is applicable for both AIO and GPIO because +//! the GPAxMSEL.GPIOy register configures for both +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setAnalogMode(uint32_t pin, GPIO_AnalogMode mode); + +//***************************************************************************** +// +//! Configures the alternate function of a GPIO pin. +//! +//! \param pinConfig is the pin configuration value, specified as only one +//! of the \b GPIO_#_???? values. +//! +//! This function configures the pin mux that selects the peripheral function +//! associated with a particular GPIO pin. Only one peripheral function at a +//! time can be associated with a GPIO pin, and each peripheral function should +//! only be associated with a single GPIO pin at a time (despite the fact that +//! many of them can be associated with more than one GPIO pin). +//! +//! The available mappings are supplied in pin_map.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +GPIO_setPinConfig(uint32_t pinConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // GPIO_H diff --git a/gpio_driverlib_cpu1/device/driverlib/hrpwm.c b/gpio_driverlib_cpu1/device/driverlib/hrpwm.c new file mode 100644 index 0000000..04aa22c --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/hrpwm.c @@ -0,0 +1,47 @@ +//########################################################################### +// +// FILE: hrpwm.c +// +// TITLE: C28x HRPWM driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "hrpwm.h" + +// +// All the API functions are in-lined in hrpwm.h +// diff --git a/gpio_driverlib_cpu1/device/driverlib/hrpwm.h b/gpio_driverlib_cpu1/device/driverlib/hrpwm.h new file mode 100644 index 0000000..2561d67 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/hrpwm.h @@ -0,0 +1,1657 @@ +//############################################################################# +// +// FILE: hrpwm.h +// +// TITLE: C28x HRPWM Driver +// +//############################################################################# +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//############################################################################# + +#ifndef HRPWM_H +#define HRPWM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup hrpwm_api HRPWM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_hrpwm.h" +#include "cpu.h" +#include "debug.h" +#include "epwm.h" +#include "hrpwm.h" + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect(), +//! HRPWM_setMEPControlMode(), HRPWM_setCounterCompareShadowLoadEvent() +//! as the \e channel parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_CHANNEL_A = 0, //!< HRPWM A + HRPWM_CHANNEL_B = 8 //!< HRPWM B +} HRPWM_Channel; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setMEPEdgeSelect() as the \e mepEdgeMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_MEP_CTRL_DISABLE = 0, + //! MEP controls rising edge + HRPWM_MEP_CTRL_RISING_EDGE = 1, + //! MEP controls falling edge + HRPWM_MEP_CTRL_FALLING_EDGE = 2, + //! MEP controls both rising and falling edge + HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE = 3 +} HRPWM_MEPEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setHRMEPCtrlMode() as the \e +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! CMPAHR/CMPBHR or TBPRDHR controls MEP edge + HRPWM_MEP_DUTY_PERIOD_CTRL = 0, + //! TBPHSHR controls MEP edge + HRPWM_MEP_PHASE_CTRL = 1 +} HRPWM_MEPCtrlMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareShadowLoadEvent(), +//! HRPWM_setRisingEdgeDelayLoadMode() and HRPWM_setFallingEdgeDelayLoadMode +//! as the \e loadEvent parameter. +// +//***************************************************************************** +typedef enum +{ + //! load when counter equals zero + HRPWM_LOAD_ON_CNTR_ZERO = 0, + //! load when counter equals period + HRPWM_LOAD_ON_CNTR_PERIOD = 1, + //! load when counter equals zero or period + HRPWM_LOAD_ON_CNTR_ZERO_PERIOD = 2, +} HRPWM_LoadMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setChannelBOutputPath() as the \e +//! outputOnB parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_OUTPUT_ON_B_NORMAL = 0, //!< ePWMxB output is normal. + HRPWM_OUTPUT_ON_B_INV_A = 1 //!< ePWMxB output is inverted + //!< version of ePWMxA signal +} HRPWM_ChannelBOutput; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setSyncPulseSource() as the \e +//! syncPulseSource parameter. +// +//***************************************************************************** +typedef enum +{ + //! Counter equals Period + HRPWM_PWMSYNC_SOURCE_PERIOD = 0, + //! Counter equals zero + HRPWM_PWMSYNC_SOURCE_ZERO = 1, + //! Counter equals COMPC when counting up + HRPWM_PWMSYNC_SOURCE_COMPC_UP = 4, + //! Counter equals COMPC when counting down + HRPWM_PWMSYNC_SOURCE_COMPC_DOWN = 5, + //! Counter equals COMPD when counting up + HRPWM_PWMSYNC_SOURCE_COMPD_UP = 6, + //! Counter equals COMPD when counting down + HRPWM_PWMSYNC_SOURCE_COMPD_DOWN = 7 +} HRPWM_SyncPulseSource; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setCounterCompareValue() as the \e +//! compModule parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_COUNTER_COMPARE_A = 0, //!< counter compare A + HRPWM_COUNTER_COMPARE_B = 4 //!< counter compare B +} HRPWM_CounterCompareModule; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_setDeadbandMEPEdgeSelect() as the \e +//! mepDBEdge. +// +//***************************************************************************** +typedef enum +{ + //! HRPWM is disabled + HRPWM_DB_MEP_CTRL_DISABLE = 0, + //! MEP controls Rising Edge Delay + HRPWM_DB_MEP_CTRL_RED = 1, + //! MEP controls Falling Edge Delay + HRPWM_DB_MEP_CTRL_FED = 2, + //! MEP controls both Falling and Rising edge delay + HRPWM_DB_MEP_CTRL_RED_FED = 3 +} HRPWM_MEPDeadBandEdgeMode; + +//***************************************************************************** +// +//! Values that can be passed to HRPWM_lockRegisters() as the \e registerGroup +//! parameter. +// +//***************************************************************************** +typedef enum +{ + HRPWM_REGISTER_GROUP_HRPWM = 0x1, //!< HRPWM register group + HRPWM_REGISTER_GROUP_GLOBAL_LOAD = 0x2, //!< Global load register group + HRPWM_REGISTER_GROUP_TRIP_ZONE = 0x4, //!< Trip zone register group + HRPWM_REGISTER_GROUP_TRIP_ZONE_CLEAR = 0x8, //!< Trip zone clear group + HRPWM_REGISTER_GROUP_DIGITAL_COMPARE = 0x10 //!< Digital compare group +} HRPWM_LockRegisterGroup; + +//***************************************************************************** +// +// Functions APIs shared with ePWM module +// +//***************************************************************************** + +// +// Time Base Sub Module related APIs +// +#define HRPWM_setTimeBaseCounter EPWM_setTimeBaseCounter +#define HRPWM_setCountModeAfterSync EPWM_setCountModeAfterSync +#define HRPWM_setClockPrescaler EPWM_setClockPrescaler +#define HRPWM_swForceSyncPulse EPWM_forceSyncPulse +#define HRPWM_setSyncOutPulseMode EPWM_setSyncOutPulseMode +#define HRPWM_setPeriodLoadMode EPWM_setPeriodLoadMode +#define HRPWM_setTimeBaseCounterMode EPWM_setTimeBaseCounterMode +#define HRPWM_selectPeriodLoadEvent EPWM_selectPeriodLoadEvent +#define HRPWM_enableOneShotSync EPWM_enableOneShotSync +#define HRPWM_disableOneShotSync EPWM_disableOneShotSync +#define HRPWM_startOneShotSync EPWM_startOneShotSync +#define HRPWM_getTimeBaseCounterOverflowStatus \ + EPWM_getTimeBaseCounterOverflowStatus +#define HRPWM_clearTimeBaseCounterOverflowEvent \ + EPWM_clearTimeBaseCounterOverflowEvent +#define HRPWM_getSyncStatus EPWM_getSyncStatus +#define HRPWM_clearSyncEvent EPWM_clearSyncEvent +#define HRPWM_getTimeBaseCounterDirection EPWM_getTimeBaseCounterDirection +#define HRPWM_setupEPWMLinks EPWM_setupEPWMLinks +#define HRPWM_setCounterCompareShadowLoadMode \ + EPWM_setCounterCompareShadowLoadMode +#define HRPWM_disableCounterCompareShadowLoadMode \ + EPWM_disableCounterCompareShadowLoadMode +#define HRPWM_getCounterCompareShadowStatus \ + EPWM_getCounterCompareShadowStatus + +// +// Action Qualifier module related APIs +// +#define HRPWM_setActionQualifierShadowLoadMode \ + EPWM_setActionQualifierShadowLoadMode +#define HRPWM_disableActionQualifierShadowLoadMode \ + EPWM_disableActionQualifierShadowLoadMode +#define HRPWM_setActionQualifierT1TriggerSource \ + EPWM_setActionQualifierT1TriggerSource +#define HRPWM_setActionQualifierT2TriggerSource \ + EPWM_setActionQualifierT2TriggerSource +#define HRPWM_setActionQualifierAction EPWM_setActionQualifierAction +#define HRPWM_setActionQualifierContSWForceShadowMode \ + EPWM_setActionQualifierContSWForceShadowMode +#define HRPWM_setActionQualifierContSWForceAction \ + EPWM_setActionQualifierContSWForceAction +/* HRPWM_setActionQualifierSwAction is kept for compatibility, +use HRPWM_setActionQualifierSWAction*/ +#define HRPWM_setActionQualifierSwAction EPWM_setActionQualifierSwAction +#define HRPWM_setActionQualifierSWAction EPWM_setActionQualifierSWAction +/* HRPWM_forceActionQualifierSwAction is kept for compatibility, +use HRPWM_forceActionQualifierSWAction*/ +#define HRPWM_forceActionQualifierSwAction EPWM_forceActionQualifierSwAction +#define HRPWM_forceActionQualifierSWAction EPWM_forceActionQualifierSWAction +// +// Dead Band Module related APIs +// +#define HRPWM_setDeadBandOutputSwapMode EPWM_setDeadBandOutputSwapMode +#define HRPWM_setDeadBandDelayMode EPWM_setDeadBandDelayMode +#define HRPWM_setDeadBandDelayPolarity EPWM_setDeadBandDelayPolarity +#define HRPWM_setRisingEdgeDeadBandDelayInput \ + EPWM_setRisingEdgeDeadBandDelayInput +#define HRPWM_setFallingEdgeDeadBandDelayInput \ + EPWM_setFallingEdgeDeadBandDelayInput +#define HRPWM_setDeadBandControlShadowLoadMode \ + EPWM_setDeadBandControlShadowLoadMode +#define HRPWM_disableDeadBandControlShadowLoadMode \ + EPWM_disableDeadBandControlShadowLoadMode +#define HRPWM_setRisingEdgeDelayCountShadowLoadMode \ + EPWM_setRisingEdgeDelayCountShadowLoadMode +#define HRPWM_disableRisingEdgeDelayCountShadowLoadMode \ + EPWM_disableRisingEdgeDelayCountShadowLoadMode +#define HRPWM_setFallingEdgeDelayCountShadowLoadMode \ + EPWM_setFallingEdgeDelayCountShadowLoadMode +#define HRPWM_disableFallingEdgeDelayCountShadowLoadMode \ + EPWM_disableFallingEdgeDelayCountShadowLoadMode +#define HRPWM_setDeadBandCounterClock EPWM_setDeadBandCounterClock +#define HRPWM_setRisingEdgeDelayCount EPWM_setRisingEdgeDelayCount +#define HRPWM_setFallingEdgeDelayCount EPWM_setFallingEdgeDelayCount + +// +// Chopper module related APIs +// +#define HRPWM_enableChopper EPWM_enableChopper +#define HRPWM_disableChopper EPWM_disableChopper +#define HRPWM_setChopperDutyCycle EPWM_setChopperDutyCycle +#define HRPWM_setChopperFreq EPWM_setChopperFreq +#define HRPWM_setChopperFirstPulseWidt EPWM_setChopperFirstPulseWidth + +// +// Trip Zone module related APIs +// +#define HRPWM_enableTripZoneSignals EPWM_enableTripZoneSignals +#define HRPWM_disableTripZoneSignals EPWM_disableTripZoneSignals +#define HRPWM_setTripZoneDigitalCompareEventCondition \ + EPWM_setTripZoneDigitalCompareEventCondition +#define HRPWM_enableTripZoneAdvAction EPWM_enableTripZoneAdvAction +#define HRPWM_disableTripZoneAdvAction EPWM_disableTripZoneAdvAction +#define HRPWM_setTripZoneAction EPWM_setTripZoneAction +#define HRPWM_setTripZoneAdvAction EPWM_setTripZoneAdvAction +#define HRPWM_setTripZoneAdvDigitalCompareActionA \ + EPWM_setTripZoneAdvDigitalCompareActionA +#define HRPWM_setTripZoneAdvDigitalCompareActionB \ + EPWM_setTripZoneAdvDigitalCompareActionB +#define HRPWM_enableTripZoneInterrupt EPWM_enableTripZoneInterrupt +#define HRPWM_disableTripZoneInterrupt EPWM_disableTripZoneInterrupt + +// +// HRPWM_getTripZoneInterruptStatus API define is obsolete please use +// HRPWM_getTripZoneFlagStatus going forward. +// +#define HRPWM_getTripZoneInterruptStatus EPWM_getTripZoneFlagStatus +#define HRPWM_getTripZoneFlagStatus EPWM_getTripZoneFlagStatus + +// +// HRPWM_getCycleByCycleTripZoneInterruptStatus API define is obsolete +// please use HRPWM_getCycleByCycleTripZoneFlagStatus going forward. +// +#define HRPWM_getCycleByCycleTripZoneInterruptStatus \ + HRPWM_getCycleByCycleTripZoneFlagStatus +#define HRPWM_getCycleByCycleTripZoneFlagStatus \ + EPWM_getCycleByCycleTripZoneFlagStatus + +// +// HRPWM_getOneShotTripZoneInterruptStatus is obsolete please use +// HRPWM_getOneShotTripZoneFlagStatus going forward. +// +#define HRPWM_getOneShotTripZoneInterruptStatus \ + HRPWM_getOneShotTripZoneFlagStatus +#define HRPWM_getOneShotTripZoneFlagStatus \ + EPWM_getOneShotTripZoneFlagStatus +#define HRPWM_selectCycleByCycleTripZoneClearEvent \ + EPWM_selectCycleByCycleTripZoneClearEvent + +// +// HRPWM_clearTripZoneInterruptFlag is obsolete please use +// HRPWM_clearTripZoneFlag going forward. +// +#define HRPWM_clearTripZoneInterruptFlag HRPWM_clearTripZoneFlag +#define HRPWM_clearTripZoneFlag EPWM_clearTripZoneFlag + +// +// HRPWM_clearCycleByCycleTripZoneInterruptFlag is obsolete please use +// HRPWM_clearCycleByCycleTripZoneFlag going forward. +// +#define HRPWM_clearCycleByCycleTripZoneInterruptFlag \ + HRPWM_clearCycleByCycleTripZoneFlag +#define HRPWM_clearCycleByCycleTripZoneFlag \ + EPWM_clearCycleByCycleTripZoneFlag + +// +// HRPWM_clearOneShotTripZoneInterruptFlag is obsolete please use +// HRPWM_clearOneShotTripZoneFlag going forward. +// +#define HRPWM_clearOneShotTripZoneInterruptFlag \ + HRPWM_clearOneShotTripZoneFlag +#define HRPWM_clearOneShotTripZoneFlag \ + EPWM_clearOneShotTripZoneFlag +#define HRPWM_forceTripZoneEvent EPWM_forceTripZoneEvent + +// +// Event Trigger related APIs +// +#define HRPWM_enableInterrupt EPWM_enableInterrupt +#define HRPWM_disableInterrupt EPWM_disableInterrupt +#define HRPWM_setInterruptSource EPWM_setInterruptSource +#define HRPWM_setInterruptEventCount EPWM_setInterruptEventCount +#define HRPWM_getEventTriggerInterruptStatus \ + EPWM_getEventTriggerInterruptStatus +#define HRPWM_clearEventTriggerInterruptFlag \ + EPWM_clearEventTriggerInterruptFlag +#define HRPWM_enableInterruptEventCountInit \ + EPWM_enableInterruptEventCountInit +#define HRPWM_disableInterruptEventCountInit \ + EPWM_disableInterruptEventCountInit +#define HRPWM_forceInterruptEventCountInit \ + EPWM_forceInterruptEventCountInit +#define HRPWM_setInterruptEventCountInitValue \ + EPWM_setInterruptEventCountInitValue +#define HRPWM_getInterruptEventCount EPWM_getInterruptEventCount +#define HRPWM_forceEventTriggerInterrupt EPWM_forceEventTriggerInterrupt + +// +// ADC SOC configuration related APIs +// +#define HRPWM_enableADCTrigger EPWM_enableADCTrigger +#define HRPWM_disableADCTrigger EPWM_disableADCTrigger +#define HRPWM_setADCTriggerSource EPWM_setADCTriggerSource +#define HRPWM_setADCTriggerEventPrescale EPWM_setADCTriggerEventPrescale +#define HRPWM_getADCTriggerFlagStatus EPWM_getADCTriggerFlagStatus +#define HRPWM_clearADCTriggerFlag EPWM_clearADCTriggerFlag +#define HRPWM_enableADCTriggerEventCountInit \ + EPWM_enableADCTriggerEventCountInit +#define HRPWM_disableADCTriggerEventCountInit \ + EPWM_disableADCTriggerEventCountInit +#define HRPWM_forceADCTriggerEventCountInit \ + EPWM_forceADCTriggerEventCountInit +#define HRPWM_setADCTriggerEventCountInitValue \ + EPWM_setADCTriggerEventCountInitValue +#define HRPWM_getADCTriggerEventCount EPWM_getADCTriggerEventCount +#define HRPWM_forceADCTrigger EPWM_forceADCTrigger + +// +// Digital Compare Module related APIs +// +#define HRPWM_selectDigitalCompareTripInput \ + EPWM_selectDigitalCompareTripInput +#define HRPWM_enableDigitalCompareBlankingWindow \ + EPWM_enableDigitalCompareBlankingWindow +#define HRPWM_disableDigitalCompareBlankingWindow \ + EPWM_disableDigitalCompareBlankingWindow +#define HRPWM_enableDigitalCompareWindowInverseMode \ + EPWM_enableDigitalCompareWindowInverseMode +#define HRPWM_disableDigitalCompareWindowInverseMode \ + EPWM_disableDigitalCompareWindowInverseMode +#define HRPWM_setDigitalCompareBlankingEvent \ + EPWM_setDigitalCompareBlankingEvent +#define HRPWM_setDigitalCompareFilterInput \ + EPWM_setDigitalCompareFilterInput +#define HRPWM_setDigitalCompareWindowOffset \ + EPWM_setDigitalCompareWindowOffset +#define HRPWM_setDigitalCompareWindowLength \ + EPWM_setDigitalCompareWindowLength +#define HRPWM_getDigitalCompareBlankingWindowOffsetCount \ + EPWM_getDigitalCompareBlankingWindowOffsetCount +#define HRPWM_getDigitalCompareBlankingWindowLengthCount \ + EPWM_getDigitalCompareBlankingWindowLengthCount +#define HRPWM_setDigitalCompareEventSource \ + EPWM_setDigitalCompareEventSource +#define HRPWM_setDigitalCompareEventSyncMode \ + EPWM_setDigitalCompareEventSyncMode +#define HRPWM_enableDigitalCompareADCTrigger \ + EPWM_enableDigitalCompareADCTrigger +#define HRPWM_disableDigitalCompareADCTrigger \ + EPWM_disableDigitalCompareADCTrigger +#define HRPWM_enableDigitalCompareSyncEvent \ + EPWM_enableDigitalCompareSyncEvent +#define HRPWM_disableDigitalCompareSyncEvent \ + EPWM_disableDigitalCompareSyncEvent +#define HRPWM_enableDigitalCompareCounterCapture \ + EPWM_enableDigitalCompareCounterCapture +#define HRPWM_disableDigitalCompareCounterCapture \ + EPWM_disableDigitalCompareCounterCapture +#define HRPWM_setDigitalCompareCounterShadowMode \ + EPWM_setDigitalCompareCounterShadowMode +#define HRPWM_getDigitalCompareCaptureStatus \ + EPWM_getDigitalCompareCaptureStatus +#define HRPWM_getDigitalCompareCaptureCount \ + EPWM_getDigitalCompareCaptureCount +#define HRPWM_enableDigitalCompareTripCombinationInput \ + EPWM_enableDigitalCompareTripCombinationInput +#define HRPWM_disableDigitalCompareTripCombinationInput \ + EPWM_disableDigitalCompareTripCombinationInput + +// +// Valley switching related APIs +// +#define HRPWM_enableValleyCapture EPWM_enableValleyCapture +#define HRPWM_disableValleyCapture EPWM_disableValleyCapture +#define HRPWM_startValleyCapture EPWM_startValleyCapture +#define HRPWM_setValleyTriggerSource EPWM_setValleyTriggerSource +#define HRPWM_setValleyTriggerEdgeCounts EPWM_setValleyTriggerEdgeCounts +#define HRPWM_enableValleyHWDelay EPWM_enableValleyHWDelay +#define HRPWM_disableValleyHWDelay EPWM_disableValleyHWDelay +#define HRPWM_setValleySWDelayValue EPWM_setValleySWDelayValue +#define HRPWM_setValleyDelayDivider EPWM_setValleyDelayDivider +#define HRPWM_getValleyEdgeStatus EPWM_getValleyEdgeStatus +#define HRPWM_getValleyCount EPWM_getValleyCount +#define HRPWM_getValleyHWDelay EPWM_getValleyHWDelay + +// +// Global Load feature related APIs +// +#define HRPWM_enableGlobalLoad EPWM_enableGlobalLoad +#define HRPWM_disableGlobalLoad EPWM_disableGlobalLoad +#define HRPWM_setGlobalLoadTrigger EPWM_setGlobalLoadTrigger +#define HRPWM_setGlobalLoadEventPrescale EPWM_setGlobalLoadEventPrescale +#define HRPWM_getGlobalLoadEventCount EPWM_getGlobalLoadEventCount +#define HRPWM_disableGlobalLoadOneShotMode EPWM_disableGlobalLoadOneShotMode +#define HRPWM_enableGlobalLoadOneShotMode EPWM_enableGlobalLoadOneShotMode +#define HRPWM_setGlobalLoadOneShotLatch EPWM_setGlobalLoadOneShotLatch +#define HRPWM_forceGlobalLoadOneShotEvent EPWM_forceGlobalLoadOneShotEvent +#define HRPWM_enableGlobalLoadRegisters EPWM_enableGlobalLoadRegisters +#define HRPWM_disableGlobalLoadRegisters EPWM_disableGlobalLoadRegisters +#define HRPWM_setEmulationMode EPWM_setEmulationMode + +//***************************************************************************** +// +// Prototypes for the API. +// +//***************************************************************************** + +//***************************************************************************** +// +//! \internal +//! Checks HRPWM base address. +//! +//! \param base specifies the HRPWM module base address. +//! +//! This function determines if an HRPWM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool HRPWM_isBaseValid(uint32_t base) +{ + return((base == EPWM1_BASE) || (base == EPWM2_BASE) || + (base == EPWM3_BASE) || (base == EPWM4_BASE) || + (base == EPWM5_BASE) || (base == EPWM6_BASE) || + (base == EPWM7_BASE) || (base == EPWM8_BASE)); +} +#endif +//***************************************************************************** +// +//! Sets the consolidated phase shift value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param phaseCount is the consolidated phase shift count value. +//! +//! This function sets the consolidated phase shift value, that is, both TBPHS +//! and TBPHSHR values are configured together. +//! +//! Call EPWM_enablePhaseShiftLoad & HRPWM_enableHRPhaseShiftLoad() functions +//! to enable loading of the phaseCount in high resolution mode. +//! +//! \b Note: phaseCount is a 24-bit value. +//! \b Note: For configuring TBPHS = 0x3C, TBPHSHR = 0x2; +//! phaseCount = 0x3C02 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setPhaseShift(uint32_t base, uint32_t phaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(phaseCount < 0x1000000U); + + // + // Write to TBPHS:TBPHSHR bits + // + HWREG(base + HRPWM_O_TBPHS) = phaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution phase shift value. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPhaseCount is the high resolution phase shift count value. +//! +//! This function sets only the high resolution phase shift(TBPHSHR) value. +//! Call the HRPWM_enableHRPhaseShiftLoad() function to enable loading of +//! the hrPhaseCount. +//! +//! \b Note: hrPhaseCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResPhaseShiftOnly(uint32_t base, uint16_t hrPhaseCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPhaseCount < 256U); + + // + // Write to TBPHSHR bits + // + HWREGH(base + HRPWM_O_TBPHS) = hrPhaseCount << 8U; +} + +//***************************************************************************** +// +//! Sets the consolidated period of time base counter used in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param periodCount is the consolidated period count value. +//! +//! This function sets the consolidated period of time base counter value +//! (TBPRD:TBPRDHR) required in high resolution mode. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct periodCount. +//! +//! \b Note: periodCount is a 24 bit value. +//! \b Note: For configuring TBPRD = 0x3C, TBPRDHR = 0xA; +//! periodCount = 0x3C0A +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTimeBasePeriod(uint32_t base, uint32_t periodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(periodCount < 0x1000000U); + + // + // Write to TBPRD:TBPRDHR bits + // + HWREG(base + HRPWM_O_TBPRDHR) = periodCount << 8U; +} + +//***************************************************************************** +// +//! Sets only the high resolution time base counter. +//! +//! \param base is the base address of the EPWM module. +//! \param hrPeriodCount is the high resolution period count value. +//! +//! This function sets only the high resolution time base counter(TBPRDHR) +//! value. +//! +//! User should map the desired period or frequency of the waveform into +//! the correct hrPeriodCount. +//! +//! \b Note: hrPeriodCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResTimeBasePeriodOnly(uint32_t base, uint16_t hrPeriodCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrPeriodCount < 256U); + + // + // Write to TBPRDHR bits + // + HWREGH(base + HRPWM_O_TBPRDHR) = hrPeriodCount << 8U; +} + +//***************************************************************************** +// +//! Gets the consolidated time base period count used in HR mode +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets the consolidated time base period(TBPRD:TBPRDHR) value +//! used in high resolution mode. +//! +//! \return The consolidated time base period count value. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getTimeBasePeriod(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRD:TBPRDHR bit + // + return(HWREG(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Gets the only the high resolution time base period count. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function gets only the high resolution time base period(TBPRDHR) value. +//! +//! \return The high resolution time base period count value. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResTimeBasePeriodOnly(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Read from TBPRDHR bit + // + return(HWREGH(base + HRPWM_O_TBPRDHR) >> 8U); +} + +//***************************************************************************** +// +//! Sets the high resolution edge controlled by MEP (Micro Edge Positioner). +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepEdgeMode edge of the PWM that is controlled by MEP (Micro Edge +//! Positioner). +//! +//! This function sets the edge of the PWM that is controlled by MEP (Micro +//! Edge Positioner). Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepEdgeMode +//! - HRPWM_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_MEP_CTRL_RISING_EDGE - MEP (Micro Edge Positioner) +//! controls rising edge. +//! - HRPWM_MEP_CTRL_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls falling edge. +//! - HRPWM_MEP_CTRL_RISING_AND_FALLING_EDGE - MEP (Micro Edge Positioner) +//! controls both edges. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPEdgeSelect(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPEdgeMode mepEdgeMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << (uint16_t)channel )) | + ((uint16_t)mepEdgeMode << (uint16_t)channel)); + EDIS; +} + +//***************************************************************************** +// +//! Sets the MEP (Micro Edge Positioner) control mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param mepCtrlMode is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the mode (register type) the MEP (Micro Edge Positioner) +//! will control. Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - mepCtrlMode +//! - HRPWM_MEP_DUTY_PERIOD_CTRL - MEP (Micro Edge Positioner) is +//! controlled by value of CMPAHR/ +//! CMPBHR(depending on the value of +//! channel) or TBPRDHR. +//! - HRPWM_MEP_PHASE_CTRL - MEP (Micro Edge Positioner) is +//! controlled by TBPHSHR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPControlMode(uint32_t base, HRPWM_Channel channel, + HRPWM_MEPCtrlMode mepCtrlMode) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the MEP control + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x1U << ((uint16_t)channel + 2U))) | + ((uint16_t)mepCtrlMode << ((uint16_t)channel + 2U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution comparator load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param channel is high resolution period module. +//! \param loadEvent is the MEP (Micro Edge Positioner) control mode. +//! +//! This function sets the shadow load mode of the high resolution comparator. +//! The function sets the COMPA or COMPB register depending on the channel +//! variable. +//! Valid values for the parameters are: +//! - channel +//! - HRPWM_CHANNEL_A - HRPWM A +//! - HRPWM_CHANNEL_B - HRPWM B +//! - loadEvent +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero or +//! period +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareShadowLoadEvent(uint32_t base, HRPWM_Channel channel, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the CMPAHR or CMPBHR load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(0x3U << ((uint16_t)channel + 3U))) | + ((uint16_t)loadEvent << ((uint16_t)channel + 3U))); + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output swap mode. +//! +//! \param base is the base address of the EPWM module. +//! \param enableOutputSwap is the output swap flag. +//! +//! This function sets the HRPWM output swap mode. If enableOutputSwap is true, +//! ePWMxA signal appears on ePWMxB output and ePWMxB signal appears on ePWMxA +//! output. If it is false ePWMxA and ePWMxB outputs are unchanged. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setOutputSwapMode(uint32_t base, bool enableOutputSwap) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set output swap mode + // + EALLOW; + if(enableOutputSwap) + { + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_SWAPAB; + } + else + { + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_SWAPAB; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the high resolution output on ePWMxB +//! +//! \param base is the base address of the EPWM module. +//! \param outputOnB is the output signal on ePWMxB. +//! +//! This function sets the HRPWM output signal on ePWMxB. If outputOnB is +//! HRPWM_OUTPUT_ON_B_INV_A, ePWMxB output is an inverted version of +//! ePWMxA. If outputOnB is HRPWM_OUTPUT_ON_B_NORMAL, ePWMxB output is +//! ePWMxB. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setChannelBOutputPath(uint32_t base, HRPWM_ChannelBOutput outputOnB) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the output on ePWM B + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) = + ((HWREGH(base + HRPWM_O_HRCNFG) & ~(HRPWM_HRCNFG_SELOUTB)) | + ((uint16_t)outputOnB << 5U)); + EDIS; +} + +//***************************************************************************** +// +//! Enables MEP (Micro Edge Positioner) automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the MEP (Micro Edge Positioner) to automatically +//! scale HRMSTEP. +//! +//! The SFO library will calculate required MEP steps per coarse steps and +//! feed it to HRMSTEP register. The MEP calibration module will use the value +//! in HRMSTEP to determine appropriate number of MEP steps represented by +//! fractional duty cycle. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Enable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) |= HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Disables MEP automatic scale mode. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the MEP (Micro Edge Positioner) from automatically +//! scaling HRMSTEP. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disableAutoConversion(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Disable MEP automatic scale + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG) &= ~HRPWM_HRCNFG_AUTOCONV; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution period feature. +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables the high resolution period feature. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_disablePeriodControl(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear HRPE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_HRPE; + EDIS; +} + +//***************************************************************************** +// +//! Enable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function enables loading of high resolution phase shift value which is +//! set by the function HRPWM_setPhaseShift(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_enablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) |= HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Disable high resolution phase load +//! +//! \param base is the base address of the EPWM module. +//! +//! This function disables loading of high resolution phase shift value. +//! +//! \return +// +//***************************************************************************** +static inline void +HRPWM_disablePhaseShiftLoad(uint32_t base) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Clear TBPHSHRLOADE bit + // + EALLOW; + HWREGH(base + HRPWM_O_HRPCTL) &= ~HRPWM_HRPCTL_TBPHSHRLOADE; + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution PWMSYNC source. +//! +//! \param base is the base address of the EPWM module. +//! \param syncPulseSource is the PWMSYNC source. +//! +//! This function sets the high resolution PWMSYNC pulse source. +//! Valid values for syncPulseSource are: +//! - HRPWM_PWMSYNC_SOURCE_PERIOD - Counter equals Period. +//! - HRPWM_PWMSYNC_SOURCE_ZERO - Counter equals zero. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_UP - Counter equals COMPC when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPC_DOWN - Counter equals COMPC when +//! counting down. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_UP - Counter equals COMPD when +//! counting up. +//! - HRPWM_PWMSYNC_SOURCE_COMPD_DOWN - Counter equals COMPD when +//! counting down. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setSyncPulseSource(uint32_t base, HRPWM_SyncPulseSource syncPulseSource) +{ + // + // Set the PWMSYNC source + // + EALLOW; + + // + // Configuration for sync pulse source equal to HRPWM_PWMSYNC_SOURCE_PERIOD + // or HRPWM_PWMSYNC_SOURCE_ZERO + // + if(syncPulseSource < HRPWM_PWMSYNC_SOURCE_COMPC_UP) + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & + ~(HRPWM_HRPCTL_PWMSYNCSELX_M | HRPWM_HRPCTL_PWMSYNCSEL)) | + ((uint16_t)syncPulseSource << 1U)); + } + else + { + HWREGH(base + HRPWM_O_HRPCTL) = + ((HWREGH(base + HRPWM_O_HRPCTL) & ~HRPWM_HRPCTL_PWMSYNCSELX_M) | + ((uint16_t)syncPulseSource << HRPWM_HRPCTL_PWMSYNCSELX_S)); + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the Translator Remainder value. +//! +//! \param base is the base address of the EPWM module. +//! \param trremVal is the translator remainder value. +//! +//! This function sets the Translator Remainder value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setTranslatorRemainder(uint32_t base, uint16_t trremVal) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(trremVal < 2048U); + + // + // Set Translator Remainder value + // + EALLOW; + HWREGH(base + HRPWM_O_TRREM) = (trremVal & HRPWM_TRREM_TRREM_M); + EDIS; +} + +//***************************************************************************** +// +//! Sets the consolidated counter compare values in HR mode. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param compCount is the consolidated counter compare count value. +//! +//! This function sets the consolidated counter compare(CMPx:CMPxHR) value +//! required in high resolution mode for counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: compCount is a 24 bit value. +//! \b Note: For configuring CMPA = 0xB4, CMPAHR = 0x64; value of +//! compCount = 0xB464 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint32_t compCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(compCount < 0x1000000U); + + // + // Write to counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPA:CMPAHR + // + HWREG(base + HRPWM_O_CMPA) = compCount << 8U; + } + else + { + // + // Write to CMPB:CMPBHR + // + HWREG(base + HRPWM_O_CMPB) = compCount << 8U; + } +} + +//***************************************************************************** +// +//! Sets only the high resolution counter compare value. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module. +//! \param hrCompCount is the high resolution counter compare count value. +//! +//! This function sets the high resolution counter compare value(CMPxHR) for +//! counter compare registers. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \b Note: hrCompCount is an 8-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule, + uint16_t hrCompCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrCompCount < 256U); + + // + // Write to the high resolution counter compare registers + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Write to CMPAHR + // + HWREGH(base + HRPWM_O_CMPA) = hrCompCount << 8U; + } + else + { + // + // Write to CMPBHR + // + HWREGH(base + HRPWM_O_CMPB) = hrCompCount << 8U; + } +} + +//***************************************************************************** +// +//! Gets the consolidated counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets the consolidated counter compare(CMPx:CMPxHR) value +//! used in high resolution for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! +//! \return None. +// +//***************************************************************************** +static inline uint32_t +HRPWM_getCounterCompareValue(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint32_t compCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + compCount = HWREG(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + compCount = HWREG(base + HRPWM_O_CMPB) >> 8U; + } + return(compCount); +} + +//***************************************************************************** +// +//! Gets only the high resolution counter compare values. +//! +//! \param base is the base address of the EPWM module. +//! \param compModule is the Counter Compare module value. +//! +//! This function gets only the high resolution counter compare(CMPxHR) value +//! for the counter compare module specified. +//! Valid values for compModule are: +//! - HRPWM_COUNTER_COMPARE_A - counter compare A. +//! - HRPWM_COUNTER_COMPARE_B - counter compare B. +//! +//! \return None. +// +//***************************************************************************** +static inline uint16_t +HRPWM_getHiResCounterCompareValueOnly(uint32_t base, + HRPWM_CounterCompareModule compModule) +{ + uint16_t hrCompCount; + + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Get counter compare value for selected module + // + if(compModule == HRPWM_COUNTER_COMPARE_A) + { + // + // Read from CMPAHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPA) >> 8U; + } + else + { + // + // Read from CMPBHR + // + hrCompCount = HWREGH(base + HRPWM_O_CMPB) >> 8U; + } + return(hrCompCount); +} + +//***************************************************************************** +// +//! Sets the consolidated RED count in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param redCount is the high resolution RED count. +//! +//! This function sets the consolidated RED (Rising Edge Delay) count +//! (DBRED:DBREDHR) value used in high resolution mode. The value of +//! redCount should be less than 0x200000. +//! +//! \b Note: redCount is a 21 bit value. +//! \b Note: For configuring DBRED = 0x4, DBREDHR = 0x1; value of +//! redCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelay(uint32_t base, uint32_t redCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(redCount < 0x200000U); + + // + // Set the consolidated RED (Rising Edge Delay) count + // + HWREG(base + HRPWM_O_DBREDHR) = redCount << 9U; +} + +//***************************************************************************** +// +//! Sets the high resolution RED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrRedCount is the high resolution RED count. +//! +//! This function sets only the high resolution RED (Rising Edge Delay) +//! count(DBREDHR) value. +//! The value of hrRedCount should be less than 128. +//! +//! \b Note: hrRedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResRisingEdgeDelayOnly(uint32_t base, uint16_t hrRedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrRedCount < 128U); + + // + // Set the High Resolution RED (Rising Edge Delay) count only + // + HWREGH(base + HRPWM_O_DBREDHR) = hrRedCount << 9U; +} + +//***************************************************************************** +// +//! Sets the consolidated FED value in high resolution mode. +//! +//! \param base is the base address of the EPWM module. +//! \param fedCount is the high resolution FED count. +//! +//! This function sets the consolidated FED (Falling Edge Delay) count +//! (DBFED: DBFEDHR) value used in high resolution mode. The value of fedCount +//! should be less than 0x200000. +//! +//! \b Note: fedCount is a 21 bit value. +//! \b Note: For configuring DBFED = 0x4, DBFEDHR = 0x1; value of +//! fedCount = ((0x4 << 7) | 0x1) = 0x201 +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelay(uint32_t base, uint32_t fedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(fedCount < 0x200000U); + + // + // Set the High Resolution FED (Falling Edge Delay) count + // + HWREG(base + HRPWM_O_DBFEDHR) = fedCount << 9U; +} + +//***************************************************************************** +// +//! Sets high resolution FED count only. +//! +//! \param base is the base address of the EPWM module. +//! \param hrFedCount is the high resolution FED count. +//! +//! This function sets only the high resolution FED (Falling Edge Delay) count +//! (DBFEDHR)value. The value of hrFedCount should be less than 128. +//! +//! \b Note: hrFedCount is a 7-bit value. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setHiResFallingEdgeDelayOnly(uint32_t base, uint16_t hrFedCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(hrFedCount < 128U); + + // + // Set the high resolution FED (Falling Edge Delay) count + // + HWREGH(base + HRPWM_O_DBFEDHR) = hrFedCount << 9U; +} + +//***************************************************************************** +// +//! Set high resolution MEP (Micro Edge Positioner) step. +//! +//! \param base is the base address of the EPWM module. +//! \param mepCount is the high resolution MEP (Micro Edge Positioner) step +//! count. +//! +//! This function sets the high resolution MEP (Micro Edge Positioner) step +//! count. The maximum value for the MEP count step is 255. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setMEPStep(uint32_t base, uint16_t mepCount) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + ASSERT(mepCount < 256U); + + // + // Set HRPWM MEP count + // + EALLOW; + HWREGH(base + HRPWM_O_HRMSTEP) = + ((HWREGH(base + HRPWM_O_HRMSTEP) & ~HRPWM_HRMSTEP_HRMSTEP_M) | + mepCount); + EDIS; +} + +//***************************************************************************** +// +//! Set high resolution Dead Band MEP (Micro Edge Positioner) control. +//! +//! \param base is the base address of the EPWM module. +//! \param mepDBEdge is the high resolution MEP (Micro Edge Positioner) control +//! edge. +//! +//! This function sets the high resolution Dead Band edge that the MEP (Micro +//! Edge Positioner) controls Valid values for mepDBEdge are: +//! - HRPWM_DB_MEP_CTRL_DISABLE - HRPWM is disabled +//! - HRPWM_DB_MEP_CTRL_RED - MEP (Micro Edge Positioner) controls +//! Rising Edge Delay +//! - HRPWM_DB_MEP_CTRL_FED - MEP (Micro Edge Positioner) controls +//! Falling Edge Delay +//! - HRPWM_DB_MEP_CTRL_RED_FED - MEP (Micro Edge Positioner) controls both +//! Falling and Rising edge delays +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setDeadbandMEPEdgeSelect(uint32_t base, + HRPWM_MEPDeadBandEdgeMode mepDBEdge) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM DB edge mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_EDGMODEDB_M) | + ((uint16_t)mepDBEdge)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band RED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Rising Edge Delay(RED)Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setRisingEdgeDelayLoadMode(uint32_t base, + HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM RED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBRED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBRED_S)); + EDIS; +} + +//***************************************************************************** +// +//! Set the high resolution Dead Band FED load mode. +//! +//! \param base is the base address of the EPWM module. +//! \param loadEvent is the shadow to active load event. +//! +//! This function sets the high resolution Falling Edge Delay(FED) Dead Band +//! count load mode. +//! Valid values for loadEvent are: +//! - HRPWM_LOAD_ON_CNTR_ZERO - load when counter equals zero. +//! - HRPWM_LOAD_ON_CNTR_PERIOD - load when counter equals period +//! - HRPWM_LOAD_ON_CNTR_ZERO_PERIOD - load when counter equals zero +//! or period. +//! +//! \return None. +// +//***************************************************************************** +static inline void +HRPWM_setFallingEdgeDelayLoadMode(uint32_t base, HRPWM_LoadMode loadEvent) +{ + // + // Check the arguments + // + ASSERT(HRPWM_isBaseValid(base)); + + // + // Set the HRPWM FED load mode + // + EALLOW; + HWREGH(base + HRPWM_O_HRCNFG2) = + ((HWREGH(base + HRPWM_O_HRCNFG2) & ~HRPWM_HRCNFG2_CTLMODEDBFED_M) | + ((uint16_t)loadEvent << HRPWM_HRCNFG2_CTLMODEDBFED_S)); + EDIS; +} + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // HRPWM_H + diff --git a/gpio_driverlib_cpu1/device/driverlib/hw_reg_inclusive_terminology.h b/gpio_driverlib_cpu1/device/driverlib/hw_reg_inclusive_terminology.h new file mode 100644 index 0000000..d3dc018 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/hw_reg_inclusive_terminology.h @@ -0,0 +1,29 @@ +#ifndef HW_REG_INCLUSIVE_TERMINOLOGY_H +#define HW_REG_INCLUSIVE_TERMINOLOGY_H + + + +//***************************************************************************** +// SPI +//***************************************************************************** +#define SPI_CTL_CONTROLLER_PERIPHERAL SPI_CTL_MASTER_SLAVE +#define SPI_PRI_PTEINV SPI_PRI_STEINV + +//***************************************************************************** +// I2C +//***************************************************************************** +#define I2C_O_TAR I2C_O_SAR + +#define I2C_TAR_TAR_S I2C_SAR_SAR_S +#define I2C_TAR_TAR_M I2C_SAR_SAR_M + +#define I2C_IER_AAT I2C_IER_AAS + +#define I2C_STR_AAT I2C_STR_AAS +#define I2C_STR_TDIR I2C_STR_SDIR + +#define I2C_MDR_CNT I2C_MDR_MST + + + +#endif // HW_REG_INCLUSIVE_TERMINOLOGY_H diff --git a/gpio_driverlib_cpu1/device/driverlib/i2c.c b/gpio_driverlib_cpu1/device/driverlib/i2c.c new file mode 100644 index 0000000..692f7a2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/i2c.c @@ -0,0 +1,351 @@ +//########################################################################### +// +// FILE: i2c.c +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "i2c.h" + +//***************************************************************************** +// +// I2C_initController +// +//***************************************************************************** +void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((10000000U / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (10000000U / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_initControllerModuleFrequency +// +//***************************************************************************** +void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + uint32_t divider; + uint32_t dValue; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT((moduleFrequency / bitRate) > 10U); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; + + switch(modPrescale) + { + case 0U: + dValue = 7U; + break; + + case 1U: + dValue = 6U; + break; + + default: + dValue = 5U; + break; + } + + // + // Set the divider for the time low + // + divider = (moduleFrequency / bitRate) - (2U * dValue); + + if(dutyCycle == I2C_DUTYCYCLE_50) + { + HWREGH(base + I2C_O_CLKH) = divider / 2U; + } + else + { + HWREGH(base + I2C_O_CLKH) = divider / 3U; + } + + HWREGH(base + I2C_O_CLKL) = divider - HWREGH(base + I2C_O_CLKH); +} + +//***************************************************************************** +// +// I2C_enableInterrupt +// +//***************************************************************************** +void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the desired basic interrupts + // + HWREGH(base + I2C_O_IER) |= (intFlags & 0xFFFFU); + + // + // Enabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) |= I2C_IER_AAT; + } + + // + // Enable desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFIENA; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// I2C_disableInterrupt +// +//***************************************************************************** +void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the desired basic interrupts. + // + HWREGH(base + I2C_O_IER) &= ~(intFlags & 0xFFFFU); + + // + // Disabling addressed-as-target interrupt separately because its bit is + // different between the IER and STR registers. + // + if((intFlags & I2C_INT_ADDR_TARGET) != 0U) + { + HWREGH(base + I2C_O_IER) &= ~I2C_IER_AAT; + } + + // + // Disable the desired FIFO interrupts. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_TXFFIENA); + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) &= ~(I2C_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// I2C_getInterruptStatus +// +//***************************************************************************** +uint32_t +I2C_getInterruptStatus(uint32_t base) +{ + uint32_t temp; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return only the status bits associated with interrupts. + // + temp = (uint32_t)HWREGH(base + I2C_O_STR) & (uint32_t)I2C_STR_INTMASK; + + // + // Read FIFO interrupt flags. + // + if((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFINT) != 0U) + { + temp |= I2C_INT_TXFF; + } + + if((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFINT) != 0U) + { + temp |= I2C_INT_RXFF; + } + + return(temp); +} + +//***************************************************************************** +// +// I2C_clearInterruptStatus +// +//***************************************************************************** +void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the interrupt flags that are located in STR. + // + HWREGH(base + I2C_O_STR) = ((uint16_t)intFlags & I2C_STR_INTMASK); + + // + // Clear the FIFO interrupt flags if needed. + // + if((intFlags & I2C_INT_TXFF) != 0U) + { + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_TXFFINTCLR; + } + + if((intFlags & I2C_INT_RXFF) != 0U) + { + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFINTCLR; + } +} +//***************************************************************************** +// +// I2C_configureModuleFrequency +// +//***************************************************************************** +void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / 10000000U) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} +//***************************************************************************** +// +// I2C_configureModuleClockFrequency +// +//***************************************************************************** +void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency) +{ + uint32_t modPrescale; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the prescaler for the module clock. + // + modPrescale = (sysclkHz / moduleFrequency) - 1U; + HWREGH(base + I2C_O_PSC) = I2C_PSC_IPSC_M & modPrescale; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/i2c.h b/gpio_driverlib_cpu1/device/driverlib/i2c.h new file mode 100644 index 0000000..634c4c8 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/i2c.h @@ -0,0 +1,1386 @@ +//########################################################################### +// +// FILE: i2c.h +// +// TITLE: C28x I2C driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef I2C_H +#define I2C_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup i2c_api I2C +//! @{ +// +//***************************************************************************** + +#include "inc/hw_i2c.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// I2C Controller commands. +// +//***************************************************************************** +#define I2C_CONTROLLER_SEND_MODE 0x0600U //!< Controller-transmitter mode +#define I2C_CONTROLLER_RECEIVE_MODE 0x0400U //!< Controller-receiver mode +#define I2C_TARGET_SEND_MODE 0x0200U //!< Target-transmitter mode +#define I2C_TARGET_RECEIVE_MODE 0x0000U //!< Target-receiver mode + +#define I2C_REPEAT_MODE 0x0080U //!< Only applies to Controller mode +#define I2C_START_BYTE_MODE 0x0010U //!< Enable start byte mode +#define I2C_FREE_DATA_FORMAT 0x0008U //!< Enable free data (no addr) format + +//***************************************************************************** +// +// I2C interrupts for use with the intFlags parameter of I2C_enableInterrupt(), +// I2C_disableInterrupt(), and I2C_clearInterruptStatus() and to be returned by +// I2C_getInterruptStatus(). +// +//***************************************************************************** +#define I2C_INT_ARB_LOST 0x00001U //!< Arbitration-lost interrupt +#define I2C_INT_NO_ACK 0x00002U //!< NACK interrupt +#define I2C_INT_REG_ACCESS_RDY 0x00004U //!< Register-access-ready interrupt +#define I2C_INT_RX_DATA_RDY 0x00008U //!< Receive-data-ready interrupt +#define I2C_INT_TX_DATA_RDY 0x00010U //!< Transmit-data-ready interrupt +#define I2C_INT_STOP_CONDITION 0x00020U //!< Stop condition detected +#define I2C_INT_ADDR_TARGET 0x00200U //!< Addressed as target interrupt +#define I2C_INT_RXFF 0x10000U //!< RX FIFO level interrupt +#define I2C_INT_TXFF 0x20000U //!< TX FIFO level interrupt + + +// +// Helpful define to mask out the bits in the I2CSTR register that aren't +// associated with interrupts. +// +#define I2C_STR_INTMASK ((uint16_t)I2C_INT_ARB_LOST | \ + (uint16_t)I2C_INT_NO_ACK | \ + (uint16_t)I2C_INT_REG_ACCESS_RDY | \ + (uint16_t)I2C_INT_RX_DATA_RDY | \ + (uint16_t)I2C_INT_TX_DATA_RDY | \ + (uint16_t)I2C_INT_STOP_CONDITION | \ + (uint16_t)I2C_INT_ADDR_TARGET) + + + + +//***************************************************************************** +// +// Flags for use as the stsFlags parameter of I2C_clearStatus() and to be +// returned by I2C_getStatus(). +// +//***************************************************************************** +#define I2C_STS_ARB_LOST 0x0001U //!< Arbitration-lost +#define I2C_STS_NO_ACK 0x0002U //!< No-acknowledgment (NACK) +#define I2C_STS_REG_ACCESS_RDY 0x0004U //!< Register-access-ready (ARDY) +#define I2C_STS_RX_DATA_RDY 0x0008U //!< Receive-data-ready +#define I2C_STS_TX_DATA_RDY 0x0010U //!< Transmit-data-ready +#define I2C_STS_STOP_CONDITION 0x0020U //!< Stop condition detected +#define I2C_STS_ADDR_ZERO 0x0100U //!< Address of all zeros detected +#define I2C_STS_ADDR_TARGET 0x0200U //!< Addressed as target +#define I2C_STS_TX_EMPTY 0x0400U //!< Transmit shift register empty +#define I2C_STS_RX_FULL 0x0800U //!< Receive shift register full +#define I2C_STS_BUS_BUSY 0x1000U //!< Bus busy, wait for STOP or reset +#define I2C_STS_NACK_SENT 0x2000U //!< NACK was sent +#define I2C_STS_TARGET_DIR 0x4000U //!< Addressed as target transmitter + +#endif + + +//***************************************************************************** +// +//! I2C interrupts to be returned by I2C_getInterruptSource(). +// +//***************************************************************************** +typedef enum +{ + I2C_INTSRC_NONE, //!< No interrupt pending + I2C_INTSRC_ARB_LOST, //!< Arbitration-lost interrupt + I2C_INTSRC_NO_ACK, //!< NACK interrupt + I2C_INTSRC_REG_ACCESS_RDY, //!< Register-access-ready interrupt + I2C_INTSRC_RX_DATA_RDY, //!< Receive-data-ready interrupt + I2C_INTSRC_TX_DATA_RDY, //!< Transmit-data-ready interrupt + I2C_INTSRC_STOP_CONDITION, //!< Stop condition detected + I2C_INTSRC_ADDR_TARGET, //!< Addressed as target interrupt +} I2C_InterruptSource; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by I2C_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + I2C_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + I2C_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + I2C_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + I2C_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + I2C_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + I2C_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + I2C_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + I2C_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + I2C_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + I2C_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + I2C_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + I2C_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + I2C_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + I2C_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + I2C_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + I2C_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + I2C_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} I2C_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by I2C_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by I2C_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + I2C_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + I2C_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + I2C_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + I2C_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + I2C_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + I2C_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + I2C_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + I2C_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + I2C_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + I2C_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + I2C_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + I2C_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + I2C_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + I2C_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + I2C_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + I2C_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + I2C_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + I2C_FIFO_RXFULL = 0x0010U //!< Receive FIFO full +} I2C_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setBitCount() as the \e size parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_BITCOUNT_1 = 1U, //!< 1 bit per data byte + I2C_BITCOUNT_2 = 2U, //!< 2 bits per data byte + I2C_BITCOUNT_3 = 3U, //!< 3 bits per data byte + I2C_BITCOUNT_4 = 4U, //!< 4 bits per data byte + I2C_BITCOUNT_5 = 5U, //!< 5 bits per data byte + I2C_BITCOUNT_6 = 6U, //!< 6 bits per data byte + I2C_BITCOUNT_7 = 7U, //!< 7 bits per data byte + I2C_BITCOUNT_8 = 0U //!< 8 bits per data byte +} I2C_BitCount; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setAddressMode() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_ADDR_MODE_7BITS = 0x0000U, //!< 7-bit address + I2C_ADDR_MODE_10BITS = 0x0100U //!< 10-bit address +} I2C_AddressMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! If SCL is low, keep it low. If high, stop when it goes low again. + I2C_EMULATION_STOP_SCL_LOW = 0x0000U, + //! Continue I2C operation regardless + I2C_EMULATION_FREE_RUN = 0x4000U +} I2C_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to I2C_initController() as the \e dutyCycle +//! parameter. +// +//***************************************************************************** +typedef enum +{ + I2C_DUTYCYCLE_33, //!< Clock duty cycle is 33% + I2C_DUTYCYCLE_50 //!< Clock duty cycle is 55% +} I2C_DutyCycle; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an I2C base address. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function determines if a I2C module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +I2C_isBaseValid(uint32_t base) +{ + return( + (base == I2CA_BASE) || + (base == I2CB_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) |= I2C_MDR_IRS; +} + +//***************************************************************************** +// +//! Disables the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables operation of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + HWREGH(base + I2C_O_MDR) &= ~(I2C_MDR_IRS); +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions enables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + I2C_O_FFTX) |= I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST; + HWREGH(base + I2C_O_FFRX) |= I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This functions disables the transmit and receive FIFOs in the I2C. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + I2C_O_FFTX) &= ~(I2C_FFTX_I2CFFEN | I2C_FFTX_TXFFRST); + HWREGH(base + I2C_O_FFRX) &= ~I2C_FFRX_RXFFRST; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, . . . or +//! \b I2C_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, . . . or +//! \b I2C_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel txLevel, + I2C_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + I2C_O_FFTX) = (HWREGH(base + I2C_O_FFTX) & + (~I2C_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + I2C_O_FFRX) = (HWREGH(base + I2C_O_FFRX) & + (~I2C_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the I2C instance used. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, +//! \b I2C_FIFO_TX2, . . . or \b I2C_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, +//! \b I2C_FIFO_RX2, . . . or \b I2C_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. The transmit FIFO interrupt flag will be set when the FIFO +//! reaches a value less than or equal to \e txLevel. The receive FIFO +//! flag will be set when the FIFO reaches a value greater than or equal to +//! \e rxLevel. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_getFIFOInterruptLevel(uint32_t base, I2C_TxFIFOLevel *txLevel, + I2C_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (I2C_TxFIFOLevel)(HWREGH(base + I2C_O_FFTX) & + I2C_FFTX_TXFFIL_M); + *rxLevel = (I2C_RxFIFOLevel)(HWREGH(base + I2C_O_FFRX) & + I2C_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b I2C_FIFO_TX0, \b I2C_FIFO_TX1, \b I2C_FIFO_TX2, \b I2C_FIFO_TX3, +//! ..., or \b I2C_FIFO_TX16 +// +//***************************************************************************** +static inline I2C_TxFIFOLevel +I2C_getTxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFTX) & I2C_FFTX_TXFFST_M) >> + I2C_FFTX_TXFFST_S); + + return((I2C_TxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b I2C_FIFO_RX0, \b I2C_FIFO_RX1, \b I2C_FIFO_RX2, \b I2C_FIFO_RX3, +//! ..., or \b I2C_FIFO_RX16 +// +//***************************************************************************** +static inline I2C_RxFIFOLevel +I2C_getRxFIFOStatus(uint32_t base) +{ + uint16_t level; + + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Get the current FIFO status + // + level = ((HWREGH(base + I2C_O_FFRX) & I2C_FFRX_RXFFST_M) >> + I2C_FFRX_RXFFST_S); + + return((I2C_RxFIFOLevel)level); +} + +//***************************************************************************** +// +//! Reads I2C Module clock prescaler value. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads the I2C prescaler value which configures the I2C module +//! clock by dividing down the SYSCLK. I2C_MODULE_CLK = SYSCLK / (I2CPSC + ) +//! +//! \return Returns the I2C prescaler(I2CPSC) cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getPreScaler(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the Prescaler register. + // + return(HWREGH(base + I2C_O_PSC)); +} + +//***************************************************************************** +// +//! Sets the address that the I2C Controller places on the bus. +//! +//! \param base is the base address of the I2C instance used. +//! \param targetAddr 7-bit or 10-bit target address +//! +//! This function configures the address that the I2C Controller places on the bus +//! when initiating a transaction. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setTargetAddress(uint32_t base, uint16_t targetAddr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(targetAddr <= I2C_TAR_TAR_M); + + HWREGH(base + I2C_O_TAR) = targetAddr; +} + +//***************************************************************************** +// +//! Sets the own address for this I2C module. +//! +//! \param base is the base address of the I2C Target module. +//! \param Addr is the 7-bit or 10-bit address +//! +//! This function writes the specified address. +//! +//! The parameter \e Addr is the value that is compared against the +//! target address sent by an I2C controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setOwnAddress(uint32_t base, uint16_t Addr) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + ASSERT(Addr <= I2C_OAR_OAR_M); + + HWREGH(base + I2C_O_OAR) = Addr; +} + +//***************************************************************************** +// +//! Indicates whether or not the I2C bus is busy. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns an indication of whether or not the I2C bus is busy. +//! This function can be used in a multi-controller environment to determine if the +//! bus is free for another data transfer. +//! +//! \return Returns \b true if the I2C bus is busy; otherwise, returns +//! \b false. +// +//***************************************************************************** +static inline bool +I2C_isBusBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + return((HWREGH(base + I2C_O_STR) & I2C_STR_BB) == I2C_STR_BB); +} + +//***************************************************************************** +// +//! Gets the current I2C module status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the status for the I2C module. +//! +//! \return The current module status, enumerated as a bit field of +//! - \b I2C_STS_ARB_LOST - Arbitration-lost +//! - \b I2C_STS_NO_ACK - No-acknowledgment (NACK) +//! - \b I2C_STS_REG_ACCESS_RDY - Register-access-ready (ARDY) +//! - \b I2C_STS_RX_DATA_RDY - Receive-data-ready +//! - \b I2C_STS_TX_DATA_RDY - Transmit-data-ready +//! - \b I2C_STS_STOP_CONDITION - Stop condition detected +//! - \b I2C_STS_ADDR_ZERO - Address of all zeros detected +//! - \b I2C_STS_ADDR_TARGET - Addressed as Target +//! - \b I2C_STS_TX_EMPTY - Transmit shift register empty +//! - \b I2C_STS_RX_FULL - Receive shift register full +//! - \b I2C_STS_BUS_BUSY - Bus busy, wait for STOP or reset +//! - \b I2C_STS_NACK_SENT - NACK was sent +//! - \b I2C_STS_TARGET_DIR- Addressed as Target transmitter +// +//***************************************************************************** +static inline uint16_t +I2C_getStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return contents of the status register + // + return(HWREGH(base + I2C_O_STR)); +} + +//***************************************************************************** +// +//! Clears I2C status flags. +//! +//! \param base is the base address of the I2C instance used. +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! +//! This function clears the specified I2C status flags. The \e stsFlags +//! parameter is the logical OR of the following values: +//! - \b I2C_STS_ARB_LOST +//! - \b I2C_STS_NO_ACK, +//! - \b I2C_STS_REG_ACCESS_RDY +//! - \b I2C_STS_RX_DATA_RDY +//! - \b I2C_STS_STOP_CONDITION +//! - \b I2C_STS_NACK_SENT +//! - \b I2C_STS_TARGET_DIR +//! +//! \note Note that some of the status flags returned by I2C_getStatus() cannot +//! be cleared by this function. Some may only be cleared by hardware or a +//! reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_clearStatus(uint32_t base, uint16_t stsFlags) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write to the status registers to clear them. + // + HWREGH(base + I2C_O_STR) = stsFlags; +} + +//***************************************************************************** +// +//! Controls the state of the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param config is the command to be issued to the I2C module. +//! +//! This function is used to control the state of the controller and target send and +//! receive operations. The \e config is a logical OR of the following options. +//! +//! One of the following four options: +//! - \b I2C_CONTROLLER_SEND_MODE - Controller-transmitter mode +//! - \b I2C_CONTROLLER_RECEIVE_MODE - Controller-receiver mode +//! - \b I2C_TARGET_SEND_MODE - Target-transmitter mode +//! - \b I2C_TARGET_RECEIVE_MODE - Target-receiver mode +//! +//! Any of the following: +//! - \b I2C_REPEAT_MODE - Sends data until stop bit is set, ignores data count +//! - \b I2C_START_BYTE_MODE - Use start byte mode +//! - \b I2C_FREE_DATA_FORMAT - Use free data format, transfers have no address +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setConfig(uint32_t base, uint16_t config) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & + ~(I2C_MDR_CNT | I2C_MDR_TRX | I2C_MDR_RM | + I2C_MDR_STB | I2C_MDR_FDF)) | config; +} + +//***************************************************************************** +// +//! Sets the data byte bit count the I2C module. +//! +//! \param base is the base address of the I2C instance used. +//! \param size is the number of bits per data byte. +//! +//! The \e size parameter is a value I2C_BITCOUNT_x where x is the number of +//! bits per data byte. The default and maximum size is 8 bits. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setBitCount(uint32_t base, I2C_BitCount size) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the selected options to the mode register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_BC_M) | + (uint16_t)size; +} + +//***************************************************************************** +// +//! Issues an I2C START condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a start condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStartCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the START condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STT; +} + +//***************************************************************************** +// +//! Issues an I2C STOP condition. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a stop condition. This +//! function is only valid when the I2C module specified by the \b base +//! parameter is a controller. +//! +//! To check on the status of the STOP condition, I2C_getStopConditionStatus() +//! can be used. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendStopCondition(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the STOP condition bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_STP; +} + +//***************************************************************************** +// +//! Issues a no-acknowledge (NACK) bit. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function causes the I2C module to generate a NACK bit. This is only +//! applicable when the I2C module is acting as a receiver. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_sendNACK(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the NACK mode bit. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_NACKMOD; +} + +//***************************************************************************** +// +//! Receives a byte that has been sent to the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads a byte of data from the I2C Data Receive Register. +//! +//! \return Returns the byte received from by the I2C cast as an uint16_t. +// +//***************************************************************************** +static inline uint16_t +I2C_getData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the contents of the receive register. + // + return(HWREGH(base + I2C_O_DRR)); +} + +//***************************************************************************** +// +//! Transmits a byte from the I2C. +//! +//! \param base is the base address of the I2C instance used. +//! \param data is the data to be transmitted from the I2C Controller. +//! +//! This function places the supplied data into I2C Data Transmit Register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_putData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Place the data into the transmit register. + // + HWREGH(base + I2C_O_DXR) = data; +} + +//***************************************************************************** +// +//! Get stop condition status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function reads and returns the stop condition bit status. +//! +//! \return Returns \b true if the STP bit has been set by the device to +//! generate a stop condition when the internal data counter of the I2C module +//! has reached 0. Returns \b false when the STP bit is zero. This bit is +//! automatically cleared after the stop condition has been generated. +// +//***************************************************************************** +static inline bool +I2C_getStopConditionStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Check the stop condition bit and return appropriately. + // + return((HWREGH(base + I2C_O_MDR) & I2C_MDR_STP) != 0U); +} + +//***************************************************************************** +// +//! Set number of bytes to be to transfer or receive when repeat mode is off. +//! +//! \param base is the base address of the I2C instance used. +//! \param count is the value to be put in the I2C data count register. +//! +//! This function sets the number of bytes to transfer or receive when repeat +//! mode is off. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setDataCount(uint32_t base, uint16_t count) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the count value to the appropriate register. + // + HWREGH(base + I2C_O_CNT) = count; +} + +//***************************************************************************** +// +//! Sets the addressing mode to either 7-bit or 10-bit. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the address mode, 7-bit or 10-bit. +//! +//! This function configures the I2C module for either a 7-bit address +//! (default) or a 10-bit address. The \e mode parameter configures the address +//! length to 10 bits when its value is \b I2C_ADDR_MODE_10BITS and 7 bits when +//! \b I2C_ADDR_MODE_7BITS. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setAddressMode(uint32_t base, I2C_AddressMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the appropriate value to the address expansion bit. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_XA) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Sets I2C emulation mode. +//! +//! \param base is the base address of the I2C instance used. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the I2C operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b I2C_EMULATION_STOP_SCL_LOW - If SCL is low when the breakpoint occurs, +//! the I2C module stops immediately. If SCL is high, the I2C module waits +//! until SCL becomes low and then stops. +//! - \b I2C_EMULATION_FREE_RUN - I2C operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_setEmulationMode(uint32_t base, I2C_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + I2C_O_MDR) = (HWREGH(base + I2C_O_MDR) & ~I2C_MDR_FREE) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Enables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function enables loopback mode. This mode is only valid during controller +//! mode and is helpful during device testing as it causes data transmitted out +//! of the data transmit register to be received in data receive register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) |= I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Disables I2C loopback mode. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +I2C_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + I2C_O_MDR) &= ~I2C_MDR_DLB; +} + +//***************************************************************************** +// +//! Returns the current I2C interrupt source. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the event that generated an I2C basic (non-FIFO) +//! interrupt. The possible sources are the following: +//! - \b I2C_INTSRC_NONE +//! - \b I2C_INTSRC_ARB_LOST +//! - \b I2C_INTSRC_NO_ACK +//! - \b I2C_INTSRC_REG_ACCESS_RDY +//! - \b I2C_INTSRC_RX_DATA_RDY +//! - \b I2C_INTSRC_TX_DATA_RDY +//! - \b I2C_INTSRC_STOP_CONDITION +//! - \b I2C_INTSRC_ADDR_TARGET +//! +//! Calling this function will result in hardware automatically clearing the +//! current interrupt code and if ready, loading the next pending enabled +//! interrupt. It will also clear the corresponding interrupt flag if the +//! source is \b I2C_INTSRC_ARB_LOST, \b I2C_INTSRC_NO_ACK, or +//! \b I2C_INTSRC_STOP_CONDITION. +//! +//! \note Note that this function differs from I2C_getInterruptStatus() in that +//! it returns a single interrupt source. I2C_getInterruptSource() will return +//! the status of all interrupt flags possible, including the flags that aren't +//! necessarily enabled to generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline I2C_InterruptSource +I2C_getInterruptSource(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(I2C_isBaseValid(base)); + + // + // Return the interrupt source value + // + return((I2C_InterruptSource)(HWREGH(base + I2C_O_ISRC) & + I2C_ISRC_INTCODE_M)); +} + + + + + + + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initController(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle); + +//***************************************************************************** +// +//! Initializes the I2C Controller. +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param bitRate is the rate of the controller clock signal, SCL. +//! \param dutyCycle is duty cycle of the SCL signal. +//! \param moduleFrequency is the module clock used by I2C module +//! +//! This function initializes operation of the I2C Controller by configuring the +//! bus speed for the controller. Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! A programmable prescaler in the I2C module divides down the input clock +//! (rate specified by \e sysclkHz) to produce the module clock (calculated to +//! be around 10 MHz in this function). That clock is then divided down further +//! to configure the SCL signal to run at the rate specified by \e bitRate. The +//! \e dutyCycle parameter determines the percentage of time high and time low +//! on the clock signal. The valid values are \b I2C_DUTYCYCLE_33 for 33% and +//! \b I2C_DUTYCYCLE_50 for 50%. +//! +//! The peripheral clock is the system clock. This value is returned by +//! SysCtl_getClock(), or it can be explicitly hard coded if it is +//! constant and known (to save the code/execution overhead of a call to +//! SysCtl_getClock()). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_initControllerModuleFrequency(uint32_t base, uint32_t sysclkHz, uint32_t bitRate, + I2C_DutyCycle dutyCycle, uint32_t moduleFrequency); + +//***************************************************************************** +// +//! Enables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated I2C Controller interrupt sources. Only the +//! sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter is the logical OR of any of the following: +//! +//! - \b I2C_INT_ARB_LOST - Arbitration-lost interrupt +//! - \b I2C_INT_NO_ACK - No-acknowledgment (NACK) interrupt +//! - \b I2C_INT_REG_ACCESS_RDY - Register-access-ready interrupt +//! - \b I2C_INT_RX_DATA_RDY - Receive-data-ready interrupt +//! - \b I2C_INT_TX_DATA_RDY - Transmit-data-ready interrupt +//! - \b I2C_INT_STOP_CONDITION - Stop condition detected +//! - \b I2C_INT_ADDR_TARGET - Addressed as target interrupt +//! - \b I2C_INT_RXFF - RX FIFO level interrupt +//! - \b I2C_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated I2C Target interrupt sources. Only +//! the sources that are enabled can be reflected to the processor interrupt. +//! Disabled sources have no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current I2C interrupt status. +//! +//! \param base is the base address of the I2C instance used. +//! +//! This function returns the interrupt status for the I2C module. +//! +//! \return The current interrupt status, enumerated as a bit field of +//! - \b I2C_INT_ARB_LOST +//! - \b I2C_INT_NO_ACK +//! - \b I2C_INT_REG_ACCESS_RDY +//! - \b I2C_INT_RX_DATA_RDY +//! - \b I2C_INT_TX_DATA_RDY +//! - \b I2C_INT_STOP_CONDITION +//! - \b I2C_INT_ADDR_TARGET +//! - \b I2C_INT_RXFF +//! - \b I2C_INT_TXFF +//! +//! \note This function will only return the status flags associated with +//! interrupts. However, a flag may be set even if its corresponding interrupt +//! is disabled. +// +//***************************************************************************** +extern uint32_t +I2C_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears I2C interrupt sources. +//! +//! \param base is the base address of the I2C instance used. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified I2C interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being triggered again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to I2C_enableInterrupt(). +//! +//! \note \b I2C_INT_RXFF and \b I2C_INT_TXFF are associated with the I2C FIFO +//! interrupt vector. All others are associated with the I2C basic interrupt. +//! +//! \note Also note that some of the status flags returned by +//! I2C_getInterruptStatus() cannot be cleared by this function. Some may only +//! be cleared by hardware or a reset of the I2C module. +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleFrequency(uint32_t base, uint32_t sysclkHz); + +//***************************************************************************** +// +//! Configures I2C Module Clock Frequency with a given module clock +//! +//! \param base is the base address of the I2C instance used. +//! \param sysclkHz is the rate of the clock supplied to the I2C module +//! (SYSCLK) in Hz. +//! \param moduleFrequency is the rate of the module clock used by I2C module +//! This function configures I2C module clock frequency by initializing +//! prescale register based on SYSCLK frequency. +//! Note that the I2C module \b must be put into +//! reset before calling this function. You can do this with the function +//! I2C_disableModule(). +//! +//! \return None. +// +//***************************************************************************** +extern void +I2C_configureModuleClockFrequency(uint32_t base, uint32_t sysclkHz, uint32_t moduleFrequency); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // I2C_H diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_adc.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_adc.h new file mode 100644 index 0000000..89bd529 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_adc.h @@ -0,0 +1,911 @@ +//########################################################################### +// +// FILE: hw_adc.h +// +// TITLE: Definitions for the ADC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ADC_H +#define HW_ADC_H + +//************************************************************************************************* +// +// The following are defines for the ADC register offsets +// +//************************************************************************************************* +#define ADC_O_CTL1 0x0U // ADC Control 1 Register +#define ADC_O_CTL2 0x1U // ADC Control 2 Register +#define ADC_O_BURSTCTL 0x2U // ADC Burst Control Register +#define ADC_O_INTFLG 0x3U // ADC Interrupt Flag Register +#define ADC_O_INTFLGCLR 0x4U // ADC Interrupt Flag Clear Register +#define ADC_O_INTOVF 0x5U // ADC Interrupt Overflow Register +#define ADC_O_INTOVFCLR 0x6U // ADC Interrupt Overflow Clear Register +#define ADC_O_INTSEL1N2 0x7U // ADC Interrupt 1 and 2 Selection Register +#define ADC_O_INTSEL3N4 0x8U // ADC Interrupt 3 and 4 Selection Register +#define ADC_O_SOCPRICTL 0x9U // ADC SOC Priority Control Register +#define ADC_O_INTSOCSEL1 0xAU // ADC Interrupt SOC Selection 1 Register +#define ADC_O_INTSOCSEL2 0xBU // ADC Interrupt SOC Selection 2 Register +#define ADC_O_SOCFLG1 0xCU // ADC SOC Flag 1 Register +#define ADC_O_SOCFRC1 0xDU // ADC SOC Force 1 Register +#define ADC_O_SOCOVF1 0xEU // ADC SOC Overflow 1 Register +#define ADC_O_SOCOVFCLR1 0xFU // ADC SOC Overflow Clear 1 Register +#define ADC_O_SOC0CTL 0x10U // ADC SOC0 Control Register +#define ADC_O_SOC1CTL 0x12U // ADC SOC1 Control Register +#define ADC_O_SOC2CTL 0x14U // ADC SOC2 Control Register +#define ADC_O_SOC3CTL 0x16U // ADC SOC3 Control Register +#define ADC_O_SOC4CTL 0x18U // ADC SOC4 Control Register +#define ADC_O_SOC5CTL 0x1AU // ADC SOC5 Control Register +#define ADC_O_SOC6CTL 0x1CU // ADC SOC6 Control Register +#define ADC_O_SOC7CTL 0x1EU // ADC SOC7 Control Register +#define ADC_O_SOC8CTL 0x20U // ADC SOC8 Control Register +#define ADC_O_SOC9CTL 0x22U // ADC SOC9 Control Register +#define ADC_O_SOC10CTL 0x24U // ADC SOC10 Control Register +#define ADC_O_SOC11CTL 0x26U // ADC SOC11 Control Register +#define ADC_O_SOC12CTL 0x28U // ADC SOC12 Control Register +#define ADC_O_SOC13CTL 0x2AU // ADC SOC13 Control Register +#define ADC_O_SOC14CTL 0x2CU // ADC SOC14 Control Register +#define ADC_O_SOC15CTL 0x2EU // ADC SOC15 Control Register +#define ADC_O_EVTSTAT 0x30U // ADC Event Status Register +#define ADC_O_EVTCLR 0x32U // ADC Event Clear Register +#define ADC_O_EVTSEL 0x34U // ADC Event Selection Register +#define ADC_O_EVTINTSEL 0x36U // ADC Event Interrupt Selection Register +#define ADC_O_OSDETECT 0x38U // ADC Open and Shorts Detect Register +#define ADC_O_COUNTER 0x39U // ADC Counter Register +#define ADC_O_REV 0x3AU // ADC Revision Register +#define ADC_O_OFFTRIM 0x3BU // ADC Offset Trim Register +#define ADC_O_PPB1CONFIG 0x40U // ADC PPB1 Config Register +#define ADC_O_PPB1STAMP 0x41U // ADC PPB1 Sample Delay Time Stamp Register +#define ADC_O_PPB1OFFCAL 0x42U // ADC PPB1 Offset Calibration Register +#define ADC_O_PPB1OFFREF 0x43U // ADC PPB1 Offset Reference Register +#define ADC_O_PPB1TRIPHI 0x44U // ADC PPB1 Trip High Register +#define ADC_O_PPB1TRIPLO 0x46U // ADC PPB1 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB2CONFIG 0x48U // ADC PPB2 Config Register +#define ADC_O_PPB2STAMP 0x49U // ADC PPB2 Sample Delay Time Stamp Register +#define ADC_O_PPB2OFFCAL 0x4AU // ADC PPB2 Offset Calibration Register +#define ADC_O_PPB2OFFREF 0x4BU // ADC PPB2 Offset Reference Register +#define ADC_O_PPB2TRIPHI 0x4CU // ADC PPB2 Trip High Register +#define ADC_O_PPB2TRIPLO 0x4EU // ADC PPB2 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB3CONFIG 0x50U // ADC PPB3 Config Register +#define ADC_O_PPB3STAMP 0x51U // ADC PPB3 Sample Delay Time Stamp Register +#define ADC_O_PPB3OFFCAL 0x52U // ADC PPB3 Offset Calibration Register +#define ADC_O_PPB3OFFREF 0x53U // ADC PPB3 Offset Reference Register +#define ADC_O_PPB3TRIPHI 0x54U // ADC PPB3 Trip High Register +#define ADC_O_PPB3TRIPLO 0x56U // ADC PPB3 Trip Low/Trigger Time Stamp Register +#define ADC_O_PPB4CONFIG 0x58U // ADC PPB4 Config Register +#define ADC_O_PPB4STAMP 0x59U // ADC PPB4 Sample Delay Time Stamp Register +#define ADC_O_PPB4OFFCAL 0x5AU // ADC PPB4 Offset Calibration Register +#define ADC_O_PPB4OFFREF 0x5BU // ADC PPB4 Offset Reference Register +#define ADC_O_PPB4TRIPHI 0x5CU // ADC PPB4 Trip High Register +#define ADC_O_PPB4TRIPLO 0x5EU // ADC PPB4 Trip Low/Trigger Time Stamp Register +#define ADC_O_INLTRIM1 0x70U // ADC Linearity Trim 1 Register +#define ADC_O_INLTRIM2 0x72U // ADC Linearity Trim 2 Register +#define ADC_O_INLTRIM3 0x74U // ADC Linearity Trim 3 Register +#define ADC_O_INLTRIM4 0x76U // ADC Linearity Trim 4 Register +#define ADC_O_INLTRIM5 0x78U // ADC Linearity Trim 5 Register +#define ADC_O_INLTRIM6 0x7AU // ADC Linearity Trim 6 Register + +#define ADC_O_RESULT0 0x0U // ADC Result 0 Register +#define ADC_O_RESULT1 0x1U // ADC Result 1 Register +#define ADC_O_RESULT2 0x2U // ADC Result 2 Register +#define ADC_O_RESULT3 0x3U // ADC Result 3 Register +#define ADC_O_RESULT4 0x4U // ADC Result 4 Register +#define ADC_O_RESULT5 0x5U // ADC Result 5 Register +#define ADC_O_RESULT6 0x6U // ADC Result 6 Register +#define ADC_O_RESULT7 0x7U // ADC Result 7 Register +#define ADC_O_RESULT8 0x8U // ADC Result 8 Register +#define ADC_O_RESULT9 0x9U // ADC Result 9 Register +#define ADC_O_RESULT10 0xAU // ADC Result 10 Register +#define ADC_O_RESULT11 0xBU // ADC Result 11 Register +#define ADC_O_RESULT12 0xCU // ADC Result 12 Register +#define ADC_O_RESULT13 0xDU // ADC Result 13 Register +#define ADC_O_RESULT14 0xEU // ADC Result 14 Register +#define ADC_O_RESULT15 0xFU // ADC Result 15 Register +#define ADC_O_PPB1RESULT 0x10U // ADC Post Processing Block 1 Result Register +#define ADC_O_PPB2RESULT 0x12U // ADC Post Processing Block 2 Result Register +#define ADC_O_PPB3RESULT 0x14U // ADC Post Processing Block 3 Result Register +#define ADC_O_PPB4RESULT 0x16U // ADC Post Processing Block 4 Result Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL1 register +// +//************************************************************************************************* +#define ADC_CTL1_INTPULSEPOS 0x4U // ADC Interrupt Pulse Position +#define ADC_CTL1_ADCPWDNZ 0x80U // ADC Power Down +#define ADC_CTL1_ADCBSYCHN_S 8U +#define ADC_CTL1_ADCBSYCHN_M 0xF00U // ADC Busy Channel +#define ADC_CTL1_ADCBSY 0x2000U // ADC Busy + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCTL2 register +// +//************************************************************************************************* +#define ADC_CTL2_PRESCALE_S 0U +#define ADC_CTL2_PRESCALE_M 0xFU // ADC Clock Prescaler +#define ADC_CTL2_RESOLUTION 0x40U // SOC Conversion Resolution +#define ADC_CTL2_SIGNALMODE 0x80U // SOC Signaling Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCBURSTCTL register +// +//************************************************************************************************* +#define ADC_BURSTCTL_BURSTTRIGSEL_S 0U +#define ADC_BURSTCTL_BURSTTRIGSEL_M 0x3FU // SOC Burst Trigger Source Select +#define ADC_BURSTCTL_BURSTSIZE_S 8U +#define ADC_BURSTCTL_BURSTSIZE_M 0xF00U // SOC Burst Size Select +#define ADC_BURSTCTL_BURSTEN 0x8000U // SOC Burst Mode Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLG register +// +//************************************************************************************************* +#define ADC_INTFLG_ADCINT1 0x1U // ADC Interrupt 1 Flag +#define ADC_INTFLG_ADCINT2 0x2U // ADC Interrupt 2 Flag +#define ADC_INTFLG_ADCINT3 0x4U // ADC Interrupt 3 Flag +#define ADC_INTFLG_ADCINT4 0x8U // ADC Interrupt 4 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTFLGCLR register +// +//************************************************************************************************* +#define ADC_INTFLGCLR_ADCINT1 0x1U // ADC Interrupt 1 Flag Clear +#define ADC_INTFLGCLR_ADCINT2 0x2U // ADC Interrupt 2 Flag Clear +#define ADC_INTFLGCLR_ADCINT3 0x4U // ADC Interrupt 3 Flag Clear +#define ADC_INTFLGCLR_ADCINT4 0x8U // ADC Interrupt 4 Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVF register +// +//************************************************************************************************* +#define ADC_INTOVF_ADCINT1 0x1U // ADC Interrupt 1 Overflow Flags +#define ADC_INTOVF_ADCINT2 0x2U // ADC Interrupt 2 Overflow Flags +#define ADC_INTOVF_ADCINT3 0x4U // ADC Interrupt 3 Overflow Flags +#define ADC_INTOVF_ADCINT4 0x8U // ADC Interrupt 4 Overflow Flags + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTOVFCLR register +// +//************************************************************************************************* +#define ADC_INTOVFCLR_ADCINT1 0x1U // ADC Interrupt 1 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT2 0x2U // ADC Interrupt 2 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT3 0x4U // ADC Interrupt 3 Overflow Clear Bits +#define ADC_INTOVFCLR_ADCINT4 0x8U // ADC Interrupt 4 Overflow Clear Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL1N2 register +// +//************************************************************************************************* +#define ADC_INTSEL1N2_INT1SEL_S 0U +#define ADC_INTSEL1N2_INT1SEL_M 0xFU // ADCINT1 EOC Source Select +#define ADC_INTSEL1N2_INT1E 0x20U // ADCINT1 Interrupt Enable +#define ADC_INTSEL1N2_INT1CONT 0x40U // ADCINT1 Continue to Interrupt Mode +#define ADC_INTSEL1N2_INT2SEL_S 8U +#define ADC_INTSEL1N2_INT2SEL_M 0xF00U // ADCINT2 EOC Source Select +#define ADC_INTSEL1N2_INT2E 0x2000U // ADCINT2 Interrupt Enable +#define ADC_INTSEL1N2_INT2CONT 0x4000U // ADCINT2 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSEL3N4 register +// +//************************************************************************************************* +#define ADC_INTSEL3N4_INT3SEL_S 0U +#define ADC_INTSEL3N4_INT3SEL_M 0xFU // ADCINT3 EOC Source Select +#define ADC_INTSEL3N4_INT3E 0x20U // ADCINT3 Interrupt Enable +#define ADC_INTSEL3N4_INT3CONT 0x40U // ADCINT3 Continue to Interrupt Mode +#define ADC_INTSEL3N4_INT4SEL_S 8U +#define ADC_INTSEL3N4_INT4SEL_M 0xF00U // ADCINT4 EOC Source Select +#define ADC_INTSEL3N4_INT4E 0x2000U // ADCINT4 Interrupt Enable +#define ADC_INTSEL3N4_INT4CONT 0x4000U // ADCINT4 Continue to Interrupt Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCPRICTL register +// +//************************************************************************************************* +#define ADC_SOCPRICTL_SOCPRIORITY_S 0U +#define ADC_SOCPRICTL_SOCPRIORITY_M 0x1FU // SOC Priority +#define ADC_SOCPRICTL_RRPOINTER_S 5U +#define ADC_SOCPRICTL_RRPOINTER_M 0x3E0U // Round Robin Pointer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL1 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL1_SOC0_S 0U +#define ADC_INTSOCSEL1_SOC0_M 0x3U // SOC0 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC1_S 2U +#define ADC_INTSOCSEL1_SOC1_M 0xCU // SOC1 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC2_S 4U +#define ADC_INTSOCSEL1_SOC2_M 0x30U // SOC2 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC3_S 6U +#define ADC_INTSOCSEL1_SOC3_M 0xC0U // SOC3 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC4_S 8U +#define ADC_INTSOCSEL1_SOC4_M 0x300U // SOC4 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC5_S 10U +#define ADC_INTSOCSEL1_SOC5_M 0xC00U // SOC5 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC6_S 12U +#define ADC_INTSOCSEL1_SOC6_M 0x3000U // SOC6 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL1_SOC7_S 14U +#define ADC_INTSOCSEL1_SOC7_M 0xC000U // SOC7 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCINTSOCSEL2 register +// +//************************************************************************************************* +#define ADC_INTSOCSEL2_SOC8_S 0U +#define ADC_INTSOCSEL2_SOC8_M 0x3U // SOC8 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC9_S 2U +#define ADC_INTSOCSEL2_SOC9_M 0xCU // SOC9 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC10_S 4U +#define ADC_INTSOCSEL2_SOC10_M 0x30U // SOC10 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC11_S 6U +#define ADC_INTSOCSEL2_SOC11_M 0xC0U // SOC11 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC12_S 8U +#define ADC_INTSOCSEL2_SOC12_M 0x300U // SOC12 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC13_S 10U +#define ADC_INTSOCSEL2_SOC13_M 0xC00U // SOC13 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC14_S 12U +#define ADC_INTSOCSEL2_SOC14_M 0x3000U // SOC14 ADC Interrupt Trigger Select +#define ADC_INTSOCSEL2_SOC15_S 14U +#define ADC_INTSOCSEL2_SOC15_M 0xC000U // SOC15 ADC Interrupt Trigger Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFLG1 register +// +//************************************************************************************************* +#define ADC_SOCFLG1_SOC0 0x1U // SOC0 Start of Conversion Flag +#define ADC_SOCFLG1_SOC1 0x2U // SOC1 Start of Conversion Flag +#define ADC_SOCFLG1_SOC2 0x4U // SOC2 Start of Conversion Flag +#define ADC_SOCFLG1_SOC3 0x8U // SOC3 Start of Conversion Flag +#define ADC_SOCFLG1_SOC4 0x10U // SOC4 Start of Conversion Flag +#define ADC_SOCFLG1_SOC5 0x20U // SOC5 Start of Conversion Flag +#define ADC_SOCFLG1_SOC6 0x40U // SOC6 Start of Conversion Flag +#define ADC_SOCFLG1_SOC7 0x80U // SOC7 Start of Conversion Flag +#define ADC_SOCFLG1_SOC8 0x100U // SOC8 Start of Conversion Flag +#define ADC_SOCFLG1_SOC9 0x200U // SOC9 Start of Conversion Flag +#define ADC_SOCFLG1_SOC10 0x400U // SOC10 Start of Conversion Flag +#define ADC_SOCFLG1_SOC11 0x800U // SOC11 Start of Conversion Flag +#define ADC_SOCFLG1_SOC12 0x1000U // SOC12 Start of Conversion Flag +#define ADC_SOCFLG1_SOC13 0x2000U // SOC13 Start of Conversion Flag +#define ADC_SOCFLG1_SOC14 0x4000U // SOC14 Start of Conversion Flag +#define ADC_SOCFLG1_SOC15 0x8000U // SOC15 Start of Conversion Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCFRC1 register +// +//************************************************************************************************* +#define ADC_SOCFRC1_SOC0 0x1U // SOC0 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC1 0x2U // SOC1 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC2 0x4U // SOC2 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC3 0x8U // SOC3 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC4 0x10U // SOC4 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC5 0x20U // SOC5 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC6 0x40U // SOC6 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC7 0x80U // SOC7 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC8 0x100U // SOC8 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC9 0x200U // SOC9 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC10 0x400U // SOC10 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC11 0x800U // SOC11 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC12 0x1000U // SOC12 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC13 0x2000U // SOC13 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC14 0x4000U // SOC14 Force Start of Conversion Bit +#define ADC_SOCFRC1_SOC15 0x8000U // SOC15 Force Start of Conversion Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVF1 register +// +//************************************************************************************************* +#define ADC_SOCOVF1_SOC0 0x1U // SOC0 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC1 0x2U // SOC1 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC2 0x4U // SOC2 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC3 0x8U // SOC3 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC4 0x10U // SOC4 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC5 0x20U // SOC5 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC6 0x40U // SOC6 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC7 0x80U // SOC7 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC8 0x100U // SOC8 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC9 0x200U // SOC9 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC10 0x400U // SOC10 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC11 0x800U // SOC11 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC12 0x1000U // SOC12 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC13 0x2000U // SOC13 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC14 0x4000U // SOC14 Start of Conversion Overflow Flag +#define ADC_SOCOVF1_SOC15 0x8000U // SOC15 Start of Conversion Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOVFCLR1 register +// +//************************************************************************************************* +#define ADC_SOCOVFCLR1_SOC0 0x1U // SOC0 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC1 0x2U // SOC1 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC2 0x4U // SOC2 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC3 0x8U // SOC3 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC4 0x10U // SOC4 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC5 0x20U // SOC5 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC6 0x40U // SOC6 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC7 0x80U // SOC7 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC8 0x100U // SOC8 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC9 0x200U // SOC9 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC10 0x400U // SOC10 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC11 0x800U // SOC11 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC12 0x1000U // SOC12 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC13 0x2000U // SOC13 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC14 0x4000U // SOC14 Clear Start of Conversion Overflow Bit +#define ADC_SOCOVFCLR1_SOC15 0x8000U // SOC15 Clear Start of Conversion Overflow Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC0CTL register +// +//************************************************************************************************* +#define ADC_SOC0CTL_ACQPS_S 0U +#define ADC_SOC0CTL_ACQPS_M 0x1FFU // SOC0 Acquisition Prescale +#define ADC_SOC0CTL_CHSEL_S 15U +#define ADC_SOC0CTL_CHSEL_M 0x78000U // SOC0 Channel Select +#define ADC_SOC0CTL_TRIGSEL_S 20U +#define ADC_SOC0CTL_TRIGSEL_M 0x1F00000U // SOC0 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC1CTL register +// +//************************************************************************************************* +#define ADC_SOC1CTL_ACQPS_S 0U +#define ADC_SOC1CTL_ACQPS_M 0x1FFU // SOC1 Acquisition Prescale +#define ADC_SOC1CTL_CHSEL_S 15U +#define ADC_SOC1CTL_CHSEL_M 0x78000U // SOC1 Channel Select +#define ADC_SOC1CTL_TRIGSEL_S 20U +#define ADC_SOC1CTL_TRIGSEL_M 0x1F00000U // SOC1 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC2CTL register +// +//************************************************************************************************* +#define ADC_SOC2CTL_ACQPS_S 0U +#define ADC_SOC2CTL_ACQPS_M 0x1FFU // SOC2 Acquisition Prescale +#define ADC_SOC2CTL_CHSEL_S 15U +#define ADC_SOC2CTL_CHSEL_M 0x78000U // SOC2 Channel Select +#define ADC_SOC2CTL_TRIGSEL_S 20U +#define ADC_SOC2CTL_TRIGSEL_M 0x1F00000U // SOC2 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC3CTL register +// +//************************************************************************************************* +#define ADC_SOC3CTL_ACQPS_S 0U +#define ADC_SOC3CTL_ACQPS_M 0x1FFU // SOC3 Acquisition Prescale +#define ADC_SOC3CTL_CHSEL_S 15U +#define ADC_SOC3CTL_CHSEL_M 0x78000U // SOC3 Channel Select +#define ADC_SOC3CTL_TRIGSEL_S 20U +#define ADC_SOC3CTL_TRIGSEL_M 0x1F00000U // SOC3 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC4CTL register +// +//************************************************************************************************* +#define ADC_SOC4CTL_ACQPS_S 0U +#define ADC_SOC4CTL_ACQPS_M 0x1FFU // SOC4 Acquisition Prescale +#define ADC_SOC4CTL_CHSEL_S 15U +#define ADC_SOC4CTL_CHSEL_M 0x78000U // SOC4 Channel Select +#define ADC_SOC4CTL_TRIGSEL_S 20U +#define ADC_SOC4CTL_TRIGSEL_M 0x1F00000U // SOC4 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC5CTL register +// +//************************************************************************************************* +#define ADC_SOC5CTL_ACQPS_S 0U +#define ADC_SOC5CTL_ACQPS_M 0x1FFU // SOC5 Acquisition Prescale +#define ADC_SOC5CTL_CHSEL_S 15U +#define ADC_SOC5CTL_CHSEL_M 0x78000U // SOC5 Channel Select +#define ADC_SOC5CTL_TRIGSEL_S 20U +#define ADC_SOC5CTL_TRIGSEL_M 0x1F00000U // SOC5 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC6CTL register +// +//************************************************************************************************* +#define ADC_SOC6CTL_ACQPS_S 0U +#define ADC_SOC6CTL_ACQPS_M 0x1FFU // SOC6 Acquisition Prescale +#define ADC_SOC6CTL_CHSEL_S 15U +#define ADC_SOC6CTL_CHSEL_M 0x78000U // SOC6 Channel Select +#define ADC_SOC6CTL_TRIGSEL_S 20U +#define ADC_SOC6CTL_TRIGSEL_M 0x1F00000U // SOC6 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC7CTL register +// +//************************************************************************************************* +#define ADC_SOC7CTL_ACQPS_S 0U +#define ADC_SOC7CTL_ACQPS_M 0x1FFU // SOC7 Acquisition Prescale +#define ADC_SOC7CTL_CHSEL_S 15U +#define ADC_SOC7CTL_CHSEL_M 0x78000U // SOC7 Channel Select +#define ADC_SOC7CTL_TRIGSEL_S 20U +#define ADC_SOC7CTL_TRIGSEL_M 0x1F00000U // SOC7 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC8CTL register +// +//************************************************************************************************* +#define ADC_SOC8CTL_ACQPS_S 0U +#define ADC_SOC8CTL_ACQPS_M 0x1FFU // SOC8 Acquisition Prescale +#define ADC_SOC8CTL_CHSEL_S 15U +#define ADC_SOC8CTL_CHSEL_M 0x78000U // SOC8 Channel Select +#define ADC_SOC8CTL_TRIGSEL_S 20U +#define ADC_SOC8CTL_TRIGSEL_M 0x1F00000U // SOC8 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC9CTL register +// +//************************************************************************************************* +#define ADC_SOC9CTL_ACQPS_S 0U +#define ADC_SOC9CTL_ACQPS_M 0x1FFU // SOC9 Acquisition Prescale +#define ADC_SOC9CTL_CHSEL_S 15U +#define ADC_SOC9CTL_CHSEL_M 0x78000U // SOC9 Channel Select +#define ADC_SOC9CTL_TRIGSEL_S 20U +#define ADC_SOC9CTL_TRIGSEL_M 0x1F00000U // SOC9 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC10CTL register +// +//************************************************************************************************* +#define ADC_SOC10CTL_ACQPS_S 0U +#define ADC_SOC10CTL_ACQPS_M 0x1FFU // SOC10 Acquisition Prescale +#define ADC_SOC10CTL_CHSEL_S 15U +#define ADC_SOC10CTL_CHSEL_M 0x78000U // SOC10 Channel Select +#define ADC_SOC10CTL_TRIGSEL_S 20U +#define ADC_SOC10CTL_TRIGSEL_M 0x1F00000U // SOC10 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC11CTL register +// +//************************************************************************************************* +#define ADC_SOC11CTL_ACQPS_S 0U +#define ADC_SOC11CTL_ACQPS_M 0x1FFU // SOC11 Acquisition Prescale +#define ADC_SOC11CTL_CHSEL_S 15U +#define ADC_SOC11CTL_CHSEL_M 0x78000U // SOC11 Channel Select +#define ADC_SOC11CTL_TRIGSEL_S 20U +#define ADC_SOC11CTL_TRIGSEL_M 0x1F00000U // SOC11 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC12CTL register +// +//************************************************************************************************* +#define ADC_SOC12CTL_ACQPS_S 0U +#define ADC_SOC12CTL_ACQPS_M 0x1FFU // SOC12 Acquisition Prescale +#define ADC_SOC12CTL_CHSEL_S 15U +#define ADC_SOC12CTL_CHSEL_M 0x78000U // SOC12 Channel Select +#define ADC_SOC12CTL_TRIGSEL_S 20U +#define ADC_SOC12CTL_TRIGSEL_M 0x1F00000U // SOC12 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC13CTL register +// +//************************************************************************************************* +#define ADC_SOC13CTL_ACQPS_S 0U +#define ADC_SOC13CTL_ACQPS_M 0x1FFU // SOC13 Acquisition Prescale +#define ADC_SOC13CTL_CHSEL_S 15U +#define ADC_SOC13CTL_CHSEL_M 0x78000U // SOC13 Channel Select +#define ADC_SOC13CTL_TRIGSEL_S 20U +#define ADC_SOC13CTL_TRIGSEL_M 0x1F00000U // SOC13 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC14CTL register +// +//************************************************************************************************* +#define ADC_SOC14CTL_ACQPS_S 0U +#define ADC_SOC14CTL_ACQPS_M 0x1FFU // SOC14 Acquisition Prescale +#define ADC_SOC14CTL_CHSEL_S 15U +#define ADC_SOC14CTL_CHSEL_M 0x78000U // SOC14 Channel Select +#define ADC_SOC14CTL_TRIGSEL_S 20U +#define ADC_SOC14CTL_TRIGSEL_M 0x1F00000U // SOC14 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOC15CTL register +// +//************************************************************************************************* +#define ADC_SOC15CTL_ACQPS_S 0U +#define ADC_SOC15CTL_ACQPS_M 0x1FFU // SOC15 Acquisition Prescale +#define ADC_SOC15CTL_CHSEL_S 15U +#define ADC_SOC15CTL_CHSEL_M 0x78000U // SOC15 Channel Select +#define ADC_SOC15CTL_TRIGSEL_S 20U +#define ADC_SOC15CTL_TRIGSEL_M 0x1F00000U // SOC15 Trigger Source Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSTAT register +// +//************************************************************************************************* +#define ADC_EVTSTAT_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Flag +#define ADC_EVTSTAT_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Flag +#define ADC_EVTSTAT_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Flag +#define ADC_EVTSTAT_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Flag +#define ADC_EVTSTAT_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Flag +#define ADC_EVTSTAT_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Flag +#define ADC_EVTSTAT_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Flag +#define ADC_EVTSTAT_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Flag +#define ADC_EVTSTAT_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Flag +#define ADC_EVTSTAT_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Flag +#define ADC_EVTSTAT_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Flag +#define ADC_EVTSTAT_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTCLR register +// +//************************************************************************************************* +#define ADC_EVTCLR_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Clear +#define ADC_EVTCLR_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Clear +#define ADC_EVTCLR_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Clear +#define ADC_EVTCLR_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Clear +#define ADC_EVTCLR_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Clear +#define ADC_EVTCLR_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Clear +#define ADC_EVTCLR_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Clear +#define ADC_EVTCLR_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Clear +#define ADC_EVTCLR_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Clear +#define ADC_EVTCLR_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Clear +#define ADC_EVTCLR_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Clear +#define ADC_EVTCLR_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTSEL register +// +//************************************************************************************************* +#define ADC_EVTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Event Enable +#define ADC_EVTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Event Enable +#define ADC_EVTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Event Enable +#define ADC_EVTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Event Enable +#define ADC_EVTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Event Enable +#define ADC_EVTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Event Enable +#define ADC_EVTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Event Enable +#define ADC_EVTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Event Enable +#define ADC_EVTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Event Enable +#define ADC_EVTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Event Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCEVTINTSEL register +// +//************************************************************************************************* +#define ADC_EVTINTSEL_PPB1TRIPHI 0x1U // Post Processing Block 1 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB1TRIPLO 0x2U // Post Processing Block 1 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB1ZERO 0x4U // Post Processing Block 1 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB2TRIPHI 0x10U // Post Processing Block 2 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB2TRIPLO 0x20U // Post Processing Block 2 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB2ZERO 0x40U // Post Processing Block 2 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB3TRIPHI 0x100U // Post Processing Block 3 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB3TRIPLO 0x200U // Post Processing Block 3 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB3ZERO 0x400U // Post Processing Block 3 Zero Crossing Interrupt + // Enable +#define ADC_EVTINTSEL_PPB4TRIPHI 0x1000U // Post Processing Block 4 Trip High Interrupt Enable +#define ADC_EVTINTSEL_PPB4TRIPLO 0x2000U // Post Processing Block 4 Trip Low Interrupt Enable +#define ADC_EVTINTSEL_PPB4ZERO 0x4000U // Post Processing Block 4 Zero Crossing Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOSDETECT register +// +//************************************************************************************************* +#define ADC_OSDETECT_DETECTCFG_S 0U +#define ADC_OSDETECT_DETECTCFG_M 0x7U // ADC Opens and Shorts Detect Configuration + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCCOUNTER register +// +//************************************************************************************************* +#define ADC_COUNTER_FREECOUNT_S 0U +#define ADC_COUNTER_FREECOUNT_M 0xFFFU // ADC Free Running Counter Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCREV register +// +//************************************************************************************************* +#define ADC_REV_TYPE_S 0U +#define ADC_REV_TYPE_M 0xFFU // ADC Type +#define ADC_REV_REV_S 8U +#define ADC_REV_REV_M 0xFF00U // ADC Revision + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCOFFTRIM register +// +//************************************************************************************************* +#define ADC_OFFTRIM_OFFTRIM_S 0U +#define ADC_OFFTRIM_OFFTRIM_M 0xFFU // ADC Offset Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1CONFIG register +// +//************************************************************************************************* +#define ADC_PPB1CONFIG_CONFIG_S 0U +#define ADC_PPB1CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 1 Configuration +#define ADC_PPB1CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 1 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1STAMP register +// +//************************************************************************************************* +#define ADC_PPB1STAMP_DLYSTAMP_S 0U +#define ADC_PPB1STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 1 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB1OFFCAL_OFFCAL_S 0U +#define ADC_PPB1OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB1TRIPHI_LIMITHI_S 0U +#define ADC_PPB1TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 1 Trip High Limit +#define ADC_PPB1TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB1TRIPLO_LIMITLO_S 0U +#define ADC_PPB1TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 1 Trip Low Limit +#define ADC_PPB1TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB1TRIPLO_REQSTAMP_S 20U +#define ADC_PPB1TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 1 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2CONFIG register +// +//************************************************************************************************* +#define ADC_PPB2CONFIG_CONFIG_S 0U +#define ADC_PPB2CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 2 Configuration +#define ADC_PPB2CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 2 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2STAMP register +// +//************************************************************************************************* +#define ADC_PPB2STAMP_DLYSTAMP_S 0U +#define ADC_PPB2STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 2 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB2OFFCAL_OFFCAL_S 0U +#define ADC_PPB2OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB2TRIPHI_LIMITHI_S 0U +#define ADC_PPB2TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 2 Trip High Limit +#define ADC_PPB2TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB2TRIPLO_LIMITLO_S 0U +#define ADC_PPB2TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 2 Trip Low Limit +#define ADC_PPB2TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB2TRIPLO_REQSTAMP_S 20U +#define ADC_PPB2TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 2 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3CONFIG register +// +//************************************************************************************************* +#define ADC_PPB3CONFIG_CONFIG_S 0U +#define ADC_PPB3CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 3 Configuration +#define ADC_PPB3CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 3 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3STAMP register +// +//************************************************************************************************* +#define ADC_PPB3STAMP_DLYSTAMP_S 0U +#define ADC_PPB3STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 3 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB3OFFCAL_OFFCAL_S 0U +#define ADC_PPB3OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB3TRIPHI_LIMITHI_S 0U +#define ADC_PPB3TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 3 Trip High Limit +#define ADC_PPB3TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB3TRIPLO_LIMITLO_S 0U +#define ADC_PPB3TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 3 Trip Low Limit +#define ADC_PPB3TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB3TRIPLO_REQSTAMP_S 20U +#define ADC_PPB3TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 3 Request Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4CONFIG register +// +//************************************************************************************************* +#define ADC_PPB4CONFIG_CONFIG_S 0U +#define ADC_PPB4CONFIG_CONFIG_M 0xFU // ADC Post Processing Block 4 Configuration +#define ADC_PPB4CONFIG_TWOSCOMPEN 0x10U // ADC Post Processing Block 4 Two's Complement Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4STAMP register +// +//************************************************************************************************* +#define ADC_PPB4STAMP_DLYSTAMP_S 0U +#define ADC_PPB4STAMP_DLYSTAMP_M 0xFFFU // ADC Post Processing Block 4 Delay Time Stamp + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4OFFCAL register +// +//************************************************************************************************* +#define ADC_PPB4OFFCAL_OFFCAL_S 0U +#define ADC_PPB4OFFCAL_OFFCAL_M 0x3FFU // ADC Post Processing Block Offset Correction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPHI register +// +//************************************************************************************************* +#define ADC_PPB4TRIPHI_LIMITHI_S 0U +#define ADC_PPB4TRIPHI_LIMITHI_M 0xFFFFU // ADC Post Processing Block 4 Trip High Limit +#define ADC_PPB4TRIPHI_HSIGN 0x10000U // High Limit Sign Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4TRIPLO register +// +//************************************************************************************************* +#define ADC_PPB4TRIPLO_LIMITLO_S 0U +#define ADC_PPB4TRIPLO_LIMITLO_M 0xFFFFU // ADC Post Processing Block 4 Trip Low Limit +#define ADC_PPB4TRIPLO_LSIGN 0x10000U // Low Limit Sign Bit +#define ADC_PPB4TRIPLO_REQSTAMP_S 20U +#define ADC_PPB4TRIPLO_REQSTAMP_M 0xFFF00000U // ADC Post Processing Block 4 Request Time Stamp + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB1RESULT register +// +//************************************************************************************************* +#define ADC_PPB1RESULT_PPBRESULT_S 0U +#define ADC_PPB1RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB1RESULT_SIGN_S 16U +#define ADC_PPB1RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB2RESULT register +// +//************************************************************************************************* +#define ADC_PPB2RESULT_PPBRESULT_S 0U +#define ADC_PPB2RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB2RESULT_SIGN_S 16U +#define ADC_PPB2RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB3RESULT register +// +//************************************************************************************************* +#define ADC_PPB3RESULT_PPBRESULT_S 0U +#define ADC_PPB3RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB3RESULT_SIGN_S 16U +#define ADC_PPB3RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCPPB4RESULT register +// +//************************************************************************************************* +#define ADC_PPB4RESULT_PPBRESULT_S 0U +#define ADC_PPB4RESULT_PPBRESULT_M 0xFFFFU // ADC Post Processing Block Result +#define ADC_PPB4RESULT_SIGN_S 16U +#define ADC_PPB4RESULT_SIGN_M 0xFFFF0000U // Sign Extended Bits + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_asysctl.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_asysctl.h new file mode 100644 index 0000000..4ee1c62 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_asysctl.h @@ -0,0 +1,145 @@ +//########################################################################### +// +// FILE: hw_asysctl.h +// +// TITLE: Definitions for the ASYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ASYSCTL_H +#define HW_ASYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the ASYSCTL register offsets +// +//************************************************************************************************* +#define ASYSCTL_O_INTOSC1TRIM 0x20U // Internal Oscillator 1 Trim Register +#define ASYSCTL_O_INTOSC2TRIM 0x22U // Internal Oscillator 2 Trim Register +#define ASYSCTL_O_TSNSCTL 0x26U // Temperature Sensor Control Register +#define ASYSCTL_O_LOCK 0x2EU // Lock Register +#define ASYSCTL_O_ANAREFTRIMA 0x36U // Analog Reference Trim A Register +#define ASYSCTL_O_ANAREFTRIMB 0x38U // Analog Reference Trim B Register +#define ASYSCTL_O_ANAREFTRIMC 0x3AU // Analog Reference Trim C Register +#define ASYSCTL_O_ANAREFTRIMD 0x3CU // Analog Reference Trim D Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC1TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC1TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTOSC2TRIM register +// +//************************************************************************************************* +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_S 0U +#define ASYSCTL_INTOSC2TRIM_VALFINETRIM_M 0xFFFU // Oscillator Value Fine Trim Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TSNSCTL register +// +//************************************************************************************************* +#define ASYSCTL_TSNSCTL_ENABLE 0x1U // Temperature Sensor Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOCK register +// +//************************************************************************************************* +#define ASYSCTL_LOCK_TSNSCTL 0x8U // Temperature Sensor Control Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMA 0x800000U // Analog Reference A Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMB 0x1000000U // Analog Reference B Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMC 0x2000000U // Analog Reference C Trim Register Lock +#define ASYSCTL_LOCK_ANAREFTRIMD 0x4000000U // Analog Reference D Trim Register Lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMA register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMA_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMA_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMA_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMB register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMB_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMB_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMB_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMC register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMC_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMC_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMC_IREFTRIM_M 0xF800U // Reference Current Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ANAREFTRIMD register +// +//************************************************************************************************* +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_S 0U +#define ASYSCTL_ANAREFTRIMD_BGVALTRIM_M 0x3FU // Bandgap Value Trim +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_S 6U +#define ASYSCTL_ANAREFTRIMD_BGSLOPETRIM_M 0x7C0U // Bandgap Slope Trim +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_S 11U +#define ASYSCTL_ANAREFTRIMD_IREFTRIM_M 0xF800U // Reference Current Trim + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_can.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_can.h new file mode 100644 index 0000000..05bc58b --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_can.h @@ -0,0 +1,514 @@ +//########################################################################### +// +// FILE: hw_can.h +// +// TITLE: Definitions for the CAN registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CAN_H +#define HW_CAN_H + +//************************************************************************************************* +// +// The following are defines for the CAN register offsets +// +//************************************************************************************************* +#define CAN_O_CTL 0x0U // CAN Control Register +#define CAN_O_ES 0x4U // Error and Status Register +#define CAN_O_ERRC 0x8U // Error Counter Register +#define CAN_O_BTR 0xCU // Bit Timing Register +#define CAN_O_INT 0x10U // Interrupt Register +#define CAN_O_TEST 0x14U // Test Register +#define CAN_O_PERR 0x1CU // CAN Parity Error Code Register +#define CAN_O_RAM_INIT 0x40U // CAN RAM Initialization Register +#define CAN_O_GLB_INT_EN 0x50U // CAN Global Interrupt Enable Register +#define CAN_O_GLB_INT_FLG 0x54U // CAN Global Interrupt Flag Register +#define CAN_O_GLB_INT_CLR 0x58U // CAN Global Interrupt Clear Register +#define CAN_O_ABOTR 0x80U // Auto-Bus-On Time Register +#define CAN_O_TXRQ_X 0x84U // CAN Transmission Request Register +#define CAN_O_TXRQ_21 0x88U // CAN Transmission Request 2_1 Register +#define CAN_O_NDAT_X 0x98U // CAN New Data Register +#define CAN_O_NDAT_21 0x9CU // CAN New Data 2_1 Register +#define CAN_O_IPEN_X 0xACU // CAN Interrupt Pending Register +#define CAN_O_IPEN_21 0xB0U // CAN Interrupt Pending 2_1 Register +#define CAN_O_MVAL_X 0xC0U // CAN Message Valid Register +#define CAN_O_MVAL_21 0xC4U // CAN Message Valid 2_1 Register +#define CAN_O_IP_MUX21 0xD8U // CAN Interrupt Multiplexer 2_1 Register +#define CAN_O_IF1CMD 0x100U // IF1 Command Register +#define CAN_O_IF1MSK 0x104U // IF1 Mask Register +#define CAN_O_IF1ARB 0x108U // IF1 Arbitration Register +#define CAN_O_IF1MCTL 0x10CU // IF1 Message Control Register +#define CAN_O_IF1DATA 0x110U // IF1 Data A Register +#define CAN_O_IF1DATB 0x114U // IF1 Data B Register +#define CAN_O_IF2CMD 0x120U // IF2 Command Register +#define CAN_O_IF2MSK 0x124U // IF2 Mask Register +#define CAN_O_IF2ARB 0x128U // IF2 Arbitration Register +#define CAN_O_IF2MCTL 0x12CU // IF2 Message Control Register +#define CAN_O_IF2DATA 0x130U // IF2 Data A Register +#define CAN_O_IF2DATB 0x134U // IF2 Data B Register +#define CAN_O_IF3OBS 0x140U // IF3 Observation Register +#define CAN_O_IF3MSK 0x144U // IF3 Mask Register +#define CAN_O_IF3ARB 0x148U // IF3 Arbitration Register +#define CAN_O_IF3MCTL 0x14CU // IF3 Message Control Register +#define CAN_O_IF3DATA 0x150U // IF3 Data A Register +#define CAN_O_IF3DATB 0x154U // IF3 Data B Register +#define CAN_O_IF3UPD 0x160U // IF3 Update Enable Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_CTL register +// +//************************************************************************************************* +#define CAN_CTL_INIT 0x1U // Initialization +#define CAN_CTL_IE0 0x2U // Interrupt line 0 Enable +#define CAN_CTL_SIE 0x4U // Status Change Interrupt Enable +#define CAN_CTL_EIE 0x8U // Error Interrupt Enable +#define CAN_CTL_DAR 0x20U // Disable Automatic Retransmission +#define CAN_CTL_CCE 0x40U // Configuration Change Enable +#define CAN_CTL_TEST 0x80U // Test Mode Enable +#define CAN_CTL_IDS 0x100U // Interruption Debug Support Enable +#define CAN_CTL_ABO 0x200U // Auto-Bus-On Enable +#define CAN_CTL_PMD_S 10U +#define CAN_CTL_PMD_M 0x3C00U // Parity on/off +#define CAN_CTL_SWR 0x8000U // SW Reset Enable +#define CAN_CTL_INITDBG 0x10000U // Debug Mode Status +#define CAN_CTL_IE1 0x20000U // Interrupt line 1 Enable Disabled + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ES register +// +//************************************************************************************************* +#define CAN_ES_LEC_S 0U +#define CAN_ES_LEC_M 0x7U // Last Error Code +#define CAN_ES_TXOK 0x8U // Transmission status +#define CAN_ES_RXOK 0x10U // Reception status +#define CAN_ES_EPASS 0x20U // Error Passive State +#define CAN_ES_EWARN 0x40U // Warning State +#define CAN_ES_BOFF 0x80U // Bus-Off State +#define CAN_ES_PER 0x100U // Parity Error Detected + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_ERRC register +// +//************************************************************************************************* +#define CAN_ERRC_TEC_S 0U +#define CAN_ERRC_TEC_M 0xFFU // Transmit Error Counter +#define CAN_ERRC_REC_S 8U +#define CAN_ERRC_REC_M 0x7F00U // Receive Error Counter +#define CAN_ERRC_RP 0x8000U // Receive Error Passive + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_BTR register +// +//************************************************************************************************* +#define CAN_BTR_BRP_S 0U +#define CAN_BTR_BRP_M 0x3FU // Baud Rate Prescaler +#define CAN_BTR_SJW_S 6U +#define CAN_BTR_SJW_M 0xC0U // Synchronization Jump Width +#define CAN_BTR_TSEG1_S 8U +#define CAN_BTR_TSEG1_M 0xF00U // Time segment +#define CAN_BTR_TSEG2_S 12U +#define CAN_BTR_TSEG2_M 0x7000U // Time segment +#define CAN_BTR_BRPE_S 16U +#define CAN_BTR_BRPE_M 0xF0000U // Baud Rate Prescaler Extension + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_INT register +// +//************************************************************************************************* +#define CAN_INT_INT0ID_S 0U +#define CAN_INT_INT0ID_M 0xFFFFU // Interrupt Identifier +#define CAN_INT_INT1ID_S 16U +#define CAN_INT_INT1ID_M 0xFF0000U // Interrupt 1 Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TEST register +// +//************************************************************************************************* +#define CAN_TEST_SILENT 0x8U // Silent Mode +#define CAN_TEST_LBACK 0x10U // Loopback Mode +#define CAN_TEST_TX_S 5U +#define CAN_TEST_TX_M 0x60U // CANTX Pin Control +#define CAN_TEST_RX 0x80U // CANRX Pin Status +#define CAN_TEST_EXL 0x100U // External Loopback Mode +#define CAN_TEST_RDA 0x200U // RAM Direct Access Enable: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_PERR register +// +//************************************************************************************************* +#define CAN_PERR_MSG_NUM_S 0U +#define CAN_PERR_MSG_NUM_M 0xFFU // Message Number +#define CAN_PERR_WORD_NUM_S 8U +#define CAN_PERR_WORD_NUM_M 0x700U // Word Number + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_RAM_INIT register +// +//************************************************************************************************* +#define CAN_RAM_INIT_KEY0 0x1U // KEY0 +#define CAN_RAM_INIT_KEY1 0x2U // KEY1 +#define CAN_RAM_INIT_KEY2 0x4U // KEY2 +#define CAN_RAM_INIT_KEY3 0x8U // KEY3 +#define CAN_RAM_INIT_CAN_RAM_INIT 0x10U // Initialize CAN Mailbox RAM +#define CAN_RAM_INIT_RAM_INIT_DONE 0x20U // CAN RAM initialization complete + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_EN register +// +//************************************************************************************************* +#define CAN_GLB_INT_EN_GLBINT0_EN 0x1U // Global Interrupt Enable for CANINT0 +#define CAN_GLB_INT_EN_GLBINT1_EN 0x2U // Global Interrupt Enable for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_FLG register +// +//************************************************************************************************* +#define CAN_GLB_INT_FLG_INT0_FLG 0x1U // Global Interrupt Flag for CANINT0 +#define CAN_GLB_INT_FLG_INT1_FLG 0x2U // Global Interrupt Flag for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_GLB_INT_CLR register +// +//************************************************************************************************* +#define CAN_GLB_INT_CLR_INT0_FLG_CLR 0x1U // Global Interrupt flag clear for CANINT0 +#define CAN_GLB_INT_CLR_INT1_FLG_CLR 0x2U // Global Interrupt flag clear for CANINT1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_TXRQ_X register +// +//************************************************************************************************* +#define CAN_TXRQ_X_TXRQSTREG1_S 0U +#define CAN_TXRQ_X_TXRQSTREG1_M 0x3U // Transmit Request Register 1 +#define CAN_TXRQ_X_TXRQSTREG2_S 2U +#define CAN_TXRQ_X_TXRQSTREG2_M 0xCU // Transmit Request Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_NDAT_X register +// +//************************************************************************************************* +#define CAN_NDAT_X_NEWDATREG1_S 0U +#define CAN_NDAT_X_NEWDATREG1_M 0x3U // New Data Register 1 +#define CAN_NDAT_X_NEWDATREG2_S 2U +#define CAN_NDAT_X_NEWDATREG2_M 0xCU // New Data Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IPEN_X register +// +//************************************************************************************************* +#define CAN_IPEN_X_INTPNDREG1_S 0U +#define CAN_IPEN_X_INTPNDREG1_M 0x3U // Interrupt Pending Register 1 +#define CAN_IPEN_X_INTPNDREG2_S 2U +#define CAN_IPEN_X_INTPNDREG2_M 0xCU // Interrupt Pending Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_MVAL_X register +// +//************************************************************************************************* +#define CAN_MVAL_X_MSGVALREG1_S 0U +#define CAN_MVAL_X_MSGVALREG1_M 0x3U // Message Valid Register 1 +#define CAN_MVAL_X_MSGVALREG2_S 2U +#define CAN_MVAL_X_MSGVALREG2_M 0xCU // Message Valid Register 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1CMD register +// +//************************************************************************************************* +#define CAN_IF1CMD_MSG_NUM_S 0U +#define CAN_IF1CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF1CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF1CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF1CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF1CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF1CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF1CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF1CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF1CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF1CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MSK register +// +//************************************************************************************************* +#define CAN_IF1MSK_MSK_S 0U +#define CAN_IF1MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF1MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF1MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1ARB register +// +//************************************************************************************************* +#define CAN_IF1ARB_ID_S 0U +#define CAN_IF1ARB_ID_M 0x1FFFFFFFU // ` +#define CAN_IF1ARB_DIR 0x20000000U // Message Direction +#define CAN_IF1ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF1ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1MCTL register +// +//************************************************************************************************* +#define CAN_IF1MCTL_DLC_S 0U +#define CAN_IF1MCTL_DLC_M 0xFU // Data length code +#define CAN_IF1MCTL_EOB 0x80U // End of Block +#define CAN_IF1MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF1MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF1MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF1MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF1MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF1MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF1MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF1MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATA register +// +//************************************************************************************************* +#define CAN_IF1DATA_DATA_0_S 0U +#define CAN_IF1DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF1DATA_DATA_1_S 8U +#define CAN_IF1DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF1DATA_DATA_2_S 16U +#define CAN_IF1DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF1DATA_DATA_3_S 24U +#define CAN_IF1DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF1DATB register +// +//************************************************************************************************* +#define CAN_IF1DATB_DATA_4_S 0U +#define CAN_IF1DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF1DATB_DATA_5_S 8U +#define CAN_IF1DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF1DATB_DATA_6_S 16U +#define CAN_IF1DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF1DATB_DATA_7_S 24U +#define CAN_IF1DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2CMD register +// +//************************************************************************************************* +#define CAN_IF2CMD_MSG_NUM_S 0U +#define CAN_IF2CMD_MSG_NUM_M 0xFFU // Message Number +#define CAN_IF2CMD_BUSY 0x8000U // Busy Flag +#define CAN_IF2CMD_DATA_B 0x10000U // Access Data Bytes 4-7 +#define CAN_IF2CMD_DATA_A 0x20000U // Access Data Bytes 0-3 +#define CAN_IF2CMD_TXRQST 0x40000U // Access Transmission Request Bit +#define CAN_IF2CMD_CLRINTPND 0x80000U // Clear Interrupt Pending Bit +#define CAN_IF2CMD_CONTROL 0x100000U // Access Control Bits +#define CAN_IF2CMD_ARB 0x200000U // Access Arbitration Bits +#define CAN_IF2CMD_MASK 0x400000U // Access Mask Bits +#define CAN_IF2CMD_DIR 0x800000U // Write/Read Direction + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MSK register +// +//************************************************************************************************* +#define CAN_IF2MSK_MSK_S 0U +#define CAN_IF2MSK_MSK_M 0x1FFFFFFFU // Identifier Mask +#define CAN_IF2MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF2MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2ARB register +// +//************************************************************************************************* +#define CAN_IF2ARB_ID_S 0U +#define CAN_IF2ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF2ARB_DIR 0x20000000U // Message Direction +#define CAN_IF2ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF2ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2MCTL register +// +//************************************************************************************************* +#define CAN_IF2MCTL_DLC_S 0U +#define CAN_IF2MCTL_DLC_M 0xFU // Data length code +#define CAN_IF2MCTL_EOB 0x80U // End of Block +#define CAN_IF2MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF2MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF2MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF2MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF2MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF2MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF2MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF2MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATA register +// +//************************************************************************************************* +#define CAN_IF2DATA_DATA_0_S 0U +#define CAN_IF2DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF2DATA_DATA_1_S 8U +#define CAN_IF2DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF2DATA_DATA_2_S 16U +#define CAN_IF2DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF2DATA_DATA_3_S 24U +#define CAN_IF2DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF2DATB register +// +//************************************************************************************************* +#define CAN_IF2DATB_DATA_4_S 0U +#define CAN_IF2DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF2DATB_DATA_5_S 8U +#define CAN_IF2DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF2DATB_DATA_6_S 16U +#define CAN_IF2DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF2DATB_DATA_7_S 24U +#define CAN_IF2DATB_DATA_7_M 0xFF000000U // Data Byte 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3OBS register +// +//************************************************************************************************* +#define CAN_IF3OBS_MASK 0x1U // Mask data read observation +#define CAN_IF3OBS_ARB 0x2U // Arbitration data read observation +#define CAN_IF3OBS_CTRL 0x4U // Ctrl read observation +#define CAN_IF3OBS_DATA_A 0x8U // Data A read observation +#define CAN_IF3OBS_DATA_B 0x10U // Data B read observation +#define CAN_IF3OBS_IF3SM 0x100U // IF3 Status of Mask data read access +#define CAN_IF3OBS_IF3SA 0x200U // IF3 Status of Arbitration data read access +#define CAN_IF3OBS_IF3SC 0x400U // IF3 Status of Control bits read access +#define CAN_IF3OBS_IF3SDA 0x800U // IF3 Status of Data A read access +#define CAN_IF3OBS_IF3SDB 0x1000U // IF3 Status of Data B read access +#define CAN_IF3OBS_IF3UPD 0x8000U // IF3 Update Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MSK register +// +//************************************************************************************************* +#define CAN_IF3MSK_MSK_S 0U +#define CAN_IF3MSK_MSK_M 0x1FFFFFFFU // Mask +#define CAN_IF3MSK_MDIR 0x40000000U // Mask Message Direction +#define CAN_IF3MSK_MXTD 0x80000000U // Mask Extended Identifier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3ARB register +// +//************************************************************************************************* +#define CAN_IF3ARB_ID_S 0U +#define CAN_IF3ARB_ID_M 0x1FFFFFFFU // Message Identifier +#define CAN_IF3ARB_DIR 0x20000000U // Message Direction +#define CAN_IF3ARB_XTD 0x40000000U // Extended Identifier +#define CAN_IF3ARB_MSGVAL 0x80000000U // Message Valid + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3MCTL register +// +//************************************************************************************************* +#define CAN_IF3MCTL_DLC_S 0U +#define CAN_IF3MCTL_DLC_M 0xFU // Data length code +#define CAN_IF3MCTL_EOB 0x80U // End of Block +#define CAN_IF3MCTL_TXRQST 0x100U // Transmit Request +#define CAN_IF3MCTL_RMTEN 0x200U // Remote Enable +#define CAN_IF3MCTL_RXIE 0x400U // Receive Interrupt Enable +#define CAN_IF3MCTL_TXIE 0x800U // Transmit Interrupt Enable +#define CAN_IF3MCTL_UMASK 0x1000U // Use Acceptance Mask +#define CAN_IF3MCTL_INTPND 0x2000U // Interrupt Pending +#define CAN_IF3MCTL_MSGLST 0x4000U // Message Lost +#define CAN_IF3MCTL_NEWDAT 0x8000U // New Data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATA register +// +//************************************************************************************************* +#define CAN_IF3DATA_DATA_0_S 0U +#define CAN_IF3DATA_DATA_0_M 0xFFU // Data Byte 0 +#define CAN_IF3DATA_DATA_1_S 8U +#define CAN_IF3DATA_DATA_1_M 0xFF00U // Data Byte 1 +#define CAN_IF3DATA_DATA_2_S 16U +#define CAN_IF3DATA_DATA_2_M 0xFF0000U // Data Byte 2 +#define CAN_IF3DATA_DATA_3_S 24U +#define CAN_IF3DATA_DATA_3_M 0xFF000000U // Data Byte 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CAN_IF3DATB register +// +//************************************************************************************************* +#define CAN_IF3DATB_DATA_4_S 0U +#define CAN_IF3DATB_DATA_4_M 0xFFU // Data Byte 4 +#define CAN_IF3DATB_DATA_5_S 8U +#define CAN_IF3DATB_DATA_5_M 0xFF00U // Data Byte 5 +#define CAN_IF3DATB_DATA_6_S 16U +#define CAN_IF3DATB_DATA_6_M 0xFF0000U // Data Byte 6 +#define CAN_IF3DATB_DATA_7_S 24U +#define CAN_IF3DATB_DATA_7_M 0xFF000000U // Data Byte 7 + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_cla.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cla.h new file mode 100644 index 0000000..0206de7 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cla.h @@ -0,0 +1,241 @@ +//########################################################################### +// +// FILE: hw_cla.h +// +// TITLE: Definitions for the CLA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLA_H +#define HW_CLA_H + +//************************************************************************************************* +// +// The following are defines for the CLA register offsets +// +//************************************************************************************************* +#ifndef __TMS320C28XX_CLA__ +#define CLA_O_MVECT1 0x0U // Task Interrupt Vector +#define CLA_O_MVECT2 0x1U // Task Interrupt Vector +#define CLA_O_MVECT3 0x2U // Task Interrupt Vector +#define CLA_O_MVECT4 0x3U // Task Interrupt Vector +#define CLA_O_MVECT5 0x4U // Task Interrupt Vector +#define CLA_O_MVECT6 0x5U // Task Interrupt Vector +#define CLA_O_MVECT7 0x6U // Task Interrupt Vector +#define CLA_O_MVECT8 0x7U // Task Interrupt Vector +#define CLA_O_MCTL 0x10U // Control Register +#define CLA_O_MIFR 0x20U // Interrupt Flag Register +#define CLA_O_MIOVF 0x21U // Interrupt Overflow Flag Register +#define CLA_O_MIFRC 0x22U // Interrupt Force Register +#define CLA_O_MICLR 0x23U // Interrupt Flag Clear Register +#define CLA_O_MICLROVF 0x24U // Interrupt Overflow Flag Clear Register +#define CLA_O_MIER 0x25U // Interrupt Enable Register +#define CLA_O_MIRUN 0x26U // Interrupt Run Status Register +#define CLA_O_MPC 0x28U // CLA Program Counter +#define CLA_O_MAR0 0x2AU // CLA Auxiliary Register 0 +#define CLA_O_MAR1 0x2BU // CLA Auxiliary Register 1 +#define CLA_O_MSTF 0x2EU // CLA Floating-Point Status Register +#define CLA_O_MR0 0x30U // CLA Floating-Point Result Register 0 +#define CLA_O_MR1 0x34U // CLA Floating-Point Result Register 1 +#define CLA_O_MR2 0x38U // CLA Floating-Point Result Register 2 +#define CLA_O_MR3 0x3CU // CLA Floating-Point Result Register 3 +#endif + +#ifdef __TMS320C28XX_CLA__ +#define CLA_O_SOFTINTEN 0x0U // CLA Software Interrupt Enable Register +#define CLA_O_SOFTINTFRC 0x2U // CLA Software Interrupt Force Register +#endif + + +#ifndef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCTL register +// +//************************************************************************************************* +#define CLA_MCTL_HARDRESET 0x1U // Hard Reset +#define CLA_MCTL_SOFTRESET 0x2U // Soft Reset +#define CLA_MCTL_IACKE 0x4U // IACK enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFR register +// +//************************************************************************************************* +#define CLA_MIFR_INT1 0x1U // Task 1 Interrupt Flag +#define CLA_MIFR_INT2 0x2U // Task 2 Interrupt Flag +#define CLA_MIFR_INT3 0x4U // Task 3 Interrupt Flag +#define CLA_MIFR_INT4 0x8U // Task 4 Interrupt Flag +#define CLA_MIFR_INT5 0x10U // Task 5 Interrupt Flag +#define CLA_MIFR_INT6 0x20U // Task 6 Interrupt Flag +#define CLA_MIFR_INT7 0x40U // Task 7 Interrupt Flag +#define CLA_MIFR_INT8 0x80U // Task 8 Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIOVF register +// +//************************************************************************************************* +#define CLA_MIOVF_INT1 0x1U // Task 1 Interrupt Overflow Flag +#define CLA_MIOVF_INT2 0x2U // Task 2 Interrupt Overflow Flag +#define CLA_MIOVF_INT3 0x4U // Task 3 Interrupt Overflow Flag +#define CLA_MIOVF_INT4 0x8U // Task 4 Interrupt Overflow Flag +#define CLA_MIOVF_INT5 0x10U // Task 5 Interrupt Overflow Flag +#define CLA_MIOVF_INT6 0x20U // Task 6 Interrupt Overflow Flag +#define CLA_MIOVF_INT7 0x40U // Task 7 Interrupt Overflow Flag +#define CLA_MIOVF_INT8 0x80U // Task 8 Interrupt Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIFRC register +// +//************************************************************************************************* +#define CLA_MIFRC_INT1 0x1U // Task 1 Interrupt Force +#define CLA_MIFRC_INT2 0x2U // Task 2 Interrupt Force +#define CLA_MIFRC_INT3 0x4U // Task 3 Interrupt Force +#define CLA_MIFRC_INT4 0x8U // Task 4 Interrupt Force +#define CLA_MIFRC_INT5 0x10U // Task 5 Interrupt Force +#define CLA_MIFRC_INT6 0x20U // Task 6 Interrupt Force +#define CLA_MIFRC_INT7 0x40U // Task 7 Interrupt Force +#define CLA_MIFRC_INT8 0x80U // Task 8 Interrupt Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLR register +// +//************************************************************************************************* +#define CLA_MICLR_INT1 0x1U // Task 1 Interrupt Flag Clear +#define CLA_MICLR_INT2 0x2U // Task 2 Interrupt Flag Clear +#define CLA_MICLR_INT3 0x4U // Task 3 Interrupt Flag Clear +#define CLA_MICLR_INT4 0x8U // Task 4 Interrupt Flag Clear +#define CLA_MICLR_INT5 0x10U // Task 5 Interrupt Flag Clear +#define CLA_MICLR_INT6 0x20U // Task 6 Interrupt Flag Clear +#define CLA_MICLR_INT7 0x40U // Task 7 Interrupt Flag Clear +#define CLA_MICLR_INT8 0x80U // Task 8 Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MICLROVF register +// +//************************************************************************************************* +#define CLA_MICLROVF_INT1 0x1U // Task 1 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT2 0x2U // Task 2 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT3 0x4U // Task 3 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT4 0x8U // Task 4 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT5 0x10U // Task 5 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT6 0x20U // Task 6 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT7 0x40U // Task 7 Interrupt Overflow Flag Clear +#define CLA_MICLROVF_INT8 0x80U // Task 8 Interrupt Overflow Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIER register +// +//************************************************************************************************* +#define CLA_MIER_INT1 0x1U // Task 1 Interrupt Enable +#define CLA_MIER_INT2 0x2U // Task 2 Interrupt Enable +#define CLA_MIER_INT3 0x4U // Task 3 Interrupt Enable +#define CLA_MIER_INT4 0x8U // Task 4 Interrupt Enable +#define CLA_MIER_INT5 0x10U // Task 5 Interrupt Enable +#define CLA_MIER_INT6 0x20U // Task 6 Interrupt Enable +#define CLA_MIER_INT7 0x40U // Task 7 Interrupt Enable +#define CLA_MIER_INT8 0x80U // Task 8 Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MIRUN register +// +//************************************************************************************************* +#define CLA_MIRUN_INT1 0x1U // Task 1 Run Status +#define CLA_MIRUN_INT2 0x2U // Task 2 Run Status +#define CLA_MIRUN_INT3 0x4U // Task 3 Run Status +#define CLA_MIRUN_INT4 0x8U // Task 4 Run Status +#define CLA_MIRUN_INT5 0x10U // Task 5 Run Status +#define CLA_MIRUN_INT6 0x20U // Task 6 Run Status +#define CLA_MIRUN_INT7 0x40U // Task 7 Run Status +#define CLA_MIRUN_INT8 0x80U // Task 8 Run Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the _MSTF register +// +//************************************************************************************************* +#define CLA_MSTF_LVF 0x1U // Latched Overflow Flag +#define CLA_MSTF_LUF 0x2U // Latched Underflow Flag +#define CLA_MSTF_NF 0x4U // Negative Float Flag +#define CLA_MSTF_ZF 0x8U // Zero Float Flag +#define CLA_MSTF_TF 0x40U // Test Flag +#define CLA_MSTF_RNDF32 0x200U // Round 32-bit Floating-Point Mode +#define CLA_MSTF_MEALLOW 0x800U // MEALLOW Status +#define CLA_MSTF_RPC_S 12U +#define CLA_MSTF_RPC_M 0xFFFF000U // Return PC + +#endif + +#ifdef __TMS320C28XX_CLA__ +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTEN register +// +//************************************************************************************************* +#define CLA_SOFTINTEN_TASK1 0x1U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK2 0x2U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK3 0x4U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK4 0x8U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK5 0x10U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK6 0x20U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK7 0x40U // Configure Software Interrupt or End of Task interrupt. +#define CLA_SOFTINTEN_TASK8 0x80U // Configure Software Interrupt or End of Task interrupt. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTINTFRC register +// +//************************************************************************************************* +#define CLA_SOFTINTFRC_TASK1 0x1U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK2 0x2U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK3 0x4U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK4 0x8U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK5 0x10U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK6 0x20U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK7 0x40U // Force CLA software interrupt for the corresponding task. +#define CLA_SOFTINTFRC_TASK8 0x80U // Force CLA software interrupt for the corresponding task. + +#endif + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_clb.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_clb.h new file mode 100644 index 0000000..4390004 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_clb.h @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: hw_clb.h +// +// TITLE: Definitions for the CLB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLB_H +#define HW_CLB_H + +//************************************************************************************************* +// +// The following are defines for the CLB register offsets +// +//************************************************************************************************* +#define CLB_O_COUNT_RESET 0x2U // Counter Block RESET +#define CLB_O_COUNT_MODE_1 0x4U // Counter Block MODE_1 +#define CLB_O_COUNT_MODE_0 0x6U // Counter Block MODE_0 +#define CLB_O_COUNT_EVENT 0x8U // Counter Block EVENT +#define CLB_O_FSM_EXTRA_IN0 0xAU // FSM Extra EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN0 0xCU // FSM EXT_IN0 +#define CLB_O_FSM_EXTERNAL_IN1 0xEU // FSM_EXT_IN1 +#define CLB_O_FSM_EXTRA_IN1 0x10U // FSM Extra_EXT_IN1 +#define CLB_O_LUT4_IN0 0x12U // LUT4_0/1/2 IN0 input source +#define CLB_O_LUT4_IN1 0x14U // LUT4_0/1/2 IN1 input source +#define CLB_O_LUT4_IN2 0x16U // LUT4_0/1/2 IN2 input source +#define CLB_O_LUT4_IN3 0x18U // LUT4_0/1/2 IN3 input source +#define CLB_O_FSM_LUT_FN1_0 0x1CU // LUT function for FSM Unit 1 and Unit 0 +#define CLB_O_FSM_LUT_FN2 0x1EU // LUT function for FSM Unit 2 +#define CLB_O_LUT4_FN1_0 0x20U // LUT function for LUT4 block of Unit 1 and 0 +#define CLB_O_LUT4_FN2 0x22U // LUT function for LUT4 block of Unit 2 +#define CLB_O_FSM_NEXT_STATE_0 0x24U // FSM Next state equations for Unit 0 +#define CLB_O_FSM_NEXT_STATE_1 0x26U // FSM Next state equations for Unit 1 +#define CLB_O_FSM_NEXT_STATE_2 0x28U // FSM Next state equations for Unit 2 +#define CLB_O_MISC_CONTROL 0x2AU // Static controls for Ctr,FSM +#define CLB_O_OUTPUT_LUT_0 0x2CU // Inp Sel, LUT fns for Out0 +#define CLB_O_OUTPUT_LUT_1 0x2EU // Inp Sel, LUT fns for Out1 +#define CLB_O_OUTPUT_LUT_2 0x30U // Inp Sel, LUT fns for Out2 +#define CLB_O_OUTPUT_LUT_3 0x32U // Inp Sel, LUT fns for Out3 +#define CLB_O_OUTPUT_LUT_4 0x34U // Inp Sel, LUT fns for Out4 +#define CLB_O_OUTPUT_LUT_5 0x36U // Inp Sel, LUT fns for Out5 +#define CLB_O_OUTPUT_LUT_6 0x38U // Inp Sel, LUT fns for Out6 +#define CLB_O_OUTPUT_LUT_7 0x3AU // Inp Sel, LUT fns for Out7 +#define CLB_O_HLC_EVENT_SEL 0x3CU // Event Selector register for the High Level controller + +#define CLB_O_LOAD_EN 0x0U // Global enable & indirect load enable control +#define CLB_O_LOAD_ADDR 0x2U // Indirect address +#define CLB_O_LOAD_DATA 0x4U // Data for indirect loads +#define CLB_O_INPUT_FILTER 0x6U // Input filter selection for both edge detection and + // synchronizers +#define CLB_O_IN_MUX_SEL_0 0x8U // Input selection to decide between Signals and GP register +#define CLB_O_LCL_MUX_SEL_1 0xAU // Input Mux selection for local mux +#define CLB_O_LCL_MUX_SEL_2 0xCU // Input Mux selection for local mux +#define CLB_O_BUF_PTR 0xEU // PUSH and PULL pointers +#define CLB_O_GP_REG 0x10U // General purpose register for CELL inputs +#define CLB_O_OUT_EN 0x12U // CELL output enable register +#define CLB_O_GLBL_MUX_SEL_1 0x14U // Global Mux select for CELL inputs +#define CLB_O_GLBL_MUX_SEL_2 0x16U // Global Mux select for CELL inputs +#define CLB_O_INTR_TAG_REG 0x20U // Interrupt Tag register +#define CLB_O_LOCK 0x22U // Lock control register +#define CLB_O_DBG_R0 0x30U // R0 of High level Controller +#define CLB_O_DBG_R1 0x32U // R1 of High level Controller +#define CLB_O_DBG_R2 0x34U // R2 of High level Controller +#define CLB_O_DBG_R3 0x36U // R3 of High level Controller +#define CLB_O_DBG_C0 0x38U // Count of Unit 0 +#define CLB_O_DBG_C1 0x3AU // Count of Unit 1 +#define CLB_O_DBG_C2 0x3CU // Count of Unit 2 +#define CLB_O_DBG_OUT 0x3EU // Outputs of various units in the Cell + +#define CLB_O_PUSH(i) (0x0U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PUSH FIFO Registers (from + // HLC) +#define CLB_O_PULL(i) (0x100U + ((i) * 0x2U)) // (0 <= i < 4) CLB_PULL FIFO Registers (TO HLC) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_RESET register +// +//************************************************************************************************* +#define CLB_COUNT_RESET_SEL_0_S 0U +#define CLB_COUNT_RESET_SEL_0_M 0x1FU // Count Reset Select 0 +#define CLB_COUNT_RESET_SEL_1_S 5U +#define CLB_COUNT_RESET_SEL_1_M 0x3E0U // Count Reset Select 1 +#define CLB_COUNT_RESET_SEL_2_S 10U +#define CLB_COUNT_RESET_SEL_2_M 0x7C00U // Count Reset Select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_1 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_1_SEL_0_S 0U +#define CLB_COUNT_MODE_1_SEL_0_M 0x1FU // Counter mode 1 select 0 +#define CLB_COUNT_MODE_1_SEL_1_S 5U +#define CLB_COUNT_MODE_1_SEL_1_M 0x3E0U // Counter mode 1 select 1 +#define CLB_COUNT_MODE_1_SEL_2_S 10U +#define CLB_COUNT_MODE_1_SEL_2_M 0x7C00U // Counter mode 1 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_MODE_0 register +// +//************************************************************************************************* +#define CLB_COUNT_MODE_0_SEL_0_S 0U +#define CLB_COUNT_MODE_0_SEL_0_M 0x1FU // Counter mode 0 select 0 +#define CLB_COUNT_MODE_0_SEL_1_S 5U +#define CLB_COUNT_MODE_0_SEL_1_M 0x3E0U // Counter mode 0 select 1 +#define CLB_COUNT_MODE_0_SEL_2_S 10U +#define CLB_COUNT_MODE_0_SEL_2_M 0x7C00U // Counter mode 0 select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_COUNT_EVENT register +// +//************************************************************************************************* +#define CLB_COUNT_EVENT_SEL_0_S 0U +#define CLB_COUNT_EVENT_SEL_0_M 0x1FU // Counter event select 0 +#define CLB_COUNT_EVENT_SEL_1_S 5U +#define CLB_COUNT_EVENT_SEL_1_M 0x3E0U // Counter event select 1 +#define CLB_COUNT_EVENT_SEL_2_S 10U +#define CLB_COUNT_EVENT_SEL_2_M 0x7C00U // Counter event select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN0_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN0_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN0_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN0_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN0_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN0_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN0 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN0_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN0_SEL_0_M 0x1FU // FSM EXT_IN0 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN0_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN0_SEL_1_M 0x3E0U // FSM EXT_IN0 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN0_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN0_SEL_2_M 0x7C00U // FSM EXT_IN0 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTERNAL_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTERNAL_IN1_SEL_0_S 0U +#define CLB_FSM_EXTERNAL_IN1_SEL_0_M 0x1FU // FSM EXT_IN1 select input for unit 0 +#define CLB_FSM_EXTERNAL_IN1_SEL_1_S 5U +#define CLB_FSM_EXTERNAL_IN1_SEL_1_M 0x3E0U // FSM EXT_IN1 select input for unit 1 +#define CLB_FSM_EXTERNAL_IN1_SEL_2_S 10U +#define CLB_FSM_EXTERNAL_IN1_SEL_2_M 0x7C00U // FSM EXT_IN1 select input for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_EXTRA_IN1 register +// +//************************************************************************************************* +#define CLB_FSM_EXTRA_IN1_SEL_0_S 0U +#define CLB_FSM_EXTRA_IN1_SEL_0_M 0x1FU // FSM extra ext input select 0 +#define CLB_FSM_EXTRA_IN1_SEL_1_S 5U +#define CLB_FSM_EXTRA_IN1_SEL_1_M 0x3E0U // FSM extra ext input select 1 +#define CLB_FSM_EXTRA_IN1_SEL_2_S 10U +#define CLB_FSM_EXTRA_IN1_SEL_2_M 0x7C00U // FSM extra ext input select 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN0 register +// +//************************************************************************************************* +#define CLB_LUT4_IN0_SEL_0_S 0U +#define CLB_LUT4_IN0_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN0_SEL_1_S 5U +#define CLB_LUT4_IN0_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN0_SEL_2_S 10U +#define CLB_LUT4_IN0_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN1 register +// +//************************************************************************************************* +#define CLB_LUT4_IN1_SEL_0_S 0U +#define CLB_LUT4_IN1_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN1_SEL_1_S 5U +#define CLB_LUT4_IN1_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN1_SEL_2_S 10U +#define CLB_LUT4_IN1_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN2 register +// +//************************************************************************************************* +#define CLB_LUT4_IN2_SEL_0_S 0U +#define CLB_LUT4_IN2_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN2_SEL_1_S 5U +#define CLB_LUT4_IN2_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN2_SEL_2_S 10U +#define CLB_LUT4_IN2_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_IN3 register +// +//************************************************************************************************* +#define CLB_LUT4_IN3_SEL_0_S 0U +#define CLB_LUT4_IN3_SEL_0_M 0x1FU // Select inputs for unit 0 +#define CLB_LUT4_IN3_SEL_1_S 5U +#define CLB_LUT4_IN3_SEL_1_M 0x3E0U // Select inputs for unit 1 +#define CLB_LUT4_IN3_SEL_2_S 10U +#define CLB_LUT4_IN3_SEL_2_M 0x7C00U // Select inputs for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN1_0 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN1_0_FN0_S 0U +#define CLB_FSM_LUT_FN1_0_FN0_M 0xFFFFU // FSM LUT output function for unit 0 +#define CLB_FSM_LUT_FN1_0_FN1_S 16U +#define CLB_FSM_LUT_FN1_0_FN1_M 0xFFFF0000U // FSM LUT output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_LUT_FN2 register +// +//************************************************************************************************* +#define CLB_FSM_LUT_FN2_FN1_S 0U +#define CLB_FSM_LUT_FN2_FN1_M 0xFFFFU // FSM LUT output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN1_0 register +// +//************************************************************************************************* +#define CLB_LUT4_FN1_0_FN0_S 0U +#define CLB_LUT4_FN1_0_FN0_M 0xFFFFU // LUT4 output function for unit 0 +#define CLB_LUT4_FN1_0_FN1_S 16U +#define CLB_LUT4_FN1_0_FN1_M 0xFFFF0000U // LUT4 output function for unit 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LUT4_FN2 register +// +//************************************************************************************************* +#define CLB_LUT4_FN2_FN1_S 0U +#define CLB_LUT4_FN2_FN1_M 0xFFFFU // LUT4 output function for unit 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_0 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_0_S0_S 0U +#define CLB_FSM_NEXT_STATE_0_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_0_S1_S 16U +#define CLB_FSM_NEXT_STATE_0_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_1 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_1_S0_S 0U +#define CLB_FSM_NEXT_STATE_1_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_1_S1_S 16U +#define CLB_FSM_NEXT_STATE_1_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_FSM_NEXT_STATE_2 register +// +//************************************************************************************************* +#define CLB_FSM_NEXT_STATE_2_S0_S 0U +#define CLB_FSM_NEXT_STATE_2_S0_M 0xFFFFU // FSM next state function for S0 +#define CLB_FSM_NEXT_STATE_2_S1_S 16U +#define CLB_FSM_NEXT_STATE_2_S1_M 0xFFFF0000U // FSM next state function for S1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_MISC_CONTROL register +// +//************************************************************************************************* +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_0 0x1U // Add/Shift for counter 0 +#define CLB_MISC_CONTROL_COUNT_DIR_0 0x2U // Direction for counter 0 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_0 0x4U // Event control for counter 0 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_1 0x8U // Add/Shift for counter 1 +#define CLB_MISC_CONTROL_COUNT_DIR_1 0x10U // Direction for counter 1 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_1 0x20U // Event control for counter 1 +#define CLB_MISC_CONTROL_COUNT_ADD_SHIFT_2 0x40U // Add/Shift for counter 2 +#define CLB_MISC_CONTROL_COUNT_DIR_2 0x80U // Direction for counter 2 +#define CLB_MISC_CONTROL_COUNT_EVENT_CTRL_2 0x100U // Event control for counter 2 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_0 0x200U // Serializer enable 0 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_1 0x400U // Serializer enable 1 +#define CLB_MISC_CONTROL_COUNT_SERIALIZER_2 0x800U // Serializer enable 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_0 0x1000U // FSM extra_sel0 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_0 0x2000U // FSM extra_sel1 for 0 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_1 0x4000U // FSM extra_sel0 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_1 0x8000U // FSM extra_sel1 for 1 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL0_2 0x10000U // FSM extra_sel0 for 2 +#define CLB_MISC_CONTROL_FSM_EXTRA_SEL1_2 0x20000U // FSM extra_sel1 for 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_0 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_0_IN0_S 0U +#define CLB_OUTPUT_LUT_0_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_0_IN1_S 5U +#define CLB_OUTPUT_LUT_0_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_0_IN2_S 10U +#define CLB_OUTPUT_LUT_0_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_0_FN_S 15U +#define CLB_OUTPUT_LUT_0_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_1 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_1_IN0_S 0U +#define CLB_OUTPUT_LUT_1_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_1_IN1_S 5U +#define CLB_OUTPUT_LUT_1_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_1_IN2_S 10U +#define CLB_OUTPUT_LUT_1_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_1_FN_S 15U +#define CLB_OUTPUT_LUT_1_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_2 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_2_IN0_S 0U +#define CLB_OUTPUT_LUT_2_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_2_IN1_S 5U +#define CLB_OUTPUT_LUT_2_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_2_IN2_S 10U +#define CLB_OUTPUT_LUT_2_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_2_FN_S 15U +#define CLB_OUTPUT_LUT_2_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_3 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_3_IN0_S 0U +#define CLB_OUTPUT_LUT_3_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_3_IN1_S 5U +#define CLB_OUTPUT_LUT_3_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_3_IN2_S 10U +#define CLB_OUTPUT_LUT_3_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_3_FN_S 15U +#define CLB_OUTPUT_LUT_3_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_4 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_4_IN0_S 0U +#define CLB_OUTPUT_LUT_4_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_4_IN1_S 5U +#define CLB_OUTPUT_LUT_4_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_4_IN2_S 10U +#define CLB_OUTPUT_LUT_4_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_4_FN_S 15U +#define CLB_OUTPUT_LUT_4_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_5 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_5_IN0_S 0U +#define CLB_OUTPUT_LUT_5_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_5_IN1_S 5U +#define CLB_OUTPUT_LUT_5_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_5_IN2_S 10U +#define CLB_OUTPUT_LUT_5_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_5_FN_S 15U +#define CLB_OUTPUT_LUT_5_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_6 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_6_IN0_S 0U +#define CLB_OUTPUT_LUT_6_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_6_IN1_S 5U +#define CLB_OUTPUT_LUT_6_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_6_IN2_S 10U +#define CLB_OUTPUT_LUT_6_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_6_FN_S 15U +#define CLB_OUTPUT_LUT_6_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_OUTPUT_LUT_7 register +// +//************************************************************************************************* +#define CLB_OUTPUT_LUT_7_IN0_S 0U +#define CLB_OUTPUT_LUT_7_IN0_M 0x1FU // Select value for IN0 of output LUT +#define CLB_OUTPUT_LUT_7_IN1_S 5U +#define CLB_OUTPUT_LUT_7_IN1_M 0x3E0U // Select value for IN1 of output LUT +#define CLB_OUTPUT_LUT_7_IN2_S 10U +#define CLB_OUTPUT_LUT_7_IN2_M 0x7C00U // Select value for IN2 of output LUT +#define CLB_OUTPUT_LUT_7_FN_S 15U +#define CLB_OUTPUT_LUT_7_FN_M 0x7F8000U // Output function for output LUT + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_HLC_EVENT_SEL register +// +//************************************************************************************************* +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_S 0U +#define CLB_HLC_EVENT_SEL_EVENT0_SEL_M 0x1FU // Event Select 0 +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_S 5U +#define CLB_HLC_EVENT_SEL_EVENT1_SEL_M 0x3E0U // Event Select 1 +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_S 10U +#define CLB_HLC_EVENT_SEL_EVENT2_SEL_M 0x7C00U // Event Select 2 +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_S 15U +#define CLB_HLC_EVENT_SEL_EVENT3_SEL_M 0xF8000U // Event Select 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_EN register +// +//************************************************************************************************* +#define CLB_LOAD_EN_LOAD_EN 0x1U // Load Enable +#define CLB_LOAD_EN_GLOBAL_EN 0x2U // Global Enable +#define CLB_LOAD_EN_STOP 0x4U // Debug stop control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOAD_ADDR register +// +//************************************************************************************************* +#define CLB_LOAD_ADDR_ADDR_S 0U +#define CLB_LOAD_ADDR_ADDR_M 0x3FU // Indirect Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INPUT_FILTER register +// +//************************************************************************************************* +#define CLB_INPUT_FILTER_FIN0_S 0U +#define CLB_INPUT_FILTER_FIN0_M 0x3U // Input filter control 0 +#define CLB_INPUT_FILTER_FIN1_S 2U +#define CLB_INPUT_FILTER_FIN1_M 0xCU // Input filter control 1 +#define CLB_INPUT_FILTER_FIN2_S 4U +#define CLB_INPUT_FILTER_FIN2_M 0x30U // Input filter control 2 +#define CLB_INPUT_FILTER_FIN3_S 6U +#define CLB_INPUT_FILTER_FIN3_M 0xC0U // Input filter control 3 +#define CLB_INPUT_FILTER_FIN4_S 8U +#define CLB_INPUT_FILTER_FIN4_M 0x300U // Input filter control 4 +#define CLB_INPUT_FILTER_FIN5_S 10U +#define CLB_INPUT_FILTER_FIN5_M 0xC00U // Input filter control 5 +#define CLB_INPUT_FILTER_FIN6_S 12U +#define CLB_INPUT_FILTER_FIN6_M 0x3000U // Input filter control 6 +#define CLB_INPUT_FILTER_FIN7_S 14U +#define CLB_INPUT_FILTER_FIN7_M 0xC000U // Input filter control 7 +#define CLB_INPUT_FILTER_SYNC0 0x10000U // Synchronizer control 0 +#define CLB_INPUT_FILTER_SYNC1 0x20000U // Synchronizer control 1 +#define CLB_INPUT_FILTER_SYNC2 0x40000U // Synchronizer control 2 +#define CLB_INPUT_FILTER_SYNC3 0x80000U // Synchronizer control 3 +#define CLB_INPUT_FILTER_SYNC4 0x100000U // Synchronizer control 4 +#define CLB_INPUT_FILTER_SYNC5 0x200000U // Synchronizer control 5 +#define CLB_INPUT_FILTER_SYNC6 0x400000U // Synchronizer control 6 +#define CLB_INPUT_FILTER_SYNC7 0x800000U // Synchronizer control 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_IN_MUX_SEL_0 register +// +//************************************************************************************************* +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_0 0x1U // Select GP register 0 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_1 0x2U // Select GP register 1 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_2 0x4U // Select GP register 2 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_3 0x8U // Select GP register 3 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_4 0x10U // Select GP register 4 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_5 0x20U // Select GP register 5 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_6 0x40U // Select GP register 6 +#define CLB_IN_MUX_SEL_0_SEL_GP_IN_7 0x80U // Select GP register 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_S 0U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_0_M 0x1FU // Local Mux select 0 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_S 5U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_1_M 0x3E0U // Local Mux select 1 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_S 10U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_2_M 0x7C00U // Local Mux select 2 +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_S 15U +#define CLB_LCL_MUX_SEL_1_LCL_MUX_SEL_IN_3_M 0xF8000U // Local Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LCL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_S 0U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_4_M 0x1FU // Local Mux select 4 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_S 5U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_5_M 0x3E0U // Local Mux select 5 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_S 10U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_6_M 0x7C00U // Local Mux select 6 +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_S 15U +#define CLB_LCL_MUX_SEL_2_LCL_MUX_SEL_IN_7_M 0xF8000U // Local Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_BUF_PTR register +// +//************************************************************************************************* +#define CLB_BUF_PTR_PULL_S 0U +#define CLB_BUF_PTR_PULL_M 0xFFU // Data pointer for pull +#define CLB_BUF_PTR_PUSH_S 16U +#define CLB_BUF_PTR_PUSH_M 0xFF0000U // Data pointer for pull + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GP_REG register +// +//************************************************************************************************* +#define CLB_GP_REG_REG_S 0U +#define CLB_GP_REG_REG_M 0xFFU // General Purpose bit register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_1 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_S 0U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_0_M 0x7FU // Global Mux select 0 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_S 7U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_1_M 0x3F80U // Global Mux select 1 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_S 14U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_2_M 0x1FC000U // Global Mux select 2 +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_S 21U +#define CLB_GLBL_MUX_SEL_1_GLBL_MUX_SEL_IN_3_M 0xFE00000U // Global Mux select 3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_GLBL_MUX_SEL_2 register +// +//************************************************************************************************* +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_S 0U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_4_M 0x7FU // Global Mux select 4 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_S 7U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_5_M 0x3F80U // Global Mux select 5 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_S 14U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_6_M 0x1FC000U // Global Mux select 6 +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_S 21U +#define CLB_GLBL_MUX_SEL_2_GLBL_MUX_SEL_IN_7_M 0xFE00000U // Global Mux select 7 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_INTR_TAG_REG register +// +//************************************************************************************************* +#define CLB_INTR_TAG_REG_TAG_S 0U +#define CLB_INTR_TAG_REG_TAG_M 0x3FU // Interrupt tag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_LOCK register +// +//************************************************************************************************* +#define CLB_LOCK_LOCK 0x1U // LOCK enable +#define CLB_LOCK_KEY_S 16U +#define CLB_LOCK_KEY_M 0xFFFF0000U // Key for enabling write + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLB_DBG_OUT register +// +//************************************************************************************************* +#define CLB_DBG_OUT_COUNT0_MATCH2 0x2U // COUNT_MATCH2 UNIT 0 +#define CLB_DBG_OUT_COUNT0_ZERO 0x4U // COUNT_ZERO UNIT 0 +#define CLB_DBG_OUT_COUNT0_MATCH1 0x8U // COUNT_MATCH1 UNIT 0 +#define CLB_DBG_OUT_FSM0_S0 0x10U // FSM_S0 UNIT 0 +#define CLB_DBG_OUT_FSM0_S1 0x20U // FSM_S1 UNIT 0 +#define CLB_DBG_OUT_FSM0_LUTOUT 0x40U // FSM_LUT_OUT UNIT 0 +#define CLB_DBG_OUT_LUT40_OUT 0x80U // LUT4_OUT UNIT 0 +#define CLB_DBG_OUT_COUNT1_MATCH2 0x200U // COUNT_MATCH2 UNIT 1 +#define CLB_DBG_OUT_COUNT1_ZERO 0x400U // COUNT_ZERO UNIT 1 +#define CLB_DBG_OUT_COUNT1_MATCH1 0x800U // COUNT_MATCH1 UNIT 1 +#define CLB_DBG_OUT_FSM1_S0 0x1000U // FSM_S0 UNIT 1 +#define CLB_DBG_OUT_FSM1_S1 0x2000U // FSM_S1 UNIT 1 +#define CLB_DBG_OUT_FSM1_LUTOUT 0x4000U // FSM_LUT_OUT UNIT 1 +#define CLB_DBG_OUT_LUT41_OUT 0x8000U // LUT4_OUT UNIT 1 +#define CLB_DBG_OUT_COUNT2_MATCH2 0x20000U // COUNT_MATCH2 UNIT 2 +#define CLB_DBG_OUT_COUNT2_ZERO 0x40000U // COUNT_ZERO UNIT 2 +#define CLB_DBG_OUT_COUNT2_MATCH1 0x80000U // COUNT_MATCH1 UNIT 2 +#define CLB_DBG_OUT_FSM2_S0 0x100000U // FSM_S0 UNIT 2 +#define CLB_DBG_OUT_FSM2_S1 0x200000U // FSM_S1 UNIT 2 +#define CLB_DBG_OUT_FSM2_LUTOUT 0x400000U // FSM_LUT_OUT UNIT 2 +#define CLB_DBG_OUT_LUT42_OUT 0x800000U // LUT4_OUT UNIT 2 +#define CLB_DBG_OUT_OUT0 0x1000000U // CELL Output 0 +#define CLB_DBG_OUT_OUT1 0x2000000U // CELL Output 1 +#define CLB_DBG_OUT_OUT2 0x4000000U // CELL Output 2 +#define CLB_DBG_OUT_OUT3 0x8000000U // CELL Output 3 +#define CLB_DBG_OUT_OUT4 0x10000000U // CELL Output 4 +#define CLB_DBG_OUT_OUT5 0x20000000U // CELL Output 5 +#define CLB_DBG_OUT_OUT6 0x40000000U // CELL Output 6 +#define CLB_DBG_OUT_OUT7 0x80000000U // CELL Output 7 + + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_clbxbar.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_clbxbar.h new file mode 100644 index 0000000..64072e2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_clbxbar.h @@ -0,0 +1,1272 @@ +//########################################################################### +// +// FILE: hw_clbxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CLBXBAR_H +#define HW_CLBXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_AUXSIG0MUX0TO15CFG 0x0U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG0MUX16TO31CFG 0x2U // CLB XBAR Mux Configuration for Output-0 +#define XBAR_O_AUXSIG1MUX0TO15CFG 0x4U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG1MUX16TO31CFG 0x6U // CLB XBAR Mux Configuration for Output-1 +#define XBAR_O_AUXSIG2MUX0TO15CFG 0x8U // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG2MUX16TO31CFG 0xAU // CLB XBAR Mux Configuration for Output-2 +#define XBAR_O_AUXSIG3MUX0TO15CFG 0xCU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG3MUX16TO31CFG 0xEU // CLB XBAR Mux Configuration for Output-3 +#define XBAR_O_AUXSIG4MUX0TO15CFG 0x10U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG4MUX16TO31CFG 0x12U // CLB XBAR Mux Configuration for Output-4 +#define XBAR_O_AUXSIG5MUX0TO15CFG 0x14U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG5MUX16TO31CFG 0x16U // CLB XBAR Mux Configuration for Output-5 +#define XBAR_O_AUXSIG6MUX0TO15CFG 0x18U // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG6MUX16TO31CFG 0x1AU // CLB XBAR Mux Configuration for Output-6 +#define XBAR_O_AUXSIG7MUX0TO15CFG 0x1CU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG7MUX16TO31CFG 0x1EU // CLB XBAR Mux Configuration for Output-7 +#define XBAR_O_AUXSIG0MUXENABLE 0x20U // CLB XBAR Mux Enable Register for Output-0 +#define XBAR_O_AUXSIG1MUXENABLE 0x22U // CLB XBAR Mux Enable Register for Output-1 +#define XBAR_O_AUXSIG2MUXENABLE 0x24U // CLB XBAR Mux Enable Register for Output-2 +#define XBAR_O_AUXSIG3MUXENABLE 0x26U // CLB XBAR Mux Enable Register for Output-3 +#define XBAR_O_AUXSIG4MUXENABLE 0x28U // CLB XBAR Mux Enable Register for Output-4 +#define XBAR_O_AUXSIG5MUXENABLE 0x2AU // CLB XBAR Mux Enable Register for Output-5 +#define XBAR_O_AUXSIG6MUXENABLE 0x2CU // CLB XBAR Mux Enable Register for Output-6 +#define XBAR_O_AUXSIG7MUXENABLE 0x2EU // CLB XBAR Mux Enable Register for Output-7 +#define XBAR_O_AUXSIGOUTINV 0x38U // CLB XBAR Output Inversion Register +#define XBAR_O_AUXSIGLOCK 0x3EU // ClbXbar Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG0MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG0 of + // CLB-XBAR +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG0MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG0 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG1MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG1 of + // CLB-XBAR +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG1MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG1 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG2MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG2 of + // CLB-XBAR +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG2MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG2 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG3MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG3 of + // CLB-XBAR +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG3MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG3 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG4MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG4 of + // CLB-XBAR +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG4MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG4 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG5MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG5 of + // CLB-XBAR +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG5MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG5 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG6MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG6 of + // CLB-XBAR +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG6MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG6 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_S 0U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX0_M 0x3U // MUX0 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_S 2U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX1_M 0xCU // MUX1 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_S 4U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX2_M 0x30U // MUX2 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_S 6U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX3_M 0xC0U // MUX3 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_S 8U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX4_M 0x300U // MUX4 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_S 10U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX5_M 0xC00U // MUX5 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_S 12U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX6_M 0x3000U // MUX6 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_S 14U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX7_M 0xC000U // MUX7 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_S 16U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX8_M 0x30000U // MUX8 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_S 18U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX9_M 0xC0000U // MUX9 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_S 20U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX10_M 0x300000U // MUX10 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_S 22U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX11_M 0xC00000U // MUX11 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_S 24U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX12_M 0x3000000U // MUX12 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_S 26U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX13_M 0xC000000U // MUX13 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_S 28U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX14_M 0x30000000U // MUX14 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_S 30U +#define XBAR_AUXSIG7MUX0TO15CFG_MUX15_M 0xC0000000U // MUX15 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_S 0U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX16_M 0x3U // MUX16 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_S 2U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX17_M 0xCU // MUX17 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_S 4U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX18_M 0x30U // MUX18 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_S 6U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX19_M 0xC0U // MUX19 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_S 8U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX20_M 0x300U // MUX20 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_S 10U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX21_M 0xC00U // MUX21 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_S 12U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX22_M 0x3000U // MUX22 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_S 14U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX23_M 0xC000U // MUX23 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_S 16U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX24_M 0x30000U // MUX24 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_S 18U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX25_M 0xC0000U // MUX25 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_S 20U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX26_M 0x300000U // MUX26 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_S 22U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX27_M 0xC00000U // MUX27 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_S 24U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX28_M 0x3000000U // MUX28 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_S 26U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX29_M 0xC000000U // MUX29 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_S 28U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX30_M 0x30000000U // MUX30 Configuration for AUXSIG7 of + // CLB-XBAR +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_S 30U +#define XBAR_AUXSIG7MUX16TO31CFG_MUX31_M 0xC0000000U // MUX31 Configuration for AUXSIG7 of + // CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG0MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG0MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIG0MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG0 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG1MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIG1MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG1 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG2MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIG2MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG2 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG3MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIG3MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG3 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG4MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIG4MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG4 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG5MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIG5MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG5 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG6MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIG6MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG6 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIG7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_AUXSIG7MUXENABLE_MUX0 0x1U // mux0 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX1 0x2U // MUX1 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX2 0x4U // MUX2 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX3 0x8U // MUX3 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX4 0x10U // MUX4 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX5 0x20U // MUX5 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX6 0x40U // MUX6 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX7 0x80U // MUX7 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX8 0x100U // MUX8 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX9 0x200U // MUX9 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX10 0x400U // MUX10 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX11 0x800U // MUX11 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX12 0x1000U // MUX12 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX13 0x2000U // MUX13 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX14 0x4000U // MUX14 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX15 0x8000U // MUX15 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX16 0x10000U // MUX16 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX17 0x20000U // MUX17 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX18 0x40000U // MUX18 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX19 0x80000U // MUX19 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX20 0x100000U // MUX20 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX21 0x200000U // MUX21 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX22 0x400000U // MUX22 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX23 0x800000U // MUX23 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX24 0x1000000U // MUX24 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX25 0x2000000U // MUX25 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX26 0x4000000U // MUX26 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX27 0x8000000U // MUX27 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX28 0x10000000U // MUX28 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX29 0x20000000U // MUX29 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX30 0x40000000U // MUX30 to drive AUXSIG7 of CLB-XBAR +#define XBAR_AUXSIG7MUXENABLE_MUX31 0x80000000U // MUX31 to drive AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGOUTINV register +// +//************************************************************************************************* +#define XBAR_AUXSIGOUTINV_OUT0 0x1U // Selects polarity for AUXSIG0 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT1 0x2U // Selects polarity for AUXSIG1 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT2 0x4U // Selects polarity for AUXSIG2 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT3 0x8U // Selects polarity for AUXSIG3 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT4 0x10U // Selects polarity for AUXSIG4 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT5 0x20U // Selects polarity for AUXSIG5 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT6 0x40U // Selects polarity for AUXSIG6 of CLB-XBAR +#define XBAR_AUXSIGOUTINV_OUT7 0x80U // Selects polarity for AUXSIG7 of CLB-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXSIGLOCK register +// +//************************************************************************************************* +#define XBAR_AUXSIGLOCK_LOCK 0x1U // Locks the configuration for CLB-XBAR +#define XBAR_AUXSIGLOCK_KEY_S 16U +#define XBAR_AUXSIGLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_cmpss.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cmpss.h new file mode 100644 index 0000000..67d32e3 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cmpss.h @@ -0,0 +1,235 @@ +//########################################################################### +// +// FILE: hw_cmpss.h +// +// TITLE: Definitions for the CMPSS registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CMPSS_H +#define HW_CMPSS_H + +//************************************************************************************************* +// +// The following are defines for the CMPSS register offsets +// +//************************************************************************************************* +#define CMPSS_O_COMPCTL 0x0U // CMPSS Comparator Control Register +#define CMPSS_O_COMPHYSCTL 0x1U // CMPSS Comparator Hysteresis Control Register +#define CMPSS_O_COMPSTS 0x2U // CMPSS Comparator Status Register +#define CMPSS_O_COMPSTSCLR 0x3U // CMPSS Comparator Status Clear Register +#define CMPSS_O_COMPDACCTL 0x4U // CMPSS DAC Control Register +#define CMPSS_O_DACHVALS 0x6U // CMPSS High DAC Value Shadow Register +#define CMPSS_O_DACHVALA 0x7U // CMPSS High DAC Value Active Register +#define CMPSS_O_RAMPMAXREFA 0x8U // CMPSS Ramp Max Reference Active Register +#define CMPSS_O_RAMPMAXREFS 0xAU // CMPSS Ramp Max Reference Shadow Register +#define CMPSS_O_RAMPDECVALA 0xCU // CMPSS Ramp Decrement Value Active Register +#define CMPSS_O_RAMPDECVALS 0xEU // CMPSS Ramp Decrement Value Shadow Register +#define CMPSS_O_RAMPSTS 0x10U // CMPSS Ramp Status Register +#define CMPSS_O_DACLVALS 0x12U // CMPSS Low DAC Value Shadow Register +#define CMPSS_O_DACLVALA 0x13U // CMPSS Low DAC Value Active Register +#define CMPSS_O_RAMPDLYA 0x14U // CMPSS Ramp Delay Active Register +#define CMPSS_O_RAMPDLYS 0x15U // CMPSS Ramp Delay Shadow Register +#define CMPSS_O_CTRIPLFILCTL 0x16U // CTRIPL Filter Control Register +#define CMPSS_O_CTRIPLFILCLKCTL 0x17U // CTRIPL Filter Clock Control Register +#define CMPSS_O_CTRIPHFILCTL 0x18U // CTRIPH Filter Control Register +#define CMPSS_O_CTRIPHFILCLKCTL 0x19U // CTRIPH Filter Clock Control Register +#define CMPSS_O_COMPLOCK 0x1AU // CMPSS Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPCTL register +// +//************************************************************************************************* +#define CMPSS_COMPCTL_COMPHSOURCE 0x1U // High Comparator Source Select +#define CMPSS_COMPCTL_COMPHINV 0x2U // High Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPHSEL_S 2U +#define CMPSS_COMPCTL_CTRIPHSEL_M 0xCU // High Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTHSEL_S 4U +#define CMPSS_COMPCTL_CTRIPOUTHSEL_M 0x30U // High Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCHEN 0x40U // High Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPLSOURCE 0x100U // Low Comparator Source Select +#define CMPSS_COMPCTL_COMPLINV 0x200U // Low Comparator Invert Select +#define CMPSS_COMPCTL_CTRIPLSEL_S 10U +#define CMPSS_COMPCTL_CTRIPLSEL_M 0xC00U // Low Comparator Trip Select +#define CMPSS_COMPCTL_CTRIPOUTLSEL_S 12U +#define CMPSS_COMPCTL_CTRIPOUTLSEL_M 0x3000U // Low Comparator Trip Output Select +#define CMPSS_COMPCTL_ASYNCLEN 0x4000U // Low Comparator Asynchronous Path Enable +#define CMPSS_COMPCTL_COMPDACE 0x8000U // Comparator/DAC Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPHYSCTL register +// +//************************************************************************************************* +#define CMPSS_COMPHYSCTL_COMPHYS_S 0U +#define CMPSS_COMPHYSCTL_COMPHYS_M 0x7U // Comparator Hysteresis Trim + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTS register +// +//************************************************************************************************* +#define CMPSS_COMPSTS_COMPHSTS 0x1U // High Comparator Status +#define CMPSS_COMPSTS_COMPHLATCH 0x2U // High Comparator Latched Status +#define CMPSS_COMPSTS_COMPLSTS 0x100U // Low Comparator Status +#define CMPSS_COMPSTS_COMPLLATCH 0x200U // Low Comparator Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPSTSCLR register +// +//************************************************************************************************* +#define CMPSS_COMPSTSCLR_HLATCHCLR 0x2U // High Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_HSYNCCLREN 0x4U // High Comparator EPWMSYNCPER Clear Enable +#define CMPSS_COMPSTSCLR_LLATCHCLR 0x200U // Low Comparator Latched Status Clear +#define CMPSS_COMPSTSCLR_LSYNCCLREN 0x400U // Low Comparator EPWMSYNCPER Clear Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPDACCTL register +// +//************************************************************************************************* +#define CMPSS_COMPDACCTL_DACSOURCE 0x1U // DAC Source Control +#define CMPSS_COMPDACCTL_RAMPSOURCE_S 1U +#define CMPSS_COMPDACCTL_RAMPSOURCE_M 0x1EU // Ramp Generator Source Control +#define CMPSS_COMPDACCTL_SELREF 0x20U // DAC Reference Select +#define CMPSS_COMPDACCTL_RAMPLOADSEL 0x40U // Ramp Load Select +#define CMPSS_COMPDACCTL_SWLOADSEL 0x80U // Software Load Select +#define CMPSS_COMPDACCTL_FREESOFT_S 14U +#define CMPSS_COMPDACCTL_FREESOFT_M 0xC000U // Free/Soft Emulation Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALS register +// +//************************************************************************************************* +#define CMPSS_DACHVALS_DACVAL_S 0U +#define CMPSS_DACHVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACHVALA register +// +//************************************************************************************************* +#define CMPSS_DACHVALA_DACVAL_S 0U +#define CMPSS_DACHVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALS register +// +//************************************************************************************************* +#define CMPSS_DACLVALS_DACVAL_S 0U +#define CMPSS_DACLVALS_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLVALA register +// +//************************************************************************************************* +#define CMPSS_DACLVALA_DACVAL_S 0U +#define CMPSS_DACLVALA_DACVAL_M 0xFFFU // DAC Value Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYA register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYA_DELAY_S 0U +#define CMPSS_RAMPDLYA_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMPDLYS register +// +//************************************************************************************************* +#define CMPSS_RAMPDLYS_DELAY_S 0U +#define CMPSS_RAMPDLYS_DELAY_M 0x1FFFU // Ramp Delay Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPLFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPLFILCTL_THRESH_S 9U +#define CMPSS_CTRIPLFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPLFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPLFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPLFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCTL_SAMPWIN_S 4U +#define CMPSS_CTRIPHFILCTL_SAMPWIN_M 0x1F0U // Sample Window +#define CMPSS_CTRIPHFILCTL_THRESH_S 9U +#define CMPSS_CTRIPHFILCTL_THRESH_M 0x3E00U // Majority Voting Threshold +#define CMPSS_CTRIPHFILCTL_FILINIT 0x8000U // Filter Initialization Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CTRIPHFILCLKCTL register +// +//************************************************************************************************* +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_S 0U +#define CMPSS_CTRIPHFILCLKCTL_CLKPRESCALE_M 0x3FFU // Sample Clock Prescale + +//************************************************************************************************* +// +// The following are defines for the bit fields in the COMPLOCK register +// +//************************************************************************************************* +#define CMPSS_COMPLOCK_COMPCTL 0x1U // COMPCTL Lock +#define CMPSS_COMPLOCK_COMPHYSCTL 0x2U // COMPHYSCTL Lock +#define CMPSS_COMPLOCK_DACCTL 0x4U // DACCTL Lock +#define CMPSS_COMPLOCK_CTRIP 0x8U // CTRIP Lock + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_cputimer.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cputimer.h new file mode 100644 index 0000000..f7613fb --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_cputimer.h @@ -0,0 +1,112 @@ +//########################################################################### +// +// FILE: hw_cputimer.h +// +// TITLE: Definitions for the CPUTIMER registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_CPUTIMER_H +#define HW_CPUTIMER_H + +//************************************************************************************************* +// +// The following are defines for the CPUTIMER register offsets +// +//************************************************************************************************* +#define CPUTIMER_O_TIM 0x0U // CPU-Timer, Counter Register +#define CPUTIMER_O_PRD 0x2U // CPU-Timer, Period Register +#define CPUTIMER_O_TCR 0x4U // CPU-Timer, Control Register +#define CPUTIMER_O_TPR 0x6U // CPU-Timer, Prescale Register +#define CPUTIMER_O_TPRH 0x7U // CPU-Timer, Prescale Register High + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TIM register +// +//************************************************************************************************* +#define CPUTIMER_TIM_LSW_S 0U +#define CPUTIMER_TIM_LSW_M 0xFFFFU // CPU-Timer Counter Registers +#define CPUTIMER_TIM_MSW_S 16U +#define CPUTIMER_TIM_MSW_M 0xFFFF0000U // CPU-Timer Counter Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRD register +// +//************************************************************************************************* +#define CPUTIMER_PRD_LSW_S 0U +#define CPUTIMER_PRD_LSW_M 0xFFFFU // CPU-Timer Period Registers +#define CPUTIMER_PRD_MSW_S 16U +#define CPUTIMER_PRD_MSW_M 0xFFFF0000U // CPU-Timer Period Registers High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TCR register +// +//************************************************************************************************* +#define CPUTIMER_TCR_TSS 0x10U // CPU-Timer stop status bit. +#define CPUTIMER_TCR_TRB 0x20U // Timer reload +#define CPUTIMER_TCR_SOFT 0x400U // Emulation modes +#define CPUTIMER_TCR_FREE 0x800U // Emulation modes +#define CPUTIMER_TCR_TIE 0x4000U // CPU-Timer Interrupt Enable. +#define CPUTIMER_TCR_TIF 0x8000U // CPU-Timer Interrupt Flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPR register +// +//************************************************************************************************* +#define CPUTIMER_TPR_TDDR_S 0U +#define CPUTIMER_TPR_TDDR_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPR_PSC_S 8U +#define CPUTIMER_TPR_PSC_M 0xFF00U // CPU-Timer Prescale Counter. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TPRH register +// +//************************************************************************************************* +#define CPUTIMER_TPRH_TDDRH_S 0U +#define CPUTIMER_TPRH_TDDRH_M 0xFFU // CPU-Timer Divide-Down. +#define CPUTIMER_TPRH_PSCH_S 8U +#define CPUTIMER_TPRH_PSCH_M 0xFF00U // CPU-Timer Prescale Counter. + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_dac.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dac.h new file mode 100644 index 0000000..3e3d3a2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dac.h @@ -0,0 +1,122 @@ +//########################################################################### +// +// FILE: hw_dac.h +// +// TITLE: Definitions for the DAC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DAC_H +#define HW_DAC_H + +//************************************************************************************************* +// +// The following are defines for the DAC register offsets +// +//************************************************************************************************* +#define DAC_O_REV 0x0U // DAC Revision Register +#define DAC_O_CTL 0x1U // DAC Control Register +#define DAC_O_VALA 0x2U // DAC Value Register - Active +#define DAC_O_VALS 0x3U // DAC Value Register - Shadow +#define DAC_O_OUTEN 0x4U // DAC Output Enable Register +#define DAC_O_LOCK 0x5U // DAC Lock Register +#define DAC_O_TRIM 0x6U // DAC Trim Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACREV register +// +//************************************************************************************************* +#define DAC_REV_REV_S 0U +#define DAC_REV_REV_M 0xFFU // DAC Revision Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACCTL register +// +//************************************************************************************************* +#define DAC_CTL_DACREFSEL 0x1U // DAC Reference Select +#define DAC_CTL_LOADMODE 0x4U // DACVALA Load Mode +#define DAC_CTL_SYNCSEL_S 4U +#define DAC_CTL_SYNCSEL_M 0xF0U // DAC EPWMSYNCPER Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALA register +// +//************************************************************************************************* +#define DAC_VALA_DACVALA_S 0U +#define DAC_VALA_DACVALA_M 0xFFFU // DAC Active Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACVALS register +// +//************************************************************************************************* +#define DAC_VALS_DACVALS_S 0U +#define DAC_VALS_DACVALS_M 0xFFFU // DAC Shadow Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACOUTEN register +// +//************************************************************************************************* +#define DAC_OUTEN_DACOUTEN 0x1U // DAC Output Code + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACLOCK register +// +//************************************************************************************************* +#define DAC_LOCK_DACCTL 0x1U // DAC Control Register Lock +#define DAC_LOCK_DACVAL 0x2U // DAC Value Register Lock +#define DAC_LOCK_DACOUTEN 0x4U // DAC Output Enable Register Lock +#define DAC_LOCK_KEY_S 12U +#define DAC_LOCK_KEY_M 0xF000U // DAC Register Lock Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DACTRIM register +// +//************************************************************************************************* +#define DAC_TRIM_OFFSET_TRIM_S 0U +#define DAC_TRIM_OFFSET_TRIM_M 0xFFU // DAC Offset Trim + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_dcsm.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dcsm.h new file mode 100644 index 0000000..c81bcb1 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dcsm.h @@ -0,0 +1,442 @@ +//########################################################################### +// +// FILE: hw_dcsm.h +// +// TITLE: Definitions for the DCSM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DCSM_H +#define HW_DCSM_H + +//************************************************************************************************* +// +// The following are defines for the DCSM register offsets +// +//************************************************************************************************* +#define DCSM_O_Z1OTP_LINKPOINTER1 0x0U // Zone 1 Link Pointer1 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER2 0x4U // Zone 1 Link Pointer2 in Z1 OTP +#define DCSM_O_Z1OTP_LINKPOINTER3 0x8U // Zone 1 Link Pointer3 in Z1 OTP +#define DCSM_O_Z1OTP_PSWDLOCK 0x10U // Secure Password Lock in Z1 OTP +#define DCSM_O_Z1OTP_CRCLOCK 0x14U // Secure CRC Lock in Z1 OTP +#define DCSM_O_Z1OTP_BOOTCTRL 0x1EU // Boot Mode in Z1 OTP + +#define DCSM_O_Z2OTP_LINKPOINTER1 0x0U // Zone 2 Link Pointer1 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER2 0x4U // Zone 2 Link Pointer2 in Z2 OTP +#define DCSM_O_Z2OTP_LINKPOINTER3 0x8U // Zone 2 Link Pointer3 in Z2 OTP +#define DCSM_O_Z2OTP_PSWDLOCK 0x10U // Secure Password Lock in Z2 OTP +#define DCSM_O_Z2OTP_CRCLOCK 0x14U // Secure CRC Lock in Z2 OTP +#define DCSM_O_Z2OTP_BOOTCTRL 0x1EU // Boot Mode in Z2 OTP + +#define DCSM_O_Z1_LINKPOINTER 0x0U // Zone 1 Link Pointer +#define DCSM_O_Z1_OTPSECLOCK 0x2U // Zone 1 OTP Secure JTAG lock +#define DCSM_O_Z1_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z1_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z1_CSMKEY0 0x10U // Zone 1 CSM Key 0 +#define DCSM_O_Z1_CSMKEY1 0x12U // Zone 1 CSM Key 1 +#define DCSM_O_Z1_CSMKEY2 0x14U // Zone 1 CSM Key 2 +#define DCSM_O_Z1_CSMKEY3 0x16U // Zone 1 CSM Key 3 +#define DCSM_O_Z1_CR 0x19U // Zone 1 CSM Control Register +#define DCSM_O_Z1_GRABSECTR 0x1AU // Zone 1 Grab Flash Sectors Register +#define DCSM_O_Z1_GRABRAMR 0x1CU // Zone 1 Grab RAM Blocks Register +#define DCSM_O_Z1_EXEONLYSECTR 0x1EU // Zone 1 Flash Execute_Only Sector Register +#define DCSM_O_Z1_EXEONLYRAMR 0x20U // Zone 1 RAM Execute_Only Block Register + +#define DCSM_O_Z2_LINKPOINTER 0x0U // Zone 2 Link Pointer +#define DCSM_O_Z2_OTPSECLOCK 0x2U // Zone 2 OTP Secure JTAG lock +#define DCSM_O_Z2_BOOTCTRL 0x4U // Boot Mode +#define DCSM_O_Z2_LINKPOINTERERR 0x6U // Link Pointer Error +#define DCSM_O_Z2_CSMKEY0 0x10U // Zone 2 CSM Key 0 +#define DCSM_O_Z2_CSMKEY1 0x12U // Zone 2 CSM Key 1 +#define DCSM_O_Z2_CSMKEY2 0x14U // Zone 2 CSM Key 2 +#define DCSM_O_Z2_CSMKEY3 0x16U // Zone 2 CSM Key 3 +#define DCSM_O_Z2_CR 0x19U // Zone 2 CSM Control Register +#define DCSM_O_Z2_GRABSECTR 0x1AU // Zone 2 Grab Flash Sectors Register +#define DCSM_O_Z2_GRABRAMR 0x1CU // Zone 2 Grab RAM Blocks Register +#define DCSM_O_Z2_EXEONLYSECTR 0x1EU // Zone 2 Flash Execute_Only Sector Register +#define DCSM_O_Z2_EXEONLYRAMR 0x20U // Zone 2 RAM Execute_Only Block Register + +#define DCSM_O_FLSEM 0x0U // Flash Wrapper Semaphore Register +#define DCSM_O_SECTSTAT 0x2U // Sectors Status Register +#define DCSM_O_RAMSTAT 0x4U // RAM Status Register + + + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z1_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone1 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z1_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone1 Password Lock. +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z1_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone1 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z1_BOOTCTRL_KEY_S 0U +#define DCSM_Z1_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z1_BOOTCTRL_BMODE_S 8U +#define DCSM_Z1_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z1_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z1_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_CR register +// +//************************************************************************************************* +#define DCSM_Z1_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z1_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z1_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z1_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z1_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z1_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z1_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z1_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z1_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z1_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z1_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z1_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z1_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z1_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z1_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z1_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z1_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z1_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z1_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z1_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z1_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z1_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z1_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z1_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z1_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z1_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z1_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z1_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z1_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z1_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z1_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_LINKPOINTER register +// +//************************************************************************************************* +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_S 0U +#define DCSM_Z2_LINKPOINTER_LINKPOINTER_M 0x1FFFFFFFU // Zone2 LINK Pointer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_OTPSECLOCK register +// +//************************************************************************************************* +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_S 4U +#define DCSM_Z2_OTPSECLOCK_PSWDLOCK_M 0xF0U // Zone2 Password Lock. +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_S 8U +#define DCSM_Z2_OTPSECLOCK_CRCLOCK_M 0xF00U // Zone2 CRC Lock. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_BOOTCTRL register +// +//************************************************************************************************* +#define DCSM_Z2_BOOTCTRL_KEY_S 0U +#define DCSM_Z2_BOOTCTRL_KEY_M 0xFFU // OTP Boot Key +#define DCSM_Z2_BOOTCTRL_BMODE_S 8U +#define DCSM_Z2_BOOTCTRL_BMODE_M 0xFF00U // OTP Boot Mode +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_S 16U +#define DCSM_Z2_BOOTCTRL_BOOTPIN0_M 0xFF0000U // OTP Boot Pin 0 Mapping +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_S 24U +#define DCSM_Z2_BOOTCTRL_BOOTPIN1_M 0xFF000000U // OTP Boot Pin 1 Mapping + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_CR register +// +//************************************************************************************************* +#define DCSM_Z2_CR_ALLZERO 0x8U // CSMPSWD All Zeros +#define DCSM_Z2_CR_ALLONE 0x10U // CSMPSWD All Ones +#define DCSM_Z2_CR_UNSECURE 0x20U // CSMPSWD Match CSMKEY +#define DCSM_Z2_CR_ARMED 0x40U // CSM Armed +#define DCSM_Z2_CR_FORCESEC 0x8000U // Force Secure + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_S 0U +#define DCSM_Z2_GRABSECTR_GRAB_SECTA_M 0x3U // Grab Flash Sector A +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_S 2U +#define DCSM_Z2_GRABSECTR_GRAB_SECTB_M 0xCU // Grab Flash Sector B +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_S 4U +#define DCSM_Z2_GRABSECTR_GRAB_SECTC_M 0x30U // Grab Flash Sector C +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_S 6U +#define DCSM_Z2_GRABSECTR_GRAB_SECTD_M 0xC0U // Grab Flash Sector D +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_S 8U +#define DCSM_Z2_GRABSECTR_GRAB_SECTE_M 0x300U // Grab Flash Sector E +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_S 10U +#define DCSM_Z2_GRABSECTR_GRAB_SECTF_M 0xC00U // Grab Flash Sector F +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_S 12U +#define DCSM_Z2_GRABSECTR_GRAB_SECTG_M 0x3000U // Grab Flash Sector G +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_S 14U +#define DCSM_Z2_GRABSECTR_GRAB_SECTH_M 0xC000U // Grab Flash Sector H +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_S 16U +#define DCSM_Z2_GRABSECTR_GRAB_SECTI_M 0x30000U // Grab Flash Sector I +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_S 18U +#define DCSM_Z2_GRABSECTR_GRAB_SECTJ_M 0xC0000U // Grab Flash Sector J +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_S 20U +#define DCSM_Z2_GRABSECTR_GRAB_SECTK_M 0x300000U // Grab Flash Sector K +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_S 22U +#define DCSM_Z2_GRABSECTR_GRAB_SECTL_M 0xC00000U // Grab Flash Sector L +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_S 24U +#define DCSM_Z2_GRABSECTR_GRAB_SECTM_M 0x3000000U // Grab Flash Sector M +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_S 26U +#define DCSM_Z2_GRABSECTR_GRAB_SECTN_M 0xC000000U // Grab Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_GRABRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_S 0U +#define DCSM_Z2_GRABRAMR_GRAB_RAM0_M 0x3U // Grab RAM LS0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_S 2U +#define DCSM_Z2_GRABRAMR_GRAB_RAM1_M 0xCU // Grab RAM LS1 +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_S 4U +#define DCSM_Z2_GRABRAMR_GRAB_RAM2_M 0x30U // Grab RAM LS2 +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_S 6U +#define DCSM_Z2_GRABRAMR_GRAB_RAM3_M 0xC0U // Grab RAM LS3 +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_S 8U +#define DCSM_Z2_GRABRAMR_GRAB_RAM4_M 0x300U // Grab RAM LS4 +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_S 10U +#define DCSM_Z2_GRABRAMR_GRAB_RAM5_M 0xC00U // Grab RAM LS5 +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_S 12U +#define DCSM_Z2_GRABRAMR_GRAB_RAM6_M 0x3000U // Grab RAM D0 +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_S 14U +#define DCSM_Z2_GRABRAMR_GRAB_RAM7_M 0xC000U // Grab RAM D1 +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_S 28U +#define DCSM_Z2_GRABRAMR_GRAB_CLA1_M 0x30000000U // Grab CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYSECTR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTA 0x1U // Execute-Only Flash Sector A +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTB 0x2U // Execute-Only Flash Sector B +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTC 0x4U // Execute-Only Flash Sector C +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTD 0x8U // Execute-Only Flash Sector D +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTE 0x10U // Execute-Only Flash Sector E +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTF 0x20U // Execute-Only Flash Sector F +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTG 0x40U // Execute-Only Flash Sector G +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTH 0x80U // Execute-Only Flash Sector H +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTI 0x100U // Execute-Only Flash Sector I +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTJ 0x200U // Execute-Only Flash Sector J +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTK 0x400U // Execute-Only Flash Sector K +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTL 0x800U // Execute-Only Flash Sector L +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTM 0x1000U // Execute-Only Flash Sector M +#define DCSM_Z2_EXEONLYSECTR_EXEONLY_SECTN 0x2000U // Execute-Only Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the Z2_EXEONLYRAMR register +// +//************************************************************************************************* +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM0 0x1U // Execute-Only RAM LS0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM1 0x2U // Execute-Only RAM LS1 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM2 0x4U // Execute-Only RAM LS2 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM3 0x8U // Execute-Only RAM LS3 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM4 0x10U // Execute-Only RAM LS4 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM5 0x20U // Execute-Only RAM LS5 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM6 0x40U // Execute-Only RAM D0 +#define DCSM_Z2_EXEONLYRAMR_EXEONLY_RAM7 0x80U // Execute-Only RAM D1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FLSEM register +// +//************************************************************************************************* +#define DCSM_FLSEM_SEM_S 0U +#define DCSM_FLSEM_SEM_M 0x3U // Flash Semaphore Bit +#define DCSM_FLSEM_KEY_S 8U +#define DCSM_FLSEM_KEY_M 0xFF00U // Semaphore Key + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECTSTAT register +// +//************************************************************************************************* +#define DCSM_SECTSTAT_STATUS_SECTA_S 0U +#define DCSM_SECTSTAT_STATUS_SECTA_M 0x3U // Zone Status Flash Sector A +#define DCSM_SECTSTAT_STATUS_SECTB_S 2U +#define DCSM_SECTSTAT_STATUS_SECTB_M 0xCU // Zone Status Flash Sector B +#define DCSM_SECTSTAT_STATUS_SECTC_S 4U +#define DCSM_SECTSTAT_STATUS_SECTC_M 0x30U // Zone Status Flash Sector C +#define DCSM_SECTSTAT_STATUS_SECTD_S 6U +#define DCSM_SECTSTAT_STATUS_SECTD_M 0xC0U // Zone Status Flash Sector D +#define DCSM_SECTSTAT_STATUS_SECTE_S 8U +#define DCSM_SECTSTAT_STATUS_SECTE_M 0x300U // Zone Status Flash Sector E +#define DCSM_SECTSTAT_STATUS_SECTF_S 10U +#define DCSM_SECTSTAT_STATUS_SECTF_M 0xC00U // Zone Status Flash Sector F +#define DCSM_SECTSTAT_STATUS_SECTG_S 12U +#define DCSM_SECTSTAT_STATUS_SECTG_M 0x3000U // Zone Status Flash Sector G +#define DCSM_SECTSTAT_STATUS_SECTH_S 14U +#define DCSM_SECTSTAT_STATUS_SECTH_M 0xC000U // Zone Status Flash Sector H +#define DCSM_SECTSTAT_STATUS_SECTI_S 16U +#define DCSM_SECTSTAT_STATUS_SECTI_M 0x30000U // Zone Status Flash Sector I +#define DCSM_SECTSTAT_STATUS_SECTJ_S 18U +#define DCSM_SECTSTAT_STATUS_SECTJ_M 0xC0000U // Zone Status Flash Sector J +#define DCSM_SECTSTAT_STATUS_SECTK_S 20U +#define DCSM_SECTSTAT_STATUS_SECTK_M 0x300000U // Zone Status Flash Sector K +#define DCSM_SECTSTAT_STATUS_SECTL_S 22U +#define DCSM_SECTSTAT_STATUS_SECTL_M 0xC00000U // Zone Status Flash Sector L +#define DCSM_SECTSTAT_STATUS_SECTM_S 24U +#define DCSM_SECTSTAT_STATUS_SECTM_M 0x3000000U // Zone Status Flash Sector M +#define DCSM_SECTSTAT_STATUS_SECTN_S 26U +#define DCSM_SECTSTAT_STATUS_SECTN_M 0xC000000U // Zone Status Flash Sector N + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAMSTAT register +// +//************************************************************************************************* +#define DCSM_RAMSTAT_STATUS_RAM0_S 0U +#define DCSM_RAMSTAT_STATUS_RAM0_M 0x3U // Zone Status RAM LS0 +#define DCSM_RAMSTAT_STATUS_RAM1_S 2U +#define DCSM_RAMSTAT_STATUS_RAM1_M 0xCU // Zone Status RAM LS1 +#define DCSM_RAMSTAT_STATUS_RAM2_S 4U +#define DCSM_RAMSTAT_STATUS_RAM2_M 0x30U // Zone Status RAM LS2 +#define DCSM_RAMSTAT_STATUS_RAM3_S 6U +#define DCSM_RAMSTAT_STATUS_RAM3_M 0xC0U // Zone Status RAM LS3 +#define DCSM_RAMSTAT_STATUS_RAM4_S 8U +#define DCSM_RAMSTAT_STATUS_RAM4_M 0x300U // Zone Status RAM LS4 +#define DCSM_RAMSTAT_STATUS_RAM5_S 10U +#define DCSM_RAMSTAT_STATUS_RAM5_M 0xC00U // Zone Status RAM LS5 +#define DCSM_RAMSTAT_STATUS_RAM6_S 12U +#define DCSM_RAMSTAT_STATUS_RAM6_M 0x3000U // Zone Status RAM D0 +#define DCSM_RAMSTAT_STATUS_RAM7_S 14U +#define DCSM_RAMSTAT_STATUS_RAM7_M 0xC000U // Zone Status RAM D1 +#define DCSM_RAMSTAT_STATUS_CLA1_S 28U +#define DCSM_RAMSTAT_STATUS_CLA1_M 0x30000000U // Zone Status CLA1 + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_dma.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dma.h new file mode 100644 index 0000000..1ecd1d7 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_dma.h @@ -0,0 +1,165 @@ +//########################################################################### +// +// FILE: hw_dma.h +// +// TITLE: Definitions for the DMA registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_DMA_H +#define HW_DMA_H + +//************************************************************************************************* +// +// The following are defines for the DMA register offsets +// +//************************************************************************************************* +#define DMA_O_CTRL 0x0U // DMA Control Register +#define DMA_O_DEBUGCTRL 0x1U // Debug Control Register +#define DMA_O_PRIORITYCTRL1 0x4U // Priority Control 1 Register +#define DMA_O_PRIORITYSTAT 0x6U // Priority Status Register + +#define DMA_O_MODE 0x0U // Mode Register +#define DMA_O_CONTROL 0x1U // Control Register +#define DMA_O_BURST_SIZE 0x2U // Burst Size Register +#define DMA_O_BURST_COUNT 0x3U // Burst Count Register +#define DMA_O_SRC_BURST_STEP 0x4U // Source Burst Step Register +#define DMA_O_DST_BURST_STEP 0x5U // Destination Burst Step Register +#define DMA_O_TRANSFER_SIZE 0x6U // Transfer Size Register +#define DMA_O_TRANSFER_COUNT 0x7U // Transfer Count Register +#define DMA_O_SRC_TRANSFER_STEP 0x8U // Source Transfer Step Register +#define DMA_O_DST_TRANSFER_STEP 0x9U // Destination Transfer Step Register +#define DMA_O_SRC_WRAP_SIZE 0xAU // Source Wrap Size Register +#define DMA_O_SRC_WRAP_COUNT 0xBU // Source Wrap Count Register +#define DMA_O_SRC_WRAP_STEP 0xCU // Source Wrap Step Register +#define DMA_O_DST_WRAP_SIZE 0xDU // Destination Wrap Size Register +#define DMA_O_DST_WRAP_COUNT 0xEU // Destination Wrap Count Register +#define DMA_O_DST_WRAP_STEP 0xFU // Destination Wrap Step Register +#define DMA_O_SRC_BEG_ADDR_SHADOW 0x10U // Source Begin Address Shadow Register +#define DMA_O_SRC_ADDR_SHADOW 0x12U // Source Address Shadow Register +#define DMA_O_SRC_BEG_ADDR_ACTIVE 0x14U // Source Begin Address Active Register +#define DMA_O_SRC_ADDR_ACTIVE 0x16U // Source Address Active Register +#define DMA_O_DST_BEG_ADDR_SHADOW 0x18U // Destination Begin Address Shadow Register +#define DMA_O_DST_ADDR_SHADOW 0x1AU // Destination Address Shadow Register +#define DMA_O_DST_BEG_ADDR_ACTIVE 0x1CU // Destination Begin Address Active Register +#define DMA_O_DST_ADDR_ACTIVE 0x1EU // Destination Address Active Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACTRL register +// +//************************************************************************************************* +#define DMA_CTRL_HARDRESET 0x1U // Hard Reset Bit +#define DMA_CTRL_PRIORITYRESET 0x2U // Priority Reset Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEBUGCTRL register +// +//************************************************************************************************* +#define DMA_DEBUGCTRL_FREE 0x8000U // Debug Mode Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYCTRL1 register +// +//************************************************************************************************* +#define DMA_PRIORITYCTRL1_CH1PRIORITY 0x1U // Ch1 Priority Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PRIORITYSTAT register +// +//************************************************************************************************* +#define DMA_PRIORITYSTAT_ACTIVESTS_S 0U +#define DMA_PRIORITYSTAT_ACTIVESTS_M 0x7U // Active Channel Status Bits +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_S 4U +#define DMA_PRIORITYSTAT_ACTIVESTS_SHADOW_M 0x70U // Active Channel Status Shadow Bits + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MODE register +// +//************************************************************************************************* +#define DMA_MODE_PERINTSEL_S 0U +#define DMA_MODE_PERINTSEL_M 0x1FU // Peripheral Interrupt and Sync Select +#define DMA_MODE_OVRINTE 0x80U // Overflow Interrupt Enable +#define DMA_MODE_PERINTE 0x100U // Peripheral Interrupt Enable +#define DMA_MODE_CHINTMODE 0x200U // Channel Interrupt Mode +#define DMA_MODE_ONESHOT 0x400U // One Shot Mode Bit +#define DMA_MODE_CONTINUOUS 0x800U // Continuous Mode Bit +#define DMA_MODE_DATASIZE 0x4000U // Data Size Mode Bit +#define DMA_MODE_CHINTE 0x8000U // Channel Interrupt Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CONTROL register +// +//************************************************************************************************* +#define DMA_CONTROL_RUN 0x1U // Run Bit +#define DMA_CONTROL_HALT 0x2U // Halt Bit +#define DMA_CONTROL_SOFTRESET 0x4U // Soft Reset Bit +#define DMA_CONTROL_PERINTFRC 0x8U // Interrupt Force Bit +#define DMA_CONTROL_PERINTCLR 0x10U // Interrupt Clear Bit +#define DMA_CONTROL_ERRCLR 0x80U // Error Clear Bit +#define DMA_CONTROL_PERINTFLG 0x100U // Interrupt Flag Bit +#define DMA_CONTROL_TRANSFERSTS 0x800U // Transfer Status Bit +#define DMA_CONTROL_BURSTSTS 0x1000U // Burst Status Bit +#define DMA_CONTROL_RUNSTS 0x2000U // Run Status Bit +#define DMA_CONTROL_OVRFLG 0x4000U // Overflow Flag Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_SIZE register +// +//************************************************************************************************* +#define DMA_BURST_SIZE_BURSTSIZE_S 0U +#define DMA_BURST_SIZE_BURSTSIZE_M 0x1FU // Burst Transfer Size + +//************************************************************************************************* +// +// The following are defines for the bit fields in the BURST_COUNT register +// +//************************************************************************************************* +#define DMA_BURST_COUNT_BURSTCOUNT_S 0U +#define DMA_BURST_COUNT_BURSTCOUNT_M 0x1FU // Burst Transfer Size + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_ecap.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ecap.h new file mode 100644 index 0000000..48981d6 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ecap.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_ecap.h +// +// TITLE: Definitions for the ECAP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_ECAP_H +#define HW_ECAP_H + +//************************************************************************************************* +// +// The following are defines for the ECAP register offsets +// +//************************************************************************************************* +#define ECAP_O_TSCTR 0x0U // Time-Stamp Counter +#define ECAP_O_CTRPHS 0x2U // Counter Phase Offset Value Register +#define ECAP_O_CAP1 0x4U // Capture 1 Register +#define ECAP_O_CAP2 0x6U // Capture 2 Register +#define ECAP_O_CAP3 0x8U // Capture 3 Register +#define ECAP_O_CAP4 0xAU // Capture 4 Register +#define ECAP_O_ECCTL1 0x14U // Capture Control Register 1 +#define ECAP_O_ECCTL2 0x15U // Capture Control Register 2 +#define ECAP_O_ECEINT 0x16U // Capture Interrupt Enable Register +#define ECAP_O_ECFLG 0x17U // Capture Interrupt Flag Register +#define ECAP_O_ECCLR 0x18U // Capture Interrupt Clear Register +#define ECAP_O_ECFRC 0x19U // Capture Interrupt Force Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL1 register +// +//************************************************************************************************* +#define ECAP_ECCTL1_CAP1POL 0x1U // Capture Event 1 Polarity select +#define ECAP_ECCTL1_CTRRST1 0x2U // Counter Reset on Capture Event 1 +#define ECAP_ECCTL1_CAP2POL 0x4U // Capture Event 2 Polarity select +#define ECAP_ECCTL1_CTRRST2 0x8U // Counter Reset on Capture Event 2 +#define ECAP_ECCTL1_CAP3POL 0x10U // Capture Event 3 Polarity select +#define ECAP_ECCTL1_CTRRST3 0x20U // Counter Reset on Capture Event 3 +#define ECAP_ECCTL1_CAP4POL 0x40U // Capture Event 4 Polarity select +#define ECAP_ECCTL1_CTRRST4 0x80U // Counter Reset on Capture Event 4 +#define ECAP_ECCTL1_CAPLDEN 0x100U // Enable Loading CAP1-4 regs on a Cap Event +#define ECAP_ECCTL1_PRESCALE_S 9U +#define ECAP_ECCTL1_PRESCALE_M 0x3E00U // Event Filter prescale select +#define ECAP_ECCTL1_FREE_SOFT_S 14U +#define ECAP_ECCTL1_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCTL2 register +// +//************************************************************************************************* +#define ECAP_ECCTL2_CONT_ONESHT 0x1U // Continuous or one-shot +#define ECAP_ECCTL2_STOP_WRAP_S 1U +#define ECAP_ECCTL2_STOP_WRAP_M 0x6U // Stop value for one-shot, Wrap for continuous +#define ECAP_ECCTL2_REARM 0x8U // One-shot re-arm +#define ECAP_ECCTL2_TSCTRSTOP 0x10U // TSCNT counter stop +#define ECAP_ECCTL2_SYNCI_EN 0x20U // Counter sync-in select +#define ECAP_ECCTL2_SYNCO_SEL_S 6U +#define ECAP_ECCTL2_SYNCO_SEL_M 0xC0U // Sync-out mode +#define ECAP_ECCTL2_SWSYNC 0x100U // SW forced counter sync +#define ECAP_ECCTL2_CAP_APWM 0x200U // CAP/APWM operating mode select +#define ECAP_ECCTL2_APWMPOL 0x400U // APWM output polarity select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECEINT register +// +//************************************************************************************************* +#define ECAP_ECEINT_CEVT1 0x2U // Capture Event 1 Interrupt Enable +#define ECAP_ECEINT_CEVT2 0x4U // Capture Event 2 Interrupt Enable +#define ECAP_ECEINT_CEVT3 0x8U // Capture Event 3 Interrupt Enable +#define ECAP_ECEINT_CEVT4 0x10U // Capture Event 4 Interrupt Enable +#define ECAP_ECEINT_CTROVF 0x20U // Counter Overflow Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_PRD 0x40U // Period Equal Interrupt Enable +#define ECAP_ECEINT_CTR_EQ_CMP 0x80U // Compare Equal Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFLG register +// +//************************************************************************************************* +#define ECAP_ECFLG_INT 0x1U // Global Flag +#define ECAP_ECFLG_CEVT1 0x2U // Capture Event 1 Interrupt Flag +#define ECAP_ECFLG_CEVT2 0x4U // Capture Event 2 Interrupt Flag +#define ECAP_ECFLG_CEVT3 0x8U // Capture Event 3 Interrupt Flag +#define ECAP_ECFLG_CEVT4 0x10U // Capture Event 4 Interrupt Flag +#define ECAP_ECFLG_CTROVF 0x20U // Counter Overflow Interrupt Flag +#define ECAP_ECFLG_CTR_PRD 0x40U // Period Equal Interrupt Flag +#define ECAP_ECFLG_CTR_CMP 0x80U // Compare Equal Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECCLR register +// +//************************************************************************************************* +#define ECAP_ECCLR_INT 0x1U // ECAP Global Interrupt Status Clear +#define ECAP_ECCLR_CEVT1 0x2U // Capture Event 1 Status Clear +#define ECAP_ECCLR_CEVT2 0x4U // Capture Event 2 Status Clear +#define ECAP_ECCLR_CEVT3 0x8U // Capture Event 3 Status Clear +#define ECAP_ECCLR_CEVT4 0x10U // Capture Event 4 Status Clear +#define ECAP_ECCLR_CTROVF 0x20U // Counter Overflow Status Clear +#define ECAP_ECCLR_CTR_PRD 0x40U // Period Equal Status Clear +#define ECAP_ECCLR_CTR_CMP 0x80U // Compare Equal Status Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECFRC register +// +//************************************************************************************************* +#define ECAP_ECFRC_CEVT1 0x2U // Capture Event 1 Force Interrupt +#define ECAP_ECFRC_CEVT2 0x4U // Capture Event 2 Force Interrupt +#define ECAP_ECFRC_CEVT3 0x8U // Capture Event 3 Force Interrupt +#define ECAP_ECFRC_CEVT4 0x10U // Capture Event 4 Force Interrupt +#define ECAP_ECFRC_CTROVF 0x20U // Counter Overflow Force Interrupt +#define ECAP_ECFRC_CTR_PRD 0x40U // Period Equal Force Interrupt +#define ECAP_ECFRC_CTR_CMP 0x80U // Compare Equal Force Interrupt + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_emif.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_emif.h new file mode 100644 index 0000000..9f1401e --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_emif.h @@ -0,0 +1,259 @@ +//########################################################################### +// +// FILE: hw_emif.h +// +// TITLE: Definitions for the EMIF registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EMIF_H +#define HW_EMIF_H + +//************************************************************************************************* +// +// The following are defines for the EMIF register offsets +// +//************************************************************************************************* +#define EMIF_O_RCSR 0x0U // Revision Code and Status Register +#define EMIF_O_ASYNC_WCCR 0x2U // Async Wait Cycle Config Register +#define EMIF_O_SDRAM_CR 0x4U // SDRAM (EMxCS0n) Config Register +#define EMIF_O_SDRAM_RCR 0x6U // SDRAM Refresh Control Register +#define EMIF_O_ASYNC_CS2_CR 0x8U // Async 1 (EMxCS2n) Config Register +#define EMIF_O_ASYNC_CS3_CR 0xAU // Async 2 (EMxCS3n) Config Register +#define EMIF_O_ASYNC_CS4_CR 0xCU // Async 3 (EMxCS4n) Config Register +#define EMIF_O_SDRAM_TR 0x10U // SDRAM Timing Register +#define EMIF_O_TOTAL_SDRAM_AR 0x18U // Total SDRAM Accesses Register +#define EMIF_O_TOTAL_SDRAM_ACTR 0x1AU // Total SDRAM Activate Register +#define EMIF_O_SDR_EXT_TMNG 0x1EU // SDRAM SR/PD Exit Timing Register +#define EMIF_O_INT_RAW 0x20U // Interrupt Raw Register +#define EMIF_O_INT_MSK 0x22U // Interrupt Masked Register +#define EMIF_O_INT_MSK_SET 0x24U // Interrupt Mask Set Register +#define EMIF_O_INT_MSK_CLR 0x26U // Interrupt Mask Clear Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCSR register +// +//************************************************************************************************* +#define EMIF_RCSR_MINOR_REVISION_S 0U +#define EMIF_RCSR_MINOR_REVISION_M 0xFFU // Minor Revision. +#define EMIF_RCSR_MAJOR_REVISION_S 8U +#define EMIF_RCSR_MAJOR_REVISION_M 0xFF00U // Major Revision. +#define EMIF_RCSR_MODULE_ID_S 16U +#define EMIF_RCSR_MODULE_ID_M 0x3FFF0000U // EMIF module ID. +#define EMIF_RCSR_FR 0x40000000U // EMIF is running in full rate or half rate. +#define EMIF_RCSR_BE 0x80000000U // EMIF endian mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_WCCR register +// +//************************************************************************************************* +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_S 0U +#define EMIF_ASYNC_WCCR_MAX_EXT_WAIT_M 0xFFU // Maximum Extended Wait cycles. +#define EMIF_ASYNC_WCCR_WP0 0x10000000U // Polarity for EMxWAIT. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_CR register +// +//************************************************************************************************* +#define EMIF_SDRAM_CR_PAGESIGE_S 0U +#define EMIF_SDRAM_CR_PAGESIGE_M 0x7U // Page Size. +#define EMIF_SDRAM_CR_IBANK_S 4U +#define EMIF_SDRAM_CR_IBANK_M 0x70U // Internal Bank setup of SDRAM devices. +#define EMIF_SDRAM_CR_BIT_11_9_LOCK 0x100U // Bits 11 to 9 are writable only if this bit + // is set. +#define EMIF_SDRAM_CR_CL_S 9U +#define EMIF_SDRAM_CR_CL_M 0xE00U // CAS Latency. +#define EMIF_SDRAM_CR_NM 0x4000U // Narrow Mode. +#define EMIF_SDRAM_CR_PDWR 0x20000000U // Perform refreshes during Power Down. +#define EMIF_SDRAM_CR_PD 0x40000000U // Power Down. +#define EMIF_SDRAM_CR_SR 0x80000000U // Self Refresh. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_RCR register +// +//************************************************************************************************* +#define EMIF_SDRAM_RCR_REFRESH_RATE_S 0U +#define EMIF_SDRAM_RCR_REFRESH_RATE_M 0x1FFFU // Refresh Rate. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS2_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS2_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS2_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS2_CR_TA_S 2U +#define EMIF_ASYNC_CS2_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS2_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS2_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS2_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS2_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS2_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS2_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS2_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS2_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS2_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS2_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS2_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS3_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS3_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS3_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS3_CR_TA_S 2U +#define EMIF_ASYNC_CS3_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS3_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS3_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS3_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS3_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS3_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS3_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS3_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS3_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS3_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS3_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS3_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ASYNC_CS4_CR register +// +//************************************************************************************************* +#define EMIF_ASYNC_CS4_CR_ASIZE_S 0U +#define EMIF_ASYNC_CS4_CR_ASIZE_M 0x3U // Asynchronous Memory Size. +#define EMIF_ASYNC_CS4_CR_TA_S 2U +#define EMIF_ASYNC_CS4_CR_TA_M 0xCU // Turn Around cycles. +#define EMIF_ASYNC_CS4_CR_R_HOLD_S 4U +#define EMIF_ASYNC_CS4_CR_R_HOLD_M 0x70U // Read Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_R_STROBE_S 7U +#define EMIF_ASYNC_CS4_CR_R_STROBE_M 0x1F80U // Read Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_R_SETUP_S 13U +#define EMIF_ASYNC_CS4_CR_R_SETUP_M 0x1E000U // Read Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_W_HOLD_S 17U +#define EMIF_ASYNC_CS4_CR_W_HOLD_M 0xE0000U // Write Strobe Hold cycles. +#define EMIF_ASYNC_CS4_CR_W_STROBE_S 20U +#define EMIF_ASYNC_CS4_CR_W_STROBE_M 0x3F00000U // Write Strobe Duration cycles. +#define EMIF_ASYNC_CS4_CR_W_SETUP_S 26U +#define EMIF_ASYNC_CS4_CR_W_SETUP_M 0x3C000000U // Write Strobe Setup cycles. +#define EMIF_ASYNC_CS4_CR_EW 0x40000000U // Extend Wait mode. +#define EMIF_ASYNC_CS4_CR_SS 0x80000000U // Select Strobe mode. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDRAM_TR register +// +//************************************************************************************************* +#define EMIF_SDRAM_TR_T_RRD_S 4U +#define EMIF_SDRAM_TR_T_RRD_M 0x70U // Activate to Activate timing for different bank. +#define EMIF_SDRAM_TR_T_RC_S 8U +#define EMIF_SDRAM_TR_T_RC_M 0xF00U // Activate to Activate timing . +#define EMIF_SDRAM_TR_T_RAS_S 12U +#define EMIF_SDRAM_TR_T_RAS_M 0xF000U // Activate to Precharge timing. +#define EMIF_SDRAM_TR_T_WR_S 16U +#define EMIF_SDRAM_TR_T_WR_M 0x70000U // Last Write to Precharge timing. +#define EMIF_SDRAM_TR_T_RCD_S 20U +#define EMIF_SDRAM_TR_T_RCD_M 0x700000U // Activate to Read/Write timing. +#define EMIF_SDRAM_TR_T_RP_S 24U +#define EMIF_SDRAM_TR_T_RP_M 0x7000000U // Precharge to Activate/Refresh timing. +#define EMIF_SDRAM_TR_T_RFC_S 27U +#define EMIF_SDRAM_TR_T_RFC_M 0xF8000000U // Refresh/Load Mode to Refresh/Activate timing + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDR_EXT_TMNG register +// +//************************************************************************************************* +#define EMIF_SDR_EXT_TMNG_T_XS_S 0U +#define EMIF_SDR_EXT_TMNG_T_XS_M 0x1FU // Self Refresh exit to new command timing. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_RAW register +// +//************************************************************************************************* +#define EMIF_INT_RAW_AT 0x1U // Asynchronous Timeout. +#define EMIF_INT_RAW_LT 0x2U // Line Trap. +#define EMIF_INT_RAW_WR_S 2U +#define EMIF_INT_RAW_WR_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK register +// +//************************************************************************************************* +#define EMIF_INT_MSK_AT_MASKED 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_LT_MASKED 0x2U // Line Trap. +#define EMIF_INT_MSK_WR_MASKED_S 2U +#define EMIF_INT_MSK_WR_MASKED_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_SET register +// +//************************************************************************************************* +#define EMIF_INT_MSK_SET_AT_MASK_SET 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_SET_LT_MASK_SET 0x2U // Line Trap. +#define EMIF_INT_MSK_SET_WR_MASK_SET_S 2U +#define EMIF_INT_MSK_SET_WR_MASK_SET_M 0x3CU // Wait Rise. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INT_MSK_CLR register +// +//************************************************************************************************* +#define EMIF_INT_MSK_CLR_AT_MASK_CLR 0x1U // Asynchronous Timeout. +#define EMIF_INT_MSK_CLR_LT_MASK_CLR 0x2U // Line Trap. +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_S 2U +#define EMIF_INT_MSK_CLR_WR_MASK_CLR_M 0x3CU // Wait Rise. + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwm.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwm.h new file mode 100644 index 0000000..6f7bf2d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwm.h @@ -0,0 +1,1050 @@ +//########################################################################### +// +// FILE: hw_epwm.h +// +// TITLE: Definitions for the EPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWM_H +#define HW_EPWM_H + +//************************************************************************************************* +// +// The following are defines for the EPWM register offsets +// +//************************************************************************************************* +#define EPWM_O_TBCTL 0x0U // Time Base Control Register +#define EPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define EPWM_O_TBCTR 0x4U // Time Base Counter Register +#define EPWM_O_TBSTS 0x5U // Time Base Status Register +#define EPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define EPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define EPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define EPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define EPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define EPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define EPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define EPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define EPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define EPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define EPWM_O_HRPWR 0x21U // HRPWM Power Register +#define EPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define EPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define EPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define EPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define EPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define EPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define EPWM_O_XLINK 0x38U // EPWMx Link Register +#define EPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define EPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define EPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define EPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define EPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define EPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define EPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define EPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define EPWM_O_TBPHS 0x60U // Time Base Phase High +#define EPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define EPWM_O_TBPRD 0x63U // Time Base Period Register +#define EPWM_O_CMPA 0x6AU // Counter Compare A Register +#define EPWM_O_CMPB 0x6CU // Compare B Register +#define EPWM_O_CMPC 0x6FU // Counter Compare C Register +#define EPWM_O_CMPD 0x71U // Counter Compare D Register +#define EPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define EPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define EPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define EPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define EPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define EPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define EPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define EPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define EPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define EPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define EPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define EPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define EPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define EPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define EPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define EPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define EPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define EPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define EPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define EPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define EPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define EPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define EPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define EPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define EPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define EPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define EPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define EPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define EPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define EPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define EPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define EPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define EPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define EPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define EPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define EPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define EPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define EPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define EPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define EPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define EPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define EPWM_TBCTL_CTRMODE_S 0U +#define EPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define EPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define EPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define EPWM_TBCTL_SYNCOSEL_S 4U +#define EPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define EPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define EPWM_TBCTL_HSPCLKDIV_S 7U +#define EPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define EPWM_TBCTL_CLKDIV_S 10U +#define EPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define EPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define EPWM_TBCTL_FREE_SOFT_S 14U +#define EPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define EPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define EPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define EPWM_TBCTL2_SYNCOSELX_S 12U +#define EPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define EPWM_TBCTL2_PRDLDSYNC_S 14U +#define EPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define EPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define EPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define EPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define EPWM_CMPCTL_LOADAMODE_S 0U +#define EPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define EPWM_CMPCTL_LOADBMODE_S 2U +#define EPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define EPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define EPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define EPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define EPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define EPWM_CMPCTL_LOADASYNC_S 10U +#define EPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define EPWM_CMPCTL_LOADBSYNC_S 12U +#define EPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define EPWM_CMPCTL2_LOADCMODE_S 0U +#define EPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define EPWM_CMPCTL2_LOADDMODE_S 2U +#define EPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define EPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define EPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define EPWM_CMPCTL2_LOADCSYNC_S 10U +#define EPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define EPWM_CMPCTL2_LOADDSYNC_S 12U +#define EPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define EPWM_DBCTL_OUT_MODE_S 0U +#define EPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define EPWM_DBCTL_POLSEL_S 2U +#define EPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define EPWM_DBCTL_IN_MODE_S 4U +#define EPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define EPWM_DBCTL_LOADREDMODE_S 6U +#define EPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define EPWM_DBCTL_LOADFEDMODE_S 8U +#define EPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define EPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define EPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define EPWM_DBCTL_OUTSWAP_S 12U +#define EPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define EPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define EPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define EPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define EPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define EPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define EPWM_AQCTL_LDAQAMODE_S 0U +#define EPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define EPWM_AQCTL_LDAQBMODE_S 2U +#define EPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define EPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define EPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define EPWM_AQCTL_LDAQASYNC_S 8U +#define EPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define EPWM_AQCTL_LDAQBSYNC_S 10U +#define EPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define EPWM_AQTSRCSEL_T1SEL_S 0U +#define EPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define EPWM_AQTSRCSEL_T2SEL_S 4U +#define EPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define EPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define EPWM_PCCTL_OSHTWTH_S 1U +#define EPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define EPWM_PCCTL_CHPFREQ_S 5U +#define EPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define EPWM_PCCTL_CHPDUTY_S 8U +#define EPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define EPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define EPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define EPWM_VCAPCTL_TRIGSEL_S 2U +#define EPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define EPWM_VCAPCTL_VDELAYDIV_S 7U +#define EPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define EPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define EPWM_VCNTCFG_STARTEDGE_S 0U +#define EPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define EPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define EPWM_VCNTCFG_STOPEDGE_S 8U +#define EPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define EPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define EPWM_HRCNFG_EDGMODE_S 0U +#define EPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define EPWM_HRCNFG_HRLOAD_S 3U +#define EPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define EPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define EPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define EPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define EPWM_HRCNFG_EDGMODEB_S 8U +#define EPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define EPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define EPWM_HRCNFG_HRLOADB_S 11U +#define EPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define EPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define EPWM_HRMSTEP_HRMSTEP_S 0U +#define EPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define EPWM_HRCNFG2_EDGMODEDB_S 0U +#define EPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define EPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define EPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define EPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define EPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define EPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define EPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define EPWM_HRPCTL_PWMSYNCSELX_S 4U +#define EPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define EPWM_TRREM_TRREM_S 0U +#define EPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define EPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define EPWM_GLDCTL_GLDMODE_S 1U +#define EPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define EPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define EPWM_GLDCTL_GLDPRD_S 7U +#define EPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define EPWM_GLDCTL_GLDCNT_S 10U +#define EPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define EPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define EPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define EPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define EPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define EPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define EPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define EPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define EPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define EPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define EPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define EPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define EPWM_XLINK_TBPRDLINK_S 0U +#define EPWM_XLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define EPWM_XLINK_CMPALINK_S 4U +#define EPWM_XLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define EPWM_XLINK_CMPBLINK_S 8U +#define EPWM_XLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define EPWM_XLINK_CMPCLINK_S 12U +#define EPWM_XLINK_CMPCLINK_M 0xF000U // CMPC Link +#define EPWM_XLINK_CMPDLINK_S 16U +#define EPWM_XLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define EPWM_XLINK_GLDCTL2LINK_S 28U +#define EPWM_XLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define EPWM_AQCTLA_ZRO_S 0U +#define EPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLA_PRD_S 2U +#define EPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLA_CAU_S 4U +#define EPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLA_CAD_S 6U +#define EPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLA_CBU_S 8U +#define EPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLA_CBD_S 10U +#define EPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define EPWM_AQCTLA2_T1U_S 0U +#define EPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLA2_T1D_S 2U +#define EPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLA2_T2U_S 4U +#define EPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLA2_T2D_S 6U +#define EPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define EPWM_AQCTLB_ZRO_S 0U +#define EPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define EPWM_AQCTLB_PRD_S 2U +#define EPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define EPWM_AQCTLB_CAU_S 4U +#define EPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define EPWM_AQCTLB_CAD_S 6U +#define EPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define EPWM_AQCTLB_CBU_S 8U +#define EPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define EPWM_AQCTLB_CBD_S 10U +#define EPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define EPWM_AQCTLB2_T1U_S 0U +#define EPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define EPWM_AQCTLB2_T1D_S 2U +#define EPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define EPWM_AQCTLB2_T2U_S 4U +#define EPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define EPWM_AQCTLB2_T2D_S 6U +#define EPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define EPWM_AQSFRC_ACTSFA_S 0U +#define EPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define EPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define EPWM_AQSFRC_ACTSFB_S 3U +#define EPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define EPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define EPWM_AQSFRC_RLDCSF_S 6U +#define EPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define EPWM_AQCSFRC_CSFA_S 0U +#define EPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define EPWM_AQCSFRC_CSFB_S 2U +#define EPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define EPWM_DBREDHR_DBREDHR_S 9U +#define EPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define EPWM_DBRED_DBRED_S 0U +#define EPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define EPWM_DBFEDHR_DBFEDHR_S 9U +#define EPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define EPWM_DBFED_DBFED_S 0U +#define EPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define EPWM_TBPHS_TBPHSHR_S 0U +#define EPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define EPWM_TBPHS_TBPHS_S 16U +#define EPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define EPWM_CMPA_CMPAHR_S 0U +#define EPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define EPWM_CMPA_CMPA_S 16U +#define EPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define EPWM_CMPB_CMPBHR_S 0U +#define EPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define EPWM_CMPB_CMPB_S 16U +#define EPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define EPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define EPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define EPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define EPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define EPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define EPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define EPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define EPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define EPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define EPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define EPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define EPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define EPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define EPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define EPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define EPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define EPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define EPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define EPWM_TZDCSEL_DCAEVT1_S 0U +#define EPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define EPWM_TZDCSEL_DCAEVT2_S 3U +#define EPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define EPWM_TZDCSEL_DCBEVT1_S 6U +#define EPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define EPWM_TZDCSEL_DCBEVT2_S 9U +#define EPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define EPWM_TZCTL_TZA_S 0U +#define EPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define EPWM_TZCTL_TZB_S 2U +#define EPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define EPWM_TZCTL_DCAEVT1_S 4U +#define EPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define EPWM_TZCTL_DCAEVT2_S 6U +#define EPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define EPWM_TZCTL_DCBEVT1_S 8U +#define EPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define EPWM_TZCTL_DCBEVT2_S 10U +#define EPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define EPWM_TZCTL2_TZAU_S 0U +#define EPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define EPWM_TZCTL2_TZAD_S 3U +#define EPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define EPWM_TZCTL2_TZBU_S 6U +#define EPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define EPWM_TZCTL2_TZBD_S 9U +#define EPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define EPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define EPWM_TZCTLDCA_DCAEVT1U_S 0U +#define EPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT1D_S 3U +#define EPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCA_DCAEVT2U_S 6U +#define EPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCA_DCAEVT2D_S 9U +#define EPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define EPWM_TZCTLDCB_DCBEVT1U_S 0U +#define EPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT1D_S 3U +#define EPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define EPWM_TZCTLDCB_DCBEVT2U_S 6U +#define EPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is UP +#define EPWM_TZCTLDCB_DCBEVT2D_S 9U +#define EPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define EPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define EPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define EPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define EPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define EPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define EPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define EPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define EPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define EPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define EPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define EPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define EPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define EPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define EPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define EPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define EPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define EPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define EPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define EPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define EPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event 2 +#define EPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define EPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define EPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define EPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define EPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define EPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define EPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define EPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event 1 +#define EPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define EPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define EPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define EPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define EPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define EPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define EPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define EPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define EPWM_TZCLR_CBCPULSE_S 14U +#define EPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define EPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define EPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define EPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define EPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define EPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define EPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define EPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define EPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define EPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define EPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define EPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define EPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define EPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define EPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define EPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define EPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define EPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define EPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define EPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define EPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define EPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define EPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define EPWM_ETSEL_INTSEL_S 0U +#define EPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define EPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define EPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define EPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define EPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define EPWM_ETSEL_SOCASEL_S 8U +#define EPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define EPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define EPWM_ETSEL_SOCBSEL_S 12U +#define EPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define EPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define EPWM_ETPS_INTPRD_S 0U +#define EPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define EPWM_ETPS_INTCNT_S 2U +#define EPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define EPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define EPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define EPWM_ETPS_SOCAPRD_S 8U +#define EPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define EPWM_ETPS_SOCACNT_S 10U +#define EPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define EPWM_ETPS_SOCBPRD_S 12U +#define EPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define EPWM_ETPS_SOCBCNT_S 14U +#define EPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define EPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define EPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define EPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define EPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define EPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define EPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define EPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define EPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define EPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define EPWM_ETINTPS_INTPRD2_S 0U +#define EPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define EPWM_ETINTPS_INTCNT2_S 4U +#define EPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define EPWM_ETSOCPS_SOCAPRD2_S 0U +#define EPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define EPWM_ETSOCPS_SOCACNT2_S 4U +#define EPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define EPWM_ETSOCPS_SOCBPRD2_S 8U +#define EPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define EPWM_ETSOCPS_SOCBCNT2_S 12U +#define EPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define EPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define EPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define EPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define EPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define EPWM_ETCNTINIT_INTINIT_S 0U +#define EPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCAINIT_S 4U +#define EPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define EPWM_ETCNTINIT_SOCBINIT_S 8U +#define EPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define EPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define EPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define EPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define EPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define EPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define EPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define EPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define EPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define EPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define EPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define EPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define EPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define EPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define EPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define EPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define EPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define EPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define EPWM_DCFCTL_SRCSEL_S 0U +#define EPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define EPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define EPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define EPWM_DCFCTL_PULSESEL_S 4U +#define EPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define EPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define EPWM_DCFCTL_EDGEMODE_S 8U +#define EPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define EPWM_DCFCTL_EDGECOUNT_S 10U +#define EPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define EPWM_DCFCTL_EDGESTATUS_S 13U +#define EPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define EPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define EPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define EPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define EPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define EPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define EPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define EPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define EPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define EPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define EPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwmxbar.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwmxbar.h new file mode 100644 index 0000000..5fb6058 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_epwmxbar.h @@ -0,0 +1,1192 @@ +//########################################################################### +// +// FILE: hw_epwmxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EPWMXBAR_H +#define HW_EPWMXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_TRIP4MUX0TO15CFG 0x0U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP4MUX16TO31CFG 0x2U // ePWM XBAR Mux Configuration for TRIP4 +#define XBAR_O_TRIP5MUX0TO15CFG 0x4U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP5MUX16TO31CFG 0x6U // ePWM XBAR Mux Configuration for TRIP5 +#define XBAR_O_TRIP7MUX0TO15CFG 0x8U // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP7MUX16TO31CFG 0xAU // ePWM XBAR Mux Configuration for TRIP7 +#define XBAR_O_TRIP8MUX0TO15CFG 0xCU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP8MUX16TO31CFG 0xEU // ePWM XBAR Mux Configuration for TRIP8 +#define XBAR_O_TRIP9MUX0TO15CFG 0x10U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP9MUX16TO31CFG 0x12U // ePWM XBAR Mux Configuration for TRIP9 +#define XBAR_O_TRIP10MUX0TO15CFG 0x14U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP10MUX16TO31CFG 0x16U // ePWM XBAR Mux Configuration for TRIP10 +#define XBAR_O_TRIP11MUX0TO15CFG 0x18U // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP11MUX16TO31CFG 0x1AU // ePWM XBAR Mux Configuration for TRIP11 +#define XBAR_O_TRIP12MUX0TO15CFG 0x1CU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP12MUX16TO31CFG 0x1EU // ePWM XBAR Mux Configuration for TRIP12 +#define XBAR_O_TRIP4MUXENABLE 0x20U // ePWM XBAR Mux Enable for TRIP4 +#define XBAR_O_TRIP5MUXENABLE 0x22U // ePWM XBAR Mux Enable for TRIP5 +#define XBAR_O_TRIP7MUXENABLE 0x24U // ePWM XBAR Mux Enable for TRIP7 +#define XBAR_O_TRIP8MUXENABLE 0x26U // ePWM XBAR Mux Enable for TRIP8 +#define XBAR_O_TRIP9MUXENABLE 0x28U // ePWM XBAR Mux Enable for TRIP9 +#define XBAR_O_TRIP10MUXENABLE 0x2AU // ePWM XBAR Mux Enable for TRIP10 +#define XBAR_O_TRIP11MUXENABLE 0x2CU // ePWM XBAR Mux Enable for TRIP11 +#define XBAR_O_TRIP12MUXENABLE 0x2EU // ePWM XBAR Mux Enable for TRIP12 +#define XBAR_O_TRIPOUTINV 0x38U // ePWM XBAR Output Inversion Register +#define XBAR_O_TRIPLOCK 0x3EU // ePWM XBAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP4MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP4 of + // EPWM-XBAR +#define XBAR_TRIP4MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP4 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP5MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP5 of + // EPWM-XBAR +#define XBAR_TRIP5MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP5 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP7MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP7 of + // EPWM-XBAR +#define XBAR_TRIP7MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP7 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP8MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP8 of + // EPWM-XBAR +#define XBAR_TRIP8MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP8 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP9MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP9MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP9MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP9MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP9MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP9MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP9MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP9MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP9MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP9MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP9MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP9MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP9MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP9MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP9MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP9MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP9MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP9MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP9MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP9MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP9MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP9MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP9MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP9MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP9MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP9MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP9MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP9MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP9MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP9MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP9MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP9MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP9 of + // EPWM-XBAR +#define XBAR_TRIP9MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP9MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP9 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP10MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP10MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP10MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP10MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP10MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP10MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP10MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP10MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP10MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP10MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP10MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP10MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP10MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP10MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP10MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP10MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP10MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP10MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP10MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP10MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP10MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP10MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP10MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP10MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP10MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP10MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP10MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP10MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP10MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP10MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP10MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP10MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP10 of + // EPWM-XBAR +#define XBAR_TRIP10MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP10MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP10 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP11MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP11MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP11MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP11MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP11MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP11MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP11MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP11MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP11MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP11MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP11MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP11MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP11MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP11MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP11MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP11MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP11MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP11MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP11MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP11MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP11MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP11MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP11MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP11MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP11MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP11MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP11MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP11MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP11MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP11MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP11MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP11MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP11 of + // EPWM-XBAR +#define XBAR_TRIP11MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP11MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP11 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX0TO15CFG_MUX0_S 0U +#define XBAR_TRIP12MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX1_S 2U +#define XBAR_TRIP12MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX2_S 4U +#define XBAR_TRIP12MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX3_S 6U +#define XBAR_TRIP12MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX4_S 8U +#define XBAR_TRIP12MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX5_S 10U +#define XBAR_TRIP12MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX6_S 12U +#define XBAR_TRIP12MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX7_S 14U +#define XBAR_TRIP12MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX8_S 16U +#define XBAR_TRIP12MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX9_S 18U +#define XBAR_TRIP12MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX10_S 20U +#define XBAR_TRIP12MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX11_S 22U +#define XBAR_TRIP12MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX12_S 24U +#define XBAR_TRIP12MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX13_S 26U +#define XBAR_TRIP12MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX14_S 28U +#define XBAR_TRIP12MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX0TO15CFG_MUX15_S 30U +#define XBAR_TRIP12MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_TRIP12MUX16TO31CFG_MUX16_S 0U +#define XBAR_TRIP12MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX17_S 2U +#define XBAR_TRIP12MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX18_S 4U +#define XBAR_TRIP12MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX19_S 6U +#define XBAR_TRIP12MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX20_S 8U +#define XBAR_TRIP12MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX21_S 10U +#define XBAR_TRIP12MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX22_S 12U +#define XBAR_TRIP12MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX23_S 14U +#define XBAR_TRIP12MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX24_S 16U +#define XBAR_TRIP12MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX25_S 18U +#define XBAR_TRIP12MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX26_S 20U +#define XBAR_TRIP12MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX27_S 22U +#define XBAR_TRIP12MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX28_S 24U +#define XBAR_TRIP12MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX29_S 26U +#define XBAR_TRIP12MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX30_S 28U +#define XBAR_TRIP12MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for TRIP12 of + // EPWM-XBAR +#define XBAR_TRIP12MUX16TO31CFG_MUX31_S 30U +#define XBAR_TRIP12MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for TRIP12 of + // EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP4MUXENABLE_MUX0 0x1U // mux0 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP4 of EPWM-XBAR +#define XBAR_TRIP4MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP4 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP5MUXENABLE_MUX0 0x1U // mux0 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP5 of EPWM-XBAR +#define XBAR_TRIP5MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP5 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP7MUXENABLE_MUX0 0x1U // mux0 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP7 of EPWM-XBAR +#define XBAR_TRIP7MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP7 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP8MUXENABLE_MUX0 0x1U // mux0 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP8 of EPWM-XBAR +#define XBAR_TRIP8MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP8 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP9MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP9MUXENABLE_MUX0 0x1U // mux0 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP9 of EPWM-XBAR +#define XBAR_TRIP9MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP9 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP10MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP10MUXENABLE_MUX0 0x1U // mux0 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP10 of EPWM-XBAR +#define XBAR_TRIP10MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP10 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP11MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP11MUXENABLE_MUX0 0x1U // mux0 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP11 of EPWM-XBAR +#define XBAR_TRIP11MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP11 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIP12MUXENABLE register +// +//************************************************************************************************* +#define XBAR_TRIP12MUXENABLE_MUX0 0x1U // mux0 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX1 0x2U // Mux1 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX2 0x4U // Mux2 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX3 0x8U // Mux3 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX4 0x10U // Mux4 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX5 0x20U // Mux5 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX6 0x40U // Mux6 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX7 0x80U // Mux7 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX8 0x100U // Mux8 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX9 0x200U // Mux9 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX10 0x400U // Mux10 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX11 0x800U // Mux11 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX12 0x1000U // Mux12 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX13 0x2000U // Mux13 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX14 0x4000U // Mux14 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX15 0x8000U // Mux15 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX16 0x10000U // Mux16 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX17 0x20000U // Mux17 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX18 0x40000U // Mux18 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX19 0x80000U // Mux19 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX20 0x100000U // Mux20 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX21 0x200000U // Mux21 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX22 0x400000U // Mux22 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX23 0x800000U // Mux23 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX24 0x1000000U // Mux24 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX25 0x2000000U // Mux25 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX26 0x4000000U // Mux26 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX27 0x8000000U // Mux27 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX28 0x10000000U // Mux28 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX29 0x20000000U // Mux29 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX30 0x40000000U // Mux30 to drive TRIP12 of EPWM-XBAR +#define XBAR_TRIP12MUXENABLE_MUX31 0x80000000U // Mux31 to drive TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPOUTINV register +// +//************************************************************************************************* +#define XBAR_TRIPOUTINV_TRIP4 0x1U // Selects polarity for TRIP4 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP5 0x2U // Selects polarity for TRIP5 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP7 0x4U // Selects polarity for TRIP7 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP8 0x8U // Selects polarity for TRIP8 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP9 0x10U // Selects polarity for TRIP9 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP10 0x20U // Selects polarity for TRIP10 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP11 0x40U // Selects polarity for TRIP11 of EPWM-XBAR +#define XBAR_TRIPOUTINV_TRIP12 0x80U // Selects polarity for TRIP12 of EPWM-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRIPLOCK register +// +//************************************************************************************************* +#define XBAR_TRIPLOCK_LOCK 0x1U // Locks the configuration for EPWM-XBAR +#define XBAR_TRIPLOCK_KEY_S 16U +#define XBAR_TRIPLOCK_KEY_M 0xFFFF0000U // Write protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_eqep.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_eqep.h new file mode 100644 index 0000000..7dbb33a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_eqep.h @@ -0,0 +1,225 @@ +//########################################################################### +// +// FILE: hw_eqep.h +// +// TITLE: Definitions for the EQEP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_EQEP_H +#define HW_EQEP_H + +//************************************************************************************************* +// +// The following are defines for the EQEP register offsets +// +//************************************************************************************************* +#define EQEP_O_QPOSCNT 0x0U // Position Counter +#define EQEP_O_QPOSINIT 0x2U // Position Counter Init +#define EQEP_O_QPOSMAX 0x4U // Maximum Position Count +#define EQEP_O_QPOSCMP 0x6U // Position Compare +#define EQEP_O_QPOSILAT 0x8U // Index Position Latch +#define EQEP_O_QPOSSLAT 0xAU // Strobe Position Latch +#define EQEP_O_QPOSLAT 0xCU // Position Latch +#define EQEP_O_QUTMR 0xEU // QEP Unit Timer +#define EQEP_O_QUPRD 0x10U // QEP Unit Period +#define EQEP_O_QWDTMR 0x12U // QEP Watchdog Timer +#define EQEP_O_QWDPRD 0x13U // QEP Watchdog Period +#define EQEP_O_QDECCTL 0x14U // Quadrature Decoder Control +#define EQEP_O_QEPCTL 0x15U // QEP Control +#define EQEP_O_QCAPCTL 0x16U // Qaudrature Capture Control +#define EQEP_O_QPOSCTL 0x17U // Position Compare Control +#define EQEP_O_QEINT 0x18U // QEP Interrupt Control +#define EQEP_O_QFLG 0x19U // QEP Interrupt Flag +#define EQEP_O_QCLR 0x1AU // QEP Interrupt Clear +#define EQEP_O_QFRC 0x1BU // QEP Interrupt Force +#define EQEP_O_QEPSTS 0x1CU // QEP Status +#define EQEP_O_QCTMR 0x1DU // QEP Capture Timer +#define EQEP_O_QCPRD 0x1EU // QEP Capture Period +#define EQEP_O_QCTMRLAT 0x1FU // QEP Capture Latch +#define EQEP_O_QCPRDLAT 0x20U // QEP Capture Period Latch + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QDECCTL register +// +//************************************************************************************************* +#define EQEP_QDECCTL_QSP 0x20U // QEPS input polarity +#define EQEP_QDECCTL_QIP 0x40U // QEPI input polarity +#define EQEP_QDECCTL_QBP 0x80U // QEPB input polarity +#define EQEP_QDECCTL_QAP 0x100U // QEPA input polarity +#define EQEP_QDECCTL_IGATE 0x200U // Index pulse gating option +#define EQEP_QDECCTL_SWAP 0x400U // CLK/DIR Signal Source for Position Counter +#define EQEP_QDECCTL_XCR 0x800U // External Clock Rate +#define EQEP_QDECCTL_SPSEL 0x1000U // Sync output pin selection +#define EQEP_QDECCTL_SOEN 0x2000U // Sync output-enable +#define EQEP_QDECCTL_QSRC_S 14U +#define EQEP_QDECCTL_QSRC_M 0xC000U // Position-counter source selection + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPCTL register +// +//************************************************************************************************* +#define EQEP_QEPCTL_WDE 0x1U // QEP watchdog enable +#define EQEP_QEPCTL_UTE 0x2U // QEP unit timer enable +#define EQEP_QEPCTL_QCLM 0x4U // QEP capture latch mode +#define EQEP_QEPCTL_QPEN 0x8U // Quadrature postotion counter enable +#define EQEP_QEPCTL_IEL_S 4U +#define EQEP_QEPCTL_IEL_M 0x30U // Index event latch +#define EQEP_QEPCTL_SEL 0x40U // Strobe event latch +#define EQEP_QEPCTL_SWI 0x80U // Software init position counter +#define EQEP_QEPCTL_IEI_S 8U +#define EQEP_QEPCTL_IEI_M 0x300U // Index event init of position count +#define EQEP_QEPCTL_SEI_S 10U +#define EQEP_QEPCTL_SEI_M 0xC00U // Strobe event init +#define EQEP_QEPCTL_PCRM_S 12U +#define EQEP_QEPCTL_PCRM_M 0x3000U // Postion counter reset +#define EQEP_QEPCTL_FREE_SOFT_S 14U +#define EQEP_QEPCTL_FREE_SOFT_M 0xC000U // Emulation mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCAPCTL register +// +//************************************************************************************************* +#define EQEP_QCAPCTL_UPPS_S 0U +#define EQEP_QCAPCTL_UPPS_M 0xFU // Unit position event prescaler +#define EQEP_QCAPCTL_CCPS_S 4U +#define EQEP_QCAPCTL_CCPS_M 0x70U // eQEP capture timer clock prescaler +#define EQEP_QCAPCTL_CEN 0x8000U // Enable eQEP capture + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QPOSCTL register +// +//************************************************************************************************* +#define EQEP_QPOSCTL_PCSPW_S 0U +#define EQEP_QPOSCTL_PCSPW_M 0xFFFU // Position compare sync pulse width +#define EQEP_QPOSCTL_PCE 0x1000U // Position compare enable/disable +#define EQEP_QPOSCTL_PCPOL 0x2000U // Polarity of sync output +#define EQEP_QPOSCTL_PCLOAD 0x4000U // Position compare of shadow load +#define EQEP_QPOSCTL_PCSHDW 0x8000U // Position compare of shadow enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEINT register +// +//************************************************************************************************* +#define EQEP_QEINT_PCE 0x2U // Position counter error interrupt enable +#define EQEP_QEINT_QPE 0x4U // Quadrature phase error interrupt enable +#define EQEP_QEINT_QDC 0x8U // Quadrature direction change interrupt enable +#define EQEP_QEINT_WTO 0x10U // Watchdog time out interrupt enable +#define EQEP_QEINT_PCU 0x20U // Position counter underflow interrupt enable +#define EQEP_QEINT_PCO 0x40U // Position counter overflow interrupt enable +#define EQEP_QEINT_PCR 0x80U // Position-compare ready interrupt enable +#define EQEP_QEINT_PCM 0x100U // Position-compare match interrupt enable +#define EQEP_QEINT_SEL 0x200U // Strobe event latch interrupt enable +#define EQEP_QEINT_IEL 0x400U // Index event latch interrupt enable +#define EQEP_QEINT_UTO 0x800U // Unit time out interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFLG register +// +//************************************************************************************************* +#define EQEP_QFLG_INT 0x1U // Global interrupt status flag +#define EQEP_QFLG_PCE 0x2U // Position counter error interrupt flag +#define EQEP_QFLG_PHE 0x4U // Quadrature phase error interrupt flag +#define EQEP_QFLG_QDC 0x8U // Quadrature direction change interrupt flag +#define EQEP_QFLG_WTO 0x10U // Watchdog timeout interrupt flag +#define EQEP_QFLG_PCU 0x20U // Position counter underflow interrupt flag +#define EQEP_QFLG_PCO 0x40U // Position counter overflow interrupt flag +#define EQEP_QFLG_PCR 0x80U // Position-compare ready interrupt flag +#define EQEP_QFLG_PCM 0x100U // eQEP compare match event interrupt flag +#define EQEP_QFLG_SEL 0x200U // Strobe event latch interrupt flag +#define EQEP_QFLG_IEL 0x400U // Index event latch interrupt flag +#define EQEP_QFLG_UTO 0x800U // Unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QCLR register +// +//************************************************************************************************* +#define EQEP_QCLR_INT 0x1U // Global interrupt clear flag +#define EQEP_QCLR_PCE 0x2U // Clear position counter error interrupt flag +#define EQEP_QCLR_PHE 0x4U // Clear quadrature phase error interrupt flag +#define EQEP_QCLR_QDC 0x8U // Clear quadrature direction change interrupt flag +#define EQEP_QCLR_WTO 0x10U // Clear watchdog timeout interrupt flag +#define EQEP_QCLR_PCU 0x20U // Clear position counter underflow interrupt flag +#define EQEP_QCLR_PCO 0x40U // Clear position counter overflow interrupt flag +#define EQEP_QCLR_PCR 0x80U // Clear position-compare ready interrupt flag +#define EQEP_QCLR_PCM 0x100U // Clear eQEP compare match event interrupt flag +#define EQEP_QCLR_SEL 0x200U // Clear strobe event latch interrupt flag +#define EQEP_QCLR_IEL 0x400U // Clear index event latch interrupt flag +#define EQEP_QCLR_UTO 0x800U // Clear unit time out interrupt flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QFRC register +// +//************************************************************************************************* +#define EQEP_QFRC_PCE 0x2U // Force position counter error interrupt +#define EQEP_QFRC_PHE 0x4U // Force quadrature phase error interrupt +#define EQEP_QFRC_QDC 0x8U // Force quadrature direction change interrupt +#define EQEP_QFRC_WTO 0x10U // Force watchdog time out interrupt +#define EQEP_QFRC_PCU 0x20U // Force position counter underflow interrupt +#define EQEP_QFRC_PCO 0x40U // Force position counter overflow interrupt +#define EQEP_QFRC_PCR 0x80U // Force position-compare ready interrupt +#define EQEP_QFRC_PCM 0x100U // Force position-compare match interrupt +#define EQEP_QFRC_SEL 0x200U // Force strobe event latch interrupt +#define EQEP_QFRC_IEL 0x400U // Force index event latch interrupt +#define EQEP_QFRC_UTO 0x800U // Force unit time out interrupt + +//************************************************************************************************* +// +// The following are defines for the bit fields in the QEPSTS register +// +//************************************************************************************************* +#define EQEP_QEPSTS_PCEF 0x1U // Position counter error flag. +#define EQEP_QEPSTS_FIMF 0x2U // First index marker flag +#define EQEP_QEPSTS_CDEF 0x4U // Capture direction error flag +#define EQEP_QEPSTS_COEF 0x8U // Capture overflow error flag +#define EQEP_QEPSTS_QDLF 0x10U // eQEP direction latch flag +#define EQEP_QEPSTS_QDF 0x20U // Quadrature direction flag +#define EQEP_QEPSTS_FIDF 0x40U // The first index marker +#define EQEP_QEPSTS_UPEVNT 0x80U // Unit position event flag + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_flash.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_flash.h new file mode 100644 index 0000000..73319f1 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_flash.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_flash.h +// +// TITLE: Definitions for the FLASH registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_FLASH_H +#define HW_FLASH_H + +//************************************************************************************************* +// +// The following are defines for the FLASH register offsets +// +//************************************************************************************************* +#define FLASH_O_FRDCNTL 0x0U // Flash Read Control Register +#define FLASH_O_FBAC 0x1EU // Flash Bank Access Control Register +#define FLASH_O_FBFALLBACK 0x20U // Flash Bank Fallback Power Register +#define FLASH_O_FBPRDY 0x22U // Flash Bank Pump Ready Register +#define FLASH_O_FPAC1 0x24U // Flash Pump Access Control Register 1 +#define FLASH_O_FMSTAT 0x2AU // Flash Module Status Register +#define FLASH_O_FRD_INTF_CTRL 0x180U // Flash Read Interface Control Register + +#define FLASH_O_ECC_ENABLE 0x0U // ECC Enable +#define FLASH_O_SINGLE_ERR_ADDR_LOW 0x2U // Single Error Address Low +#define FLASH_O_SINGLE_ERR_ADDR_HIGH 0x4U // Single Error Address High +#define FLASH_O_UNC_ERR_ADDR_LOW 0x6U // Uncorrectable Error Address Low +#define FLASH_O_UNC_ERR_ADDR_HIGH 0x8U // Uncorrectable Error Address High +#define FLASH_O_ERR_STATUS 0xAU // Error Status +#define FLASH_O_ERR_POS 0xCU // Error Position +#define FLASH_O_ERR_STATUS_CLR 0xEU // Error Status Clear +#define FLASH_O_ERR_CNT 0x10U // Error Control +#define FLASH_O_ERR_THRESHOLD 0x12U // Error Threshold +#define FLASH_O_ERR_INTFLG 0x14U // Error Interrupt Flag +#define FLASH_O_ERR_INTCLR 0x16U // Error Interrupt Flag Clear +#define FLASH_O_FDATAH_TEST 0x18U // Data High Test +#define FLASH_O_FDATAL_TEST 0x1AU // Data Low Test +#define FLASH_O_FADDR_TEST 0x1CU // ECC Test Address +#define FLASH_O_FECC_TEST 0x1EU // ECC Test Address +#define FLASH_O_FECC_CTRL 0x20U // ECC Control +#define FLASH_O_FOUTH_TEST 0x22U // Test Data Out High +#define FLASH_O_FOUTL_TEST 0x24U // Test Data Out Low +#define FLASH_O_FECC_STATUS 0x26U // ECC Status + +#define FLASH_O_PUMPREQUEST 0x0U // Flash programming semaphore PUMP request register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRDCNTL register +// +//************************************************************************************************* +#define FLASH_FRDCNTL_RWAIT_S 8U +#define FLASH_FRDCNTL_RWAIT_M 0xF00U // Random Read Waitstate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBAC register +// +//************************************************************************************************* +#define FLASH_FBAC_VREADST_S 0U +#define FLASH_FBAC_VREADST_M 0xFFU // VREAD Setup Time Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBFALLBACK register +// +//************************************************************************************************* +#define FLASH_FBFALLBACK_BNKPWR0_S 0U +#define FLASH_FBFALLBACK_BNKPWR0_M 0x3U // Bank Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FBPRDY register +// +//************************************************************************************************* +#define FLASH_FBPRDY_BANKRDY 0x1U // Flash Bank Active Power State +#define FLASH_FBPRDY_PUMPRDY 0x8000U // Flash Pump Active Power Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FPAC1 register +// +//************************************************************************************************* +#define FLASH_FPAC1_PMPPWR 0x1U // Charge Pump Fallback Power Mode +#define FLASH_FPAC1_PSLEEP_S 16U +#define FLASH_FPAC1_PSLEEP_M 0xFFF0000U // Pump Sleep Down Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FMSTAT register +// +//************************************************************************************************* +#define FLASH_FMSTAT_PSUSP 0x2U // Program Suspend. +#define FLASH_FMSTAT_ESUSP 0x4U // Erase Suspend. +#define FLASH_FMSTAT_VOLTSTAT 0x8U // Flash Pump Power Status +#define FLASH_FMSTAT_CSTAT 0x10U // Command Fail Status +#define FLASH_FMSTAT_INVDAT 0x20U // Invalid Data +#define FLASH_FMSTAT_PGM 0x40U // Program Operation Status +#define FLASH_FMSTAT_ERS 0x80U // Erase Operation Status +#define FLASH_FMSTAT_BUSY 0x100U // Busy Bit +#define FLASH_FMSTAT_EV 0x400U // Erase Verify Status +#define FLASH_FMSTAT_PGV 0x1000U // Programming Verify Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FRD_INTF_CTRL register +// +//************************************************************************************************* +#define FLASH_FRD_INTF_CTRL_PREFETCH_EN 0x1U // Prefetch Enable +#define FLASH_FRD_INTF_CTRL_DATA_CACHE_EN 0x2U // Data Cache Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ECC_ENABLE register +// +//************************************************************************************************* +#define FLASH_ECC_ENABLE_ENABLE_S 0U +#define FLASH_ECC_ENABLE_ENABLE_M 0xFU // Enable ECC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_FAIL_0_L 0x1U // Lower 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_L 0x2U // Lower 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_L 0x4U // Lower 64 bits Uncorrectable error occurred +#define FLASH_ERR_STATUS_FAIL_0_H 0x10000U // Upper 64bits Single Bit Error Corrected Value 0 +#define FLASH_ERR_STATUS_FAIL_1_H 0x20000U // Upper 64bits Single Bit Error Corrected Value 1 +#define FLASH_ERR_STATUS_UNC_ERR_H 0x40000U // Upper 64 bits Uncorrectable error occurred + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_POS register +// +//************************************************************************************************* +#define FLASH_ERR_POS_ERR_POS_L_S 0U +#define FLASH_ERR_POS_ERR_POS_L_M 0x3FU // Bit Position of Single bit Error in lower 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_L 0x100U // Error Type in lower 64 bits +#define FLASH_ERR_POS_ERR_POS_H_S 16U +#define FLASH_ERR_POS_ERR_POS_H_M 0x3F0000U // Bit Position of Single bit Error in upper 64 + // bits +#define FLASH_ERR_POS_ERR_TYPE_H 0x1000000U // Error Type in upper 64 bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_STATUS_CLR register +// +//************************************************************************************************* +#define FLASH_ERR_STATUS_CLR_FAIL_0_L_CLR 0x1U // Lower 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_L_CLR 0x2U // Lower 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_L_CLR 0x4U // Lower 64 bits Uncorrectable error + // occurred Clear +#define FLASH_ERR_STATUS_CLR_FAIL_0_H_CLR 0x10000U // Upper 64bits Single Bit Error Corrected + // Value 0 Clear +#define FLASH_ERR_STATUS_CLR_FAIL_1_H_CLR 0x20000U // Upper 64bits Single Bit Error Corrected + // Value 1 Clear +#define FLASH_ERR_STATUS_CLR_UNC_ERR_H_CLR 0x40000U // Upper 64 bits Uncorrectable error + // occurred Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_CNT register +// +//************************************************************************************************* +#define FLASH_ERR_CNT_ERR_CNT_S 0U +#define FLASH_ERR_CNT_ERR_CNT_M 0xFFFFU // Error counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_THRESHOLD register +// +//************************************************************************************************* +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_S 0U +#define FLASH_ERR_THRESHOLD_ERR_THRESHOLD_M 0xFFFFU // Error Threshold + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTFLG register +// +//************************************************************************************************* +#define FLASH_ERR_INTFLG_SINGLE_ERR_INTFLG 0x1U // Single Error Interrupt Flag +#define FLASH_ERR_INTFLG_UNC_ERR_INTFLG 0x2U // Uncorrectable Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ERR_INTCLR register +// +//************************************************************************************************* +#define FLASH_ERR_INTCLR_SINGLE_ERR_INTCLR 0x1U // Single Error Interrupt Flag Clear +#define FLASH_ERR_INTCLR_UNC_ERR_INTCLR 0x2U // Uncorrectable Interrupt Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FADDR_TEST register +// +//************************************************************************************************* +#define FLASH_FADDR_TEST_ADDRL_S 3U +#define FLASH_FADDR_TEST_ADDRL_M 0xFFF8U // ECC Address Low +#define FLASH_FADDR_TEST_ADDRH_S 16U +#define FLASH_FADDR_TEST_ADDRH_M 0x3F0000U // ECC Address High + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_TEST register +// +//************************************************************************************************* +#define FLASH_FECC_TEST_ECC_S 0U +#define FLASH_FECC_TEST_ECC_M 0xFFU // ECC Control Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_CTRL register +// +//************************************************************************************************* +#define FLASH_FECC_CTRL_ECC_TEST_EN 0x1U // Enable ECC Test Logic +#define FLASH_FECC_CTRL_ECC_SELECT 0x2U // ECC Bit Select +#define FLASH_FECC_CTRL_DO_ECC_CALC 0x4U // Enable ECC Calculation + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FECC_STATUS register +// +//************************************************************************************************* +#define FLASH_FECC_STATUS_SINGLE_ERR 0x1U // Test Result is Single Bit Error +#define FLASH_FECC_STATUS_UNC_ERR 0x2U // Test Result is Uncorrectable Error +#define FLASH_FECC_STATUS_DATA_ERR_POS_S 2U +#define FLASH_FECC_STATUS_DATA_ERR_POS_M 0xFCU // Holds Bit Position of Error +#define FLASH_FECC_STATUS_ERR_TYPE 0x100U // Holds Bit Position of 8 Check Bits of Error + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PUMPREQUEST register +// +//************************************************************************************************* +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_S 0U +#define FLASH_PUMPREQUEST_PUMP_OWNERSHIP_M 0x3U // Flash Pump Request Semaphore between + // CPU1 and CPU2 +#define FLASH_PUMPREQUEST_KEY_S 16U +#define FLASH_PUMPREQUEST_KEY_M 0xFFFF0000U // Key Qualifier for writes to this + // register + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_gpio.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_gpio.h new file mode 100644 index 0000000..0be426d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_gpio.h @@ -0,0 +1,4018 @@ +//########################################################################### +// +// FILE: hw_gpio.h +// +// TITLE: Definitions for the GPIO registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_GPIO_H +#define HW_GPIO_H + +//************************************************************************************************* +// +// The following are defines for the GPIO register offsets +// +//************************************************************************************************* +#define GPIO_O_GPACTRL 0x0U // GPIO A Qualification Sampling Period Control (GPIO0 to 31) +#define GPIO_O_GPAQSEL1 0x2U // GPIO A Qualifier Select 1 Register (GPIO0 to 15) +#define GPIO_O_GPAQSEL2 0x4U // GPIO A Qualifier Select 2 Register (GPIO16 to 31) +#define GPIO_O_GPAMUX1 0x6U // GPIO A Mux 1 Register (GPIO0 to 15) +#define GPIO_O_GPAMUX2 0x8U // GPIO A Mux 2 Register (GPIO16 to 31) +#define GPIO_O_GPADIR 0xAU // GPIO A Direction Register (GPIO0 to 31) +#define GPIO_O_GPAPUD 0xCU // GPIO A Pull Up Disable Register (GPIO0 to 31) +#define GPIO_O_GPAINV 0x10U // GPIO A Input Polarity Invert Registers (GPIO0 to 31) +#define GPIO_O_GPAODR 0x12U // GPIO A Open Drain Output Register (GPIO0 to GPIO31) +#define GPIO_O_GPAGMUX1 0x20U // GPIO A Peripheral Group Mux (GPIO0 to 15) +#define GPIO_O_GPAGMUX2 0x22U // GPIO A Peripheral Group Mux (GPIO16 to 31) +#define GPIO_O_GPACSEL1 0x28U // GPIO A Core Select Register (GPIO0 to 7) +#define GPIO_O_GPACSEL2 0x2AU // GPIO A Core Select Register (GPIO8 to 15) +#define GPIO_O_GPACSEL3 0x2CU // GPIO A Core Select Register (GPIO16 to 23) +#define GPIO_O_GPACSEL4 0x2EU // GPIO A Core Select Register (GPIO24 to 31) +#define GPIO_O_GPALOCK 0x3CU // GPIO A Lock Configuration Register (GPIO0 to 31) +#define GPIO_O_GPACR 0x3EU // GPIO A Lock Commit Register (GPIO0 to 31) +#define GPIO_O_GPBCTRL 0x40U // GPIO B Qualification Sampling Period Control (GPIO32 to 63) +#define GPIO_O_GPBQSEL1 0x42U // GPIO B Qualifier Select 1 Register (GPIO32 to 47) +#define GPIO_O_GPBQSEL2 0x44U // GPIO B Qualifier Select 2 Register (GPIO48 to 63) +#define GPIO_O_GPBMUX1 0x46U // GPIO B Mux 1 Register (GPIO32 to 47) +#define GPIO_O_GPBMUX2 0x48U // GPIO B Mux 2 Register (GPIO48 to 63) +#define GPIO_O_GPBDIR 0x4AU // GPIO B Direction Register (GPIO32 to 63) +#define GPIO_O_GPBPUD 0x4CU // GPIO B Pull Up Disable Register (GPIO32 to 63) +#define GPIO_O_GPBINV 0x50U // GPIO B Input Polarity Invert Registers (GPIO32 to 63) +#define GPIO_O_GPBODR 0x52U // GPIO B Open Drain Output Register (GPIO32 to GPIO63) +#define GPIO_O_GPBAMSEL 0x54U // GPIO B Analog Mode Select register (GPIO32 to GPIO63) +#define GPIO_O_GPBGMUX1 0x60U // GPIO B Peripheral Group Mux (GPIO32 to 47) +#define GPIO_O_GPBGMUX2 0x62U // GPIO B Peripheral Group Mux (GPIO48 to 63) +#define GPIO_O_GPBCSEL1 0x68U // GPIO B Core Select Register (GPIO32 to 39) +#define GPIO_O_GPBCSEL2 0x6AU // GPIO B Core Select Register (GPIO40 to 47) +#define GPIO_O_GPBCSEL3 0x6CU // GPIO B Core Select Register (GPIO48 to 55) +#define GPIO_O_GPBCSEL4 0x6EU // GPIO B Core Select Register (GPIO56 to 63) +#define GPIO_O_GPBLOCK 0x7CU // GPIO B Lock Configuration Register (GPIO32 to 63) +#define GPIO_O_GPBCR 0x7EU // GPIO B Lock Commit Register (GPIO32 to 63) +#define GPIO_O_GPCCTRL 0x80U // GPIO C Qualification Sampling Period Control (GPIO64 to 95) +#define GPIO_O_GPCQSEL1 0x82U // GPIO C Qualifier Select 1 Register (GPIO64 to 79) +#define GPIO_O_GPCQSEL2 0x84U // GPIO C Qualifier Select 2 Register (GPIO80 to 95) +#define GPIO_O_GPCMUX1 0x86U // GPIO C Mux 1 Register (GPIO64 to 79) +#define GPIO_O_GPCMUX2 0x88U // GPIO C Mux 2 Register (GPIO80 to 95) +#define GPIO_O_GPCDIR 0x8AU // GPIO C Direction Register (GPIO64 to 95) +#define GPIO_O_GPCPUD 0x8CU // GPIO C Pull Up Disable Register (GPIO64 to 95) +#define GPIO_O_GPCINV 0x90U // GPIO C Input Polarity Invert Registers (GPIO64 to 95) +#define GPIO_O_GPCODR 0x92U // GPIO C Open Drain Output Register (GPIO64 to GPIO95) +#define GPIO_O_GPCGMUX1 0xA0U // GPIO C Peripheral Group Mux (GPIO64 to 79) +#define GPIO_O_GPCGMUX2 0xA2U // GPIO C Peripheral Group Mux (GPIO80 to 95) +#define GPIO_O_GPCCSEL1 0xA8U // GPIO C Core Select Register (GPIO64 to 71) +#define GPIO_O_GPCCSEL2 0xAAU // GPIO C Core Select Register (GPIO72 to 79) +#define GPIO_O_GPCCSEL3 0xACU // GPIO C Core Select Register (GPIO80 to 87) +#define GPIO_O_GPCCSEL4 0xAEU // GPIO C Core Select Register (GPIO88 to 95) +#define GPIO_O_GPCLOCK 0xBCU // GPIO C Lock Configuration Register (GPIO64 to 95) +#define GPIO_O_GPCCR 0xBEU // GPIO C Lock Commit Register (GPIO64 to 95) +#define GPIO_O_GPDCTRL 0xC0U // GPIO D Qualification Sampling Period Control (GPIO96 to 127) +#define GPIO_O_GPDQSEL1 0xC2U // GPIO D Qualifier Select 1 Register (GPIO96 to 111) +#define GPIO_O_GPDQSEL2 0xC4U // GPIO D Qualifier Select 2 Register (GPIO112 to 127) +#define GPIO_O_GPDMUX1 0xC6U // GPIO D Mux 1 Register (GPIO96 to 111) +#define GPIO_O_GPDMUX2 0xC8U // GPIO D Mux 2 Register (GPIO112 to 127) +#define GPIO_O_GPDDIR 0xCAU // GPIO D Direction Register (GPIO96 to 127) +#define GPIO_O_GPDPUD 0xCCU // GPIO D Pull Up Disable Register (GPIO96 to 127) +#define GPIO_O_GPDINV 0xD0U // GPIO D Input Polarity Invert Registers (GPIO96 to 127) +#define GPIO_O_GPDODR 0xD2U // GPIO D Open Drain Output Register (GPIO96 to GPIO127) +#define GPIO_O_GPDGMUX1 0xE0U // GPIO D Peripheral Group Mux (GPIO96 to 111) +#define GPIO_O_GPDGMUX2 0xE2U // GPIO D Peripheral Group Mux (GPIO112 to 127) +#define GPIO_O_GPDCSEL1 0xE8U // GPIO D Core Select Register (GPIO96 to 103) +#define GPIO_O_GPDCSEL2 0xEAU // GPIO D Core Select Register (GPIO104 to 111) +#define GPIO_O_GPDCSEL3 0xECU // GPIO D Core Select Register (GPIO112 to 119) +#define GPIO_O_GPDCSEL4 0xEEU // GPIO D Core Select Register (GPIO120 to 127) +#define GPIO_O_GPDLOCK 0xFCU // GPIO D Lock Configuration Register (GPIO96 to 127) +#define GPIO_O_GPDCR 0xFEU // GPIO D Lock Commit Register (GPIO96 to 127) +#define GPIO_O_GPECTRL 0x100U // GPIO E Qualification Sampling Period Control (GPIO128 to 159) +#define GPIO_O_GPEQSEL1 0x102U // GPIO E Qualifier Select 1 Register (GPIO128 to 143) +#define GPIO_O_GPEQSEL2 0x104U // GPIO E Qualifier Select 2 Register (GPIO144 to 159) +#define GPIO_O_GPEMUX1 0x106U // GPIO E Mux 1 Register (GPIO128 to 143) +#define GPIO_O_GPEMUX2 0x108U // GPIO E Mux 2 Register (GPIO144 to 159) +#define GPIO_O_GPEDIR 0x10AU // GPIO E Direction Register (GPIO128 to 159) +#define GPIO_O_GPEPUD 0x10CU // GPIO E Pull Up Disable Register (GPIO128 to 159) +#define GPIO_O_GPEINV 0x110U // GPIO E Input Polarity Invert Registers (GPIO128 to 159) +#define GPIO_O_GPEODR 0x112U // GPIO E Open Drain Output Register (GPIO128 to GPIO159) +#define GPIO_O_GPEGMUX1 0x120U // GPIO E Peripheral Group Mux (GPIO128 to 143) +#define GPIO_O_GPEGMUX2 0x122U // GPIO E Peripheral Group Mux (GPIO144 to 159) +#define GPIO_O_GPECSEL1 0x128U // GPIO E Core Select Register (GPIO128 to 135) +#define GPIO_O_GPECSEL2 0x12AU // GPIO E Core Select Register (GPIO136 to 143) +#define GPIO_O_GPECSEL3 0x12CU // GPIO E Core Select Register (GPIO144 to 151) +#define GPIO_O_GPECSEL4 0x12EU // GPIO E Core Select Register (GPIO152 to 159) +#define GPIO_O_GPELOCK 0x13CU // GPIO E Lock Configuration Register (GPIO128 to 159) +#define GPIO_O_GPECR 0x13EU // GPIO E Lock Commit Register (GPIO128 to 159) +#define GPIO_O_GPFCTRL 0x140U // GPIO F Qualification Sampling Period Control (GPIO160 to 168) +#define GPIO_O_GPFQSEL1 0x142U // GPIO F Qualifier Select 1 Register (GPIO160 to 168) +#define GPIO_O_GPFMUX1 0x146U // GPIO F Mux 1 Register (GPIO160 to 168) +#define GPIO_O_GPFDIR 0x14AU // GPIO F Direction Register (GPIO160 to 168) +#define GPIO_O_GPFPUD 0x14CU // GPIO F Pull Up Disable Register (GPIO160 to 168) +#define GPIO_O_GPFINV 0x150U // GPIO F Input Polarity Invert Registers (GPIO160 to 168) +#define GPIO_O_GPFODR 0x152U // GPIO F Open Drain Output Register (GPIO160 to GPIO168) +#define GPIO_O_GPFGMUX1 0x160U // GPIO F Peripheral Group Mux (GPIO160 to 168) +#define GPIO_O_GPFCSEL1 0x168U // GPIO F Core Select Register (GPIO160 to 167) +#define GPIO_O_GPFCSEL2 0x16AU // GPIO F Core Select Register (GPIO168) +#define GPIO_O_GPFLOCK 0x17CU // GPIO F Lock Configuration Register (GPIO160 to 168) +#define GPIO_O_GPFCR 0x17EU // GPIO F Lock Commit Register (GPIO160 to 168) + +#define GPIO_O_GPADAT 0x0U // GPIO A Data Register (GPIO0 to 31) +#define GPIO_O_GPASET 0x2U // GPIO A Data Set Register (GPIO0 to 31) +#define GPIO_O_GPACLEAR 0x4U // GPIO A Data Clear Register (GPIO0 to 31) +#define GPIO_O_GPATOGGLE 0x6U // GPIO A Data Toggle Register (GPIO0 to 31) +#define GPIO_O_GPBDAT 0x8U // GPIO B Data Register (GPIO32 to 63) +#define GPIO_O_GPBSET 0xAU // GPIO B Data Set Register (GPIO32 to 63) +#define GPIO_O_GPBCLEAR 0xCU // GPIO B Data Clear Register (GPIO32 to 63) +#define GPIO_O_GPBTOGGLE 0xEU // GPIO B Data Toggle Register (GPIO32 to 63) +#define GPIO_O_GPCDAT 0x10U // GPIO C Data Register (GPIO64 to 95) +#define GPIO_O_GPCSET 0x12U // GPIO C Data Set Register (GPIO64 to 95) +#define GPIO_O_GPCCLEAR 0x14U // GPIO C Data Clear Register (GPIO64 to 95) +#define GPIO_O_GPCTOGGLE 0x16U // GPIO C Data Toggle Register (GPIO64 to 95) +#define GPIO_O_GPDDAT 0x18U // GPIO D Data Register (GPIO96 to 127) +#define GPIO_O_GPDSET 0x1AU // GPIO D Data Set Register (GPIO96 to 127) +#define GPIO_O_GPDCLEAR 0x1CU // GPIO D Data Clear Register (GPIO96 to 127) +#define GPIO_O_GPDTOGGLE 0x1EU // GPIO D Data Toggle Register (GPIO96 to 127) +#define GPIO_O_GPEDAT 0x20U // GPIO E Data Register (GPIO128 to 159) +#define GPIO_O_GPESET 0x22U // GPIO E Data Set Register (GPIO128 to 159) +#define GPIO_O_GPECLEAR 0x24U // GPIO E Data Clear Register (GPIO128 to 159) +#define GPIO_O_GPETOGGLE 0x26U // GPIO E Data Toggle Register (GPIO128 to 159) +#define GPIO_O_GPFDAT 0x28U // GPIO F Data Register (GPIO160 to 168) +#define GPIO_O_GPFSET 0x2AU // GPIO F Data Set Register (GPIO160 to 168) +#define GPIO_O_GPFCLEAR 0x2CU // GPIO F Data Clear Register (GPIO160 to 168) +#define GPIO_O_GPFTOGGLE 0x2EU // GPIO F Data Toggle Register (GPIO160 to 168) + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACTRL register +// +//************************************************************************************************* +#define GPIO_GPACTRL_QUALPRD0_S 0U +#define GPIO_GPACTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO0 to GPIO7 +#define GPIO_GPACTRL_QUALPRD1_S 8U +#define GPIO_GPACTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO8 to + // GPIO15 +#define GPIO_GPACTRL_QUALPRD2_S 16U +#define GPIO_GPACTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO16 to + // GPIO23 +#define GPIO_GPACTRL_QUALPRD3_S 24U +#define GPIO_GPACTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO24 to + // GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL1_GPIO0_S 0U +#define GPIO_GPAQSEL1_GPIO0_M 0x3U // Select input qualification type for GPIO0 +#define GPIO_GPAQSEL1_GPIO1_S 2U +#define GPIO_GPAQSEL1_GPIO1_M 0xCU // Select input qualification type for GPIO1 +#define GPIO_GPAQSEL1_GPIO2_S 4U +#define GPIO_GPAQSEL1_GPIO2_M 0x30U // Select input qualification type for GPIO2 +#define GPIO_GPAQSEL1_GPIO3_S 6U +#define GPIO_GPAQSEL1_GPIO3_M 0xC0U // Select input qualification type for GPIO3 +#define GPIO_GPAQSEL1_GPIO4_S 8U +#define GPIO_GPAQSEL1_GPIO4_M 0x300U // Select input qualification type for GPIO4 +#define GPIO_GPAQSEL1_GPIO5_S 10U +#define GPIO_GPAQSEL1_GPIO5_M 0xC00U // Select input qualification type for GPIO5 +#define GPIO_GPAQSEL1_GPIO6_S 12U +#define GPIO_GPAQSEL1_GPIO6_M 0x3000U // Select input qualification type for GPIO6 +#define GPIO_GPAQSEL1_GPIO7_S 14U +#define GPIO_GPAQSEL1_GPIO7_M 0xC000U // Select input qualification type for GPIO7 +#define GPIO_GPAQSEL1_GPIO8_S 16U +#define GPIO_GPAQSEL1_GPIO8_M 0x30000U // Select input qualification type for GPIO8 +#define GPIO_GPAQSEL1_GPIO9_S 18U +#define GPIO_GPAQSEL1_GPIO9_M 0xC0000U // Select input qualification type for GPIO9 +#define GPIO_GPAQSEL1_GPIO10_S 20U +#define GPIO_GPAQSEL1_GPIO10_M 0x300000U // Select input qualification type for GPIO10 +#define GPIO_GPAQSEL1_GPIO11_S 22U +#define GPIO_GPAQSEL1_GPIO11_M 0xC00000U // Select input qualification type for GPIO11 +#define GPIO_GPAQSEL1_GPIO12_S 24U +#define GPIO_GPAQSEL1_GPIO12_M 0x3000000U // Select input qualification type for GPIO12 +#define GPIO_GPAQSEL1_GPIO13_S 26U +#define GPIO_GPAQSEL1_GPIO13_M 0xC000000U // Select input qualification type for GPIO13 +#define GPIO_GPAQSEL1_GPIO14_S 28U +#define GPIO_GPAQSEL1_GPIO14_M 0x30000000U // Select input qualification type for GPIO14 +#define GPIO_GPAQSEL1_GPIO15_S 30U +#define GPIO_GPAQSEL1_GPIO15_M 0xC0000000U // Select input qualification type for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPAQSEL2_GPIO16_S 0U +#define GPIO_GPAQSEL2_GPIO16_M 0x3U // Select input qualification type for GPIO16 +#define GPIO_GPAQSEL2_GPIO17_S 2U +#define GPIO_GPAQSEL2_GPIO17_M 0xCU // Select input qualification type for GPIO17 +#define GPIO_GPAQSEL2_GPIO18_S 4U +#define GPIO_GPAQSEL2_GPIO18_M 0x30U // Select input qualification type for GPIO18 +#define GPIO_GPAQSEL2_GPIO19_S 6U +#define GPIO_GPAQSEL2_GPIO19_M 0xC0U // Select input qualification type for GPIO19 +#define GPIO_GPAQSEL2_GPIO20_S 8U +#define GPIO_GPAQSEL2_GPIO20_M 0x300U // Select input qualification type for GPIO20 +#define GPIO_GPAQSEL2_GPIO21_S 10U +#define GPIO_GPAQSEL2_GPIO21_M 0xC00U // Select input qualification type for GPIO21 +#define GPIO_GPAQSEL2_GPIO22_S 12U +#define GPIO_GPAQSEL2_GPIO22_M 0x3000U // Select input qualification type for GPIO22 +#define GPIO_GPAQSEL2_GPIO23_S 14U +#define GPIO_GPAQSEL2_GPIO23_M 0xC000U // Select input qualification type for GPIO23 +#define GPIO_GPAQSEL2_GPIO24_S 16U +#define GPIO_GPAQSEL2_GPIO24_M 0x30000U // Select input qualification type for GPIO24 +#define GPIO_GPAQSEL2_GPIO25_S 18U +#define GPIO_GPAQSEL2_GPIO25_M 0xC0000U // Select input qualification type for GPIO25 +#define GPIO_GPAQSEL2_GPIO26_S 20U +#define GPIO_GPAQSEL2_GPIO26_M 0x300000U // Select input qualification type for GPIO26 +#define GPIO_GPAQSEL2_GPIO27_S 22U +#define GPIO_GPAQSEL2_GPIO27_M 0xC00000U // Select input qualification type for GPIO27 +#define GPIO_GPAQSEL2_GPIO28_S 24U +#define GPIO_GPAQSEL2_GPIO28_M 0x3000000U // Select input qualification type for GPIO28 +#define GPIO_GPAQSEL2_GPIO29_S 26U +#define GPIO_GPAQSEL2_GPIO29_M 0xC000000U // Select input qualification type for GPIO29 +#define GPIO_GPAQSEL2_GPIO30_S 28U +#define GPIO_GPAQSEL2_GPIO30_M 0x30000000U // Select input qualification type for GPIO30 +#define GPIO_GPAQSEL2_GPIO31_S 30U +#define GPIO_GPAQSEL2_GPIO31_M 0xC0000000U // Select input qualification type for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAMUX1_GPIO0_S 0U +#define GPIO_GPAMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAMUX1_GPIO1_S 2U +#define GPIO_GPAMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAMUX1_GPIO2_S 4U +#define GPIO_GPAMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAMUX1_GPIO3_S 6U +#define GPIO_GPAMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAMUX1_GPIO4_S 8U +#define GPIO_GPAMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAMUX1_GPIO5_S 10U +#define GPIO_GPAMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAMUX1_GPIO6_S 12U +#define GPIO_GPAMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAMUX1_GPIO7_S 14U +#define GPIO_GPAMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAMUX1_GPIO8_S 16U +#define GPIO_GPAMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAMUX1_GPIO9_S 18U +#define GPIO_GPAMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAMUX1_GPIO10_S 20U +#define GPIO_GPAMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAMUX1_GPIO11_S 22U +#define GPIO_GPAMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAMUX1_GPIO12_S 24U +#define GPIO_GPAMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAMUX1_GPIO13_S 26U +#define GPIO_GPAMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAMUX1_GPIO14_S 28U +#define GPIO_GPAMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAMUX1_GPIO15_S 30U +#define GPIO_GPAMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAMUX2_GPIO16_S 0U +#define GPIO_GPAMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAMUX2_GPIO17_S 2U +#define GPIO_GPAMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAMUX2_GPIO18_S 4U +#define GPIO_GPAMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAMUX2_GPIO19_S 6U +#define GPIO_GPAMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAMUX2_GPIO20_S 8U +#define GPIO_GPAMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAMUX2_GPIO21_S 10U +#define GPIO_GPAMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAMUX2_GPIO22_S 12U +#define GPIO_GPAMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAMUX2_GPIO23_S 14U +#define GPIO_GPAMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAMUX2_GPIO24_S 16U +#define GPIO_GPAMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAMUX2_GPIO25_S 18U +#define GPIO_GPAMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAMUX2_GPIO26_S 20U +#define GPIO_GPAMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAMUX2_GPIO27_S 22U +#define GPIO_GPAMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAMUX2_GPIO28_S 24U +#define GPIO_GPAMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAMUX2_GPIO29_S 26U +#define GPIO_GPAMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAMUX2_GPIO30_S 28U +#define GPIO_GPAMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAMUX2_GPIO31_S 30U +#define GPIO_GPAMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADIR register +// +//************************************************************************************************* +#define GPIO_GPADIR_GPIO0 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO1 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO2 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO3 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO4 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO5 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO6 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO7 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO8 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO9 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO10 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO11 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO12 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO13 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO14 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO15 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO16 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO17 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO18 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO19 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO20 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO21 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO22 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO23 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO24 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO25 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO26 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO27 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO28 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO29 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO30 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPADIR_GPIO31 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAPUD register +// +//************************************************************************************************* +#define GPIO_GPAPUD_GPIO0 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO1 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO2 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO3 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO4 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO5 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO6 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO7 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO8 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO9 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO10 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO11 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO12 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO13 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO14 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO15 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO16 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO17 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO18 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO19 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO20 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO21 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO22 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO23 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO24 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO25 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO26 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO27 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO28 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO29 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO30 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPAPUD_GPIO31 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAINV register +// +//************************************************************************************************* +#define GPIO_GPAINV_GPIO0 0x1U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO1 0x2U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO2 0x4U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO3 0x8U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO4 0x10U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO5 0x20U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO6 0x40U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO7 0x80U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO8 0x100U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO9 0x200U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO10 0x400U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO11 0x800U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO12 0x1000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO13 0x2000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO14 0x4000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO15 0x8000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO16 0x10000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO17 0x20000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO18 0x40000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO19 0x80000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO20 0x100000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO21 0x200000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO22 0x400000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO23 0x800000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO24 0x1000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO25 0x2000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO26 0x4000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO27 0x8000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO28 0x10000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO29 0x20000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO30 0x40000000U // Input inversion control for this pin +#define GPIO_GPAINV_GPIO31 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAODR register +// +//************************************************************************************************* +#define GPIO_GPAODR_GPIO0 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO1 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO2 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO3 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO4 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO5 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO6 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO7 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO8 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO9 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO10 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO11 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO12 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO13 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO14 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO15 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO16 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO17 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO18 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO19 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO20 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO21 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO22 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO23 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO24 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO25 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO26 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO27 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO28 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO29 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO30 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPAODR_GPIO31 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX1_GPIO0_S 0U +#define GPIO_GPAGMUX1_GPIO0_M 0x3U // Defines pin-muxing selection for GPIO0 +#define GPIO_GPAGMUX1_GPIO1_S 2U +#define GPIO_GPAGMUX1_GPIO1_M 0xCU // Defines pin-muxing selection for GPIO1 +#define GPIO_GPAGMUX1_GPIO2_S 4U +#define GPIO_GPAGMUX1_GPIO2_M 0x30U // Defines pin-muxing selection for GPIO2 +#define GPIO_GPAGMUX1_GPIO3_S 6U +#define GPIO_GPAGMUX1_GPIO3_M 0xC0U // Defines pin-muxing selection for GPIO3 +#define GPIO_GPAGMUX1_GPIO4_S 8U +#define GPIO_GPAGMUX1_GPIO4_M 0x300U // Defines pin-muxing selection for GPIO4 +#define GPIO_GPAGMUX1_GPIO5_S 10U +#define GPIO_GPAGMUX1_GPIO5_M 0xC00U // Defines pin-muxing selection for GPIO5 +#define GPIO_GPAGMUX1_GPIO6_S 12U +#define GPIO_GPAGMUX1_GPIO6_M 0x3000U // Defines pin-muxing selection for GPIO6 +#define GPIO_GPAGMUX1_GPIO7_S 14U +#define GPIO_GPAGMUX1_GPIO7_M 0xC000U // Defines pin-muxing selection for GPIO7 +#define GPIO_GPAGMUX1_GPIO8_S 16U +#define GPIO_GPAGMUX1_GPIO8_M 0x30000U // Defines pin-muxing selection for GPIO8 +#define GPIO_GPAGMUX1_GPIO9_S 18U +#define GPIO_GPAGMUX1_GPIO9_M 0xC0000U // Defines pin-muxing selection for GPIO9 +#define GPIO_GPAGMUX1_GPIO10_S 20U +#define GPIO_GPAGMUX1_GPIO10_M 0x300000U // Defines pin-muxing selection for GPIO10 +#define GPIO_GPAGMUX1_GPIO11_S 22U +#define GPIO_GPAGMUX1_GPIO11_M 0xC00000U // Defines pin-muxing selection for GPIO11 +#define GPIO_GPAGMUX1_GPIO12_S 24U +#define GPIO_GPAGMUX1_GPIO12_M 0x3000000U // Defines pin-muxing selection for GPIO12 +#define GPIO_GPAGMUX1_GPIO13_S 26U +#define GPIO_GPAGMUX1_GPIO13_M 0xC000000U // Defines pin-muxing selection for GPIO13 +#define GPIO_GPAGMUX1_GPIO14_S 28U +#define GPIO_GPAGMUX1_GPIO14_M 0x30000000U // Defines pin-muxing selection for GPIO14 +#define GPIO_GPAGMUX1_GPIO15_S 30U +#define GPIO_GPAGMUX1_GPIO15_M 0xC0000000U // Defines pin-muxing selection for GPIO15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPAGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPAGMUX2_GPIO16_S 0U +#define GPIO_GPAGMUX2_GPIO16_M 0x3U // Defines pin-muxing selection for GPIO16 +#define GPIO_GPAGMUX2_GPIO17_S 2U +#define GPIO_GPAGMUX2_GPIO17_M 0xCU // Defines pin-muxing selection for GPIO17 +#define GPIO_GPAGMUX2_GPIO18_S 4U +#define GPIO_GPAGMUX2_GPIO18_M 0x30U // Defines pin-muxing selection for GPIO18 +#define GPIO_GPAGMUX2_GPIO19_S 6U +#define GPIO_GPAGMUX2_GPIO19_M 0xC0U // Defines pin-muxing selection for GPIO19 +#define GPIO_GPAGMUX2_GPIO20_S 8U +#define GPIO_GPAGMUX2_GPIO20_M 0x300U // Defines pin-muxing selection for GPIO20 +#define GPIO_GPAGMUX2_GPIO21_S 10U +#define GPIO_GPAGMUX2_GPIO21_M 0xC00U // Defines pin-muxing selection for GPIO21 +#define GPIO_GPAGMUX2_GPIO22_S 12U +#define GPIO_GPAGMUX2_GPIO22_M 0x3000U // Defines pin-muxing selection for GPIO22 +#define GPIO_GPAGMUX2_GPIO23_S 14U +#define GPIO_GPAGMUX2_GPIO23_M 0xC000U // Defines pin-muxing selection for GPIO23 +#define GPIO_GPAGMUX2_GPIO24_S 16U +#define GPIO_GPAGMUX2_GPIO24_M 0x30000U // Defines pin-muxing selection for GPIO24 +#define GPIO_GPAGMUX2_GPIO25_S 18U +#define GPIO_GPAGMUX2_GPIO25_M 0xC0000U // Defines pin-muxing selection for GPIO25 +#define GPIO_GPAGMUX2_GPIO26_S 20U +#define GPIO_GPAGMUX2_GPIO26_M 0x300000U // Defines pin-muxing selection for GPIO26 +#define GPIO_GPAGMUX2_GPIO27_S 22U +#define GPIO_GPAGMUX2_GPIO27_M 0xC00000U // Defines pin-muxing selection for GPIO27 +#define GPIO_GPAGMUX2_GPIO28_S 24U +#define GPIO_GPAGMUX2_GPIO28_M 0x3000000U // Defines pin-muxing selection for GPIO28 +#define GPIO_GPAGMUX2_GPIO29_S 26U +#define GPIO_GPAGMUX2_GPIO29_M 0xC000000U // Defines pin-muxing selection for GPIO29 +#define GPIO_GPAGMUX2_GPIO30_S 28U +#define GPIO_GPAGMUX2_GPIO30_M 0x30000000U // Defines pin-muxing selection for GPIO30 +#define GPIO_GPAGMUX2_GPIO31_S 30U +#define GPIO_GPAGMUX2_GPIO31_M 0xC0000000U // Defines pin-muxing selection for GPIO31 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL1 register +// +//************************************************************************************************* +#define GPIO_GPACSEL1_GPIO0_S 0U +#define GPIO_GPACSEL1_GPIO0_M 0xFU // GPIO0 Master CPU Select +#define GPIO_GPACSEL1_GPIO1_S 4U +#define GPIO_GPACSEL1_GPIO1_M 0xF0U // GPIO1 Master CPU Select +#define GPIO_GPACSEL1_GPIO2_S 8U +#define GPIO_GPACSEL1_GPIO2_M 0xF00U // GPIO2 Master CPU Select +#define GPIO_GPACSEL1_GPIO3_S 12U +#define GPIO_GPACSEL1_GPIO3_M 0xF000U // GPIO3 Master CPU Select +#define GPIO_GPACSEL1_GPIO4_S 16U +#define GPIO_GPACSEL1_GPIO4_M 0xF0000U // GPIO4 Master CPU Select +#define GPIO_GPACSEL1_GPIO5_S 20U +#define GPIO_GPACSEL1_GPIO5_M 0xF00000U // GPIO5 Master CPU Select +#define GPIO_GPACSEL1_GPIO6_S 24U +#define GPIO_GPACSEL1_GPIO6_M 0xF000000U // GPIO6 Master CPU Select +#define GPIO_GPACSEL1_GPIO7_S 28U +#define GPIO_GPACSEL1_GPIO7_M 0xF0000000U // GPIO7 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL2 register +// +//************************************************************************************************* +#define GPIO_GPACSEL2_GPIO8_S 0U +#define GPIO_GPACSEL2_GPIO8_M 0xFU // GPIO8 Master CPU Select +#define GPIO_GPACSEL2_GPIO9_S 4U +#define GPIO_GPACSEL2_GPIO9_M 0xF0U // GPIO9 Master CPU Select +#define GPIO_GPACSEL2_GPIO10_S 8U +#define GPIO_GPACSEL2_GPIO10_M 0xF00U // GPIO10 Master CPU Select +#define GPIO_GPACSEL2_GPIO11_S 12U +#define GPIO_GPACSEL2_GPIO11_M 0xF000U // GPIO11 Master CPU Select +#define GPIO_GPACSEL2_GPIO12_S 16U +#define GPIO_GPACSEL2_GPIO12_M 0xF0000U // GPIO12 Master CPU Select +#define GPIO_GPACSEL2_GPIO13_S 20U +#define GPIO_GPACSEL2_GPIO13_M 0xF00000U // GPIO13 Master CPU Select +#define GPIO_GPACSEL2_GPIO14_S 24U +#define GPIO_GPACSEL2_GPIO14_M 0xF000000U // GPIO14 Master CPU Select +#define GPIO_GPACSEL2_GPIO15_S 28U +#define GPIO_GPACSEL2_GPIO15_M 0xF0000000U // GPIO15 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL3 register +// +//************************************************************************************************* +#define GPIO_GPACSEL3_GPIO16_S 0U +#define GPIO_GPACSEL3_GPIO16_M 0xFU // GPIO16 Master CPU Select +#define GPIO_GPACSEL3_GPIO17_S 4U +#define GPIO_GPACSEL3_GPIO17_M 0xF0U // GPIO17 Master CPU Select +#define GPIO_GPACSEL3_GPIO18_S 8U +#define GPIO_GPACSEL3_GPIO18_M 0xF00U // GPIO18 Master CPU Select +#define GPIO_GPACSEL3_GPIO19_S 12U +#define GPIO_GPACSEL3_GPIO19_M 0xF000U // GPIO19 Master CPU Select +#define GPIO_GPACSEL3_GPIO20_S 16U +#define GPIO_GPACSEL3_GPIO20_M 0xF0000U // GPIO20 Master CPU Select +#define GPIO_GPACSEL3_GPIO21_S 20U +#define GPIO_GPACSEL3_GPIO21_M 0xF00000U // GPIO21 Master CPU Select +#define GPIO_GPACSEL3_GPIO22_S 24U +#define GPIO_GPACSEL3_GPIO22_M 0xF000000U // GPIO22 Master CPU Select +#define GPIO_GPACSEL3_GPIO23_S 28U +#define GPIO_GPACSEL3_GPIO23_M 0xF0000000U // GPIO23 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACSEL4 register +// +//************************************************************************************************* +#define GPIO_GPACSEL4_GPIO24_S 0U +#define GPIO_GPACSEL4_GPIO24_M 0xFU // GPIO24 Master CPU Select +#define GPIO_GPACSEL4_GPIO25_S 4U +#define GPIO_GPACSEL4_GPIO25_M 0xF0U // GPIO25 Master CPU Select +#define GPIO_GPACSEL4_GPIO26_S 8U +#define GPIO_GPACSEL4_GPIO26_M 0xF00U // GPIO26 Master CPU Select +#define GPIO_GPACSEL4_GPIO27_S 12U +#define GPIO_GPACSEL4_GPIO27_M 0xF000U // GPIO27 Master CPU Select +#define GPIO_GPACSEL4_GPIO28_S 16U +#define GPIO_GPACSEL4_GPIO28_M 0xF0000U // GPIO28 Master CPU Select +#define GPIO_GPACSEL4_GPIO29_S 20U +#define GPIO_GPACSEL4_GPIO29_M 0xF00000U // GPIO29 Master CPU Select +#define GPIO_GPACSEL4_GPIO30_S 24U +#define GPIO_GPACSEL4_GPIO30_M 0xF000000U // GPIO30 Master CPU Select +#define GPIO_GPACSEL4_GPIO31_S 28U +#define GPIO_GPACSEL4_GPIO31_M 0xF0000000U // GPIO31 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPALOCK register +// +//************************************************************************************************* +#define GPIO_GPALOCK_GPIO0 0x1U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO1 0x2U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO2 0x4U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO3 0x8U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO4 0x10U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO5 0x20U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO6 0x40U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO7 0x80U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO8 0x100U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO9 0x200U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO10 0x400U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO11 0x800U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO12 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO13 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO14 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO15 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO16 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO17 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO18 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO19 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO20 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO21 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO22 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO23 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO24 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO25 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO26 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO27 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO28 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO29 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO30 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPALOCK_GPIO31 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACR register +// +//************************************************************************************************* +#define GPIO_GPACR_GPIO0 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO1 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO2 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO3 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO4 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO5 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO6 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO7 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO8 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO9 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO10 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO11 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO12 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO13 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO14 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO15 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO16 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO17 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO18 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO19 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO20 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO21 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO22 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO23 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO24 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO25 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO26 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO27 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO28 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO29 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO30 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPACR_GPIO31 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCTRL register +// +//************************************************************************************************* +#define GPIO_GPBCTRL_QUALPRD0_S 0U +#define GPIO_GPBCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO32 to + // GPIO39 +#define GPIO_GPBCTRL_QUALPRD1_S 8U +#define GPIO_GPBCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO40 to + // GPIO47 +#define GPIO_GPBCTRL_QUALPRD2_S 16U +#define GPIO_GPBCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO48 to + // GPIO55 +#define GPIO_GPBCTRL_QUALPRD3_S 24U +#define GPIO_GPBCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO56 to + // GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL1_GPIO32_S 0U +#define GPIO_GPBQSEL1_GPIO32_M 0x3U // Select input qualification type for GPIO32 +#define GPIO_GPBQSEL1_GPIO33_S 2U +#define GPIO_GPBQSEL1_GPIO33_M 0xCU // Select input qualification type for GPIO33 +#define GPIO_GPBQSEL1_GPIO34_S 4U +#define GPIO_GPBQSEL1_GPIO34_M 0x30U // Select input qualification type for GPIO34 +#define GPIO_GPBQSEL1_GPIO35_S 6U +#define GPIO_GPBQSEL1_GPIO35_M 0xC0U // Select input qualification type for GPIO35 +#define GPIO_GPBQSEL1_GPIO36_S 8U +#define GPIO_GPBQSEL1_GPIO36_M 0x300U // Select input qualification type for GPIO36 +#define GPIO_GPBQSEL1_GPIO37_S 10U +#define GPIO_GPBQSEL1_GPIO37_M 0xC00U // Select input qualification type for GPIO37 +#define GPIO_GPBQSEL1_GPIO38_S 12U +#define GPIO_GPBQSEL1_GPIO38_M 0x3000U // Select input qualification type for GPIO38 +#define GPIO_GPBQSEL1_GPIO39_S 14U +#define GPIO_GPBQSEL1_GPIO39_M 0xC000U // Select input qualification type for GPIO39 +#define GPIO_GPBQSEL1_GPIO40_S 16U +#define GPIO_GPBQSEL1_GPIO40_M 0x30000U // Select input qualification type for GPIO40 +#define GPIO_GPBQSEL1_GPIO41_S 18U +#define GPIO_GPBQSEL1_GPIO41_M 0xC0000U // Select input qualification type for GPIO41 +#define GPIO_GPBQSEL1_GPIO42_S 20U +#define GPIO_GPBQSEL1_GPIO42_M 0x300000U // Select input qualification type for GPIO42 +#define GPIO_GPBQSEL1_GPIO43_S 22U +#define GPIO_GPBQSEL1_GPIO43_M 0xC00000U // Select input qualification type for GPIO43 +#define GPIO_GPBQSEL1_GPIO44_S 24U +#define GPIO_GPBQSEL1_GPIO44_M 0x3000000U // Select input qualification type for GPIO44 +#define GPIO_GPBQSEL1_GPIO45_S 26U +#define GPIO_GPBQSEL1_GPIO45_M 0xC000000U // Select input qualification type for GPIO45 +#define GPIO_GPBQSEL1_GPIO46_S 28U +#define GPIO_GPBQSEL1_GPIO46_M 0x30000000U // Select input qualification type for GPIO46 +#define GPIO_GPBQSEL1_GPIO47_S 30U +#define GPIO_GPBQSEL1_GPIO47_M 0xC0000000U // Select input qualification type for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBQSEL2_GPIO48_S 0U +#define GPIO_GPBQSEL2_GPIO48_M 0x3U // Select input qualification type for GPIO48 +#define GPIO_GPBQSEL2_GPIO49_S 2U +#define GPIO_GPBQSEL2_GPIO49_M 0xCU // Select input qualification type for GPIO49 +#define GPIO_GPBQSEL2_GPIO50_S 4U +#define GPIO_GPBQSEL2_GPIO50_M 0x30U // Select input qualification type for GPIO50 +#define GPIO_GPBQSEL2_GPIO51_S 6U +#define GPIO_GPBQSEL2_GPIO51_M 0xC0U // Select input qualification type for GPIO51 +#define GPIO_GPBQSEL2_GPIO52_S 8U +#define GPIO_GPBQSEL2_GPIO52_M 0x300U // Select input qualification type for GPIO52 +#define GPIO_GPBQSEL2_GPIO53_S 10U +#define GPIO_GPBQSEL2_GPIO53_M 0xC00U // Select input qualification type for GPIO53 +#define GPIO_GPBQSEL2_GPIO54_S 12U +#define GPIO_GPBQSEL2_GPIO54_M 0x3000U // Select input qualification type for GPIO54 +#define GPIO_GPBQSEL2_GPIO55_S 14U +#define GPIO_GPBQSEL2_GPIO55_M 0xC000U // Select input qualification type for GPIO55 +#define GPIO_GPBQSEL2_GPIO56_S 16U +#define GPIO_GPBQSEL2_GPIO56_M 0x30000U // Select input qualification type for GPIO56 +#define GPIO_GPBQSEL2_GPIO57_S 18U +#define GPIO_GPBQSEL2_GPIO57_M 0xC0000U // Select input qualification type for GPIO57 +#define GPIO_GPBQSEL2_GPIO58_S 20U +#define GPIO_GPBQSEL2_GPIO58_M 0x300000U // Select input qualification type for GPIO58 +#define GPIO_GPBQSEL2_GPIO59_S 22U +#define GPIO_GPBQSEL2_GPIO59_M 0xC00000U // Select input qualification type for GPIO59 +#define GPIO_GPBQSEL2_GPIO60_S 24U +#define GPIO_GPBQSEL2_GPIO60_M 0x3000000U // Select input qualification type for GPIO60 +#define GPIO_GPBQSEL2_GPIO61_S 26U +#define GPIO_GPBQSEL2_GPIO61_M 0xC000000U // Select input qualification type for GPIO61 +#define GPIO_GPBQSEL2_GPIO62_S 28U +#define GPIO_GPBQSEL2_GPIO62_M 0x30000000U // Select input qualification type for GPIO62 +#define GPIO_GPBQSEL2_GPIO63_S 30U +#define GPIO_GPBQSEL2_GPIO63_M 0xC0000000U // Select input qualification type for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBMUX1_GPIO32_S 0U +#define GPIO_GPBMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBMUX1_GPIO33_S 2U +#define GPIO_GPBMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBMUX1_GPIO34_S 4U +#define GPIO_GPBMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBMUX1_GPIO35_S 6U +#define GPIO_GPBMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBMUX1_GPIO36_S 8U +#define GPIO_GPBMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBMUX1_GPIO37_S 10U +#define GPIO_GPBMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBMUX1_GPIO38_S 12U +#define GPIO_GPBMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBMUX1_GPIO39_S 14U +#define GPIO_GPBMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBMUX1_GPIO40_S 16U +#define GPIO_GPBMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBMUX1_GPIO41_S 18U +#define GPIO_GPBMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBMUX1_GPIO42_S 20U +#define GPIO_GPBMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBMUX1_GPIO43_S 22U +#define GPIO_GPBMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBMUX1_GPIO44_S 24U +#define GPIO_GPBMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBMUX1_GPIO45_S 26U +#define GPIO_GPBMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBMUX1_GPIO46_S 28U +#define GPIO_GPBMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBMUX1_GPIO47_S 30U +#define GPIO_GPBMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBMUX2_GPIO48_S 0U +#define GPIO_GPBMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBMUX2_GPIO49_S 2U +#define GPIO_GPBMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBMUX2_GPIO50_S 4U +#define GPIO_GPBMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBMUX2_GPIO51_S 6U +#define GPIO_GPBMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBMUX2_GPIO52_S 8U +#define GPIO_GPBMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBMUX2_GPIO53_S 10U +#define GPIO_GPBMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBMUX2_GPIO54_S 12U +#define GPIO_GPBMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBMUX2_GPIO55_S 14U +#define GPIO_GPBMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBMUX2_GPIO56_S 16U +#define GPIO_GPBMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBMUX2_GPIO57_S 18U +#define GPIO_GPBMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBMUX2_GPIO58_S 20U +#define GPIO_GPBMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBMUX2_GPIO59_S 22U +#define GPIO_GPBMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBMUX2_GPIO60_S 24U +#define GPIO_GPBMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBMUX2_GPIO61_S 26U +#define GPIO_GPBMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBMUX2_GPIO62_S 28U +#define GPIO_GPBMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBMUX2_GPIO63_S 30U +#define GPIO_GPBMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDIR register +// +//************************************************************************************************* +#define GPIO_GPBDIR_GPIO32 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO33 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO34 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO35 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO36 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO37 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO38 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO39 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO40 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO41 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO42 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO43 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO44 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO45 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO46 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO47 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO48 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO49 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO50 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO51 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO52 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO53 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO54 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO55 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO56 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO57 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO58 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO59 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO60 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO61 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO62 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPBDIR_GPIO63 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBPUD register +// +//************************************************************************************************* +#define GPIO_GPBPUD_GPIO32 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO33 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO34 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO35 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO36 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO37 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO38 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO39 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO40 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO41 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO42 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO43 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO44 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO45 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO46 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO47 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO48 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO49 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO50 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO51 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO52 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO53 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO54 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO55 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO56 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO57 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO58 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO59 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO60 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO61 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO62 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPBPUD_GPIO63 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBINV register +// +//************************************************************************************************* +#define GPIO_GPBINV_GPIO32 0x1U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO33 0x2U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO34 0x4U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO35 0x8U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO36 0x10U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO37 0x20U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO38 0x40U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO39 0x80U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO40 0x100U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO41 0x200U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO42 0x400U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO43 0x800U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO44 0x1000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO45 0x2000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO46 0x4000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO47 0x8000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO48 0x10000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO49 0x20000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO50 0x40000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO51 0x80000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO52 0x100000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO53 0x200000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO54 0x400000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO55 0x800000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO56 0x1000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO57 0x2000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO58 0x4000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO59 0x8000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO60 0x10000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO61 0x20000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO62 0x40000000U // Input inversion control for this pin +#define GPIO_GPBINV_GPIO63 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBODR register +// +//************************************************************************************************* +#define GPIO_GPBODR_GPIO32 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO33 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO34 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO35 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO36 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO37 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO38 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO39 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO40 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO41 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO42 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO43 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO44 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO45 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO46 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO47 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO48 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO49 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO50 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO51 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO52 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO53 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO54 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO55 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO56 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO57 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO58 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO59 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO60 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO61 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO62 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPBODR_GPIO63 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBAMSEL register +// +//************************************************************************************************* +#define GPIO_GPBAMSEL_GPIO42 0x400U // Analog Mode select for this pin +#define GPIO_GPBAMSEL_GPIO43 0x800U // Analog Mode select for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX1_GPIO32_S 0U +#define GPIO_GPBGMUX1_GPIO32_M 0x3U // Defines pin-muxing selection for GPIO32 +#define GPIO_GPBGMUX1_GPIO33_S 2U +#define GPIO_GPBGMUX1_GPIO33_M 0xCU // Defines pin-muxing selection for GPIO33 +#define GPIO_GPBGMUX1_GPIO34_S 4U +#define GPIO_GPBGMUX1_GPIO34_M 0x30U // Defines pin-muxing selection for GPIO34 +#define GPIO_GPBGMUX1_GPIO35_S 6U +#define GPIO_GPBGMUX1_GPIO35_M 0xC0U // Defines pin-muxing selection for GPIO35 +#define GPIO_GPBGMUX1_GPIO36_S 8U +#define GPIO_GPBGMUX1_GPIO36_M 0x300U // Defines pin-muxing selection for GPIO36 +#define GPIO_GPBGMUX1_GPIO37_S 10U +#define GPIO_GPBGMUX1_GPIO37_M 0xC00U // Defines pin-muxing selection for GPIO37 +#define GPIO_GPBGMUX1_GPIO38_S 12U +#define GPIO_GPBGMUX1_GPIO38_M 0x3000U // Defines pin-muxing selection for GPIO38 +#define GPIO_GPBGMUX1_GPIO39_S 14U +#define GPIO_GPBGMUX1_GPIO39_M 0xC000U // Defines pin-muxing selection for GPIO39 +#define GPIO_GPBGMUX1_GPIO40_S 16U +#define GPIO_GPBGMUX1_GPIO40_M 0x30000U // Defines pin-muxing selection for GPIO40 +#define GPIO_GPBGMUX1_GPIO41_S 18U +#define GPIO_GPBGMUX1_GPIO41_M 0xC0000U // Defines pin-muxing selection for GPIO41 +#define GPIO_GPBGMUX1_GPIO42_S 20U +#define GPIO_GPBGMUX1_GPIO42_M 0x300000U // Defines pin-muxing selection for GPIO42 +#define GPIO_GPBGMUX1_GPIO43_S 22U +#define GPIO_GPBGMUX1_GPIO43_M 0xC00000U // Defines pin-muxing selection for GPIO43 +#define GPIO_GPBGMUX1_GPIO44_S 24U +#define GPIO_GPBGMUX1_GPIO44_M 0x3000000U // Defines pin-muxing selection for GPIO44 +#define GPIO_GPBGMUX1_GPIO45_S 26U +#define GPIO_GPBGMUX1_GPIO45_M 0xC000000U // Defines pin-muxing selection for GPIO45 +#define GPIO_GPBGMUX1_GPIO46_S 28U +#define GPIO_GPBGMUX1_GPIO46_M 0x30000000U // Defines pin-muxing selection for GPIO46 +#define GPIO_GPBGMUX1_GPIO47_S 30U +#define GPIO_GPBGMUX1_GPIO47_M 0xC0000000U // Defines pin-muxing selection for GPIO47 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPBGMUX2_GPIO48_S 0U +#define GPIO_GPBGMUX2_GPIO48_M 0x3U // Defines pin-muxing selection for GPIO48 +#define GPIO_GPBGMUX2_GPIO49_S 2U +#define GPIO_GPBGMUX2_GPIO49_M 0xCU // Defines pin-muxing selection for GPIO49 +#define GPIO_GPBGMUX2_GPIO50_S 4U +#define GPIO_GPBGMUX2_GPIO50_M 0x30U // Defines pin-muxing selection for GPIO50 +#define GPIO_GPBGMUX2_GPIO51_S 6U +#define GPIO_GPBGMUX2_GPIO51_M 0xC0U // Defines pin-muxing selection for GPIO51 +#define GPIO_GPBGMUX2_GPIO52_S 8U +#define GPIO_GPBGMUX2_GPIO52_M 0x300U // Defines pin-muxing selection for GPIO52 +#define GPIO_GPBGMUX2_GPIO53_S 10U +#define GPIO_GPBGMUX2_GPIO53_M 0xC00U // Defines pin-muxing selection for GPIO53 +#define GPIO_GPBGMUX2_GPIO54_S 12U +#define GPIO_GPBGMUX2_GPIO54_M 0x3000U // Defines pin-muxing selection for GPIO54 +#define GPIO_GPBGMUX2_GPIO55_S 14U +#define GPIO_GPBGMUX2_GPIO55_M 0xC000U // Defines pin-muxing selection for GPIO55 +#define GPIO_GPBGMUX2_GPIO56_S 16U +#define GPIO_GPBGMUX2_GPIO56_M 0x30000U // Defines pin-muxing selection for GPIO56 +#define GPIO_GPBGMUX2_GPIO57_S 18U +#define GPIO_GPBGMUX2_GPIO57_M 0xC0000U // Defines pin-muxing selection for GPIO57 +#define GPIO_GPBGMUX2_GPIO58_S 20U +#define GPIO_GPBGMUX2_GPIO58_M 0x300000U // Defines pin-muxing selection for GPIO58 +#define GPIO_GPBGMUX2_GPIO59_S 22U +#define GPIO_GPBGMUX2_GPIO59_M 0xC00000U // Defines pin-muxing selection for GPIO59 +#define GPIO_GPBGMUX2_GPIO60_S 24U +#define GPIO_GPBGMUX2_GPIO60_M 0x3000000U // Defines pin-muxing selection for GPIO60 +#define GPIO_GPBGMUX2_GPIO61_S 26U +#define GPIO_GPBGMUX2_GPIO61_M 0xC000000U // Defines pin-muxing selection for GPIO61 +#define GPIO_GPBGMUX2_GPIO62_S 28U +#define GPIO_GPBGMUX2_GPIO62_M 0x30000000U // Defines pin-muxing selection for GPIO62 +#define GPIO_GPBGMUX2_GPIO63_S 30U +#define GPIO_GPBGMUX2_GPIO63_M 0xC0000000U // Defines pin-muxing selection for GPIO63 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL1_GPIO32_S 0U +#define GPIO_GPBCSEL1_GPIO32_M 0xFU // GPIO32 Master CPU Select +#define GPIO_GPBCSEL1_GPIO33_S 4U +#define GPIO_GPBCSEL1_GPIO33_M 0xF0U // GPIO33 Master CPU Select +#define GPIO_GPBCSEL1_GPIO34_S 8U +#define GPIO_GPBCSEL1_GPIO34_M 0xF00U // GPIO34 Master CPU Select +#define GPIO_GPBCSEL1_GPIO35_S 12U +#define GPIO_GPBCSEL1_GPIO35_M 0xF000U // GPIO35 Master CPU Select +#define GPIO_GPBCSEL1_GPIO36_S 16U +#define GPIO_GPBCSEL1_GPIO36_M 0xF0000U // GPIO36 Master CPU Select +#define GPIO_GPBCSEL1_GPIO37_S 20U +#define GPIO_GPBCSEL1_GPIO37_M 0xF00000U // GPIO37 Master CPU Select +#define GPIO_GPBCSEL1_GPIO38_S 24U +#define GPIO_GPBCSEL1_GPIO38_M 0xF000000U // GPIO38 Master CPU Select +#define GPIO_GPBCSEL1_GPIO39_S 28U +#define GPIO_GPBCSEL1_GPIO39_M 0xF0000000U // GPIO39 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL2_GPIO40_S 0U +#define GPIO_GPBCSEL2_GPIO40_M 0xFU // GPIO40 Master CPU Select +#define GPIO_GPBCSEL2_GPIO41_S 4U +#define GPIO_GPBCSEL2_GPIO41_M 0xF0U // GPIO41 Master CPU Select +#define GPIO_GPBCSEL2_GPIO42_S 8U +#define GPIO_GPBCSEL2_GPIO42_M 0xF00U // GPIO42 Master CPU Select +#define GPIO_GPBCSEL2_GPIO43_S 12U +#define GPIO_GPBCSEL2_GPIO43_M 0xF000U // GPIO43 Master CPU Select +#define GPIO_GPBCSEL2_GPIO44_S 16U +#define GPIO_GPBCSEL2_GPIO44_M 0xF0000U // GPIO44 Master CPU Select +#define GPIO_GPBCSEL2_GPIO45_S 20U +#define GPIO_GPBCSEL2_GPIO45_M 0xF00000U // GPIO45 Master CPU Select +#define GPIO_GPBCSEL2_GPIO46_S 24U +#define GPIO_GPBCSEL2_GPIO46_M 0xF000000U // GPIO46 Master CPU Select +#define GPIO_GPBCSEL2_GPIO47_S 28U +#define GPIO_GPBCSEL2_GPIO47_M 0xF0000000U // GPIO47 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL3_GPIO48_S 0U +#define GPIO_GPBCSEL3_GPIO48_M 0xFU // GPIO48 Master CPU Select +#define GPIO_GPBCSEL3_GPIO49_S 4U +#define GPIO_GPBCSEL3_GPIO49_M 0xF0U // GPIO49 Master CPU Select +#define GPIO_GPBCSEL3_GPIO50_S 8U +#define GPIO_GPBCSEL3_GPIO50_M 0xF00U // GPIO50 Master CPU Select +#define GPIO_GPBCSEL3_GPIO51_S 12U +#define GPIO_GPBCSEL3_GPIO51_M 0xF000U // GPIO51 Master CPU Select +#define GPIO_GPBCSEL3_GPIO52_S 16U +#define GPIO_GPBCSEL3_GPIO52_M 0xF0000U // GPIO52 Master CPU Select +#define GPIO_GPBCSEL3_GPIO53_S 20U +#define GPIO_GPBCSEL3_GPIO53_M 0xF00000U // GPIO53 Master CPU Select +#define GPIO_GPBCSEL3_GPIO54_S 24U +#define GPIO_GPBCSEL3_GPIO54_M 0xF000000U // GPIO54 Master CPU Select +#define GPIO_GPBCSEL3_GPIO55_S 28U +#define GPIO_GPBCSEL3_GPIO55_M 0xF0000000U // GPIO55 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPBCSEL4_GPIO56_S 0U +#define GPIO_GPBCSEL4_GPIO56_M 0xFU // GPIO56 Master CPU Select +#define GPIO_GPBCSEL4_GPIO57_S 4U +#define GPIO_GPBCSEL4_GPIO57_M 0xF0U // GPIO57 Master CPU Select +#define GPIO_GPBCSEL4_GPIO58_S 8U +#define GPIO_GPBCSEL4_GPIO58_M 0xF00U // GPIO58 Master CPU Select +#define GPIO_GPBCSEL4_GPIO59_S 12U +#define GPIO_GPBCSEL4_GPIO59_M 0xF000U // GPIO59 Master CPU Select +#define GPIO_GPBCSEL4_GPIO60_S 16U +#define GPIO_GPBCSEL4_GPIO60_M 0xF0000U // GPIO60 Master CPU Select +#define GPIO_GPBCSEL4_GPIO61_S 20U +#define GPIO_GPBCSEL4_GPIO61_M 0xF00000U // GPIO61 Master CPU Select +#define GPIO_GPBCSEL4_GPIO62_S 24U +#define GPIO_GPBCSEL4_GPIO62_M 0xF000000U // GPIO62 Master CPU Select +#define GPIO_GPBCSEL4_GPIO63_S 28U +#define GPIO_GPBCSEL4_GPIO63_M 0xF0000000U // GPIO63 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBLOCK register +// +//************************************************************************************************* +#define GPIO_GPBLOCK_GPIO32 0x1U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO33 0x2U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO34 0x4U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO35 0x8U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO36 0x10U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO37 0x20U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO38 0x40U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO39 0x80U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO40 0x100U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO41 0x200U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO42 0x400U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO43 0x800U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO44 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO45 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO46 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO47 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO48 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO49 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO50 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO51 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO52 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO53 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO54 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO55 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO56 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO57 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO58 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO59 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO60 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO61 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO62 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPBLOCK_GPIO63 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCR register +// +//************************************************************************************************* +#define GPIO_GPBCR_GPIO32 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO33 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO34 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO35 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO36 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO37 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO38 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO39 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO40 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO41 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO42 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO43 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO44 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO45 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO46 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO47 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO48 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO49 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO50 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO51 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO52 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO53 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO54 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO55 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO56 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO57 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO58 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO59 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO60 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO61 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO62 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPBCR_GPIO63 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCTRL register +// +//************************************************************************************************* +#define GPIO_GPCCTRL_QUALPRD0_S 0U +#define GPIO_GPCCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO64 to + // GPIO71 +#define GPIO_GPCCTRL_QUALPRD1_S 8U +#define GPIO_GPCCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO72 to + // GPIO79 +#define GPIO_GPCCTRL_QUALPRD2_S 16U +#define GPIO_GPCCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO80 to + // GPIO87 +#define GPIO_GPCCTRL_QUALPRD3_S 24U +#define GPIO_GPCCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO88 to + // GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL1_GPIO64_S 0U +#define GPIO_GPCQSEL1_GPIO64_M 0x3U // Select input qualification type for GPIO64 +#define GPIO_GPCQSEL1_GPIO65_S 2U +#define GPIO_GPCQSEL1_GPIO65_M 0xCU // Select input qualification type for GPIO65 +#define GPIO_GPCQSEL1_GPIO66_S 4U +#define GPIO_GPCQSEL1_GPIO66_M 0x30U // Select input qualification type for GPIO66 +#define GPIO_GPCQSEL1_GPIO67_S 6U +#define GPIO_GPCQSEL1_GPIO67_M 0xC0U // Select input qualification type for GPIO67 +#define GPIO_GPCQSEL1_GPIO68_S 8U +#define GPIO_GPCQSEL1_GPIO68_M 0x300U // Select input qualification type for GPIO68 +#define GPIO_GPCQSEL1_GPIO69_S 10U +#define GPIO_GPCQSEL1_GPIO69_M 0xC00U // Select input qualification type for GPIO69 +#define GPIO_GPCQSEL1_GPIO70_S 12U +#define GPIO_GPCQSEL1_GPIO70_M 0x3000U // Select input qualification type for GPIO70 +#define GPIO_GPCQSEL1_GPIO71_S 14U +#define GPIO_GPCQSEL1_GPIO71_M 0xC000U // Select input qualification type for GPIO71 +#define GPIO_GPCQSEL1_GPIO72_S 16U +#define GPIO_GPCQSEL1_GPIO72_M 0x30000U // Select input qualification type for GPIO72 +#define GPIO_GPCQSEL1_GPIO73_S 18U +#define GPIO_GPCQSEL1_GPIO73_M 0xC0000U // Select input qualification type for GPIO73 +#define GPIO_GPCQSEL1_GPIO74_S 20U +#define GPIO_GPCQSEL1_GPIO74_M 0x300000U // Select input qualification type for GPIO74 +#define GPIO_GPCQSEL1_GPIO75_S 22U +#define GPIO_GPCQSEL1_GPIO75_M 0xC00000U // Select input qualification type for GPIO75 +#define GPIO_GPCQSEL1_GPIO76_S 24U +#define GPIO_GPCQSEL1_GPIO76_M 0x3000000U // Select input qualification type for GPIO76 +#define GPIO_GPCQSEL1_GPIO77_S 26U +#define GPIO_GPCQSEL1_GPIO77_M 0xC000000U // Select input qualification type for GPIO77 +#define GPIO_GPCQSEL1_GPIO78_S 28U +#define GPIO_GPCQSEL1_GPIO78_M 0x30000000U // Select input qualification type for GPIO78 +#define GPIO_GPCQSEL1_GPIO79_S 30U +#define GPIO_GPCQSEL1_GPIO79_M 0xC0000000U // Select input qualification type for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCQSEL2_GPIO80_S 0U +#define GPIO_GPCQSEL2_GPIO80_M 0x3U // Select input qualification type for GPIO80 +#define GPIO_GPCQSEL2_GPIO81_S 2U +#define GPIO_GPCQSEL2_GPIO81_M 0xCU // Select input qualification type for GPIO81 +#define GPIO_GPCQSEL2_GPIO82_S 4U +#define GPIO_GPCQSEL2_GPIO82_M 0x30U // Select input qualification type for GPIO82 +#define GPIO_GPCQSEL2_GPIO83_S 6U +#define GPIO_GPCQSEL2_GPIO83_M 0xC0U // Select input qualification type for GPIO83 +#define GPIO_GPCQSEL2_GPIO84_S 8U +#define GPIO_GPCQSEL2_GPIO84_M 0x300U // Select input qualification type for GPIO84 +#define GPIO_GPCQSEL2_GPIO85_S 10U +#define GPIO_GPCQSEL2_GPIO85_M 0xC00U // Select input qualification type for GPIO85 +#define GPIO_GPCQSEL2_GPIO86_S 12U +#define GPIO_GPCQSEL2_GPIO86_M 0x3000U // Select input qualification type for GPIO86 +#define GPIO_GPCQSEL2_GPIO87_S 14U +#define GPIO_GPCQSEL2_GPIO87_M 0xC000U // Select input qualification type for GPIO87 +#define GPIO_GPCQSEL2_GPIO88_S 16U +#define GPIO_GPCQSEL2_GPIO88_M 0x30000U // Select input qualification type for GPIO88 +#define GPIO_GPCQSEL2_GPIO89_S 18U +#define GPIO_GPCQSEL2_GPIO89_M 0xC0000U // Select input qualification type for GPIO89 +#define GPIO_GPCQSEL2_GPIO90_S 20U +#define GPIO_GPCQSEL2_GPIO90_M 0x300000U // Select input qualification type for GPIO90 +#define GPIO_GPCQSEL2_GPIO91_S 22U +#define GPIO_GPCQSEL2_GPIO91_M 0xC00000U // Select input qualification type for GPIO91 +#define GPIO_GPCQSEL2_GPIO92_S 24U +#define GPIO_GPCQSEL2_GPIO92_M 0x3000000U // Select input qualification type for GPIO92 +#define GPIO_GPCQSEL2_GPIO93_S 26U +#define GPIO_GPCQSEL2_GPIO93_M 0xC000000U // Select input qualification type for GPIO93 +#define GPIO_GPCQSEL2_GPIO94_S 28U +#define GPIO_GPCQSEL2_GPIO94_M 0x30000000U // Select input qualification type for GPIO94 +#define GPIO_GPCQSEL2_GPIO95_S 30U +#define GPIO_GPCQSEL2_GPIO95_M 0xC0000000U // Select input qualification type for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCMUX1_GPIO64_S 0U +#define GPIO_GPCMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCMUX1_GPIO65_S 2U +#define GPIO_GPCMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCMUX1_GPIO66_S 4U +#define GPIO_GPCMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCMUX1_GPIO67_S 6U +#define GPIO_GPCMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCMUX1_GPIO68_S 8U +#define GPIO_GPCMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCMUX1_GPIO69_S 10U +#define GPIO_GPCMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCMUX1_GPIO70_S 12U +#define GPIO_GPCMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCMUX1_GPIO71_S 14U +#define GPIO_GPCMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCMUX1_GPIO72_S 16U +#define GPIO_GPCMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCMUX1_GPIO73_S 18U +#define GPIO_GPCMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCMUX1_GPIO74_S 20U +#define GPIO_GPCMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCMUX1_GPIO75_S 22U +#define GPIO_GPCMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCMUX1_GPIO76_S 24U +#define GPIO_GPCMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCMUX1_GPIO77_S 26U +#define GPIO_GPCMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCMUX1_GPIO78_S 28U +#define GPIO_GPCMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCMUX1_GPIO79_S 30U +#define GPIO_GPCMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCMUX2_GPIO80_S 0U +#define GPIO_GPCMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCMUX2_GPIO81_S 2U +#define GPIO_GPCMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCMUX2_GPIO82_S 4U +#define GPIO_GPCMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCMUX2_GPIO83_S 6U +#define GPIO_GPCMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCMUX2_GPIO84_S 8U +#define GPIO_GPCMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCMUX2_GPIO85_S 10U +#define GPIO_GPCMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCMUX2_GPIO86_S 12U +#define GPIO_GPCMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCMUX2_GPIO87_S 14U +#define GPIO_GPCMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCMUX2_GPIO88_S 16U +#define GPIO_GPCMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCMUX2_GPIO89_S 18U +#define GPIO_GPCMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCMUX2_GPIO90_S 20U +#define GPIO_GPCMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCMUX2_GPIO91_S 22U +#define GPIO_GPCMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCMUX2_GPIO92_S 24U +#define GPIO_GPCMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCMUX2_GPIO93_S 26U +#define GPIO_GPCMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCMUX2_GPIO94_S 28U +#define GPIO_GPCMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCMUX2_GPIO95_S 30U +#define GPIO_GPCMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDIR register +// +//************************************************************************************************* +#define GPIO_GPCDIR_GPIO64 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO65 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO66 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO67 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO68 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO69 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO70 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO71 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO72 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO73 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO74 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO75 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO76 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO77 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO78 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO79 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO80 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO81 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO82 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO83 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO84 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO85 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO86 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO87 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO88 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO89 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO90 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO91 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO92 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO93 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO94 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPCDIR_GPIO95 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCPUD register +// +//************************************************************************************************* +#define GPIO_GPCPUD_GPIO64 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO65 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO66 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO67 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO68 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO69 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO70 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO71 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO72 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO73 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO74 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO75 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO76 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO77 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO78 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO79 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO80 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO81 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO82 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO83 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO84 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO85 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO86 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO87 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO88 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO89 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO90 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO91 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO92 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO93 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO94 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPCPUD_GPIO95 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCINV register +// +//************************************************************************************************* +#define GPIO_GPCINV_GPIO64 0x1U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO65 0x2U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO66 0x4U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO67 0x8U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO68 0x10U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO69 0x20U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO70 0x40U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO71 0x80U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO72 0x100U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO73 0x200U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO74 0x400U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO75 0x800U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO76 0x1000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO77 0x2000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO78 0x4000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO79 0x8000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO80 0x10000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO81 0x20000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO82 0x40000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO83 0x80000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO84 0x100000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO85 0x200000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO86 0x400000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO87 0x800000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO88 0x1000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO89 0x2000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO90 0x4000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO91 0x8000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO92 0x10000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO93 0x20000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO94 0x40000000U // Input inversion control for this pin +#define GPIO_GPCINV_GPIO95 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCODR register +// +//************************************************************************************************* +#define GPIO_GPCODR_GPIO64 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO65 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO66 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO67 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO68 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO69 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO70 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO71 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO72 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO73 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO74 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO75 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO76 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO77 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO78 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO79 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO80 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO81 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO82 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO83 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO84 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO85 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO86 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO87 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO88 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO89 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO90 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO91 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO92 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO93 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO94 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPCODR_GPIO95 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX1_GPIO64_S 0U +#define GPIO_GPCGMUX1_GPIO64_M 0x3U // Defines pin-muxing selection for GPIO64 +#define GPIO_GPCGMUX1_GPIO65_S 2U +#define GPIO_GPCGMUX1_GPIO65_M 0xCU // Defines pin-muxing selection for GPIO65 +#define GPIO_GPCGMUX1_GPIO66_S 4U +#define GPIO_GPCGMUX1_GPIO66_M 0x30U // Defines pin-muxing selection for GPIO66 +#define GPIO_GPCGMUX1_GPIO67_S 6U +#define GPIO_GPCGMUX1_GPIO67_M 0xC0U // Defines pin-muxing selection for GPIO67 +#define GPIO_GPCGMUX1_GPIO68_S 8U +#define GPIO_GPCGMUX1_GPIO68_M 0x300U // Defines pin-muxing selection for GPIO68 +#define GPIO_GPCGMUX1_GPIO69_S 10U +#define GPIO_GPCGMUX1_GPIO69_M 0xC00U // Defines pin-muxing selection for GPIO69 +#define GPIO_GPCGMUX1_GPIO70_S 12U +#define GPIO_GPCGMUX1_GPIO70_M 0x3000U // Defines pin-muxing selection for GPIO70 +#define GPIO_GPCGMUX1_GPIO71_S 14U +#define GPIO_GPCGMUX1_GPIO71_M 0xC000U // Defines pin-muxing selection for GPIO71 +#define GPIO_GPCGMUX1_GPIO72_S 16U +#define GPIO_GPCGMUX1_GPIO72_M 0x30000U // Defines pin-muxing selection for GPIO72 +#define GPIO_GPCGMUX1_GPIO73_S 18U +#define GPIO_GPCGMUX1_GPIO73_M 0xC0000U // Defines pin-muxing selection for GPIO73 +#define GPIO_GPCGMUX1_GPIO74_S 20U +#define GPIO_GPCGMUX1_GPIO74_M 0x300000U // Defines pin-muxing selection for GPIO74 +#define GPIO_GPCGMUX1_GPIO75_S 22U +#define GPIO_GPCGMUX1_GPIO75_M 0xC00000U // Defines pin-muxing selection for GPIO75 +#define GPIO_GPCGMUX1_GPIO76_S 24U +#define GPIO_GPCGMUX1_GPIO76_M 0x3000000U // Defines pin-muxing selection for GPIO76 +#define GPIO_GPCGMUX1_GPIO77_S 26U +#define GPIO_GPCGMUX1_GPIO77_M 0xC000000U // Defines pin-muxing selection for GPIO77 +#define GPIO_GPCGMUX1_GPIO78_S 28U +#define GPIO_GPCGMUX1_GPIO78_M 0x30000000U // Defines pin-muxing selection for GPIO78 +#define GPIO_GPCGMUX1_GPIO79_S 30U +#define GPIO_GPCGMUX1_GPIO79_M 0xC0000000U // Defines pin-muxing selection for GPIO79 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPCGMUX2_GPIO80_S 0U +#define GPIO_GPCGMUX2_GPIO80_M 0x3U // Defines pin-muxing selection for GPIO80 +#define GPIO_GPCGMUX2_GPIO81_S 2U +#define GPIO_GPCGMUX2_GPIO81_M 0xCU // Defines pin-muxing selection for GPIO81 +#define GPIO_GPCGMUX2_GPIO82_S 4U +#define GPIO_GPCGMUX2_GPIO82_M 0x30U // Defines pin-muxing selection for GPIO82 +#define GPIO_GPCGMUX2_GPIO83_S 6U +#define GPIO_GPCGMUX2_GPIO83_M 0xC0U // Defines pin-muxing selection for GPIO83 +#define GPIO_GPCGMUX2_GPIO84_S 8U +#define GPIO_GPCGMUX2_GPIO84_M 0x300U // Defines pin-muxing selection for GPIO84 +#define GPIO_GPCGMUX2_GPIO85_S 10U +#define GPIO_GPCGMUX2_GPIO85_M 0xC00U // Defines pin-muxing selection for GPIO85 +#define GPIO_GPCGMUX2_GPIO86_S 12U +#define GPIO_GPCGMUX2_GPIO86_M 0x3000U // Defines pin-muxing selection for GPIO86 +#define GPIO_GPCGMUX2_GPIO87_S 14U +#define GPIO_GPCGMUX2_GPIO87_M 0xC000U // Defines pin-muxing selection for GPIO87 +#define GPIO_GPCGMUX2_GPIO88_S 16U +#define GPIO_GPCGMUX2_GPIO88_M 0x30000U // Defines pin-muxing selection for GPIO88 +#define GPIO_GPCGMUX2_GPIO89_S 18U +#define GPIO_GPCGMUX2_GPIO89_M 0xC0000U // Defines pin-muxing selection for GPIO89 +#define GPIO_GPCGMUX2_GPIO90_S 20U +#define GPIO_GPCGMUX2_GPIO90_M 0x300000U // Defines pin-muxing selection for GPIO90 +#define GPIO_GPCGMUX2_GPIO91_S 22U +#define GPIO_GPCGMUX2_GPIO91_M 0xC00000U // Defines pin-muxing selection for GPIO91 +#define GPIO_GPCGMUX2_GPIO92_S 24U +#define GPIO_GPCGMUX2_GPIO92_M 0x3000000U // Defines pin-muxing selection for GPIO92 +#define GPIO_GPCGMUX2_GPIO93_S 26U +#define GPIO_GPCGMUX2_GPIO93_M 0xC000000U // Defines pin-muxing selection for GPIO93 +#define GPIO_GPCGMUX2_GPIO94_S 28U +#define GPIO_GPCGMUX2_GPIO94_M 0x30000000U // Defines pin-muxing selection for GPIO94 +#define GPIO_GPCGMUX2_GPIO95_S 30U +#define GPIO_GPCGMUX2_GPIO95_M 0xC0000000U // Defines pin-muxing selection for GPIO95 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL1_GPIO64_S 0U +#define GPIO_GPCCSEL1_GPIO64_M 0xFU // GPIO64 Master CPU Select +#define GPIO_GPCCSEL1_GPIO65_S 4U +#define GPIO_GPCCSEL1_GPIO65_M 0xF0U // GPIO65 Master CPU Select +#define GPIO_GPCCSEL1_GPIO66_S 8U +#define GPIO_GPCCSEL1_GPIO66_M 0xF00U // GPIO66 Master CPU Select +#define GPIO_GPCCSEL1_GPIO67_S 12U +#define GPIO_GPCCSEL1_GPIO67_M 0xF000U // GPIO67 Master CPU Select +#define GPIO_GPCCSEL1_GPIO68_S 16U +#define GPIO_GPCCSEL1_GPIO68_M 0xF0000U // GPIO68 Master CPU Select +#define GPIO_GPCCSEL1_GPIO69_S 20U +#define GPIO_GPCCSEL1_GPIO69_M 0xF00000U // GPIO69 Master CPU Select +#define GPIO_GPCCSEL1_GPIO70_S 24U +#define GPIO_GPCCSEL1_GPIO70_M 0xF000000U // GPIO70 Master CPU Select +#define GPIO_GPCCSEL1_GPIO71_S 28U +#define GPIO_GPCCSEL1_GPIO71_M 0xF0000000U // GPIO71 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL2_GPIO72_S 0U +#define GPIO_GPCCSEL2_GPIO72_M 0xFU // GPIO72 Master CPU Select +#define GPIO_GPCCSEL2_GPIO73_S 4U +#define GPIO_GPCCSEL2_GPIO73_M 0xF0U // GPIO73 Master CPU Select +#define GPIO_GPCCSEL2_GPIO74_S 8U +#define GPIO_GPCCSEL2_GPIO74_M 0xF00U // GPIO74 Master CPU Select +#define GPIO_GPCCSEL2_GPIO75_S 12U +#define GPIO_GPCCSEL2_GPIO75_M 0xF000U // GPIO75 Master CPU Select +#define GPIO_GPCCSEL2_GPIO76_S 16U +#define GPIO_GPCCSEL2_GPIO76_M 0xF0000U // GPIO76 Master CPU Select +#define GPIO_GPCCSEL2_GPIO77_S 20U +#define GPIO_GPCCSEL2_GPIO77_M 0xF00000U // GPIO77 Master CPU Select +#define GPIO_GPCCSEL2_GPIO78_S 24U +#define GPIO_GPCCSEL2_GPIO78_M 0xF000000U // GPIO78 Master CPU Select +#define GPIO_GPCCSEL2_GPIO79_S 28U +#define GPIO_GPCCSEL2_GPIO79_M 0xF0000000U // GPIO79 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL3_GPIO80_S 0U +#define GPIO_GPCCSEL3_GPIO80_M 0xFU // GPIO80 Master CPU Select +#define GPIO_GPCCSEL3_GPIO81_S 4U +#define GPIO_GPCCSEL3_GPIO81_M 0xF0U // GPIO81 Master CPU Select +#define GPIO_GPCCSEL3_GPIO82_S 8U +#define GPIO_GPCCSEL3_GPIO82_M 0xF00U // GPIO82 Master CPU Select +#define GPIO_GPCCSEL3_GPIO83_S 12U +#define GPIO_GPCCSEL3_GPIO83_M 0xF000U // GPIO83 Master CPU Select +#define GPIO_GPCCSEL3_GPIO84_S 16U +#define GPIO_GPCCSEL3_GPIO84_M 0xF0000U // GPIO84 Master CPU Select +#define GPIO_GPCCSEL3_GPIO85_S 20U +#define GPIO_GPCCSEL3_GPIO85_M 0xF00000U // GPIO85 Master CPU Select +#define GPIO_GPCCSEL3_GPIO86_S 24U +#define GPIO_GPCCSEL3_GPIO86_M 0xF000000U // GPIO86 Master CPU Select +#define GPIO_GPCCSEL3_GPIO87_S 28U +#define GPIO_GPCCSEL3_GPIO87_M 0xF0000000U // GPIO87 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPCCSEL4_GPIO88_S 0U +#define GPIO_GPCCSEL4_GPIO88_M 0xFU // GPIO88 Master CPU Select +#define GPIO_GPCCSEL4_GPIO89_S 4U +#define GPIO_GPCCSEL4_GPIO89_M 0xF0U // GPIO89 Master CPU Select +#define GPIO_GPCCSEL4_GPIO90_S 8U +#define GPIO_GPCCSEL4_GPIO90_M 0xF00U // GPIO90 Master CPU Select +#define GPIO_GPCCSEL4_GPIO91_S 12U +#define GPIO_GPCCSEL4_GPIO91_M 0xF000U // GPIO91 Master CPU Select +#define GPIO_GPCCSEL4_GPIO92_S 16U +#define GPIO_GPCCSEL4_GPIO92_M 0xF0000U // GPIO92 Master CPU Select +#define GPIO_GPCCSEL4_GPIO93_S 20U +#define GPIO_GPCCSEL4_GPIO93_M 0xF00000U // GPIO93 Master CPU Select +#define GPIO_GPCCSEL4_GPIO94_S 24U +#define GPIO_GPCCSEL4_GPIO94_M 0xF000000U // GPIO94 Master CPU Select +#define GPIO_GPCCSEL4_GPIO95_S 28U +#define GPIO_GPCCSEL4_GPIO95_M 0xF0000000U // GPIO95 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCLOCK register +// +//************************************************************************************************* +#define GPIO_GPCLOCK_GPIO64 0x1U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO65 0x2U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO66 0x4U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO67 0x8U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO68 0x10U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO69 0x20U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO70 0x40U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO71 0x80U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO72 0x100U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO73 0x200U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO74 0x400U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO75 0x800U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO76 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO77 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO78 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO79 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO80 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO81 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO82 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO83 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO84 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO85 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO86 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO87 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO88 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO89 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO90 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO91 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO92 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO93 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO94 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPCLOCK_GPIO95 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCR register +// +//************************************************************************************************* +#define GPIO_GPCCR_GPIO64 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO65 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO66 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO67 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO68 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO69 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO70 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO71 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO72 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO73 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO74 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO75 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO76 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO77 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO78 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO79 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO80 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO81 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO82 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO83 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO84 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO85 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO86 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO87 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO88 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO89 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO90 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO91 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO92 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO93 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO94 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPCCR_GPIO95 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCTRL register +// +//************************************************************************************************* +#define GPIO_GPDCTRL_QUALPRD0_S 0U +#define GPIO_GPDCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO96 to + // GPIO103 +#define GPIO_GPDCTRL_QUALPRD1_S 8U +#define GPIO_GPDCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO104 to + // GPIO111 +#define GPIO_GPDCTRL_QUALPRD2_S 16U +#define GPIO_GPDCTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO112 to + // GPIO119 +#define GPIO_GPDCTRL_QUALPRD3_S 24U +#define GPIO_GPDCTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO120 to + // GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL1_GPIO96_S 0U +#define GPIO_GPDQSEL1_GPIO96_M 0x3U // Select input qualification type for GPIO96 +#define GPIO_GPDQSEL1_GPIO97_S 2U +#define GPIO_GPDQSEL1_GPIO97_M 0xCU // Select input qualification type for GPIO97 +#define GPIO_GPDQSEL1_GPIO98_S 4U +#define GPIO_GPDQSEL1_GPIO98_M 0x30U // Select input qualification type for GPIO98 +#define GPIO_GPDQSEL1_GPIO99_S 6U +#define GPIO_GPDQSEL1_GPIO99_M 0xC0U // Select input qualification type for GPIO99 +#define GPIO_GPDQSEL1_GPIO100_S 8U +#define GPIO_GPDQSEL1_GPIO100_M 0x300U // Select input qualification type for GPIO100 +#define GPIO_GPDQSEL1_GPIO101_S 10U +#define GPIO_GPDQSEL1_GPIO101_M 0xC00U // Select input qualification type for GPIO101 +#define GPIO_GPDQSEL1_GPIO102_S 12U +#define GPIO_GPDQSEL1_GPIO102_M 0x3000U // Select input qualification type for GPIO102 +#define GPIO_GPDQSEL1_GPIO103_S 14U +#define GPIO_GPDQSEL1_GPIO103_M 0xC000U // Select input qualification type for GPIO103 +#define GPIO_GPDQSEL1_GPIO104_S 16U +#define GPIO_GPDQSEL1_GPIO104_M 0x30000U // Select input qualification type for GPIO104 +#define GPIO_GPDQSEL1_GPIO105_S 18U +#define GPIO_GPDQSEL1_GPIO105_M 0xC0000U // Select input qualification type for GPIO105 +#define GPIO_GPDQSEL1_GPIO106_S 20U +#define GPIO_GPDQSEL1_GPIO106_M 0x300000U // Select input qualification type for GPIO106 +#define GPIO_GPDQSEL1_GPIO107_S 22U +#define GPIO_GPDQSEL1_GPIO107_M 0xC00000U // Select input qualification type for GPIO107 +#define GPIO_GPDQSEL1_GPIO108_S 24U +#define GPIO_GPDQSEL1_GPIO108_M 0x3000000U // Select input qualification type for GPIO108 +#define GPIO_GPDQSEL1_GPIO109_S 26U +#define GPIO_GPDQSEL1_GPIO109_M 0xC000000U // Select input qualification type for GPIO109 +#define GPIO_GPDQSEL1_GPIO110_S 28U +#define GPIO_GPDQSEL1_GPIO110_M 0x30000000U // Select input qualification type for GPIO110 +#define GPIO_GPDQSEL1_GPIO111_S 30U +#define GPIO_GPDQSEL1_GPIO111_M 0xC0000000U // Select input qualification type for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDQSEL2_GPIO112_S 0U +#define GPIO_GPDQSEL2_GPIO112_M 0x3U // Select input qualification type for GPIO112 +#define GPIO_GPDQSEL2_GPIO113_S 2U +#define GPIO_GPDQSEL2_GPIO113_M 0xCU // Select input qualification type for GPIO113 +#define GPIO_GPDQSEL2_GPIO114_S 4U +#define GPIO_GPDQSEL2_GPIO114_M 0x30U // Select input qualification type for GPIO114 +#define GPIO_GPDQSEL2_GPIO115_S 6U +#define GPIO_GPDQSEL2_GPIO115_M 0xC0U // Select input qualification type for GPIO115 +#define GPIO_GPDQSEL2_GPIO116_S 8U +#define GPIO_GPDQSEL2_GPIO116_M 0x300U // Select input qualification type for GPIO116 +#define GPIO_GPDQSEL2_GPIO117_S 10U +#define GPIO_GPDQSEL2_GPIO117_M 0xC00U // Select input qualification type for GPIO117 +#define GPIO_GPDQSEL2_GPIO118_S 12U +#define GPIO_GPDQSEL2_GPIO118_M 0x3000U // Select input qualification type for GPIO118 +#define GPIO_GPDQSEL2_GPIO119_S 14U +#define GPIO_GPDQSEL2_GPIO119_M 0xC000U // Select input qualification type for GPIO119 +#define GPIO_GPDQSEL2_GPIO120_S 16U +#define GPIO_GPDQSEL2_GPIO120_M 0x30000U // Select input qualification type for GPIO120 +#define GPIO_GPDQSEL2_GPIO121_S 18U +#define GPIO_GPDQSEL2_GPIO121_M 0xC0000U // Select input qualification type for GPIO121 +#define GPIO_GPDQSEL2_GPIO122_S 20U +#define GPIO_GPDQSEL2_GPIO122_M 0x300000U // Select input qualification type for GPIO122 +#define GPIO_GPDQSEL2_GPIO123_S 22U +#define GPIO_GPDQSEL2_GPIO123_M 0xC00000U // Select input qualification type for GPIO123 +#define GPIO_GPDQSEL2_GPIO124_S 24U +#define GPIO_GPDQSEL2_GPIO124_M 0x3000000U // Select input qualification type for GPIO124 +#define GPIO_GPDQSEL2_GPIO125_S 26U +#define GPIO_GPDQSEL2_GPIO125_M 0xC000000U // Select input qualification type for GPIO125 +#define GPIO_GPDQSEL2_GPIO126_S 28U +#define GPIO_GPDQSEL2_GPIO126_M 0x30000000U // Select input qualification type for GPIO126 +#define GPIO_GPDQSEL2_GPIO127_S 30U +#define GPIO_GPDQSEL2_GPIO127_M 0xC0000000U // Select input qualification type for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDMUX1_GPIO96_S 0U +#define GPIO_GPDMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDMUX1_GPIO97_S 2U +#define GPIO_GPDMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDMUX1_GPIO98_S 4U +#define GPIO_GPDMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDMUX1_GPIO99_S 6U +#define GPIO_GPDMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDMUX1_GPIO100_S 8U +#define GPIO_GPDMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDMUX1_GPIO101_S 10U +#define GPIO_GPDMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDMUX1_GPIO102_S 12U +#define GPIO_GPDMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDMUX1_GPIO103_S 14U +#define GPIO_GPDMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDMUX1_GPIO104_S 16U +#define GPIO_GPDMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDMUX1_GPIO105_S 18U +#define GPIO_GPDMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDMUX1_GPIO106_S 20U +#define GPIO_GPDMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDMUX1_GPIO107_S 22U +#define GPIO_GPDMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDMUX1_GPIO108_S 24U +#define GPIO_GPDMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDMUX1_GPIO109_S 26U +#define GPIO_GPDMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDMUX1_GPIO110_S 28U +#define GPIO_GPDMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDMUX1_GPIO111_S 30U +#define GPIO_GPDMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDMUX2_GPIO112_S 0U +#define GPIO_GPDMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDMUX2_GPIO113_S 2U +#define GPIO_GPDMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDMUX2_GPIO114_S 4U +#define GPIO_GPDMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDMUX2_GPIO115_S 6U +#define GPIO_GPDMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDMUX2_GPIO116_S 8U +#define GPIO_GPDMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDMUX2_GPIO117_S 10U +#define GPIO_GPDMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDMUX2_GPIO118_S 12U +#define GPIO_GPDMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDMUX2_GPIO119_S 14U +#define GPIO_GPDMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDMUX2_GPIO120_S 16U +#define GPIO_GPDMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDMUX2_GPIO121_S 18U +#define GPIO_GPDMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDMUX2_GPIO122_S 20U +#define GPIO_GPDMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDMUX2_GPIO123_S 22U +#define GPIO_GPDMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDMUX2_GPIO124_S 24U +#define GPIO_GPDMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDMUX2_GPIO125_S 26U +#define GPIO_GPDMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDMUX2_GPIO126_S 28U +#define GPIO_GPDMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDMUX2_GPIO127_S 30U +#define GPIO_GPDMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDIR register +// +//************************************************************************************************* +#define GPIO_GPDDIR_GPIO96 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO97 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO98 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO99 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO100 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO101 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO102 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO103 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO104 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO105 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO106 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO107 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO108 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO109 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO110 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO111 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO112 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO113 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO114 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO115 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO116 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO117 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO118 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO119 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO120 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO121 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO122 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO123 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO124 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO125 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO126 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPDDIR_GPIO127 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDPUD register +// +//************************************************************************************************* +#define GPIO_GPDPUD_GPIO96 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO97 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO98 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO99 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO100 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO101 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO102 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO103 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO104 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO105 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO106 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO107 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO108 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO109 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO110 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO111 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO112 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO113 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO114 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO115 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO116 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO117 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO118 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO119 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO120 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO121 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO122 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO123 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO124 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO125 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO126 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPDPUD_GPIO127 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDINV register +// +//************************************************************************************************* +#define GPIO_GPDINV_GPIO96 0x1U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO97 0x2U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO98 0x4U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO99 0x8U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO100 0x10U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO101 0x20U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO102 0x40U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO103 0x80U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO104 0x100U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO105 0x200U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO106 0x400U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO107 0x800U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO108 0x1000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO109 0x2000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO110 0x4000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO111 0x8000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO112 0x10000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO113 0x20000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO114 0x40000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO115 0x80000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO116 0x100000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO117 0x200000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO118 0x400000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO119 0x800000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO120 0x1000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO121 0x2000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO122 0x4000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO123 0x8000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO124 0x10000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO125 0x20000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO126 0x40000000U // Input inversion control for this pin +#define GPIO_GPDINV_GPIO127 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDODR register +// +//************************************************************************************************* +#define GPIO_GPDODR_GPIO96 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO97 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO98 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO99 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO100 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO101 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO102 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO103 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO104 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO105 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO106 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO107 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO108 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO109 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO110 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO111 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO112 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO113 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO114 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO115 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO116 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO117 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO118 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO119 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO120 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO121 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO122 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO123 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO124 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO125 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO126 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPDODR_GPIO127 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX1_GPIO96_S 0U +#define GPIO_GPDGMUX1_GPIO96_M 0x3U // Defines pin-muxing selection for GPIO96 +#define GPIO_GPDGMUX1_GPIO97_S 2U +#define GPIO_GPDGMUX1_GPIO97_M 0xCU // Defines pin-muxing selection for GPIO97 +#define GPIO_GPDGMUX1_GPIO98_S 4U +#define GPIO_GPDGMUX1_GPIO98_M 0x30U // Defines pin-muxing selection for GPIO98 +#define GPIO_GPDGMUX1_GPIO99_S 6U +#define GPIO_GPDGMUX1_GPIO99_M 0xC0U // Defines pin-muxing selection for GPIO99 +#define GPIO_GPDGMUX1_GPIO100_S 8U +#define GPIO_GPDGMUX1_GPIO100_M 0x300U // Defines pin-muxing selection for GPIO100 +#define GPIO_GPDGMUX1_GPIO101_S 10U +#define GPIO_GPDGMUX1_GPIO101_M 0xC00U // Defines pin-muxing selection for GPIO101 +#define GPIO_GPDGMUX1_GPIO102_S 12U +#define GPIO_GPDGMUX1_GPIO102_M 0x3000U // Defines pin-muxing selection for GPIO102 +#define GPIO_GPDGMUX1_GPIO103_S 14U +#define GPIO_GPDGMUX1_GPIO103_M 0xC000U // Defines pin-muxing selection for GPIO103 +#define GPIO_GPDGMUX1_GPIO104_S 16U +#define GPIO_GPDGMUX1_GPIO104_M 0x30000U // Defines pin-muxing selection for GPIO104 +#define GPIO_GPDGMUX1_GPIO105_S 18U +#define GPIO_GPDGMUX1_GPIO105_M 0xC0000U // Defines pin-muxing selection for GPIO105 +#define GPIO_GPDGMUX1_GPIO106_S 20U +#define GPIO_GPDGMUX1_GPIO106_M 0x300000U // Defines pin-muxing selection for GPIO106 +#define GPIO_GPDGMUX1_GPIO107_S 22U +#define GPIO_GPDGMUX1_GPIO107_M 0xC00000U // Defines pin-muxing selection for GPIO107 +#define GPIO_GPDGMUX1_GPIO108_S 24U +#define GPIO_GPDGMUX1_GPIO108_M 0x3000000U // Defines pin-muxing selection for GPIO108 +#define GPIO_GPDGMUX1_GPIO109_S 26U +#define GPIO_GPDGMUX1_GPIO109_M 0xC000000U // Defines pin-muxing selection for GPIO109 +#define GPIO_GPDGMUX1_GPIO110_S 28U +#define GPIO_GPDGMUX1_GPIO110_M 0x30000000U // Defines pin-muxing selection for GPIO110 +#define GPIO_GPDGMUX1_GPIO111_S 30U +#define GPIO_GPDGMUX1_GPIO111_M 0xC0000000U // Defines pin-muxing selection for GPIO111 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPDGMUX2_GPIO112_S 0U +#define GPIO_GPDGMUX2_GPIO112_M 0x3U // Defines pin-muxing selection for GPIO112 +#define GPIO_GPDGMUX2_GPIO113_S 2U +#define GPIO_GPDGMUX2_GPIO113_M 0xCU // Defines pin-muxing selection for GPIO113 +#define GPIO_GPDGMUX2_GPIO114_S 4U +#define GPIO_GPDGMUX2_GPIO114_M 0x30U // Defines pin-muxing selection for GPIO114 +#define GPIO_GPDGMUX2_GPIO115_S 6U +#define GPIO_GPDGMUX2_GPIO115_M 0xC0U // Defines pin-muxing selection for GPIO115 +#define GPIO_GPDGMUX2_GPIO116_S 8U +#define GPIO_GPDGMUX2_GPIO116_M 0x300U // Defines pin-muxing selection for GPIO116 +#define GPIO_GPDGMUX2_GPIO117_S 10U +#define GPIO_GPDGMUX2_GPIO117_M 0xC00U // Defines pin-muxing selection for GPIO117 +#define GPIO_GPDGMUX2_GPIO118_S 12U +#define GPIO_GPDGMUX2_GPIO118_M 0x3000U // Defines pin-muxing selection for GPIO118 +#define GPIO_GPDGMUX2_GPIO119_S 14U +#define GPIO_GPDGMUX2_GPIO119_M 0xC000U // Defines pin-muxing selection for GPIO119 +#define GPIO_GPDGMUX2_GPIO120_S 16U +#define GPIO_GPDGMUX2_GPIO120_M 0x30000U // Defines pin-muxing selection for GPIO120 +#define GPIO_GPDGMUX2_GPIO121_S 18U +#define GPIO_GPDGMUX2_GPIO121_M 0xC0000U // Defines pin-muxing selection for GPIO121 +#define GPIO_GPDGMUX2_GPIO122_S 20U +#define GPIO_GPDGMUX2_GPIO122_M 0x300000U // Defines pin-muxing selection for GPIO122 +#define GPIO_GPDGMUX2_GPIO123_S 22U +#define GPIO_GPDGMUX2_GPIO123_M 0xC00000U // Defines pin-muxing selection for GPIO123 +#define GPIO_GPDGMUX2_GPIO124_S 24U +#define GPIO_GPDGMUX2_GPIO124_M 0x3000000U // Defines pin-muxing selection for GPIO124 +#define GPIO_GPDGMUX2_GPIO125_S 26U +#define GPIO_GPDGMUX2_GPIO125_M 0xC000000U // Defines pin-muxing selection for GPIO125 +#define GPIO_GPDGMUX2_GPIO126_S 28U +#define GPIO_GPDGMUX2_GPIO126_M 0x30000000U // Defines pin-muxing selection for GPIO126 +#define GPIO_GPDGMUX2_GPIO127_S 30U +#define GPIO_GPDGMUX2_GPIO127_M 0xC0000000U // Defines pin-muxing selection for GPIO127 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL1_GPIO96_S 0U +#define GPIO_GPDCSEL1_GPIO96_M 0xFU // GPIO96 Master CPU Select +#define GPIO_GPDCSEL1_GPIO97_S 4U +#define GPIO_GPDCSEL1_GPIO97_M 0xF0U // GPIO97 Master CPU Select +#define GPIO_GPDCSEL1_GPIO98_S 8U +#define GPIO_GPDCSEL1_GPIO98_M 0xF00U // GPIO98 Master CPU Select +#define GPIO_GPDCSEL1_GPIO99_S 12U +#define GPIO_GPDCSEL1_GPIO99_M 0xF000U // GPIO99 Master CPU Select +#define GPIO_GPDCSEL1_GPIO100_S 16U +#define GPIO_GPDCSEL1_GPIO100_M 0xF0000U // GPIO100 Master CPU Select +#define GPIO_GPDCSEL1_GPIO101_S 20U +#define GPIO_GPDCSEL1_GPIO101_M 0xF00000U // GPIO101 Master CPU Select +#define GPIO_GPDCSEL1_GPIO102_S 24U +#define GPIO_GPDCSEL1_GPIO102_M 0xF000000U // GPIO102 Master CPU Select +#define GPIO_GPDCSEL1_GPIO103_S 28U +#define GPIO_GPDCSEL1_GPIO103_M 0xF0000000U // GPIO103 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL2_GPIO104_S 0U +#define GPIO_GPDCSEL2_GPIO104_M 0xFU // GPIO104 Master CPU Select +#define GPIO_GPDCSEL2_GPIO105_S 4U +#define GPIO_GPDCSEL2_GPIO105_M 0xF0U // GPIO105 Master CPU Select +#define GPIO_GPDCSEL2_GPIO106_S 8U +#define GPIO_GPDCSEL2_GPIO106_M 0xF00U // GPIO106 Master CPU Select +#define GPIO_GPDCSEL2_GPIO107_S 12U +#define GPIO_GPDCSEL2_GPIO107_M 0xF000U // GPIO107 Master CPU Select +#define GPIO_GPDCSEL2_GPIO108_S 16U +#define GPIO_GPDCSEL2_GPIO108_M 0xF0000U // GPIO108 Master CPU Select +#define GPIO_GPDCSEL2_GPIO109_S 20U +#define GPIO_GPDCSEL2_GPIO109_M 0xF00000U // GPIO109 Master CPU Select +#define GPIO_GPDCSEL2_GPIO110_S 24U +#define GPIO_GPDCSEL2_GPIO110_M 0xF000000U // GPIO110 Master CPU Select +#define GPIO_GPDCSEL2_GPIO111_S 28U +#define GPIO_GPDCSEL2_GPIO111_M 0xF0000000U // GPIO111 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL3 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL3_GPIO112_S 0U +#define GPIO_GPDCSEL3_GPIO112_M 0xFU // GPIO112 Master CPU Select +#define GPIO_GPDCSEL3_GPIO113_S 4U +#define GPIO_GPDCSEL3_GPIO113_M 0xF0U // GPIO113 Master CPU Select +#define GPIO_GPDCSEL3_GPIO114_S 8U +#define GPIO_GPDCSEL3_GPIO114_M 0xF00U // GPIO114 Master CPU Select +#define GPIO_GPDCSEL3_GPIO115_S 12U +#define GPIO_GPDCSEL3_GPIO115_M 0xF000U // GPIO115 Master CPU Select +#define GPIO_GPDCSEL3_GPIO116_S 16U +#define GPIO_GPDCSEL3_GPIO116_M 0xF0000U // GPIO116 Master CPU Select +#define GPIO_GPDCSEL3_GPIO117_S 20U +#define GPIO_GPDCSEL3_GPIO117_M 0xF00000U // GPIO117 Master CPU Select +#define GPIO_GPDCSEL3_GPIO118_S 24U +#define GPIO_GPDCSEL3_GPIO118_M 0xF000000U // GPIO118 Master CPU Select +#define GPIO_GPDCSEL3_GPIO119_S 28U +#define GPIO_GPDCSEL3_GPIO119_M 0xF0000000U // GPIO119 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCSEL4 register +// +//************************************************************************************************* +#define GPIO_GPDCSEL4_GPIO120_S 0U +#define GPIO_GPDCSEL4_GPIO120_M 0xFU // GPIO120 Master CPU Select +#define GPIO_GPDCSEL4_GPIO121_S 4U +#define GPIO_GPDCSEL4_GPIO121_M 0xF0U // GPIO121 Master CPU Select +#define GPIO_GPDCSEL4_GPIO122_S 8U +#define GPIO_GPDCSEL4_GPIO122_M 0xF00U // GPIO122 Master CPU Select +#define GPIO_GPDCSEL4_GPIO123_S 12U +#define GPIO_GPDCSEL4_GPIO123_M 0xF000U // GPIO123 Master CPU Select +#define GPIO_GPDCSEL4_GPIO124_S 16U +#define GPIO_GPDCSEL4_GPIO124_M 0xF0000U // GPIO124 Master CPU Select +#define GPIO_GPDCSEL4_GPIO125_S 20U +#define GPIO_GPDCSEL4_GPIO125_M 0xF00000U // GPIO125 Master CPU Select +#define GPIO_GPDCSEL4_GPIO126_S 24U +#define GPIO_GPDCSEL4_GPIO126_M 0xF000000U // GPIO126 Master CPU Select +#define GPIO_GPDCSEL4_GPIO127_S 28U +#define GPIO_GPDCSEL4_GPIO127_M 0xF0000000U // GPIO127 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDLOCK register +// +//************************************************************************************************* +#define GPIO_GPDLOCK_GPIO96 0x1U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO97 0x2U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO98 0x4U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO99 0x8U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO100 0x10U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO101 0x20U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO102 0x40U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO103 0x80U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO104 0x100U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO105 0x200U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO106 0x400U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO107 0x800U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO108 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO109 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO110 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO111 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO112 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO113 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO114 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO115 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO116 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO117 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO118 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO119 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO120 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO121 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO122 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO123 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO124 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO125 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO126 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPDLOCK_GPIO127 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCR register +// +//************************************************************************************************* +#define GPIO_GPDCR_GPIO96 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO97 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO98 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO99 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO100 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO101 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO102 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO103 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO104 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO105 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO106 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO107 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO108 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO109 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO110 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO111 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO112 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO113 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO114 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO115 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO116 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO117 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO118 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO119 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO120 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO121 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO122 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO123 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO124 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO125 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO126 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPDCR_GPIO127 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECTRL register +// +//************************************************************************************************* +#define GPIO_GPECTRL_QUALPRD0_S 0U +#define GPIO_GPECTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO128 to + // GPIO135 +#define GPIO_GPECTRL_QUALPRD1_S 8U +#define GPIO_GPECTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO136 to + // GPIO143 +#define GPIO_GPECTRL_QUALPRD2_S 16U +#define GPIO_GPECTRL_QUALPRD2_M 0xFF0000U // Qualification sampling period for GPIO144 to + // GPIO151 +#define GPIO_GPECTRL_QUALPRD3_S 24U +#define GPIO_GPECTRL_QUALPRD3_M 0xFF000000U // Qualification sampling period for GPIO152 to + // GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL1_GPIO128_S 0U +#define GPIO_GPEQSEL1_GPIO128_M 0x3U // Select input qualification type for GPIO128 +#define GPIO_GPEQSEL1_GPIO129_S 2U +#define GPIO_GPEQSEL1_GPIO129_M 0xCU // Select input qualification type for GPIO129 +#define GPIO_GPEQSEL1_GPIO130_S 4U +#define GPIO_GPEQSEL1_GPIO130_M 0x30U // Select input qualification type for GPIO130 +#define GPIO_GPEQSEL1_GPIO131_S 6U +#define GPIO_GPEQSEL1_GPIO131_M 0xC0U // Select input qualification type for GPIO131 +#define GPIO_GPEQSEL1_GPIO132_S 8U +#define GPIO_GPEQSEL1_GPIO132_M 0x300U // Select input qualification type for GPIO132 +#define GPIO_GPEQSEL1_GPIO133_S 10U +#define GPIO_GPEQSEL1_GPIO133_M 0xC00U // Select input qualification type for GPIO133 +#define GPIO_GPEQSEL1_GPIO134_S 12U +#define GPIO_GPEQSEL1_GPIO134_M 0x3000U // Select input qualification type for GPIO134 +#define GPIO_GPEQSEL1_GPIO135_S 14U +#define GPIO_GPEQSEL1_GPIO135_M 0xC000U // Select input qualification type for GPIO135 +#define GPIO_GPEQSEL1_GPIO136_S 16U +#define GPIO_GPEQSEL1_GPIO136_M 0x30000U // Select input qualification type for GPIO136 +#define GPIO_GPEQSEL1_GPIO137_S 18U +#define GPIO_GPEQSEL1_GPIO137_M 0xC0000U // Select input qualification type for GPIO137 +#define GPIO_GPEQSEL1_GPIO138_S 20U +#define GPIO_GPEQSEL1_GPIO138_M 0x300000U // Select input qualification type for GPIO138 +#define GPIO_GPEQSEL1_GPIO139_S 22U +#define GPIO_GPEQSEL1_GPIO139_M 0xC00000U // Select input qualification type for GPIO139 +#define GPIO_GPEQSEL1_GPIO140_S 24U +#define GPIO_GPEQSEL1_GPIO140_M 0x3000000U // Select input qualification type for GPIO140 +#define GPIO_GPEQSEL1_GPIO141_S 26U +#define GPIO_GPEQSEL1_GPIO141_M 0xC000000U // Select input qualification type for GPIO141 +#define GPIO_GPEQSEL1_GPIO142_S 28U +#define GPIO_GPEQSEL1_GPIO142_M 0x30000000U // Select input qualification type for GPIO142 +#define GPIO_GPEQSEL1_GPIO143_S 30U +#define GPIO_GPEQSEL1_GPIO143_M 0xC0000000U // Select input qualification type for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEQSEL2 register +// +//************************************************************************************************* +#define GPIO_GPEQSEL2_GPIO144_S 0U +#define GPIO_GPEQSEL2_GPIO144_M 0x3U // Select input qualification type for GPIO144 +#define GPIO_GPEQSEL2_GPIO145_S 2U +#define GPIO_GPEQSEL2_GPIO145_M 0xCU // Select input qualification type for GPIO145 +#define GPIO_GPEQSEL2_GPIO146_S 4U +#define GPIO_GPEQSEL2_GPIO146_M 0x30U // Select input qualification type for GPIO146 +#define GPIO_GPEQSEL2_GPIO147_S 6U +#define GPIO_GPEQSEL2_GPIO147_M 0xC0U // Select input qualification type for GPIO147 +#define GPIO_GPEQSEL2_GPIO148_S 8U +#define GPIO_GPEQSEL2_GPIO148_M 0x300U // Select input qualification type for GPIO148 +#define GPIO_GPEQSEL2_GPIO149_S 10U +#define GPIO_GPEQSEL2_GPIO149_M 0xC00U // Select input qualification type for GPIO149 +#define GPIO_GPEQSEL2_GPIO150_S 12U +#define GPIO_GPEQSEL2_GPIO150_M 0x3000U // Select input qualification type for GPIO150 +#define GPIO_GPEQSEL2_GPIO151_S 14U +#define GPIO_GPEQSEL2_GPIO151_M 0xC000U // Select input qualification type for GPIO151 +#define GPIO_GPEQSEL2_GPIO152_S 16U +#define GPIO_GPEQSEL2_GPIO152_M 0x30000U // Select input qualification type for GPIO152 +#define GPIO_GPEQSEL2_GPIO153_S 18U +#define GPIO_GPEQSEL2_GPIO153_M 0xC0000U // Select input qualification type for GPIO153 +#define GPIO_GPEQSEL2_GPIO154_S 20U +#define GPIO_GPEQSEL2_GPIO154_M 0x300000U // Select input qualification type for GPIO154 +#define GPIO_GPEQSEL2_GPIO155_S 22U +#define GPIO_GPEQSEL2_GPIO155_M 0xC00000U // Select input qualification type for GPIO155 +#define GPIO_GPEQSEL2_GPIO156_S 24U +#define GPIO_GPEQSEL2_GPIO156_M 0x3000000U // Select input qualification type for GPIO156 +#define GPIO_GPEQSEL2_GPIO157_S 26U +#define GPIO_GPEQSEL2_GPIO157_M 0xC000000U // Select input qualification type for GPIO157 +#define GPIO_GPEQSEL2_GPIO158_S 28U +#define GPIO_GPEQSEL2_GPIO158_M 0x30000000U // Select input qualification type for GPIO158 +#define GPIO_GPEQSEL2_GPIO159_S 30U +#define GPIO_GPEQSEL2_GPIO159_M 0xC0000000U // Select input qualification type for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEMUX1_GPIO128_S 0U +#define GPIO_GPEMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEMUX1_GPIO129_S 2U +#define GPIO_GPEMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEMUX1_GPIO130_S 4U +#define GPIO_GPEMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEMUX1_GPIO131_S 6U +#define GPIO_GPEMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEMUX1_GPIO132_S 8U +#define GPIO_GPEMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEMUX1_GPIO133_S 10U +#define GPIO_GPEMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEMUX1_GPIO134_S 12U +#define GPIO_GPEMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEMUX1_GPIO135_S 14U +#define GPIO_GPEMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEMUX1_GPIO136_S 16U +#define GPIO_GPEMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEMUX1_GPIO137_S 18U +#define GPIO_GPEMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEMUX1_GPIO138_S 20U +#define GPIO_GPEMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEMUX1_GPIO139_S 22U +#define GPIO_GPEMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEMUX1_GPIO140_S 24U +#define GPIO_GPEMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEMUX1_GPIO141_S 26U +#define GPIO_GPEMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEMUX1_GPIO142_S 28U +#define GPIO_GPEMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEMUX1_GPIO143_S 30U +#define GPIO_GPEMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEMUX2_GPIO144_S 0U +#define GPIO_GPEMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEMUX2_GPIO145_S 2U +#define GPIO_GPEMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEMUX2_GPIO146_S 4U +#define GPIO_GPEMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEMUX2_GPIO147_S 6U +#define GPIO_GPEMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEMUX2_GPIO148_S 8U +#define GPIO_GPEMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEMUX2_GPIO149_S 10U +#define GPIO_GPEMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEMUX2_GPIO150_S 12U +#define GPIO_GPEMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEMUX2_GPIO151_S 14U +#define GPIO_GPEMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEMUX2_GPIO152_S 16U +#define GPIO_GPEMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEMUX2_GPIO153_S 18U +#define GPIO_GPEMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEMUX2_GPIO154_S 20U +#define GPIO_GPEMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEMUX2_GPIO155_S 22U +#define GPIO_GPEMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEMUX2_GPIO156_S 24U +#define GPIO_GPEMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEMUX2_GPIO157_S 26U +#define GPIO_GPEMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEMUX2_GPIO158_S 28U +#define GPIO_GPEMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEMUX2_GPIO159_S 30U +#define GPIO_GPEMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDIR register +// +//************************************************************************************************* +#define GPIO_GPEDIR_GPIO128 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO129 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO130 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO131 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO132 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO133 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO134 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO135 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO136 0x100U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO137 0x200U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO138 0x400U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO139 0x800U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO140 0x1000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO141 0x2000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO142 0x4000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO143 0x8000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO144 0x10000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO145 0x20000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO146 0x40000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO147 0x80000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO148 0x100000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO149 0x200000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO150 0x400000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO151 0x800000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO152 0x1000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO153 0x2000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO154 0x4000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO155 0x8000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO156 0x10000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO157 0x20000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO158 0x40000000U // Defines direction for this pin in GPIO mode +#define GPIO_GPEDIR_GPIO159 0x80000000U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEPUD register +// +//************************************************************************************************* +#define GPIO_GPEPUD_GPIO128 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO129 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO130 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO131 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO132 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO133 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO134 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO135 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO136 0x100U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO137 0x200U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO138 0x400U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO139 0x800U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO140 0x1000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO141 0x2000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO142 0x4000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO143 0x8000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO144 0x10000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO145 0x20000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO146 0x40000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO147 0x80000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO148 0x100000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO149 0x200000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO150 0x400000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO151 0x800000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO152 0x1000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO153 0x2000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO154 0x4000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO155 0x8000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO156 0x10000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO157 0x20000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO158 0x40000000U // Pull-Up Disable control for this pin +#define GPIO_GPEPUD_GPIO159 0x80000000U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEINV register +// +//************************************************************************************************* +#define GPIO_GPEINV_GPIO128 0x1U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO129 0x2U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO130 0x4U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO131 0x8U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO132 0x10U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO133 0x20U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO134 0x40U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO135 0x80U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO136 0x100U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO137 0x200U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO138 0x400U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO139 0x800U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO140 0x1000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO141 0x2000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO142 0x4000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO143 0x8000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO144 0x10000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO145 0x20000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO146 0x40000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO147 0x80000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO148 0x100000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO149 0x200000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO150 0x400000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO151 0x800000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO152 0x1000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO153 0x2000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO154 0x4000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO155 0x8000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO156 0x10000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO157 0x20000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO158 0x40000000U // Input inversion control for this pin +#define GPIO_GPEINV_GPIO159 0x80000000U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEODR register +// +//************************************************************************************************* +#define GPIO_GPEODR_GPIO128 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO129 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO130 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO131 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO132 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO133 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO134 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO135 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO136 0x100U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO137 0x200U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO138 0x400U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO139 0x800U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO140 0x1000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO141 0x2000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO142 0x4000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO143 0x8000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO144 0x10000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO145 0x20000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO146 0x40000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO147 0x80000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO148 0x100000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO149 0x200000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO150 0x400000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO151 0x800000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO152 0x1000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO153 0x2000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO154 0x4000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO155 0x8000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO156 0x10000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO157 0x20000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO158 0x40000000U // Outpout Open-Drain control for this pin +#define GPIO_GPEODR_GPIO159 0x80000000U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX1_GPIO128_S 0U +#define GPIO_GPEGMUX1_GPIO128_M 0x3U // Defines pin-muxing selection for GPIO128 +#define GPIO_GPEGMUX1_GPIO129_S 2U +#define GPIO_GPEGMUX1_GPIO129_M 0xCU // Defines pin-muxing selection for GPIO129 +#define GPIO_GPEGMUX1_GPIO130_S 4U +#define GPIO_GPEGMUX1_GPIO130_M 0x30U // Defines pin-muxing selection for GPIO130 +#define GPIO_GPEGMUX1_GPIO131_S 6U +#define GPIO_GPEGMUX1_GPIO131_M 0xC0U // Defines pin-muxing selection for GPIO131 +#define GPIO_GPEGMUX1_GPIO132_S 8U +#define GPIO_GPEGMUX1_GPIO132_M 0x300U // Defines pin-muxing selection for GPIO132 +#define GPIO_GPEGMUX1_GPIO133_S 10U +#define GPIO_GPEGMUX1_GPIO133_M 0xC00U // Defines pin-muxing selection for GPIO133 +#define GPIO_GPEGMUX1_GPIO134_S 12U +#define GPIO_GPEGMUX1_GPIO134_M 0x3000U // Defines pin-muxing selection for GPIO134 +#define GPIO_GPEGMUX1_GPIO135_S 14U +#define GPIO_GPEGMUX1_GPIO135_M 0xC000U // Defines pin-muxing selection for GPIO135 +#define GPIO_GPEGMUX1_GPIO136_S 16U +#define GPIO_GPEGMUX1_GPIO136_M 0x30000U // Defines pin-muxing selection for GPIO136 +#define GPIO_GPEGMUX1_GPIO137_S 18U +#define GPIO_GPEGMUX1_GPIO137_M 0xC0000U // Defines pin-muxing selection for GPIO137 +#define GPIO_GPEGMUX1_GPIO138_S 20U +#define GPIO_GPEGMUX1_GPIO138_M 0x300000U // Defines pin-muxing selection for GPIO138 +#define GPIO_GPEGMUX1_GPIO139_S 22U +#define GPIO_GPEGMUX1_GPIO139_M 0xC00000U // Defines pin-muxing selection for GPIO139 +#define GPIO_GPEGMUX1_GPIO140_S 24U +#define GPIO_GPEGMUX1_GPIO140_M 0x3000000U // Defines pin-muxing selection for GPIO140 +#define GPIO_GPEGMUX1_GPIO141_S 26U +#define GPIO_GPEGMUX1_GPIO141_M 0xC000000U // Defines pin-muxing selection for GPIO141 +#define GPIO_GPEGMUX1_GPIO142_S 28U +#define GPIO_GPEGMUX1_GPIO142_M 0x30000000U // Defines pin-muxing selection for GPIO142 +#define GPIO_GPEGMUX1_GPIO143_S 30U +#define GPIO_GPEGMUX1_GPIO143_M 0xC0000000U // Defines pin-muxing selection for GPIO143 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEGMUX2 register +// +//************************************************************************************************* +#define GPIO_GPEGMUX2_GPIO144_S 0U +#define GPIO_GPEGMUX2_GPIO144_M 0x3U // Defines pin-muxing selection for GPIO144 +#define GPIO_GPEGMUX2_GPIO145_S 2U +#define GPIO_GPEGMUX2_GPIO145_M 0xCU // Defines pin-muxing selection for GPIO145 +#define GPIO_GPEGMUX2_GPIO146_S 4U +#define GPIO_GPEGMUX2_GPIO146_M 0x30U // Defines pin-muxing selection for GPIO146 +#define GPIO_GPEGMUX2_GPIO147_S 6U +#define GPIO_GPEGMUX2_GPIO147_M 0xC0U // Defines pin-muxing selection for GPIO147 +#define GPIO_GPEGMUX2_GPIO148_S 8U +#define GPIO_GPEGMUX2_GPIO148_M 0x300U // Defines pin-muxing selection for GPIO148 +#define GPIO_GPEGMUX2_GPIO149_S 10U +#define GPIO_GPEGMUX2_GPIO149_M 0xC00U // Defines pin-muxing selection for GPIO149 +#define GPIO_GPEGMUX2_GPIO150_S 12U +#define GPIO_GPEGMUX2_GPIO150_M 0x3000U // Defines pin-muxing selection for GPIO150 +#define GPIO_GPEGMUX2_GPIO151_S 14U +#define GPIO_GPEGMUX2_GPIO151_M 0xC000U // Defines pin-muxing selection for GPIO151 +#define GPIO_GPEGMUX2_GPIO152_S 16U +#define GPIO_GPEGMUX2_GPIO152_M 0x30000U // Defines pin-muxing selection for GPIO152 +#define GPIO_GPEGMUX2_GPIO153_S 18U +#define GPIO_GPEGMUX2_GPIO153_M 0xC0000U // Defines pin-muxing selection for GPIO153 +#define GPIO_GPEGMUX2_GPIO154_S 20U +#define GPIO_GPEGMUX2_GPIO154_M 0x300000U // Defines pin-muxing selection for GPIO154 +#define GPIO_GPEGMUX2_GPIO155_S 22U +#define GPIO_GPEGMUX2_GPIO155_M 0xC00000U // Defines pin-muxing selection for GPIO155 +#define GPIO_GPEGMUX2_GPIO156_S 24U +#define GPIO_GPEGMUX2_GPIO156_M 0x3000000U // Defines pin-muxing selection for GPIO156 +#define GPIO_GPEGMUX2_GPIO157_S 26U +#define GPIO_GPEGMUX2_GPIO157_M 0xC000000U // Defines pin-muxing selection for GPIO157 +#define GPIO_GPEGMUX2_GPIO158_S 28U +#define GPIO_GPEGMUX2_GPIO158_M 0x30000000U // Defines pin-muxing selection for GPIO158 +#define GPIO_GPEGMUX2_GPIO159_S 30U +#define GPIO_GPEGMUX2_GPIO159_M 0xC0000000U // Defines pin-muxing selection for GPIO159 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL1 register +// +//************************************************************************************************* +#define GPIO_GPECSEL1_GPIO128_S 0U +#define GPIO_GPECSEL1_GPIO128_M 0xFU // GPIO128 Master CPU Select +#define GPIO_GPECSEL1_GPIO129_S 4U +#define GPIO_GPECSEL1_GPIO129_M 0xF0U // GPIO129 Master CPU Select +#define GPIO_GPECSEL1_GPIO130_S 8U +#define GPIO_GPECSEL1_GPIO130_M 0xF00U // GPIO130 Master CPU Select +#define GPIO_GPECSEL1_GPIO131_S 12U +#define GPIO_GPECSEL1_GPIO131_M 0xF000U // GPIO131 Master CPU Select +#define GPIO_GPECSEL1_GPIO132_S 16U +#define GPIO_GPECSEL1_GPIO132_M 0xF0000U // GPIO132 Master CPU Select +#define GPIO_GPECSEL1_GPIO133_S 20U +#define GPIO_GPECSEL1_GPIO133_M 0xF00000U // GPIO133 Master CPU Select +#define GPIO_GPECSEL1_GPIO134_S 24U +#define GPIO_GPECSEL1_GPIO134_M 0xF000000U // GPIO134 Master CPU Select +#define GPIO_GPECSEL1_GPIO135_S 28U +#define GPIO_GPECSEL1_GPIO135_M 0xF0000000U // GPIO135 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL2 register +// +//************************************************************************************************* +#define GPIO_GPECSEL2_GPIO136_S 0U +#define GPIO_GPECSEL2_GPIO136_M 0xFU // GPIO136 Master CPU Select +#define GPIO_GPECSEL2_GPIO137_S 4U +#define GPIO_GPECSEL2_GPIO137_M 0xF0U // GPIO137 Master CPU Select +#define GPIO_GPECSEL2_GPIO138_S 8U +#define GPIO_GPECSEL2_GPIO138_M 0xF00U // GPIO138 Master CPU Select +#define GPIO_GPECSEL2_GPIO139_S 12U +#define GPIO_GPECSEL2_GPIO139_M 0xF000U // GPIO139 Master CPU Select +#define GPIO_GPECSEL2_GPIO140_S 16U +#define GPIO_GPECSEL2_GPIO140_M 0xF0000U // GPIO140 Master CPU Select +#define GPIO_GPECSEL2_GPIO141_S 20U +#define GPIO_GPECSEL2_GPIO141_M 0xF00000U // GPIO141 Master CPU Select +#define GPIO_GPECSEL2_GPIO142_S 24U +#define GPIO_GPECSEL2_GPIO142_M 0xF000000U // GPIO142 Master CPU Select +#define GPIO_GPECSEL2_GPIO143_S 28U +#define GPIO_GPECSEL2_GPIO143_M 0xF0000000U // GPIO143 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL3 register +// +//************************************************************************************************* +#define GPIO_GPECSEL3_GPIO144_S 0U +#define GPIO_GPECSEL3_GPIO144_M 0xFU // GPIO144 Master CPU Select +#define GPIO_GPECSEL3_GPIO145_S 4U +#define GPIO_GPECSEL3_GPIO145_M 0xF0U // GPIO145 Master CPU Select +#define GPIO_GPECSEL3_GPIO146_S 8U +#define GPIO_GPECSEL3_GPIO146_M 0xF00U // GPIO146 Master CPU Select +#define GPIO_GPECSEL3_GPIO147_S 12U +#define GPIO_GPECSEL3_GPIO147_M 0xF000U // GPIO147 Master CPU Select +#define GPIO_GPECSEL3_GPIO148_S 16U +#define GPIO_GPECSEL3_GPIO148_M 0xF0000U // GPIO148 Master CPU Select +#define GPIO_GPECSEL3_GPIO149_S 20U +#define GPIO_GPECSEL3_GPIO149_M 0xF00000U // GPIO149 Master CPU Select +#define GPIO_GPECSEL3_GPIO150_S 24U +#define GPIO_GPECSEL3_GPIO150_M 0xF000000U // GPIO150 Master CPU Select +#define GPIO_GPECSEL3_GPIO151_S 28U +#define GPIO_GPECSEL3_GPIO151_M 0xF0000000U // GPIO151 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECSEL4 register +// +//************************************************************************************************* +#define GPIO_GPECSEL4_GPIO152_S 0U +#define GPIO_GPECSEL4_GPIO152_M 0xFU // GPIO152 Master CPU Select +#define GPIO_GPECSEL4_GPIO153_S 4U +#define GPIO_GPECSEL4_GPIO153_M 0xF0U // GPIO153 Master CPU Select +#define GPIO_GPECSEL4_GPIO154_S 8U +#define GPIO_GPECSEL4_GPIO154_M 0xF00U // GPIO154 Master CPU Select +#define GPIO_GPECSEL4_GPIO155_S 12U +#define GPIO_GPECSEL4_GPIO155_M 0xF000U // GPIO155 Master CPU Select +#define GPIO_GPECSEL4_GPIO156_S 16U +#define GPIO_GPECSEL4_GPIO156_M 0xF0000U // GPIO156 Master CPU Select +#define GPIO_GPECSEL4_GPIO157_S 20U +#define GPIO_GPECSEL4_GPIO157_M 0xF00000U // GPIO157 Master CPU Select +#define GPIO_GPECSEL4_GPIO158_S 24U +#define GPIO_GPECSEL4_GPIO158_M 0xF000000U // GPIO158 Master CPU Select +#define GPIO_GPECSEL4_GPIO159_S 28U +#define GPIO_GPECSEL4_GPIO159_M 0xF0000000U // GPIO159 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPELOCK register +// +//************************************************************************************************* +#define GPIO_GPELOCK_GPIO128 0x1U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO129 0x2U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO130 0x4U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO131 0x8U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO132 0x10U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO133 0x20U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO134 0x40U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO135 0x80U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO136 0x100U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO137 0x200U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO138 0x400U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO139 0x800U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO140 0x1000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO141 0x2000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO142 0x4000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO143 0x8000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO144 0x10000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO145 0x20000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO146 0x40000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO147 0x80000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO148 0x100000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO149 0x200000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO150 0x400000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO151 0x800000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO152 0x1000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO153 0x2000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO154 0x4000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO155 0x8000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO156 0x10000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO157 0x20000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO158 0x40000000U // Configuration Lock bit for this pin +#define GPIO_GPELOCK_GPIO159 0x80000000U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECR register +// +//************************************************************************************************* +#define GPIO_GPECR_GPIO128 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO129 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO130 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO131 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO132 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO133 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO134 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO135 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO136 0x100U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO137 0x200U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO138 0x400U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO139 0x800U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO140 0x1000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO141 0x2000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO142 0x4000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO143 0x8000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO144 0x10000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO145 0x20000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO146 0x40000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO147 0x80000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO148 0x100000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO149 0x200000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO150 0x400000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO151 0x800000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO152 0x1000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO153 0x2000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO154 0x4000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO155 0x8000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO156 0x10000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO157 0x20000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO158 0x40000000U // Configuration lock commit bit for this pin +#define GPIO_GPECR_GPIO159 0x80000000U // Configuration lock commit bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCTRL register +// +//************************************************************************************************* +#define GPIO_GPFCTRL_QUALPRD0_S 0U +#define GPIO_GPFCTRL_QUALPRD0_M 0xFFU // Qualification sampling period for GPIO160 to GPIO167 +#define GPIO_GPFCTRL_QUALPRD1_S 8U +#define GPIO_GPFCTRL_QUALPRD1_M 0xFF00U // Qualification sampling period for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFQSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFQSEL1_GPIO160_S 0U +#define GPIO_GPFQSEL1_GPIO160_M 0x3U // Select input qualification type for GPIO160 +#define GPIO_GPFQSEL1_GPIO161_S 2U +#define GPIO_GPFQSEL1_GPIO161_M 0xCU // Select input qualification type for GPIO161 +#define GPIO_GPFQSEL1_GPIO162_S 4U +#define GPIO_GPFQSEL1_GPIO162_M 0x30U // Select input qualification type for GPIO162 +#define GPIO_GPFQSEL1_GPIO163_S 6U +#define GPIO_GPFQSEL1_GPIO163_M 0xC0U // Select input qualification type for GPIO163 +#define GPIO_GPFQSEL1_GPIO164_S 8U +#define GPIO_GPFQSEL1_GPIO164_M 0x300U // Select input qualification type for GPIO164 +#define GPIO_GPFQSEL1_GPIO165_S 10U +#define GPIO_GPFQSEL1_GPIO165_M 0xC00U // Select input qualification type for GPIO165 +#define GPIO_GPFQSEL1_GPIO166_S 12U +#define GPIO_GPFQSEL1_GPIO166_M 0x3000U // Select input qualification type for GPIO166 +#define GPIO_GPFQSEL1_GPIO167_S 14U +#define GPIO_GPFQSEL1_GPIO167_M 0xC000U // Select input qualification type for GPIO167 +#define GPIO_GPFQSEL1_GPIO168_S 16U +#define GPIO_GPFQSEL1_GPIO168_M 0x30000U // Select input qualification type for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFMUX1_GPIO160_S 0U +#define GPIO_GPFMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFMUX1_GPIO161_S 2U +#define GPIO_GPFMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFMUX1_GPIO162_S 4U +#define GPIO_GPFMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFMUX1_GPIO163_S 6U +#define GPIO_GPFMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFMUX1_GPIO164_S 8U +#define GPIO_GPFMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFMUX1_GPIO165_S 10U +#define GPIO_GPFMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFMUX1_GPIO166_S 12U +#define GPIO_GPFMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFMUX1_GPIO167_S 14U +#define GPIO_GPFMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFMUX1_GPIO168_S 16U +#define GPIO_GPFMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDIR register +// +//************************************************************************************************* +#define GPIO_GPFDIR_GPIO160 0x1U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO161 0x2U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO162 0x4U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO163 0x8U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO164 0x10U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO165 0x20U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO166 0x40U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO167 0x80U // Defines direction for this pin in GPIO mode +#define GPIO_GPFDIR_GPIO168 0x100U // Defines direction for this pin in GPIO mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFPUD register +// +//************************************************************************************************* +#define GPIO_GPFPUD_GPIO160 0x1U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO161 0x2U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO162 0x4U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO163 0x8U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO164 0x10U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO165 0x20U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO166 0x40U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO167 0x80U // Pull-Up Disable control for this pin +#define GPIO_GPFPUD_GPIO168 0x100U // Pull-Up Disable control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFINV register +// +//************************************************************************************************* +#define GPIO_GPFINV_GPIO160 0x1U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO161 0x2U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO162 0x4U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO163 0x8U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO164 0x10U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO165 0x20U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO166 0x40U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO167 0x80U // Input inversion control for this pin +#define GPIO_GPFINV_GPIO168 0x100U // Input inversion control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFODR register +// +//************************************************************************************************* +#define GPIO_GPFODR_GPIO160 0x1U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO161 0x2U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO162 0x4U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO163 0x8U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO164 0x10U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO165 0x20U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO166 0x40U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO167 0x80U // Outpout Open-Drain control for this pin +#define GPIO_GPFODR_GPIO168 0x100U // Outpout Open-Drain control for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFGMUX1 register +// +//************************************************************************************************* +#define GPIO_GPFGMUX1_GPIO160_S 0U +#define GPIO_GPFGMUX1_GPIO160_M 0x3U // Defines pin-muxing selection for GPIO160 +#define GPIO_GPFGMUX1_GPIO161_S 2U +#define GPIO_GPFGMUX1_GPIO161_M 0xCU // Defines pin-muxing selection for GPIO161 +#define GPIO_GPFGMUX1_GPIO162_S 4U +#define GPIO_GPFGMUX1_GPIO162_M 0x30U // Defines pin-muxing selection for GPIO162 +#define GPIO_GPFGMUX1_GPIO163_S 6U +#define GPIO_GPFGMUX1_GPIO163_M 0xC0U // Defines pin-muxing selection for GPIO163 +#define GPIO_GPFGMUX1_GPIO164_S 8U +#define GPIO_GPFGMUX1_GPIO164_M 0x300U // Defines pin-muxing selection for GPIO164 +#define GPIO_GPFGMUX1_GPIO165_S 10U +#define GPIO_GPFGMUX1_GPIO165_M 0xC00U // Defines pin-muxing selection for GPIO165 +#define GPIO_GPFGMUX1_GPIO166_S 12U +#define GPIO_GPFGMUX1_GPIO166_M 0x3000U // Defines pin-muxing selection for GPIO166 +#define GPIO_GPFGMUX1_GPIO167_S 14U +#define GPIO_GPFGMUX1_GPIO167_M 0xC000U // Defines pin-muxing selection for GPIO167 +#define GPIO_GPFGMUX1_GPIO168_S 16U +#define GPIO_GPFGMUX1_GPIO168_M 0x30000U // Defines pin-muxing selection for GPIO168 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL1 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL1_GPIO160_S 0U +#define GPIO_GPFCSEL1_GPIO160_M 0xFU // GPIO160 Master CPU Select +#define GPIO_GPFCSEL1_GPIO161_S 4U +#define GPIO_GPFCSEL1_GPIO161_M 0xF0U // GPIO161 Master CPU Select +#define GPIO_GPFCSEL1_GPIO162_S 8U +#define GPIO_GPFCSEL1_GPIO162_M 0xF00U // GPIO162 Master CPU Select +#define GPIO_GPFCSEL1_GPIO163_S 12U +#define GPIO_GPFCSEL1_GPIO163_M 0xF000U // GPIO163 Master CPU Select +#define GPIO_GPFCSEL1_GPIO164_S 16U +#define GPIO_GPFCSEL1_GPIO164_M 0xF0000U // GPIO164 Master CPU Select +#define GPIO_GPFCSEL1_GPIO165_S 20U +#define GPIO_GPFCSEL1_GPIO165_M 0xF00000U // GPIO165 Master CPU Select +#define GPIO_GPFCSEL1_GPIO166_S 24U +#define GPIO_GPFCSEL1_GPIO166_M 0xF000000U // GPIO166 Master CPU Select +#define GPIO_GPFCSEL1_GPIO167_S 28U +#define GPIO_GPFCSEL1_GPIO167_M 0xF0000000U // GPIO167 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCSEL2 register +// +//************************************************************************************************* +#define GPIO_GPFCSEL2_GPIO168_S 0U +#define GPIO_GPFCSEL2_GPIO168_M 0xFU // GPIO168 Master CPU Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFLOCK register +// +//************************************************************************************************* +#define GPIO_GPFLOCK_GPIO160 0x1U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO161 0x2U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO162 0x4U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO163 0x8U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO164 0x10U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO165 0x20U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO166 0x40U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO167 0x80U // Configuration Lock bit for this pin +#define GPIO_GPFLOCK_GPIO168 0x100U // Configuration Lock bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCR register +// +//************************************************************************************************* +#define GPIO_GPFCR_GPIO160 0x1U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO161 0x2U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO162 0x4U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO163 0x8U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO164 0x10U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO165 0x20U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO166 0x40U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO167 0x80U // Configuration lock commit bit for this pin +#define GPIO_GPFCR_GPIO168 0x100U // Configuration lock commit bit for this pin + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPADAT register +// +//************************************************************************************************* +#define GPIO_GPADAT_GPIO0 0x1U // Data Register for this pin +#define GPIO_GPADAT_GPIO1 0x2U // Data Register for this pin +#define GPIO_GPADAT_GPIO2 0x4U // Data Register for this pin +#define GPIO_GPADAT_GPIO3 0x8U // Data Register for this pin +#define GPIO_GPADAT_GPIO4 0x10U // Data Register for this pin +#define GPIO_GPADAT_GPIO5 0x20U // Data Register for this pin +#define GPIO_GPADAT_GPIO6 0x40U // Data Register for this pin +#define GPIO_GPADAT_GPIO7 0x80U // Data Register for this pin +#define GPIO_GPADAT_GPIO8 0x100U // Data Register for this pin +#define GPIO_GPADAT_GPIO9 0x200U // Data Register for this pin +#define GPIO_GPADAT_GPIO10 0x400U // Data Register for this pin +#define GPIO_GPADAT_GPIO11 0x800U // Data Register for this pin +#define GPIO_GPADAT_GPIO12 0x1000U // Data Register for this pin +#define GPIO_GPADAT_GPIO13 0x2000U // Data Register for this pin +#define GPIO_GPADAT_GPIO14 0x4000U // Data Register for this pin +#define GPIO_GPADAT_GPIO15 0x8000U // Data Register for this pin +#define GPIO_GPADAT_GPIO16 0x10000U // Data Register for this pin +#define GPIO_GPADAT_GPIO17 0x20000U // Data Register for this pin +#define GPIO_GPADAT_GPIO18 0x40000U // Data Register for this pin +#define GPIO_GPADAT_GPIO19 0x80000U // Data Register for this pin +#define GPIO_GPADAT_GPIO20 0x100000U // Data Register for this pin +#define GPIO_GPADAT_GPIO21 0x200000U // Data Register for this pin +#define GPIO_GPADAT_GPIO22 0x400000U // Data Register for this pin +#define GPIO_GPADAT_GPIO23 0x800000U // Data Register for this pin +#define GPIO_GPADAT_GPIO24 0x1000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO25 0x2000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO26 0x4000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO27 0x8000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO28 0x10000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO29 0x20000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO30 0x40000000U // Data Register for this pin +#define GPIO_GPADAT_GPIO31 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPASET register +// +//************************************************************************************************* +#define GPIO_GPASET_GPIO0 0x1U // Output Set bit for this pin +#define GPIO_GPASET_GPIO1 0x2U // Output Set bit for this pin +#define GPIO_GPASET_GPIO2 0x4U // Output Set bit for this pin +#define GPIO_GPASET_GPIO3 0x8U // Output Set bit for this pin +#define GPIO_GPASET_GPIO4 0x10U // Output Set bit for this pin +#define GPIO_GPASET_GPIO5 0x20U // Output Set bit for this pin +#define GPIO_GPASET_GPIO6 0x40U // Output Set bit for this pin +#define GPIO_GPASET_GPIO7 0x80U // Output Set bit for this pin +#define GPIO_GPASET_GPIO8 0x100U // Output Set bit for this pin +#define GPIO_GPASET_GPIO9 0x200U // Output Set bit for this pin +#define GPIO_GPASET_GPIO10 0x400U // Output Set bit for this pin +#define GPIO_GPASET_GPIO11 0x800U // Output Set bit for this pin +#define GPIO_GPASET_GPIO12 0x1000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO13 0x2000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO14 0x4000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO15 0x8000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO16 0x10000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO17 0x20000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO18 0x40000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO19 0x80000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO20 0x100000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO21 0x200000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO22 0x400000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO23 0x800000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO24 0x1000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO25 0x2000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO26 0x4000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO27 0x8000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO28 0x10000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO29 0x20000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO30 0x40000000U // Output Set bit for this pin +#define GPIO_GPASET_GPIO31 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPACLEAR register +// +//************************************************************************************************* +#define GPIO_GPACLEAR_GPIO0 0x1U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO1 0x2U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO2 0x4U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO3 0x8U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO4 0x10U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO5 0x20U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO6 0x40U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO7 0x80U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO8 0x100U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO9 0x200U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO10 0x400U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO11 0x800U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO12 0x1000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO13 0x2000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO14 0x4000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO15 0x8000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO16 0x10000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO17 0x20000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO18 0x40000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO19 0x80000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO20 0x100000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO21 0x200000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO22 0x400000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO23 0x800000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO24 0x1000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO25 0x2000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO26 0x4000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO27 0x8000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO28 0x10000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO29 0x20000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO30 0x40000000U // Output Clear bit for this pin +#define GPIO_GPACLEAR_GPIO31 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPATOGGLE register +// +//************************************************************************************************* +#define GPIO_GPATOGGLE_GPIO0 0x1U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO1 0x2U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO2 0x4U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO3 0x8U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO4 0x10U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO5 0x20U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO6 0x40U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO7 0x80U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO8 0x100U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO9 0x200U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO10 0x400U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO11 0x800U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO12 0x1000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO13 0x2000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO14 0x4000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO15 0x8000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO16 0x10000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO17 0x20000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO18 0x40000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO19 0x80000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO20 0x100000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO21 0x200000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO22 0x400000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO23 0x800000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO24 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO25 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO26 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO27 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO28 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO29 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO30 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPATOGGLE_GPIO31 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBDAT register +// +//************************************************************************************************* +#define GPIO_GPBDAT_GPIO32 0x1U // Data Register for this pin +#define GPIO_GPBDAT_GPIO33 0x2U // Data Register for this pin +#define GPIO_GPBDAT_GPIO34 0x4U // Data Register for this pin +#define GPIO_GPBDAT_GPIO35 0x8U // Data Register for this pin +#define GPIO_GPBDAT_GPIO36 0x10U // Data Register for this pin +#define GPIO_GPBDAT_GPIO37 0x20U // Data Register for this pin +#define GPIO_GPBDAT_GPIO38 0x40U // Data Register for this pin +#define GPIO_GPBDAT_GPIO39 0x80U // Data Register for this pin +#define GPIO_GPBDAT_GPIO40 0x100U // Data Register for this pin +#define GPIO_GPBDAT_GPIO41 0x200U // Data Register for this pin +#define GPIO_GPBDAT_GPIO42 0x400U // Data Register for this pin +#define GPIO_GPBDAT_GPIO43 0x800U // Data Register for this pin +#define GPIO_GPBDAT_GPIO44 0x1000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO45 0x2000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO46 0x4000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO47 0x8000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO48 0x10000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO49 0x20000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO50 0x40000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO51 0x80000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO52 0x100000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO53 0x200000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO54 0x400000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO55 0x800000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO56 0x1000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO57 0x2000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO58 0x4000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO59 0x8000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO60 0x10000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO61 0x20000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO62 0x40000000U // Data Register for this pin +#define GPIO_GPBDAT_GPIO63 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBSET register +// +//************************************************************************************************* +#define GPIO_GPBSET_GPIO32 0x1U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO33 0x2U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO34 0x4U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO35 0x8U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO36 0x10U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO37 0x20U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO38 0x40U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO39 0x80U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO40 0x100U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO41 0x200U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO42 0x400U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO43 0x800U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO44 0x1000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO45 0x2000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO46 0x4000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO47 0x8000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO48 0x10000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO49 0x20000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO50 0x40000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO51 0x80000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO52 0x100000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO53 0x200000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO54 0x400000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO55 0x800000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO56 0x1000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO57 0x2000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO58 0x4000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO59 0x8000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO60 0x10000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO61 0x20000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO62 0x40000000U // Output Set bit for this pin +#define GPIO_GPBSET_GPIO63 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBCLEAR register +// +//************************************************************************************************* +#define GPIO_GPBCLEAR_GPIO32 0x1U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO33 0x2U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO34 0x4U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO35 0x8U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO36 0x10U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO37 0x20U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO38 0x40U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO39 0x80U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO40 0x100U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO41 0x200U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO42 0x400U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO43 0x800U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO44 0x1000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO45 0x2000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO46 0x4000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO47 0x8000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO48 0x10000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO49 0x20000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO50 0x40000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO51 0x80000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO52 0x100000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO53 0x200000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO54 0x400000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO55 0x800000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO56 0x1000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO57 0x2000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO58 0x4000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO59 0x8000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO60 0x10000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO61 0x20000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO62 0x40000000U // Output Clear bit for this pin +#define GPIO_GPBCLEAR_GPIO63 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPBTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPBTOGGLE_GPIO32 0x1U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO33 0x2U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO34 0x4U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO35 0x8U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO36 0x10U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO37 0x20U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO38 0x40U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO39 0x80U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO40 0x100U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO41 0x200U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO42 0x400U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO43 0x800U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO44 0x1000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO45 0x2000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO46 0x4000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO47 0x8000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO48 0x10000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO49 0x20000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO50 0x40000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO51 0x80000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO52 0x100000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO53 0x200000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO54 0x400000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO55 0x800000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO56 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO57 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO58 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO59 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO60 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO61 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO62 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPBTOGGLE_GPIO63 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCDAT register +// +//************************************************************************************************* +#define GPIO_GPCDAT_GPIO64 0x1U // Data Register for this pin +#define GPIO_GPCDAT_GPIO65 0x2U // Data Register for this pin +#define GPIO_GPCDAT_GPIO66 0x4U // Data Register for this pin +#define GPIO_GPCDAT_GPIO67 0x8U // Data Register for this pin +#define GPIO_GPCDAT_GPIO68 0x10U // Data Register for this pin +#define GPIO_GPCDAT_GPIO69 0x20U // Data Register for this pin +#define GPIO_GPCDAT_GPIO70 0x40U // Data Register for this pin +#define GPIO_GPCDAT_GPIO71 0x80U // Data Register for this pin +#define GPIO_GPCDAT_GPIO72 0x100U // Data Register for this pin +#define GPIO_GPCDAT_GPIO73 0x200U // Data Register for this pin +#define GPIO_GPCDAT_GPIO74 0x400U // Data Register for this pin +#define GPIO_GPCDAT_GPIO75 0x800U // Data Register for this pin +#define GPIO_GPCDAT_GPIO76 0x1000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO77 0x2000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO78 0x4000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO79 0x8000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO80 0x10000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO81 0x20000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO82 0x40000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO83 0x80000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO84 0x100000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO85 0x200000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO86 0x400000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO87 0x800000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO88 0x1000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO89 0x2000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO90 0x4000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO91 0x8000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO92 0x10000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO93 0x20000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO94 0x40000000U // Data Register for this pin +#define GPIO_GPCDAT_GPIO95 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCSET register +// +//************************************************************************************************* +#define GPIO_GPCSET_GPIO64 0x1U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO65 0x2U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO66 0x4U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO67 0x8U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO68 0x10U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO69 0x20U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO70 0x40U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO71 0x80U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO72 0x100U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO73 0x200U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO74 0x400U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO75 0x800U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO76 0x1000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO77 0x2000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO78 0x4000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO79 0x8000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO80 0x10000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO81 0x20000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO82 0x40000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO83 0x80000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO84 0x100000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO85 0x200000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO86 0x400000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO87 0x800000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO88 0x1000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO89 0x2000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO90 0x4000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO91 0x8000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO92 0x10000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO93 0x20000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO94 0x40000000U // Output Set bit for this pin +#define GPIO_GPCSET_GPIO95 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCCLEAR register +// +//************************************************************************************************* +#define GPIO_GPCCLEAR_GPIO64 0x1U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO65 0x2U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO66 0x4U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO67 0x8U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO68 0x10U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO69 0x20U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO70 0x40U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO71 0x80U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO72 0x100U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO73 0x200U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO74 0x400U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO75 0x800U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO76 0x1000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO77 0x2000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO78 0x4000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO79 0x8000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO80 0x10000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO81 0x20000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO82 0x40000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO83 0x80000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO84 0x100000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO85 0x200000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO86 0x400000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO87 0x800000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO88 0x1000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO89 0x2000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO90 0x4000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO91 0x8000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO92 0x10000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO93 0x20000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO94 0x40000000U // Output Clear bit for this pin +#define GPIO_GPCCLEAR_GPIO95 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPCTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPCTOGGLE_GPIO64 0x1U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO65 0x2U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO66 0x4U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO67 0x8U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO68 0x10U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO69 0x20U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO70 0x40U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO71 0x80U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO72 0x100U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO73 0x200U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO74 0x400U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO75 0x800U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO76 0x1000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO77 0x2000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO78 0x4000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO79 0x8000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO80 0x10000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO81 0x20000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO82 0x40000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO83 0x80000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO84 0x100000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO85 0x200000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO86 0x400000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO87 0x800000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO88 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO89 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO90 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO91 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO92 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO93 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO94 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPCTOGGLE_GPIO95 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDDAT register +// +//************************************************************************************************* +#define GPIO_GPDDAT_GPIO96 0x1U // Data Register for this pin +#define GPIO_GPDDAT_GPIO97 0x2U // Data Register for this pin +#define GPIO_GPDDAT_GPIO98 0x4U // Data Register for this pin +#define GPIO_GPDDAT_GPIO99 0x8U // Data Register for this pin +#define GPIO_GPDDAT_GPIO100 0x10U // Data Register for this pin +#define GPIO_GPDDAT_GPIO101 0x20U // Data Register for this pin +#define GPIO_GPDDAT_GPIO102 0x40U // Data Register for this pin +#define GPIO_GPDDAT_GPIO103 0x80U // Data Register for this pin +#define GPIO_GPDDAT_GPIO104 0x100U // Data Register for this pin +#define GPIO_GPDDAT_GPIO105 0x200U // Data Register for this pin +#define GPIO_GPDDAT_GPIO106 0x400U // Data Register for this pin +#define GPIO_GPDDAT_GPIO107 0x800U // Data Register for this pin +#define GPIO_GPDDAT_GPIO108 0x1000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO109 0x2000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO110 0x4000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO111 0x8000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO112 0x10000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO113 0x20000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO114 0x40000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO115 0x80000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO116 0x100000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO117 0x200000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO118 0x400000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO119 0x800000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO120 0x1000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO121 0x2000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO122 0x4000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO123 0x8000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO124 0x10000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO125 0x20000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO126 0x40000000U // Data Register for this pin +#define GPIO_GPDDAT_GPIO127 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDSET register +// +//************************************************************************************************* +#define GPIO_GPDSET_GPIO96 0x1U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO97 0x2U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO98 0x4U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO99 0x8U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO100 0x10U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO101 0x20U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO102 0x40U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO103 0x80U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO104 0x100U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO105 0x200U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO106 0x400U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO107 0x800U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO108 0x1000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO109 0x2000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO110 0x4000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO111 0x8000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO112 0x10000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO113 0x20000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO114 0x40000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO115 0x80000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO116 0x100000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO117 0x200000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO118 0x400000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO119 0x800000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO120 0x1000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO121 0x2000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO122 0x4000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO123 0x8000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO124 0x10000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO125 0x20000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO126 0x40000000U // Output Set bit for this pin +#define GPIO_GPDSET_GPIO127 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDCLEAR register +// +//************************************************************************************************* +#define GPIO_GPDCLEAR_GPIO96 0x1U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO97 0x2U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO98 0x4U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO99 0x8U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO100 0x10U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO101 0x20U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO102 0x40U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO103 0x80U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO104 0x100U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO105 0x200U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO106 0x400U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO107 0x800U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO108 0x1000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO109 0x2000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO110 0x4000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO111 0x8000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO112 0x10000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO113 0x20000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO114 0x40000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO115 0x80000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO116 0x100000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO117 0x200000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO118 0x400000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO119 0x800000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO120 0x1000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO121 0x2000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO122 0x4000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO123 0x8000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO124 0x10000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO125 0x20000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO126 0x40000000U // Output Clear bit for this pin +#define GPIO_GPDCLEAR_GPIO127 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPDTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPDTOGGLE_GPIO96 0x1U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO97 0x2U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO98 0x4U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO99 0x8U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO100 0x10U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO101 0x20U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO102 0x40U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO103 0x80U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO104 0x100U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO105 0x200U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO106 0x400U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO107 0x800U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO108 0x1000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO109 0x2000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO110 0x4000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO111 0x8000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO112 0x10000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO113 0x20000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO114 0x40000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO115 0x80000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO116 0x100000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO117 0x200000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO118 0x400000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO119 0x800000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO120 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO121 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO122 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO123 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO124 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO125 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO126 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPDTOGGLE_GPIO127 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPEDAT register +// +//************************************************************************************************* +#define GPIO_GPEDAT_GPIO128 0x1U // Data Register for this pin +#define GPIO_GPEDAT_GPIO129 0x2U // Data Register for this pin +#define GPIO_GPEDAT_GPIO130 0x4U // Data Register for this pin +#define GPIO_GPEDAT_GPIO131 0x8U // Data Register for this pin +#define GPIO_GPEDAT_GPIO132 0x10U // Data Register for this pin +#define GPIO_GPEDAT_GPIO133 0x20U // Data Register for this pin +#define GPIO_GPEDAT_GPIO134 0x40U // Data Register for this pin +#define GPIO_GPEDAT_GPIO135 0x80U // Data Register for this pin +#define GPIO_GPEDAT_GPIO136 0x100U // Data Register for this pin +#define GPIO_GPEDAT_GPIO137 0x200U // Data Register for this pin +#define GPIO_GPEDAT_GPIO138 0x400U // Data Register for this pin +#define GPIO_GPEDAT_GPIO139 0x800U // Data Register for this pin +#define GPIO_GPEDAT_GPIO140 0x1000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO141 0x2000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO142 0x4000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO143 0x8000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO144 0x10000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO145 0x20000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO146 0x40000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO147 0x80000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO148 0x100000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO149 0x200000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO150 0x400000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO151 0x800000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO152 0x1000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO153 0x2000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO154 0x4000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO155 0x8000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO156 0x10000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO157 0x20000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO158 0x40000000U // Data Register for this pin +#define GPIO_GPEDAT_GPIO159 0x80000000U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPESET register +// +//************************************************************************************************* +#define GPIO_GPESET_GPIO128 0x1U // Output Set bit for this pin +#define GPIO_GPESET_GPIO129 0x2U // Output Set bit for this pin +#define GPIO_GPESET_GPIO130 0x4U // Output Set bit for this pin +#define GPIO_GPESET_GPIO131 0x8U // Output Set bit for this pin +#define GPIO_GPESET_GPIO132 0x10U // Output Set bit for this pin +#define GPIO_GPESET_GPIO133 0x20U // Output Set bit for this pin +#define GPIO_GPESET_GPIO134 0x40U // Output Set bit for this pin +#define GPIO_GPESET_GPIO135 0x80U // Output Set bit for this pin +#define GPIO_GPESET_GPIO136 0x100U // Output Set bit for this pin +#define GPIO_GPESET_GPIO137 0x200U // Output Set bit for this pin +#define GPIO_GPESET_GPIO138 0x400U // Output Set bit for this pin +#define GPIO_GPESET_GPIO139 0x800U // Output Set bit for this pin +#define GPIO_GPESET_GPIO140 0x1000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO141 0x2000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO142 0x4000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO143 0x8000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO144 0x10000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO145 0x20000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO146 0x40000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO147 0x80000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO148 0x100000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO149 0x200000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO150 0x400000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO151 0x800000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO152 0x1000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO153 0x2000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO154 0x4000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO155 0x8000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO156 0x10000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO157 0x20000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO158 0x40000000U // Output Set bit for this pin +#define GPIO_GPESET_GPIO159 0x80000000U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPECLEAR register +// +//************************************************************************************************* +#define GPIO_GPECLEAR_GPIO128 0x1U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO129 0x2U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO130 0x4U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO131 0x8U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO132 0x10U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO133 0x20U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO134 0x40U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO135 0x80U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO136 0x100U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO137 0x200U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO138 0x400U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO139 0x800U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO140 0x1000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO141 0x2000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO142 0x4000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO143 0x8000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO144 0x10000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO145 0x20000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO146 0x40000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO147 0x80000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO148 0x100000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO149 0x200000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO150 0x400000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO151 0x800000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO152 0x1000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO153 0x2000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO154 0x4000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO155 0x8000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO156 0x10000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO157 0x20000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO158 0x40000000U // Output Clear bit for this pin +#define GPIO_GPECLEAR_GPIO159 0x80000000U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPETOGGLE register +// +//************************************************************************************************* +#define GPIO_GPETOGGLE_GPIO128 0x1U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO129 0x2U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO130 0x4U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO131 0x8U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO132 0x10U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO133 0x20U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO134 0x40U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO135 0x80U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO136 0x100U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO137 0x200U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO138 0x400U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO139 0x800U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO140 0x1000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO141 0x2000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO142 0x4000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO143 0x8000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO144 0x10000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO145 0x20000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO146 0x40000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO147 0x80000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO148 0x100000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO149 0x200000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO150 0x400000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO151 0x800000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO152 0x1000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO153 0x2000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO154 0x4000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO155 0x8000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO156 0x10000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO157 0x20000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO158 0x40000000U // Output Toggle bit for this pin +#define GPIO_GPETOGGLE_GPIO159 0x80000000U // Output Toggle bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFDAT register +// +//************************************************************************************************* +#define GPIO_GPFDAT_GPIO160 0x1U // Data Register for this pin +#define GPIO_GPFDAT_GPIO161 0x2U // Data Register for this pin +#define GPIO_GPFDAT_GPIO162 0x4U // Data Register for this pin +#define GPIO_GPFDAT_GPIO163 0x8U // Data Register for this pin +#define GPIO_GPFDAT_GPIO164 0x10U // Data Register for this pin +#define GPIO_GPFDAT_GPIO165 0x20U // Data Register for this pin +#define GPIO_GPFDAT_GPIO166 0x40U // Data Register for this pin +#define GPIO_GPFDAT_GPIO167 0x80U // Data Register for this pin +#define GPIO_GPFDAT_GPIO168 0x100U // Data Register for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFSET register +// +//************************************************************************************************* +#define GPIO_GPFSET_GPIO160 0x1U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO161 0x2U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO162 0x4U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO163 0x8U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO164 0x10U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO165 0x20U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO166 0x40U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO167 0x80U // Output Set bit for this pin +#define GPIO_GPFSET_GPIO168 0x100U // Output Set bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFCLEAR register +// +//************************************************************************************************* +#define GPIO_GPFCLEAR_GPIO160 0x1U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO161 0x2U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO162 0x4U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO163 0x8U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO164 0x10U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO165 0x20U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO166 0x40U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO167 0x80U // Output Clear bit for this pin +#define GPIO_GPFCLEAR_GPIO168 0x100U // Output Clear bit for this pin + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPFTOGGLE register +// +//************************************************************************************************* +#define GPIO_GPFTOGGLE_GPIO160 0x1U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO161 0x2U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO162 0x4U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO163 0x8U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO164 0x10U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO165 0x20U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO166 0x40U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO167 0x80U // Output Toggle bit for this pin +#define GPIO_GPFTOGGLE_GPIO168 0x100U // Output Toggle bit for this pin + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_hic.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_hic.h new file mode 100644 index 0000000..07d544f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_hic.h @@ -0,0 +1,344 @@ +//########################################################################### +// +// FILE: hw_hic.h +// +// TITLE: Definitions for the HIC registers. +// +//########################################################################### +// $TI Release: $ +// $Release Date: $ +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HIC_H +#define HW_HIC_H + +//************************************************************************************************* +// +// The following are defines for the HIC register offsets +// +//************************************************************************************************* +#define HIC_O_REV 0x0U // Module Revision Register +#define HIC_O_GCR 0x2U // Global Control Register +#define HIC_O_LOCK 0x4U // Lock Register +#define HIC_O_MODECR 0x6U // Mode Control Register +#define HIC_O_PINPOLCR 0x8U // Pin Polarity Control Register +#define HIC_O_BASESEL 0xAU // Base Select Register +#define HIC_O_HOSTCR 0xCU // Host Control Register +#define HIC_O_ERRADDR 0xEU // Host Error Address register +#define HIC_O_H2DTOKEN 0x10U // Host to Device Token Register +#define HIC_O_D2HTOKEN 0x12U // Devie to Host Token Register +#define HIC_O_DBADDR0 0x14U // Device Base Address Register 0 +#define HIC_O_DBADDR1 0x16U // Device Base Address Register 1 +#define HIC_O_DBADDR2 0x18U // Device Base Address Register 2 +#define HIC_O_DBADDR3 0x1AU // Device Base Address Register 3 +#define HIC_O_DBADDR4 0x1CU // Device Base Address Register 4 +#define HIC_O_DBADDR5 0x1EU // Device Base Address Register 5 +#define HIC_O_DBADDR6 0x20U // Device Base Address Register 6 +#define HIC_O_DBADDR7 0x22U // Device Base Address Register 7 +#define HIC_O_H2DINTEN 0x28U // H2D Interrupt Enable +#define HIC_O_H2DINTFLG 0x2AU // H2D Interrupt status Flag +#define HIC_O_H2DINTCLR 0x2CU // H2D Interrupt status Clear +#define HIC_O_H2DINTFRC 0x2EU // H2D Interrupt Set Force +#define HIC_O_D2HINTEN 0x30U // D2H Interrupt Enable +#define HIC_O_D2HINTFLG 0x32U // D2H Interrupt status Flag +#define HIC_O_D2HINTCLR 0x34U // D2H Interrupt status Clear +#define HIC_O_D2HINTFRC 0x36U // D2H Interrupt Set Force +#define HIC_O_ACCVIOADDR 0x38U // Access Violation Address +#define HIC_O_H2D_BUF0 0x40U // Host to Device Buffer 0 +#define HIC_O_H2D_BUF1 0x42U // Host to Device Buffer 1 +#define HIC_O_H2D_BUF2 0x44U // Host to Device Buffer 2 +#define HIC_O_H2D_BUF3 0x46U // Host to Device Buffer 3 +#define HIC_O_H2D_BUF4 0x48U // Host to Device Buffer 4 +#define HIC_O_H2D_BUF5 0x4AU // Host to Device Buffer 5 +#define HIC_O_H2D_BUF6 0x4CU // Host to Device Buffer 6 +#define HIC_O_H2D_BUF7 0x4EU // Host to Device Buffer 7 +#define HIC_O_H2D_BUF8 0x50U // Host to Device Buffer 8 +#define HIC_O_H2D_BUF9 0x52U // Host to Device Buffer 9 +#define HIC_O_H2D_BUF10 0x54U // Host to Device Buffer 10 +#define HIC_O_H2D_BUF11 0x56U // Host to Device Buffer 11 +#define HIC_O_H2D_BUF12 0x58U // Host to Device Buffer 12 +#define HIC_O_H2D_BUF13 0x5AU // Host to Device Buffer 13 +#define HIC_O_H2D_BUF14 0x5CU // Host to Device Buffer 14 +#define HIC_O_H2D_BUF15 0x5EU // Host to Device Buffer 15 +#define HIC_O_D2H_BUF0 0x60U // Device to Host Buffer 0 +#define HIC_O_D2H_BUF1 0x62U // Device to Host Buffer 1 +#define HIC_O_D2H_BUF2 0x64U // Device to Host Buffer 2 +#define HIC_O_D2H_BUF3 0x66U // Device to Host Buffer 3 +#define HIC_O_D2H_BUF4 0x68U // Device to Host Buffer 4 +#define HIC_O_D2H_BUF5 0x6AU // Device to Host Buffer 5 +#define HIC_O_D2H_BUF6 0x6CU // Device to Host Buffer 6 +#define HIC_O_D2H_BUF7 0x6EU // Device to Host Buffer 7 +#define HIC_O_D2H_BUF8 0x70U // Device to Host Buffer 8 +#define HIC_O_D2H_BUF9 0x72U // Device to Host Buffer 9 +#define HIC_O_D2H_BUF10 0x74U // Device to Host Buffer 10 +#define HIC_O_D2H_BUF11 0x76U // Device to Host Buffer 11 +#define HIC_O_D2H_BUF12 0x78U // Device to Host Buffer 12 +#define HIC_O_D2H_BUF13 0x7AU // Device to Host Buffer 13 +#define HIC_O_D2H_BUF14 0x7CU // Device to Host Buffer 14 +#define HIC_O_D2H_BUF15 0x7EU // Device to Host Buffer 15 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICREV register +// +//************************************************************************************************* +#define HIC_REV_MINOR_S 0U +#define HIC_REV_MINOR_M 0x3FU // Minor Revision Number +#define HIC_REV_CUSTOM_S 6U +#define HIC_REV_CUSTOM_M 0xC0U // Custom Module Number +#define HIC_REV_MAJOR_S 8U +#define HIC_REV_MAJOR_M 0x700U // Major Revision Number +#define HIC_REV_RTL_S 11U +#define HIC_REV_RTL_M 0xF800U // Design Release Number +#define HIC_REV_FUNC_S 16U +#define HIC_REV_FUNC_M 0xFFF0000U // Functional Release Number +#define HIC_REV_SCHEME_S 30U +#define HIC_REV_SCHEME_M 0xC0000000U // Defines Scheme for Module +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICGCR register +// +//************************************************************************************************* +#define HIC_GCR_HICEN_S 0U +#define HIC_GCR_HICEN_M 0xFU // Host Interface Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICLOCK register +// +//************************************************************************************************* +#define HIC_LOCK_LOCK 0x1U // LOCK enable +#define HIC_LOCK_WRITE_ENABLE_KEY_S 16U +#define HIC_LOCK_WRITE_ENABLE_KEY_M 0xFFFF0000U // Key for enabling write +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICMODECR register +// +//************************************************************************************************* +#define HIC_MODECR_DW_MODE_S 0U +#define HIC_MODECR_DW_MODE_M 0x3U // Data Width Mode +#define HIC_MODECR_RW_MODE 0x10U // Read-Write Mode +#define HIC_MODECR_BEN_PRESENT 0x20U // Byte Enable Pins are present +#define HIC_MODECR_RDY_PRESENT 0x40U // Ready pin present +#define HIC_MODECR_H2DBUF_DEVWREN 0x100U // Write Enable for Device to H2D Buffer +#define HIC_MODECR_D2HBUF_HOSTWREN 0x200U // Write Enable for Host to D2H Buffer +#define HIC_MODECR_EN_DEVACC 0x400U // Enable Host access to Device region +#define HIC_MODECR_EN_HOSTWREALLOW 0x800U // Enable Host Write to EALLOWCTL register +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICPINPOLCR register +// +//************************************************************************************************* +#define HIC_PINPOLCR_CS_POL 0x1U // Chip Select Polarity +#define HIC_PINPOLCR_BEN_POL 0x2U // Byte Enable Polarity +#define HIC_PINPOLCR_OE_POL 0x4U // Output Enable Polarity +#define HIC_PINPOLCR_WE_POL 0x8U // Write Enable Polarity +#define HIC_PINPOLCR_RDY_POL 0x10U // Ready Polarity +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICBASESEL register +// +//************************************************************************************************* +#define HIC_BASESEL_BASE_SELECT_S 0U +#define HIC_BASESEL_BASE_SELECT_M 0x7U // Base Select +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICHOSTCR register +// +//************************************************************************************************* +#define HIC_HOSTCR_EALLOW_EN 0x1U // EALLOW Enable +#define HIC_HOSTCR_ACCSIZE 0x2U // Access Size +#define HIC_HOSTCR_PAGESEL 0x4U // Page Select +#define HIC_HOSTCR_HKEY_S 8U +#define HIC_HOSTCR_HKEY_M 0xFF00U // Host Key +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICERRADDR register +// +//************************************************************************************************* +#define HIC_ERRADDR_H2D_ERR_ADDR_S 0U +#define HIC_ERRADDR_H2D_ERR_ADDR_M 0xFFU // Address of the Host bus captured upon an + // error for Device +#define HIC_ERRADDR_H2D_BASE_SEL_S 12U +#define HIC_ERRADDR_H2D_BASE_SEL_M 0x7000U // Base Select corresponding to H2D error event +#define HIC_ERRADDR_D2H_ERR_ADDR_S 16U +#define HIC_ERRADDR_D2H_ERR_ADDR_M 0xFF0000U // Address of the Host bus captured upon an + // error for Host +#define HIC_ERRADDR_D2H_BASE_SEL_S 28U +#define HIC_ERRADDR_D2H_BASE_SEL_M 0x70000000U // Base Select corresponding to D2H error event +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR0 register +// +//************************************************************************************************* +#define HIC_DBADDR0_BASE_ADDR_S 7U +#define HIC_DBADDR0_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR1 register +// +//************************************************************************************************* +#define HIC_DBADDR1_BASE_ADDR_S 7U +#define HIC_DBADDR1_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR2 register +// +//************************************************************************************************* +#define HIC_DBADDR2_BASE_ADDR_S 7U +#define HIC_DBADDR2_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR3 register +// +//************************************************************************************************* +#define HIC_DBADDR3_BASE_ADDR_S 7U +#define HIC_DBADDR3_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR4 register +// +//************************************************************************************************* +#define HIC_DBADDR4_BASE_ADDR_S 7U +#define HIC_DBADDR4_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR5 register +// +//************************************************************************************************* +#define HIC_DBADDR5_BASE_ADDR_S 7U +#define HIC_DBADDR5_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR6 register +// +//************************************************************************************************* +#define HIC_DBADDR6_BASE_ADDR_S 7U +#define HIC_DBADDR6_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICDBADDR7 register +// +//************************************************************************************************* +#define HIC_DBADDR7_BASE_ADDR_S 7U +#define HIC_DBADDR7_BASE_ADDR_M 0xFFFFFF80U // Base address of device region +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTEN register +// +//************************************************************************************************* +#define HIC_H2DINTEN_H2D_INTEN 0x1U // Host To Device Interrupt Enable +#define HIC_H2DINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_H2DINTEN_ILLWR_INTEN 0x4U // Illegal Write event interrupt enable +#define HIC_H2DINTEN_ILLRD_INTEN 0x8U // Illegal Read event interrupt enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFLG register +// +//************************************************************************************************* +#define HIC_H2DINTFLG_H2D_FLG 0x1U // Host To Device Interrupt Flag +#define HIC_H2DINTFLG_BUSERR_FLG 0x2U // BusError Interrupt Flag +#define HIC_H2DINTFLG_ILLWR_FLG 0x4U // Illegal write event interrupt flag +#define HIC_H2DINTFLG_ILLRD_FLG 0x8U // Illegal read event interrupt flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTCLR register +// +//************************************************************************************************* +#define HIC_H2DINTCLR_H2D_CLR 0x1U // Host To Device Interrupt Clear +#define HIC_H2DINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_H2DINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_H2DINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICH2DINTFRC register +// +//************************************************************************************************* +#define HIC_H2DINTFRC_H2D_INTFRC 0x1U // Host To Device Force Set +#define HIC_H2DINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_H2DINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_H2DINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTEN register +// +//************************************************************************************************* +#define HIC_D2HINTEN_D2H_INTEN 0x1U // Device to Host Data Ready Interrupt Enable +#define HIC_D2HINTEN_BUSERR_INTEN 0x2U // BusError Interrupt Enable +#define HIC_D2HINTEN_ILLWR_INTEN 0x4U // Illegal Write event Interrupt Enable +#define HIC_D2HINTEN_ILLRD_INTEN 0x8U // Illegal Read event Interrupt Enable +#define HIC_D2HINTEN_ACCVIO_INTEN 0x10U // Access Violation Interrupt Enable +#define HIC_D2HINTEN_EVTRIG_INTEN_S 16U +#define HIC_D2HINTEN_EVTRIG_INTEN_M 0xFFFF0000U // Event Trigger Interrupt Enable +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFLG register +// +//************************************************************************************************* +#define HIC_D2HINTFLG_D2H_FLG 0x1U // Device to Host Data Ready Flag +#define HIC_D2HINTFLG_BUSERR_FLG 0x2U // BusError Flag +#define HIC_D2HINTFLG_ILLWR_FLG 0x4U // Illegal Write event Flag +#define HIC_D2HINTFLG_ILLRD_FLG 0x8U // Illegal Read event Flag +#define HIC_D2HINTFLG_ACCVIO_FLG 0x10U // Access Violation Flag +#define HIC_D2HINTFLG_EVTRIG_FLG_S 16U +#define HIC_D2HINTFLG_EVTRIG_FLG_M 0xFFFF0000U // Event Trigger Flag +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTCLR register +// +//************************************************************************************************* +#define HIC_D2HINTCLR_D2H_CLR 0x1U // Device to Host Interrupt Clear +#define HIC_D2HINTCLR_BUSERR_CLR 0x2U // BusError Interrupt Clear +#define HIC_D2HINTCLR_ILLWR_CLR 0x4U // Illegal Write Interrupt Clear +#define HIC_D2HINTCLR_ILLRD_CLR 0x8U // Illegal Read Interrupt Clear +#define HIC_D2HINTCLR_ACCVIO_CLR 0x10U // Access Violation Interrupt Clear +#define HIC_D2HINTCLR_EVTRIG_CLR_S 16U +#define HIC_D2HINTCLR_EVTRIG_CLR_M 0xFFFF0000U // Event Trigger Interrupt Clear +//************************************************************************************************* +// +// The following are defines for the bit fields in the HICD2HINTFRC register +// +//************************************************************************************************* +#define HIC_D2HINTFRC_D2H_INTFRC 0x1U // Device to Host Force Set +#define HIC_D2HINTFRC_BUSERR_INTFRC 0x2U // BusError Interrupt Force Set +#define HIC_D2HINTFRC_ILLWR_INTFRC 0x4U // Illegal Write Interrupt Force Set +#define HIC_D2HINTFRC_ILLRD_INTFRC 0x8U // Illegal Read Interrupt Force Set +#define HIC_D2HINTFRC_ACCVIO_INTFRC 0x10U // Access Violation Interrupt Force Set +#define HIC_D2HINTFRC_EVTRIG_INTFRC_S 16U +#define HIC_D2HINTFRC_EVTRIG_INTFRC_M 0xFFFF0000U // Event Trigger Interrupt Force Set + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_hrpwm.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_hrpwm.h new file mode 100644 index 0000000..a6c899f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_hrpwm.h @@ -0,0 +1,1058 @@ +//########################################################################### +// +// FILE: hw_hrpwm.h +// +// TITLE: Definitions for the HRPWM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_HRPWM_H +#define HW_HRPWM_H + +//************************************************************************************************* +// +// The following are defines for the HRPWM register offsets +// +//************************************************************************************************* +#define HRPWM_O_TBCTL 0x0U // Time Base Control Register +#define HRPWM_O_TBCTL2 0x1U // Time Base Control Register 2 +#define HRPWM_O_TBCTR 0x4U // Time Base Counter Register +#define HRPWM_O_TBSTS 0x5U // Time Base Status Register +#define HRPWM_O_CMPCTL 0x8U // Counter Compare Control Register +#define HRPWM_O_CMPCTL2 0x9U // Counter Compare Control Register 2 +#define HRPWM_O_DBCTL 0xCU // Dead-Band Generator Control Register +#define HRPWM_O_DBCTL2 0xDU // Dead-Band Generator Control Register 2 +#define HRPWM_O_AQCTL 0x10U // Action Qualifier Control Register +#define HRPWM_O_AQTSRCSEL 0x11U // Action Qualifier Trigger Event Source Select Register +#define HRPWM_O_PCCTL 0x14U // PWM Chopper Control Register +#define HRPWM_O_VCAPCTL 0x18U // Valley Capture Control Register +#define HRPWM_O_VCNTCFG 0x19U // Valley Counter Config Register +#define HRPWM_O_HRCNFG 0x20U // HRPWM Configuration Register +#define HRPWM_O_HRPWR 0x21U // HRPWM Power Register +#define HRPWM_O_HRMSTEP 0x26U // HRPWM MEP Step Register +#define HRPWM_O_HRCNFG2 0x27U // HRPWM Configuration 2 Register +#define HRPWM_O_HRPCTL 0x2DU // High Resolution Period Control Register +#define HRPWM_O_TRREM 0x2EU // HRPWM High Resolution Remainder Register +#define HRPWM_O_GLDCTL 0x34U // Global PWM Load Control Register +#define HRPWM_O_GLDCFG 0x35U // Global PWM Load Config Register +#define HRPWM_O_EPWMXLINK 0x38U // EPWMx Link Register +#define HRPWM_O_AQCTLA 0x40U // Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLA2 0x41U // Additional Action Qualifier Control Register For Output A +#define HRPWM_O_AQCTLB 0x42U // Action Qualifier Control Register For Output B +#define HRPWM_O_AQCTLB2 0x43U // Additional Action Qualifier Control Register For Output B +#define HRPWM_O_AQSFRC 0x47U // Action Qualifier Software Force Register +#define HRPWM_O_AQCSFRC 0x49U // Action Qualifier Continuous S/W Force Register +#define HRPWM_O_DBREDHR 0x50U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBRED 0x51U // Dead-Band Generator Rising Edge Delay High Resolution + // Mirror Register +#define HRPWM_O_DBFEDHR 0x52U // Dead-Band Generator Falling Edge Delay High Resolution + // Register +#define HRPWM_O_DBFED 0x53U // Dead-Band Generator Falling Edge Delay Count Register +#define HRPWM_O_TBPHS 0x60U // Time Base Phase High +#define HRPWM_O_TBPRDHR 0x62U // Time Base Period High Resolution Register +#define HRPWM_O_TBPRD 0x63U // Time Base Period Register +#define HRPWM_O_CMPA 0x6AU // Counter Compare A Register +#define HRPWM_O_CMPB 0x6CU // Compare B Register +#define HRPWM_O_CMPC 0x6FU // Counter Compare C Register +#define HRPWM_O_CMPD 0x71U // Counter Compare D Register +#define HRPWM_O_GLDCTL2 0x74U // Global PWM Load Control Register 2 +#define HRPWM_O_SWVDELVAL 0x77U // Software Valley Mode Delay Register +#define HRPWM_O_TZSEL 0x80U // Trip Zone Select Register +#define HRPWM_O_TZDCSEL 0x82U // Trip Zone Digital Comparator Select Register +#define HRPWM_O_TZCTL 0x84U // Trip Zone Control Register +#define HRPWM_O_TZCTL2 0x85U // Additional Trip Zone Control Register +#define HRPWM_O_TZCTLDCA 0x86U // Trip Zone Control Register Digital Compare A +#define HRPWM_O_TZCTLDCB 0x87U // Trip Zone Control Register Digital Compare B +#define HRPWM_O_TZEINT 0x8DU // Trip Zone Enable Interrupt Register +#define HRPWM_O_TZFLG 0x93U // Trip Zone Flag Register +#define HRPWM_O_TZCBCFLG 0x94U // Trip Zone CBC Flag Register +#define HRPWM_O_TZOSTFLG 0x95U // Trip Zone OST Flag Register +#define HRPWM_O_TZCLR 0x97U // Trip Zone Clear Register +#define HRPWM_O_TZCBCCLR 0x98U // Trip Zone CBC Clear Register +#define HRPWM_O_TZOSTCLR 0x99U // Trip Zone OST Clear Register +#define HRPWM_O_TZFRC 0x9BU // Trip Zone Force Register +#define HRPWM_O_ETSEL 0xA4U // Event Trigger Selection Register +#define HRPWM_O_ETPS 0xA6U // Event Trigger Pre-Scale Register +#define HRPWM_O_ETFLG 0xA8U // Event Trigger Flag Register +#define HRPWM_O_ETCLR 0xAAU // Event Trigger Clear Register +#define HRPWM_O_ETFRC 0xACU // Event Trigger Force Register +#define HRPWM_O_ETINTPS 0xAEU // Event-Trigger Interrupt Pre-Scale Register +#define HRPWM_O_ETSOCPS 0xB0U // Event-Trigger SOC Pre-Scale Register +#define HRPWM_O_ETCNTINITCTL 0xB2U // Event-Trigger Counter Initialization Control Register +#define HRPWM_O_ETCNTINIT 0xB4U // Event-Trigger Counter Initialization Register +#define HRPWM_O_DCTRIPSEL 0xC0U // Digital Compare Trip Select Register +#define HRPWM_O_DCACTL 0xC3U // Digital Compare A Control Register +#define HRPWM_O_DCBCTL 0xC4U // Digital Compare B Control Register +#define HRPWM_O_DCFCTL 0xC7U // Digital Compare Filter Control Register +#define HRPWM_O_DCCAPCTL 0xC8U // Digital Compare Capture Control Register +#define HRPWM_O_DCFOFFSET 0xC9U // Digital Compare Filter Offset Register +#define HRPWM_O_DCFOFFSETCNT 0xCAU // Digital Compare Filter Offset Counter Register +#define HRPWM_O_DCFWINDOW 0xCBU // Digital Compare Filter Window Register +#define HRPWM_O_DCFWINDOWCNT 0xCCU // Digital Compare Filter Window Counter Register +#define HRPWM_O_DCCAP 0xCFU // Digital Compare Counter Capture Register +#define HRPWM_O_DCAHTRIPSEL 0xD2U // Digital Compare AH Trip Select +#define HRPWM_O_DCALTRIPSEL 0xD3U // Digital Compare AL Trip Select +#define HRPWM_O_DCBHTRIPSEL 0xD4U // Digital Compare BH Trip Select +#define HRPWM_O_DCBLTRIPSEL 0xD5U // Digital Compare BL Trip Select +#define HRPWM_O_HWVDELVAL 0xFDU // Hardware Valley Mode Delay Register +#define HRPWM_O_VCNTVAL 0xFEU // Hardware Valley Counter Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL register +// +//************************************************************************************************* +#define HRPWM_TBCTL_CTRMODE_S 0U +#define HRPWM_TBCTL_CTRMODE_M 0x3U // Counter Mode +#define HRPWM_TBCTL_PHSEN 0x4U // Phase Load Enable +#define HRPWM_TBCTL_PRDLD 0x8U // Active Period Load +#define HRPWM_TBCTL_SYNCOSEL_S 4U +#define HRPWM_TBCTL_SYNCOSEL_M 0x30U // Sync Output Select +#define HRPWM_TBCTL_SWFSYNC 0x40U // Software Force Sync Pulse +#define HRPWM_TBCTL_HSPCLKDIV_S 7U +#define HRPWM_TBCTL_HSPCLKDIV_M 0x380U // High Speed TBCLK Pre-scaler +#define HRPWM_TBCTL_CLKDIV_S 10U +#define HRPWM_TBCTL_CLKDIV_M 0x1C00U // Time Base Clock Pre-scaler +#define HRPWM_TBCTL_PHSDIR 0x2000U // Phase Direction Bit +#define HRPWM_TBCTL_FREE_SOFT_S 14U +#define HRPWM_TBCTL_FREE_SOFT_M 0xC000U // Emulation Mode Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBCTL2 register +// +//************************************************************************************************* +#define HRPWM_TBCTL2_OSHTSYNCMODE 0x40U // One shot sync mode +#define HRPWM_TBCTL2_OSHTSYNC 0x80U // One shot sync +#define HRPWM_TBCTL2_SYNCOSELX_S 12U +#define HRPWM_TBCTL2_SYNCOSELX_M 0x3000U // Syncout selection +#define HRPWM_TBCTL2_PRDLDSYNC_S 14U +#define HRPWM_TBCTL2_PRDLDSYNC_M 0xC000U // PRD Shadow to Active Load on SYNC Event + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBSTS register +// +//************************************************************************************************* +#define HRPWM_TBSTS_CTRDIR 0x1U // Counter Direction Status +#define HRPWM_TBSTS_SYNCI 0x2U // External Input Sync Status +#define HRPWM_TBSTS_CTRMAX 0x4U // Counter Max Latched Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL register +// +//************************************************************************************************* +#define HRPWM_CMPCTL_LOADAMODE_S 0U +#define HRPWM_CMPCTL_LOADAMODE_M 0x3U // Active Compare A Load +#define HRPWM_CMPCTL_LOADBMODE_S 2U +#define HRPWM_CMPCTL_LOADBMODE_M 0xCU // Active Compare B Load +#define HRPWM_CMPCTL_SHDWAMODE 0x10U // Compare A Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWBMODE 0x40U // Compare B Register Block Operating Mode +#define HRPWM_CMPCTL_SHDWAFULL 0x100U // Compare A Shadow Register Full Status +#define HRPWM_CMPCTL_SHDWBFULL 0x200U // Compare B Shadow Register Full Status +#define HRPWM_CMPCTL_LOADASYNC_S 10U +#define HRPWM_CMPCTL_LOADASYNC_M 0xC00U // Active Compare A Load on SYNC +#define HRPWM_CMPCTL_LOADBSYNC_S 12U +#define HRPWM_CMPCTL_LOADBSYNC_M 0x3000U // Active Compare B Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPCTL2 register +// +//************************************************************************************************* +#define HRPWM_CMPCTL2_LOADCMODE_S 0U +#define HRPWM_CMPCTL2_LOADCMODE_M 0x3U // Active Compare C Load +#define HRPWM_CMPCTL2_LOADDMODE_S 2U +#define HRPWM_CMPCTL2_LOADDMODE_M 0xCU // Active Compare D load +#define HRPWM_CMPCTL2_SHDWCMODE 0x10U // Compare C Block Operating Mode +#define HRPWM_CMPCTL2_SHDWDMODE 0x40U // Compare D Block Operating Mode +#define HRPWM_CMPCTL2_LOADCSYNC_S 10U +#define HRPWM_CMPCTL2_LOADCSYNC_M 0xC00U // Active Compare C Load on SYNC +#define HRPWM_CMPCTL2_LOADDSYNC_S 12U +#define HRPWM_CMPCTL2_LOADDSYNC_M 0x3000U // Active Compare D Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL register +// +//************************************************************************************************* +#define HRPWM_DBCTL_OUT_MODE_S 0U +#define HRPWM_DBCTL_OUT_MODE_M 0x3U // Dead Band Output Mode Control +#define HRPWM_DBCTL_POLSEL_S 2U +#define HRPWM_DBCTL_POLSEL_M 0xCU // Polarity Select Control +#define HRPWM_DBCTL_IN_MODE_S 4U +#define HRPWM_DBCTL_IN_MODE_M 0x30U // Dead Band Input Select Mode Control +#define HRPWM_DBCTL_LOADREDMODE_S 6U +#define HRPWM_DBCTL_LOADREDMODE_M 0xC0U // Active DBRED Load Mode +#define HRPWM_DBCTL_LOADFEDMODE_S 8U +#define HRPWM_DBCTL_LOADFEDMODE_M 0x300U // Active DBFED Load Mode +#define HRPWM_DBCTL_SHDWDBREDMODE 0x400U // DBRED Block Operating Mode +#define HRPWM_DBCTL_SHDWDBFEDMODE 0x800U // DBFED Block Operating Mode +#define HRPWM_DBCTL_OUTSWAP_S 12U +#define HRPWM_DBCTL_OUTSWAP_M 0x3000U // Dead Band Output Swap Control +#define HRPWM_DBCTL_DEDB_MODE 0x4000U // Dead Band Dual-Edge B Mode Control +#define HRPWM_DBCTL_HALFCYCLE 0x8000U // Half Cycle Clocking Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBCTL2 register +// +//************************************************************************************************* +#define HRPWM_DBCTL2_LOADDBCTLMODE_S 0U +#define HRPWM_DBCTL2_LOADDBCTLMODE_M 0x3U // DBCTL Load from Shadow Mode Select +#define HRPWM_DBCTL2_SHDWDBCTLMODE 0x4U // DBCTL Load mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTL register +// +//************************************************************************************************* +#define HRPWM_AQCTL_LDAQAMODE_S 0U +#define HRPWM_AQCTL_LDAQAMODE_M 0x3U // Action Qualifier A Load Select +#define HRPWM_AQCTL_LDAQBMODE_S 2U +#define HRPWM_AQCTL_LDAQBMODE_M 0xCU // Action Qualifier B Load Select +#define HRPWM_AQCTL_SHDWAQAMODE 0x10U // Action Qualifer A Operating Mode +#define HRPWM_AQCTL_SHDWAQBMODE 0x40U // Action Qualifier B Operating Mode +#define HRPWM_AQCTL_LDAQASYNC_S 8U +#define HRPWM_AQCTL_LDAQASYNC_M 0x300U // AQCTLA Register Load on SYNC +#define HRPWM_AQCTL_LDAQBSYNC_S 10U +#define HRPWM_AQCTL_LDAQBSYNC_M 0xC00U // AQCTLB Register Load on SYNC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQTSRCSEL register +// +//************************************************************************************************* +#define HRPWM_AQTSRCSEL_T1SEL_S 0U +#define HRPWM_AQTSRCSEL_T1SEL_M 0xFU // T1 Event Source Select Bits +#define HRPWM_AQTSRCSEL_T2SEL_S 4U +#define HRPWM_AQTSRCSEL_T2SEL_M 0xF0U // T2 Event Source Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCCTL register +// +//************************************************************************************************* +#define HRPWM_PCCTL_CHPEN 0x1U // PWM chopping enable +#define HRPWM_PCCTL_OSHTWTH_S 1U +#define HRPWM_PCCTL_OSHTWTH_M 0x1EU // One-shot pulse width +#define HRPWM_PCCTL_CHPFREQ_S 5U +#define HRPWM_PCCTL_CHPFREQ_M 0xE0U // Chopping clock frequency +#define HRPWM_PCCTL_CHPDUTY_S 8U +#define HRPWM_PCCTL_CHPDUTY_M 0x700U // Chopping clock Duty cycle + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCAPCTL register +// +//************************************************************************************************* +#define HRPWM_VCAPCTL_VCAPE 0x1U // Valley Capture mode +#define HRPWM_VCAPCTL_VCAPSTART 0x2U // Valley Capture Start +#define HRPWM_VCAPCTL_TRIGSEL_S 2U +#define HRPWM_VCAPCTL_TRIGSEL_M 0x1CU // Capture Trigger Select +#define HRPWM_VCAPCTL_VDELAYDIV_S 7U +#define HRPWM_VCAPCTL_VDELAYDIV_M 0x380U // Valley Delay Mode Divide Enable +#define HRPWM_VCAPCTL_EDGEFILTDLYSEL 0x400U // Valley Switching Mode Delay Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the VCNTCFG register +// +//************************************************************************************************* +#define HRPWM_VCNTCFG_STARTEDGE_S 0U +#define HRPWM_VCNTCFG_STARTEDGE_M 0xFU // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STARTEDGESTS 0x80U // Start Edge Status Bit +#define HRPWM_VCNTCFG_STOPEDGE_S 8U +#define HRPWM_VCNTCFG_STOPEDGE_M 0xF00U // Counter Start Edge Selection +#define HRPWM_VCNTCFG_STOPEDGESTS 0x8000U // Stop Edge Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG register +// +//************************************************************************************************* +#define HRPWM_HRCNFG_EDGMODE_S 0U +#define HRPWM_HRCNFG_EDGMODE_M 0x3U // ePWMxA Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODE 0x4U // ePWMxA Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOAD_S 3U +#define HRPWM_HRCNFG_HRLOAD_M 0x18U // ePWMxA Shadow Mode Select Bits +#define HRPWM_HRCNFG_SELOUTB 0x20U // EPWMB Output Selection Bit +#define HRPWM_HRCNFG_AUTOCONV 0x40U // Autoconversion Bit +#define HRPWM_HRCNFG_SWAPAB 0x80U // Swap EPWMA and EPWMB Outputs Bit +#define HRPWM_HRCNFG_EDGMODEB_S 8U +#define HRPWM_HRCNFG_EDGMODEB_M 0x300U // ePWMxB Edge Mode Select Bits +#define HRPWM_HRCNFG_CTLMODEB 0x400U // ePWMxB Control Mode Select Bits +#define HRPWM_HRCNFG_HRLOADB_S 11U +#define HRPWM_HRCNFG_HRLOADB_M 0x1800U // ePWMxB Shadow Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPWR register +// +//************************************************************************************************* +#define HRPWM_HRPWR_CALPWRON 0x8000U // Calibration Power On + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRMSTEP register +// +//************************************************************************************************* +#define HRPWM_HRMSTEP_HRMSTEP_S 0U +#define HRPWM_HRMSTEP_HRMSTEP_M 0xFFU // High Resolution Micro Step Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRCNFG2 register +// +//************************************************************************************************* +#define HRPWM_HRCNFG2_EDGMODEDB_S 0U +#define HRPWM_HRCNFG2_EDGMODEDB_M 0x3U // Dead-Band Edge-Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBRED_S 2U +#define HRPWM_HRCNFG2_CTLMODEDBRED_M 0xCU // DBRED Control Mode Select Bits +#define HRPWM_HRCNFG2_CTLMODEDBFED_S 4U +#define HRPWM_HRCNFG2_CTLMODEDBFED_M 0x30U // DBFED Control Mode Select Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the HRPCTL register +// +//************************************************************************************************* +#define HRPWM_HRPCTL_HRPE 0x1U // High Resolution Period Enable +#define HRPWM_HRPCTL_PWMSYNCSEL 0x2U // EPWMSYNCPER Source Select +#define HRPWM_HRPCTL_TBPHSHRLOADE 0x4U // TBPHSHR Load Enable +#define HRPWM_HRPCTL_PWMSYNCSELX_S 4U +#define HRPWM_HRPCTL_PWMSYNCSELX_M 0x70U // EPWMSYNCPER Extended Source Select Bit: + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TRREM register +// +//************************************************************************************************* +#define HRPWM_TRREM_TRREM_S 0U +#define HRPWM_TRREM_TRREM_M 0x7FFU // HRPWM Remainder Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL register +// +//************************************************************************************************* +#define HRPWM_GLDCTL_GLD 0x1U // Global Shadow to Active load event control +#define HRPWM_GLDCTL_GLDMODE_S 1U +#define HRPWM_GLDCTL_GLDMODE_M 0x1EU // Shadow to Active Global Load Pulse Selection +#define HRPWM_GLDCTL_OSHTMODE 0x20U // One Shot Load mode control bit +#define HRPWM_GLDCTL_GLDPRD_S 7U +#define HRPWM_GLDCTL_GLDPRD_M 0x380U // Global Load Strobe Period Select Register +#define HRPWM_GLDCTL_GLDCNT_S 10U +#define HRPWM_GLDCTL_GLDCNT_M 0x1C00U // Global Load Strobe Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCFG register +// +//************************************************************************************************* +#define HRPWM_GLDCFG_TBPRD_TBPRDHR 0x1U // Global load event configuration for TBPRD:TBPRDHR +#define HRPWM_GLDCFG_CMPA_CMPAHR 0x2U // Global load event configuration for CMPA:CMPAHR +#define HRPWM_GLDCFG_CMPB_CMPBHR 0x4U // Global load event configuration for CMPB:CMPBHR +#define HRPWM_GLDCFG_CMPC 0x8U // Global load event configuration for CMPC +#define HRPWM_GLDCFG_CMPD 0x10U // Global load event configuration for CMPD +#define HRPWM_GLDCFG_DBRED_DBREDHR 0x20U // Global load event configuration for DBRED:DBREDHR +#define HRPWM_GLDCFG_DBFED_DBFEDHR 0x40U // Global load event configuration for DBFED:DBFEDHR +#define HRPWM_GLDCFG_DBCTL 0x80U // Global load event configuration for DBCTL +#define HRPWM_GLDCFG_AQCTLA_AQCTLA2 0x100U // Global load event configuration for AQCTLA/A2 +#define HRPWM_GLDCFG_AQCTLB_AQCTLB2 0x200U // Global load event configuration for AQCTLB/B2 +#define HRPWM_GLDCFG_AQCSFRC 0x400U // Global load event configuration for AQCSFRC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EPWMXLINK register +// +//************************************************************************************************* +#define HRPWM_EPWMXLINK_TBPRDLINK_S 0U +#define HRPWM_EPWMXLINK_TBPRDLINK_M 0xFU // TBPRD:TBPRDHR Link +#define HRPWM_EPWMXLINK_CMPALINK_S 4U +#define HRPWM_EPWMXLINK_CMPALINK_M 0xF0U // CMPA:CMPAHR Link +#define HRPWM_EPWMXLINK_CMPBLINK_S 8U +#define HRPWM_EPWMXLINK_CMPBLINK_M 0xF00U // CMPB:CMPBHR Link +#define HRPWM_EPWMXLINK_CMPCLINK_S 12U +#define HRPWM_EPWMXLINK_CMPCLINK_M 0xF000U // CMPC Link +#define HRPWM_EPWMXLINK_CMPDLINK_S 16U +#define HRPWM_EPWMXLINK_CMPDLINK_M 0xF0000U // CMPD Link +#define HRPWM_EPWMXLINK_GLDCTL2LINK_S 28U +#define HRPWM_EPWMXLINK_GLDCTL2LINK_M 0xF0000000U // GLDCTL2 Link + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA register +// +//************************************************************************************************* +#define HRPWM_AQCTLA_ZRO_S 0U +#define HRPWM_AQCTLA_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLA_PRD_S 2U +#define HRPWM_AQCTLA_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLA_CAU_S 4U +#define HRPWM_AQCTLA_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLA_CAD_S 6U +#define HRPWM_AQCTLA_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLA_CBU_S 8U +#define HRPWM_AQCTLA_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLA_CBD_S 10U +#define HRPWM_AQCTLA_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLA2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLA2_T1U_S 0U +#define HRPWM_AQCTLA2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLA2_T1D_S 2U +#define HRPWM_AQCTLA2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLA2_T2U_S 4U +#define HRPWM_AQCTLA2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLA2_T2D_S 6U +#define HRPWM_AQCTLA2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB register +// +//************************************************************************************************* +#define HRPWM_AQCTLB_ZRO_S 0U +#define HRPWM_AQCTLB_ZRO_M 0x3U // Action Counter = Zero +#define HRPWM_AQCTLB_PRD_S 2U +#define HRPWM_AQCTLB_PRD_M 0xCU // Action Counter = Period +#define HRPWM_AQCTLB_CAU_S 4U +#define HRPWM_AQCTLB_CAU_M 0x30U // Action Counter = Compare A Up +#define HRPWM_AQCTLB_CAD_S 6U +#define HRPWM_AQCTLB_CAD_M 0xC0U // Action Counter = Compare A Down +#define HRPWM_AQCTLB_CBU_S 8U +#define HRPWM_AQCTLB_CBU_M 0x300U // Action Counter = Compare B Up +#define HRPWM_AQCTLB_CBD_S 10U +#define HRPWM_AQCTLB_CBD_M 0xC00U // Action Counter = Compare B Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCTLB2 register +// +//************************************************************************************************* +#define HRPWM_AQCTLB2_T1U_S 0U +#define HRPWM_AQCTLB2_T1U_M 0x3U // Action when event occurs on T1 in UP-Count +#define HRPWM_AQCTLB2_T1D_S 2U +#define HRPWM_AQCTLB2_T1D_M 0xCU // Action when event occurs on T1 in DOWN-Count +#define HRPWM_AQCTLB2_T2U_S 4U +#define HRPWM_AQCTLB2_T2U_M 0x30U // Action when event occurs on T2 in UP-Count +#define HRPWM_AQCTLB2_T2D_S 6U +#define HRPWM_AQCTLB2_T2D_M 0xC0U // Action when event occurs on T2 in DOWN-Count + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQSFRC register +// +//************************************************************************************************* +#define HRPWM_AQSFRC_ACTSFA_S 0U +#define HRPWM_AQSFRC_ACTSFA_M 0x3U // Action when One-time SW Force A Invoked +#define HRPWM_AQSFRC_OTSFA 0x4U // One-time SW Force A Output +#define HRPWM_AQSFRC_ACTSFB_S 3U +#define HRPWM_AQSFRC_ACTSFB_M 0x18U // Action when One-time SW Force B Invoked +#define HRPWM_AQSFRC_OTSFB 0x20U // One-time SW Force A Output +#define HRPWM_AQSFRC_RLDCSF_S 6U +#define HRPWM_AQSFRC_RLDCSF_M 0xC0U // Reload from Shadow Options + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AQCSFRC register +// +//************************************************************************************************* +#define HRPWM_AQCSFRC_CSFA_S 0U +#define HRPWM_AQCSFRC_CSFA_M 0x3U // Continuous Software Force on output A +#define HRPWM_AQCSFRC_CSFB_S 2U +#define HRPWM_AQCSFRC_CSFB_M 0xCU // Continuous Software Force on output B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBREDHR register +// +//************************************************************************************************* +#define HRPWM_DBREDHR_DBREDHR_S 9U +#define HRPWM_DBREDHR_DBREDHR_M 0xFE00U // DBREDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBRED register +// +//************************************************************************************************* +#define HRPWM_DBRED_DBRED_S 0U +#define HRPWM_DBRED_DBRED_M 0x3FFFU // Rising edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFEDHR register +// +//************************************************************************************************* +#define HRPWM_DBFEDHR_DBFEDHR_S 9U +#define HRPWM_DBFEDHR_DBFEDHR_M 0xFE00U // DBFEDHR High Resolution Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DBFED register +// +//************************************************************************************************* +#define HRPWM_DBFED_DBFED_S 0U +#define HRPWM_DBFED_DBFED_M 0x3FFFU // Falling edge delay value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TBPHS register +// +//************************************************************************************************* +#define HRPWM_TBPHS_TBPHSHR_S 0U +#define HRPWM_TBPHS_TBPHSHR_M 0xFFFFU // Extension Register for HRPWM Phase (8-bits) +#define HRPWM_TBPHS_TBPHS_S 16U +#define HRPWM_TBPHS_TBPHS_M 0xFFFF0000U // Phase Offset Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPA register +// +//************************************************************************************************* +#define HRPWM_CMPA_CMPAHR_S 0U +#define HRPWM_CMPA_CMPAHR_M 0xFFFFU // Compare A HRPWM Extension Register +#define HRPWM_CMPA_CMPA_S 16U +#define HRPWM_CMPA_CMPA_M 0xFFFF0000U // Compare A Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CMPB register +// +//************************************************************************************************* +#define HRPWM_CMPB_CMPBHR_S 0U +#define HRPWM_CMPB_CMPBHR_M 0xFFFFU // Compare B High Resolution Bits +#define HRPWM_CMPB_CMPB_S 16U +#define HRPWM_CMPB_CMPB_M 0xFFFF0000U // Compare B Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GLDCTL2 register +// +//************************************************************************************************* +#define HRPWM_GLDCTL2_OSHTLD 0x1U // Enable reload event in one shot mode +#define HRPWM_GLDCTL2_GFRCLD 0x2U // Force reload event in one shot mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZSEL register +// +//************************************************************************************************* +#define HRPWM_TZSEL_CBC1 0x1U // TZ1 CBC select +#define HRPWM_TZSEL_CBC2 0x2U // TZ2 CBC select +#define HRPWM_TZSEL_CBC3 0x4U // TZ3 CBC select +#define HRPWM_TZSEL_CBC4 0x8U // TZ4 CBC select +#define HRPWM_TZSEL_CBC5 0x10U // TZ5 CBC select +#define HRPWM_TZSEL_CBC6 0x20U // TZ6 CBC select +#define HRPWM_TZSEL_DCAEVT2 0x40U // DCAEVT2 CBC select +#define HRPWM_TZSEL_DCBEVT2 0x80U // DCBEVT2 CBC select +#define HRPWM_TZSEL_OSHT1 0x100U // One-shot TZ1 select +#define HRPWM_TZSEL_OSHT2 0x200U // One-shot TZ2 select +#define HRPWM_TZSEL_OSHT3 0x400U // One-shot TZ3 select +#define HRPWM_TZSEL_OSHT4 0x800U // One-shot TZ4 select +#define HRPWM_TZSEL_OSHT5 0x1000U // One-shot TZ5 select +#define HRPWM_TZSEL_OSHT6 0x2000U // One-shot TZ6 select +#define HRPWM_TZSEL_DCAEVT1 0x4000U // One-shot DCAEVT1 select +#define HRPWM_TZSEL_DCBEVT1 0x8000U // One-shot DCBEVT1 select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZDCSEL register +// +//************************************************************************************************* +#define HRPWM_TZDCSEL_DCAEVT1_S 0U +#define HRPWM_TZDCSEL_DCAEVT1_M 0x7U // Digital Compare Output A Event 1 +#define HRPWM_TZDCSEL_DCAEVT2_S 3U +#define HRPWM_TZDCSEL_DCAEVT2_M 0x38U // Digital Compare Output A Event 2 +#define HRPWM_TZDCSEL_DCBEVT1_S 6U +#define HRPWM_TZDCSEL_DCBEVT1_M 0x1C0U // Digital Compare Output B Event 1 +#define HRPWM_TZDCSEL_DCBEVT2_S 9U +#define HRPWM_TZDCSEL_DCBEVT2_M 0xE00U // Digital Compare Output B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL register +// +//************************************************************************************************* +#define HRPWM_TZCTL_TZA_S 0U +#define HRPWM_TZCTL_TZA_M 0x3U // TZ1 to TZ6 Trip Action On EPWMxA +#define HRPWM_TZCTL_TZB_S 2U +#define HRPWM_TZCTL_TZB_M 0xCU // TZ1 to TZ6 Trip Action On EPWMxB +#define HRPWM_TZCTL_DCAEVT1_S 4U +#define HRPWM_TZCTL_DCAEVT1_M 0x30U // EPWMxA action on DCAEVT1 +#define HRPWM_TZCTL_DCAEVT2_S 6U +#define HRPWM_TZCTL_DCAEVT2_M 0xC0U // EPWMxA action on DCAEVT2 +#define HRPWM_TZCTL_DCBEVT1_S 8U +#define HRPWM_TZCTL_DCBEVT1_M 0x300U // EPWMxB action on DCBEVT1 +#define HRPWM_TZCTL_DCBEVT2_S 10U +#define HRPWM_TZCTL_DCBEVT2_M 0xC00U // EPWMxB action on DCBEVT2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTL2 register +// +//************************************************************************************************* +#define HRPWM_TZCTL2_TZAU_S 0U +#define HRPWM_TZCTL2_TZAU_M 0x7U // Trip Action On EPWMxA while Count direction is UP +#define HRPWM_TZCTL2_TZAD_S 3U +#define HRPWM_TZCTL2_TZAD_M 0x38U // Trip Action On EPWMxA while Count direction is DOWN +#define HRPWM_TZCTL2_TZBU_S 6U +#define HRPWM_TZCTL2_TZBU_M 0x1C0U // Trip Action On EPWMxB while Count direction is UP +#define HRPWM_TZCTL2_TZBD_S 9U +#define HRPWM_TZCTL2_TZBD_M 0xE00U // Trip Action On EPWMxB while Count direction is DOWN +#define HRPWM_TZCTL2_ETZE 0x8000U // TZCTL2 Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCA register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCA_DCAEVT1U_S 0U +#define HRPWM_TZCTLDCA_DCAEVT1U_M 0x7U // DCAEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT1D_S 3U +#define HRPWM_TZCTLDCA_DCAEVT1D_M 0x38U // DCAEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCA_DCAEVT2U_S 6U +#define HRPWM_TZCTLDCA_DCAEVT2U_M 0x1C0U // DCAEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCA_DCAEVT2D_S 9U +#define HRPWM_TZCTLDCA_DCAEVT2D_M 0xE00U // DCAEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCTLDCB register +// +//************************************************************************************************* +#define HRPWM_TZCTLDCB_DCBEVT1U_S 0U +#define HRPWM_TZCTLDCB_DCBEVT1U_M 0x7U // DCBEVT1 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT1D_S 3U +#define HRPWM_TZCTLDCB_DCBEVT1D_M 0x38U // DCBEVT1 Action On EPWMxA while Count direction is + // DOWN +#define HRPWM_TZCTLDCB_DCBEVT2U_S 6U +#define HRPWM_TZCTLDCB_DCBEVT2U_M 0x1C0U // DCBEVT2 Action On EPWMxA while Count direction is + // UP +#define HRPWM_TZCTLDCB_DCBEVT2D_S 9U +#define HRPWM_TZCTLDCB_DCBEVT2D_M 0xE00U // DCBEVT2 Action On EPWMxA while Count direction is + // DOWN + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZEINT register +// +//************************************************************************************************* +#define HRPWM_TZEINT_CBC 0x2U // Trip Zones Cycle By Cycle Int Enable +#define HRPWM_TZEINT_OST 0x4U // Trip Zones One Shot Int Enable +#define HRPWM_TZEINT_DCAEVT1 0x8U // Digital Compare A Event 1 Int Enable +#define HRPWM_TZEINT_DCAEVT2 0x10U // Digital Compare A Event 2 Int Enable +#define HRPWM_TZEINT_DCBEVT1 0x20U // Digital Compare B Event 1 Int Enable +#define HRPWM_TZEINT_DCBEVT2 0x40U // Digital Compare B Event 2 Int Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFLG register +// +//************************************************************************************************* +#define HRPWM_TZFLG_INT 0x1U // Global Int Status Flag +#define HRPWM_TZFLG_CBC 0x2U // Trip Zones Cycle By Cycle Flag +#define HRPWM_TZFLG_OST 0x4U // Trip Zones One Shot Flag +#define HRPWM_TZFLG_DCAEVT1 0x8U // Digital Compare A Event 1 Flag +#define HRPWM_TZFLG_DCAEVT2 0x10U // Digital Compare A Event 2 Flag +#define HRPWM_TZFLG_DCBEVT1 0x20U // Digital Compare B Event 1 Flag +#define HRPWM_TZFLG_DCBEVT2 0x40U // Digital Compare B Event 2 Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCFLG register +// +//************************************************************************************************* +#define HRPWM_TZCBCFLG_CBC1 0x1U // Latched Status Flag for CBC1 Trip Latch +#define HRPWM_TZCBCFLG_CBC2 0x2U // Latched Status Flag for CBC2 Trip Latch +#define HRPWM_TZCBCFLG_CBC3 0x4U // Latched Status Flag for CBC3 Trip Latch +#define HRPWM_TZCBCFLG_CBC4 0x8U // Latched Status Flag for CBC4 Trip Latch +#define HRPWM_TZCBCFLG_CBC5 0x10U // Latched Status Flag for CBC5 Trip Latch +#define HRPWM_TZCBCFLG_CBC6 0x20U // Latched Status Flag for CBC6 Trip Latch +#define HRPWM_TZCBCFLG_DCAEVT2 0x40U // Latched Status Flag for Digital Compare Output A Event + // 2 +#define HRPWM_TZCBCFLG_DCBEVT2 0x80U // Latched Status Flag for Digital Compare Output B Event + // 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTFLG register +// +//************************************************************************************************* +#define HRPWM_TZOSTFLG_OST1 0x1U // Latched Status Flag for OST1 Trip Latch +#define HRPWM_TZOSTFLG_OST2 0x2U // Latched Status Flag for OST2 Trip Latch +#define HRPWM_TZOSTFLG_OST3 0x4U // Latched Status Flag for OST3 Trip Latch +#define HRPWM_TZOSTFLG_OST4 0x8U // Latched Status Flag for OST4 Trip Latch +#define HRPWM_TZOSTFLG_OST5 0x10U // Latched Status Flag for OST5 Trip Latch +#define HRPWM_TZOSTFLG_OST6 0x20U // Latched Status Flag for OST6 Trip Latch +#define HRPWM_TZOSTFLG_DCAEVT1 0x40U // Latched Status Flag for Digital Compare Output A Event + // 1 +#define HRPWM_TZOSTFLG_DCBEVT1 0x80U // Latched Status Flag for Digital Compare Output B Event + // 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCLR register +// +//************************************************************************************************* +#define HRPWM_TZCLR_INT 0x1U // Global Interrupt Clear Flag +#define HRPWM_TZCLR_CBC 0x2U // Cycle-By-Cycle Flag Clear +#define HRPWM_TZCLR_OST 0x4U // One-Shot Flag Clear +#define HRPWM_TZCLR_DCAEVT1 0x8U // DCAVET1 Flag Clear +#define HRPWM_TZCLR_DCAEVT2 0x10U // DCAEVT2 Flag Clear +#define HRPWM_TZCLR_DCBEVT1 0x20U // DCBEVT1 Flag Clear +#define HRPWM_TZCLR_DCBEVT2 0x40U // DCBEVT2 Flag Clear +#define HRPWM_TZCLR_CBCPULSE_S 14U +#define HRPWM_TZCLR_CBCPULSE_M 0xC000U // Clear Pulse for CBC Trip Latch + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZCBCCLR register +// +//************************************************************************************************* +#define HRPWM_TZCBCCLR_CBC1 0x1U // Clear Flag for Cycle-By-Cycle (CBC1) Trip Latch +#define HRPWM_TZCBCCLR_CBC2 0x2U // Clear Flag for Cycle-By-Cycle (CBC2) Trip Latch +#define HRPWM_TZCBCCLR_CBC3 0x4U // Clear Flag for Cycle-By-Cycle (CBC3) Trip Latch +#define HRPWM_TZCBCCLR_CBC4 0x8U // Clear Flag for Cycle-By-Cycle (CBC4) Trip Latch +#define HRPWM_TZCBCCLR_CBC5 0x10U // Clear Flag for Cycle-By-Cycle (CBC5) Trip Latch +#define HRPWM_TZCBCCLR_CBC6 0x20U // Clear Flag for Cycle-By-Cycle (CBC6) Trip Latch +#define HRPWM_TZCBCCLR_DCAEVT2 0x40U // Clear Flag forDCAEVT2 selected for CBC +#define HRPWM_TZCBCCLR_DCBEVT2 0x80U // Clear Flag for DCBEVT2 selected for CBC + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZOSTCLR register +// +//************************************************************************************************* +#define HRPWM_TZOSTCLR_OST1 0x1U // Clear Flag for Oneshot (OST1) Trip Latch +#define HRPWM_TZOSTCLR_OST2 0x2U // Clear Flag for Oneshot (OST2) Trip Latch +#define HRPWM_TZOSTCLR_OST3 0x4U // Clear Flag for Oneshot (OST3) Trip Latch +#define HRPWM_TZOSTCLR_OST4 0x8U // Clear Flag for Oneshot (OST4) Trip Latch +#define HRPWM_TZOSTCLR_OST5 0x10U // Clear Flag for Oneshot (OST5) Trip Latch +#define HRPWM_TZOSTCLR_OST6 0x20U // Clear Flag for Oneshot (OST6) Trip Latch +#define HRPWM_TZOSTCLR_DCAEVT1 0x40U // Clear Flag for DCAEVT1 selected for OST +#define HRPWM_TZOSTCLR_DCBEVT1 0x80U // Clear Flag for DCBEVT1 selected for OST + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TZFRC register +// +//************************************************************************************************* +#define HRPWM_TZFRC_CBC 0x2U // Force Trip Zones Cycle By Cycle Event +#define HRPWM_TZFRC_OST 0x4U // Force Trip Zones One Shot Event +#define HRPWM_TZFRC_DCAEVT1 0x8U // Force Digital Compare A Event 1 +#define HRPWM_TZFRC_DCAEVT2 0x10U // Force Digital Compare A Event 2 +#define HRPWM_TZFRC_DCBEVT1 0x20U // Force Digital Compare B Event 1 +#define HRPWM_TZFRC_DCBEVT2 0x40U // Force Digital Compare B Event 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSEL register +// +//************************************************************************************************* +#define HRPWM_ETSEL_INTSEL_S 0U +#define HRPWM_ETSEL_INTSEL_M 0x7U // EPWMxINTn Select +#define HRPWM_ETSEL_INTEN 0x8U // EPWMxINTn Enable +#define HRPWM_ETSEL_SOCASELCMP 0x10U // EPWMxSOCA Compare Select +#define HRPWM_ETSEL_SOCBSELCMP 0x20U // EPWMxSOCB Compare Select +#define HRPWM_ETSEL_INTSELCMP 0x40U // EPWMxINT Compare Select +#define HRPWM_ETSEL_SOCASEL_S 8U +#define HRPWM_ETSEL_SOCASEL_M 0x700U // Start of Conversion A Select +#define HRPWM_ETSEL_SOCAEN 0x800U // Start of Conversion A Enable +#define HRPWM_ETSEL_SOCBSEL_S 12U +#define HRPWM_ETSEL_SOCBSEL_M 0x7000U // Start of Conversion B Select +#define HRPWM_ETSEL_SOCBEN 0x8000U // Start of Conversion B Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETPS register +// +//************************************************************************************************* +#define HRPWM_ETPS_INTPRD_S 0U +#define HRPWM_ETPS_INTPRD_M 0x3U // EPWMxINTn Period Select +#define HRPWM_ETPS_INTCNT_S 2U +#define HRPWM_ETPS_INTCNT_M 0xCU // EPWMxINTn Counter Register +#define HRPWM_ETPS_INTPSSEL 0x10U // EPWMxINTn Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCPSSEL 0x20U // EPWMxSOC A/B Pre-Scale Selection Bits +#define HRPWM_ETPS_SOCAPRD_S 8U +#define HRPWM_ETPS_SOCAPRD_M 0x300U // EPWMxSOCA Period Select +#define HRPWM_ETPS_SOCACNT_S 10U +#define HRPWM_ETPS_SOCACNT_M 0xC00U // EPWMxSOCA Counter Register +#define HRPWM_ETPS_SOCBPRD_S 12U +#define HRPWM_ETPS_SOCBPRD_M 0x3000U // EPWMxSOCB Period Select +#define HRPWM_ETPS_SOCBCNT_S 14U +#define HRPWM_ETPS_SOCBCNT_M 0xC000U // EPWMxSOCB Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFLG register +// +//************************************************************************************************* +#define HRPWM_ETFLG_INT 0x1U // EPWMxINTn Flag +#define HRPWM_ETFLG_SOCA 0x4U // EPWMxSOCA Flag +#define HRPWM_ETFLG_SOCB 0x8U // EPWMxSOCB Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCLR register +// +//************************************************************************************************* +#define HRPWM_ETCLR_INT 0x1U // EPWMxINTn Clear +#define HRPWM_ETCLR_SOCA 0x4U // EPWMxSOCA Clear +#define HRPWM_ETCLR_SOCB 0x8U // EPWMxSOCB Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETFRC register +// +//************************************************************************************************* +#define HRPWM_ETFRC_INT 0x1U // EPWMxINTn Force +#define HRPWM_ETFRC_SOCA 0x4U // EPWMxSOCA Force +#define HRPWM_ETFRC_SOCB 0x8U // EPWMxSOCB Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETINTPS register +// +//************************************************************************************************* +#define HRPWM_ETINTPS_INTPRD2_S 0U +#define HRPWM_ETINTPS_INTPRD2_M 0xFU // EPWMxINTn Period Select +#define HRPWM_ETINTPS_INTCNT2_S 4U +#define HRPWM_ETINTPS_INTCNT2_M 0xF0U // EPWMxINTn Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETSOCPS register +// +//************************************************************************************************* +#define HRPWM_ETSOCPS_SOCAPRD2_S 0U +#define HRPWM_ETSOCPS_SOCAPRD2_M 0xFU // EPWMxSOCA Period Select +#define HRPWM_ETSOCPS_SOCACNT2_S 4U +#define HRPWM_ETSOCPS_SOCACNT2_M 0xF0U // EPWMxSOCA Counter Register +#define HRPWM_ETSOCPS_SOCBPRD2_S 8U +#define HRPWM_ETSOCPS_SOCBPRD2_M 0xF00U // EPWMxSOCB Period Select +#define HRPWM_ETSOCPS_SOCBCNT2_S 12U +#define HRPWM_ETSOCPS_SOCBCNT2_M 0xF000U // EPWMxSOCB Counter Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINITCTL register +// +//************************************************************************************************* +#define HRPWM_ETCNTINITCTL_INTINITFRC 0x400U // EPWMxINT Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCAINITFRC 0x800U // EPWMxSOCA Counter Initialization Force +#define HRPWM_ETCNTINITCTL_SOCBINITFRC 0x1000U // EPWMxSOCB Counter Initialization Force +#define HRPWM_ETCNTINITCTL_INTINITEN 0x2000U // EPWMxINT Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCAINITEN 0x4000U // EPWMxSOCA Counter Initialization Enable +#define HRPWM_ETCNTINITCTL_SOCBINITEN 0x8000U // EPWMxSOCB Counter Initialization Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ETCNTINIT register +// +//************************************************************************************************* +#define HRPWM_ETCNTINIT_INTINIT_S 0U +#define HRPWM_ETCNTINIT_INTINIT_M 0xFU // EPWMxINT Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCAINIT_S 4U +#define HRPWM_ETCNTINIT_SOCAINIT_M 0xF0U // EPWMxSOCA Counter Initialization Bits +#define HRPWM_ETCNTINIT_SOCBINIT_S 8U +#define HRPWM_ETCNTINIT_SOCBINIT_M 0xF00U // EPWMxSOCB Counter Initialization Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_S 0U +#define HRPWM_DCTRIPSEL_DCAHCOMPSEL_M 0xFU // Digital Compare A High COMP Input Select +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_S 4U +#define HRPWM_DCTRIPSEL_DCALCOMPSEL_M 0xF0U // Digital Compare A Low COMP Input Select +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_S 8U +#define HRPWM_DCTRIPSEL_DCBHCOMPSEL_M 0xF00U // Digital Compare B High COMP Input Select +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_S 12U +#define HRPWM_DCTRIPSEL_DCBLCOMPSEL_M 0xF000U // Digital Compare B Low COMP Input Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCACTL register +// +//************************************************************************************************* +#define HRPWM_DCACTL_EVT1SRCSEL 0x1U // DCAEVT1 Source Signal +#define HRPWM_DCACTL_EVT1FRCSYNCSEL 0x2U // DCAEVT1 Force Sync Signal +#define HRPWM_DCACTL_EVT1SOCE 0x4U // DCAEVT1 SOC Enable +#define HRPWM_DCACTL_EVT1SYNCE 0x8U // DCAEVT1 SYNC Enable +#define HRPWM_DCACTL_EVT2SRCSEL 0x100U // DCAEVT2 Source Signal +#define HRPWM_DCACTL_EVT2FRCSYNCSEL 0x200U // DCAEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBCTL register +// +//************************************************************************************************* +#define HRPWM_DCBCTL_EVT1SRCSEL 0x1U // DCBEVT1 Source Signal +#define HRPWM_DCBCTL_EVT1FRCSYNCSEL 0x2U // DCBEVT1 Force Sync Signal +#define HRPWM_DCBCTL_EVT1SOCE 0x4U // DCBEVT1 SOC Enable +#define HRPWM_DCBCTL_EVT1SYNCE 0x8U // DCBEVT1 SYNC Enable +#define HRPWM_DCBCTL_EVT2SRCSEL 0x100U // DCBEVT2 Source Signal +#define HRPWM_DCBCTL_EVT2FRCSYNCSEL 0x200U // DCBEVT2 Force Sync Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCFCTL register +// +//************************************************************************************************* +#define HRPWM_DCFCTL_SRCSEL_S 0U +#define HRPWM_DCFCTL_SRCSEL_M 0x3U // Filter Block Signal Source Select +#define HRPWM_DCFCTL_BLANKE 0x4U // Blanking Enable/Disable +#define HRPWM_DCFCTL_BLANKINV 0x8U // Blanking Window Inversion +#define HRPWM_DCFCTL_PULSESEL_S 4U +#define HRPWM_DCFCTL_PULSESEL_M 0x30U // Pulse Select for Blanking & Capture Alignment +#define HRPWM_DCFCTL_EDGEFILTSEL 0x40U // Edge Filter Select +#define HRPWM_DCFCTL_EDGEMODE_S 8U +#define HRPWM_DCFCTL_EDGEMODE_M 0x300U // Edge Mode +#define HRPWM_DCFCTL_EDGECOUNT_S 10U +#define HRPWM_DCFCTL_EDGECOUNT_M 0x1C00U // Edge Count +#define HRPWM_DCFCTL_EDGESTATUS_S 13U +#define HRPWM_DCFCTL_EDGESTATUS_M 0xE000U // Edge Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCCAPCTL register +// +//************************************************************************************************* +#define HRPWM_DCCAPCTL_CAPE 0x1U // Counter Capture Enable +#define HRPWM_DCCAPCTL_SHDWMODE 0x2U // Counter Capture Mode +#define HRPWM_DCCAPCTL_CAPSTS 0x2000U // Latched Status Flag for Capture Event +#define HRPWM_DCCAPCTL_CAPCLR 0x4000U // DC Capture Latched Status Clear Flag +#define HRPWM_DCCAPCTL_CAPMODE 0x8000U // Counter Capture Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCAHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCAHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAH Mux +#define HRPWM_DCAHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCALTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCALTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCAL Mux +#define HRPWM_DCALTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCAL Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBHTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBHTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBH Mux +#define HRPWM_DCBHTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBH Mux + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DCBLTRIPSEL register +// +//************************************************************************************************* +#define HRPWM_DCBLTRIPSEL_TRIPINPUT1 0x1U // Trip Input 1 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT2 0x2U // Trip Input 2 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT3 0x4U // Trip Input 3 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT4 0x8U // Trip Input 4 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT5 0x10U // Trip Input 5 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT6 0x20U // Trip Input 6 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT7 0x40U // Trip Input 7 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT8 0x80U // Trip Input 8 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT9 0x100U // Trip Input 9 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT10 0x200U // Trip Input 10 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT11 0x400U // Trip Input 11 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT12 0x800U // Trip Input 12 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT14 0x2000U // Trip Input 14 Select to DCBL Mux +#define HRPWM_DCBLTRIPSEL_TRIPINPUT15 0x4000U // Trip Input 15 Select to DCBL Mux + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_i2c.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_i2c.h new file mode 100644 index 0000000..e37ef50 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_i2c.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_i2c.h +// +// TITLE: Definitions for the I2C registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_I2C_H +#define HW_I2C_H + +//************************************************************************************************* +// +// The following are defines for the I2C register offsets +// +//************************************************************************************************* +#define I2C_O_OAR 0x0U // I2C Own address +#define I2C_O_IER 0x1U // I2C Interrupt Enable +#define I2C_O_STR 0x2U // I2C Status +#define I2C_O_CLKL 0x3U // I2C Clock low-time divider +#define I2C_O_CLKH 0x4U // I2C Clock high-time divider +#define I2C_O_CNT 0x5U // I2C Data count +#define I2C_O_DRR 0x6U // I2C Data receive +#define I2C_O_SAR 0x7U // I2C Slave address +#define I2C_O_DXR 0x8U // I2C Data Transmit +#define I2C_O_MDR 0x9U // I2C Mode +#define I2C_O_ISRC 0xAU // I2C Interrupt Source +#define I2C_O_EMDR 0xBU // I2C Extended Mode +#define I2C_O_PSC 0xCU // I2C Prescaler +#define I2C_O_FFTX 0x20U // I2C FIFO Transmit +#define I2C_O_FFRX 0x21U // I2C FIFO Receive + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2COAR register +// +//************************************************************************************************* +#define I2C_OAR_OAR_S 0U +#define I2C_OAR_OAR_M 0x3FFU // I2C Own address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CIER register +// +//************************************************************************************************* +#define I2C_IER_ARBL 0x1U // Arbitration-lost interrupt enable +#define I2C_IER_NACK 0x2U // No-acknowledgment interrupt enable +#define I2C_IER_ARDY 0x4U // Register-access-ready interrupt enable +#define I2C_IER_RRDY 0x8U // Receive-data-ready interrupt enable +#define I2C_IER_XRDY 0x10U // Transmit-data-ready interrupt enable +#define I2C_IER_SCD 0x20U // Stop condition detected interrupt enable +#define I2C_IER_AAS 0x40U // Addressed as slave interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSTR register +// +//************************************************************************************************* +#define I2C_STR_ARBL 0x1U // Arbitration-lost interrupt flag bit +#define I2C_STR_NACK 0x2U // No-acknowledgment interrupt flag bit. +#define I2C_STR_ARDY 0x4U // Register-access-ready interrupt flag bit +#define I2C_STR_RRDY 0x8U // Receive-data-ready interrupt flag bit. +#define I2C_STR_XRDY 0x10U // Transmit-data-ready interrupt flag bit. +#define I2C_STR_SCD 0x20U // Stop condition detected bit. +#define I2C_STR_AD0 0x100U // Address 0 bits +#define I2C_STR_AAS 0x200U // Addressed-as-slave bit +#define I2C_STR_XSMT 0x400U // Transmit shift register empty bit. +#define I2C_STR_RSFULL 0x800U // Receive shift register full bit. +#define I2C_STR_BB 0x1000U // Bus busy bit. +#define I2C_STR_NACKSNT 0x2000U // NACK sent bit. +#define I2C_STR_SDIR 0x4000U // Slave direction bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDRR register +// +//************************************************************************************************* +#define I2C_DRR_DATA_S 0U +#define I2C_DRR_DATA_M 0xFFU // Receive data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CSAR register +// +//************************************************************************************************* +#define I2C_SAR_SAR_S 0U +#define I2C_SAR_SAR_M 0x3FFU // Slave Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CDXR register +// +//************************************************************************************************* +#define I2C_DXR_DATA_S 0U +#define I2C_DXR_DATA_M 0xFFU // Transmit data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CMDR register +// +//************************************************************************************************* +#define I2C_MDR_BC_S 0U +#define I2C_MDR_BC_M 0x7U // Bit count bits. +#define I2C_MDR_FDF 0x8U // Free Data Format +#define I2C_MDR_STB 0x10U // START Byte Mode +#define I2C_MDR_IRS 0x20U // I2C Module Reset +#define I2C_MDR_DLB 0x40U // Digital Loopback Mode +#define I2C_MDR_RM 0x80U // Repeat Mode +#define I2C_MDR_XA 0x100U // Expanded Address Mode +#define I2C_MDR_TRX 0x200U // Transmitter Mode +#define I2C_MDR_MST 0x400U // Master Mode +#define I2C_MDR_STP 0x800U // STOP Condition +#define I2C_MDR_STT 0x2000U // START condition bit +#define I2C_MDR_FREE 0x4000U // Debug Action +#define I2C_MDR_NACKMOD 0x8000U // NACK mode bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CISRC register +// +//************************************************************************************************* +#define I2C_ISRC_INTCODE_S 0U +#define I2C_ISRC_INTCODE_M 0x7U // Interrupt code bits. +#define I2C_ISRC_WRITE_ZEROS_S 8U +#define I2C_ISRC_WRITE_ZEROS_M 0xF00U // Always write all 0s to this field + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CEMDR register +// +//************************************************************************************************* +#define I2C_EMDR_BC 0x1U // Backwards compatibility mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CPSC register +// +//************************************************************************************************* +#define I2C_PSC_IPSC_S 0U +#define I2C_PSC_IPSC_M 0xFFU // I2C Prescaler Divide Down + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFTX register +// +//************************************************************************************************* +#define I2C_FFTX_TXFFIL_S 0U +#define I2C_FFTX_TXFFIL_M 0x1FU // Transmit FIFO Interrupt Level +#define I2C_FFTX_TXFFIENA 0x20U // Transmit FIFO Interrupt Enable +#define I2C_FFTX_TXFFINTCLR 0x40U // Transmit FIFO Interrupt Flag Clear +#define I2C_FFTX_TXFFINT 0x80U // Transmit FIFO Interrupt Flag +#define I2C_FFTX_TXFFST_S 8U +#define I2C_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define I2C_FFTX_TXFFRST 0x2000U // Transmit FIFO Reset +#define I2C_FFTX_I2CFFEN 0x4000U // Transmit FIFO Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the I2CFFRX register +// +//************************************************************************************************* +#define I2C_FFRX_RXFFIL_S 0U +#define I2C_FFRX_RXFFIL_M 0x1FU // Receive FIFO Interrupt Level +#define I2C_FFRX_RXFFIENA 0x20U // Receive FIFO Interrupt Enable +#define I2C_FFRX_RXFFINTCLR 0x40U // Receive FIFO Interrupt Flag Clear +#define I2C_FFRX_RXFFINT 0x80U // Receive FIFO Interrupt Flag +#define I2C_FFRX_RXFFST_S 8U +#define I2C_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define I2C_FFRX_RXFFRST 0x2000U // Receive FIFO Reset + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_inputxbar.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_inputxbar.h new file mode 100644 index 0000000..a2567f2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_inputxbar.h @@ -0,0 +1,92 @@ +//########################################################################### +// +// FILE: hw_inputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_INPUTXBAR_H +#define HW_INPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_INPUT1SELECT 0x0U // INPUT1 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT2SELECT 0x1U // INPUT2 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT3SELECT 0x2U // INPUT3 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT4SELECT 0x3U // INPUT4 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT5SELECT 0x4U // INPUT5 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT6SELECT 0x5U // INPUT6 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT7SELECT 0x6U // INPUT7 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT8SELECT 0x7U // INPUT8 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT9SELECT 0x8U // INPUT9 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT10SELECT 0x9U // INPUT10 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT11SELECT 0xAU // INPUT11 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT12SELECT 0xBU // INPUT12 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT13SELECT 0xCU // INPUT13 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUT14SELECT 0xDU // INPUT14 Input Select Register (GPIO0 to x) +#define XBAR_O_INPUTSELECTLOCK 0x1EU // Input Select Lock Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INPUTSELECTLOCK register +// +//************************************************************************************************* +#define XBAR_INPUTSELECTLOCK_INPUT1SELECT 0x1U // Lock bit for INPUT1SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT2SELECT 0x2U // Lock bit for INPUT2SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT3SELECT 0x4U // Lock bit for INPUT3SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT4SELECT 0x8U // Lock bit for INPUT4SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT5SELECT 0x10U // Lock bit for INPUT5SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT6SELECT 0x20U // Lock bit for INPUT6SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT7SELECT 0x40U // Lock bit for INPUT7SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT8SELECT 0x80U // Lock bit for INPUT8SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT9SELECT 0x100U // Lock bit for INPUT9SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT10SELECT 0x200U // Lock bit for INPUT10SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT11SELECT 0x400U // Lock bit for INPUT11SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT12SELECT 0x800U // Lock bit for INPUT12SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT13SELECT 0x1000U // Lock bit for INPUT13SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT14SELECT 0x2000U // Lock bit for INPUT14SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT15SELECT 0x4000U // Lock bit for INPUT15SELECT Register +#define XBAR_INPUTSELECTLOCK_INPUT16SELECT 0x8000U // Lock bit for INPUT16SELECT Register + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_ints.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ints.h new file mode 100644 index 0000000..d49c58d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ints.h @@ -0,0 +1,212 @@ +//########################################################################### +// +// FILE: hw_ints.h +// +// TITLE: Definitions of interrupt numbers for use with interrupt.c. +// +//########################################################################### +// +// +//########################################################################### + +#ifndef HW_INTS_H +#define HW_INTS_H + +//***************************************************************************** +// +// PIE Interrupt Numbers +// +// 0x00FF = PIE Table Row # +// 0xFF00 = PIE Table Column # +// 0xFFFF0000 = PIE Vector ID +// +//***************************************************************************** + +// Lower PIE Group 1 +#define INT_ADCA1 0x00200101U // 1.1 - ADCA Interrupt 1 +#define INT_ADCB1 0x00210102U // 1.2 - ADCB Interrupt 1 +#define INT_ADCC1 0x00220103U // 1.3 - ADCC Interrupt 1 +#define INT_XINT1 0x00230104U // 1.4 - XINT1 Interrupt +#define INT_XINT2 0x00240105U // 1.5 - XINT2 Interrupt +#define INT_ADCD1 0x00250106U // 1.6 - ADCD Interrupt 1 +#define INT_TIMER0 0x00260107U // 1.7 - Timer 0 Interrupt +#define INT_WAKE 0x00270108U // 1.8 - Standby and Halt Wakeup Interrupt + +// Lower PIE Group 2 +#define INT_EPWM1_TZ 0x00280201U // 2.1 - ePWM1 Trip Zone Interrupt +#define INT_EPWM2_TZ 0x00290202U // 2.2 - ePWM2 Trip Zone Interrupt +#define INT_EPWM3_TZ 0x002A0203U // 2.3 - ePWM3 Trip Zone Interrupt +#define INT_EPWM4_TZ 0x002B0204U // 2.4 - ePWM4 Trip Zone Interrupt +#define INT_EPWM5_TZ 0x002C0205U // 2.5 - ePWM5 Trip Zone Interrupt +#define INT_EPWM6_TZ 0x002D0206U // 2.6 - ePWM6 Trip Zone Interrupt +#define INT_EPWM7_TZ 0x002E0207U // 2.7 - ePWM7 Trip Zone Interrupt +#define INT_EPWM8_TZ 0x002F0208U // 2.8 - ePWM8 Trip Zone Interrupt + +// Lower PIE Group 3 +#define INT_EPWM1 0x00300301U // 3.1 - ePWM1 Interrupt +#define INT_EPWM2 0x00310302U // 3.2 - ePWM2 Interrupt +#define INT_EPWM3 0x00320303U // 3.3 - ePWM3 Interrupt +#define INT_EPWM4 0x00330304U // 3.4 - ePWM4 Interrupt +#define INT_EPWM5 0x00340305U // 3.5 - ePWM5 Interrupt +#define INT_EPWM6 0x00350306U // 3.6 - ePWM6 Interrupt +#define INT_EPWM7 0x00360307U // 3.7 - ePWM7 Interrupt +#define INT_EPWM8 0x00370308U // 3.8 - ePWM8 Interrupt + +// Lower PIE Group 4 +#define INT_ECAP1 0x00380401U // 4.1 - eCAP1 Interrupt +#define INT_ECAP2 0x00390402U // 4.2 - eCAP2 Interrupt +#define INT_ECAP3 0x003A0403U // 4.3 - eCAP3 Interrupt +#define INT_ECAP4 0x003B0404U // 4.4 - eCAP4 Interrupt +#define INT_ECAP5 0x003C0405U // 4.5 - eCAP5 Interrupt +#define INT_ECAP6 0x003D0406U // 4.6 - eCAP6 Interrupt +// Lower PIE Group 5 +#define INT_EQEP1 0x00400501U // 5.1 - eQEP1 Interrupt +#define INT_EQEP2 0x00410502U // 5.2 - eQEP2 Interrupt +#define INT_EQEP3 0x00420503U // 5.3 - eQEP3 Interrupt +#define INT_CLB1 0x00440505U // 5.5 - CLB1 (Reconfigurable Logic) Interrupt +#define INT_CLB2 0x00450506U // 5.6 - CLB2 (Reconfigurable Logic) Interrupt +#define INT_CLB3 0x00460507U // 5.7 - CLB3 (Reconfigurable Logic) Interrupt +#define INT_CLB4 0x00470508U // 5.8 - CLB4 (Reconfigurable Logic) Interrupt + +// Lower PIE Group 6 +#define INT_SPIA_RX 0x00480601U // 6.1 - SPIA Receive Interrupt +#define INT_SPIA_TX 0x00490602U // 6.2 - SPIA Transmit Interrupt +#define INT_SPIB_RX 0x004A0603U // 6.3 - SPIB Receive Interrupt +#define INT_SPIB_TX 0x004B0604U // 6.4 - SPIB Transmit Interrupt +#define INT_MCBSPA_RX 0x004C0605U // 6.5 - McBSPA Receive Interrupt +#define INT_MCBSPA_TX 0x004D0606U // 6.6 - McBSPA Transmit Interrupt +#define INT_MCBSPB_RX 0x004E0607U // 6.7 - McBSPB Receive Interrupt +#define INT_MCBSPB_TX 0x004F0608U // 6.8 - McBSPB Transmit Interrupt + +// Lower PIE Group 7 +#define INT_DMA_CH1 0x00500701U // 7.1 - DMA Channel 1 Interrupt +#define INT_DMA_CH2 0x00510702U // 7.2 - DMA Channel 2 Interrupt +#define INT_DMA_CH3 0x00520703U // 7.3 - DMA Channel 3 Interrupt +#define INT_DMA_CH4 0x00530704U // 7.4 - DMA Channel 4 Interrupt +#define INT_DMA_CH5 0x00540705U // 7.5 - DMA Channel 5 Interrupt +#define INT_DMA_CH6 0x00550706U // 7.6 - DMA Channel 6 Interrupt + +// Lower PIE Group 8 +#define INT_I2CA 0x00580801U // 8.1 - I2CA Interrupt 1 +#define INT_I2CA_FIFO 0x00590802U // 8.2 - I2CA Interrupt 2 +#define INT_I2CB 0x005A0803U // 8.3 - I2CB Interrupt 1 +#define INT_I2CB_FIFO 0x005B0804U // 8.4 - I2CB Interrupt 2 +#define INT_SCIC_RX 0x005C0805U // 8.5 - SCIC Receive Interrupt +#define INT_SCIC_TX 0x005D0806U // 8.6 - SCIC Transmit Interrupt +#define INT_SCID_RX 0x005E0807U // 8.7 - SCID Receive Interrupt +#define INT_SCID_TX 0x005F0808U // 8.8 - SCID Transmit Interrupt + +// Lower PIE Group 9 +#define INT_SCIA_RX 0x00600901U // 9.1 - SCIA Receive Interrupt +#define INT_SCIA_TX 0x00610902U // 9.2 - SCIA Transmit Interrupt +#define INT_SCIB_RX 0x00620903U // 9.3 - SCIB Receive Interrupt +#define INT_SCIB_TX 0x00630904U // 9.4 - SCIB Transmit Interrupt +#define INT_CANA0 0x00640905U // 9.5 - CANA Interrupt 0 +#define INT_CANA1 0x00650906U // 9.6 - CANA Interrupt 1 +#define INT_CANB0 0x00660907U // 9.7 - CANB Interrupt 0 +#define INT_CANB1 0x00670908U // 9.8 - CANB Interrupt 1 + +// Lower PIE Group 10 +#define INT_ADCA_EVT 0x00680A01U // 10.1 - ADCA Event Interrupt +#define INT_ADCA2 0x00690A02U // 10.2 - ADCA Interrupt 2 +#define INT_ADCA3 0x006A0A03U // 10.3 - ADCA Interrupt 3 +#define INT_ADCA4 0x006B0A04U // 10.4 - ADCA Interrupt 4 +#define INT_ADCB_EVT 0x006C0A05U // 10.5 - ADCB Event Interrupt +#define INT_ADCB2 0x006D0A06U // 10.6 - ADCB Interrupt 2 +#define INT_ADCB3 0x006E0A07U // 10.7 - ADCB Interrupt 3 +#define INT_ADCB4 0x006F0A08U // 10.8 - ADCB Interrupt 4 + +// Lower PIE Group 11 +#define INT_CLA1_1 0x00700B01U // 11.1 - CLA1 Interrupt 1 +#define INT_CLA1_2 0x00710B02U // 11.2 - CLA1 Interrupt 2 +#define INT_CLA1_3 0x00720B03U // 11.3 - CLA1 Interrupt 3 +#define INT_CLA1_4 0x00730B04U // 11.4 - CLA1 Interrupt 4 +#define INT_CLA1_5 0x00740B05U // 11.5 - CLA1 Interrupt 5 +#define INT_CLA1_6 0x00750B06U // 11.6 - CLA1 Interrupt 6 +#define INT_CLA1_7 0x00760B07U // 11.7 - CLA1 Interrupt 7 +#define INT_CLA1_8 0x00770B08U // 11.8 - CLA1 Interrupt 8 + +// Lower PIE Group 12 +#define INT_XINT3 0x00780C01U // 12.1 - XINT3 Interrupt +#define INT_XINT4 0x00790C02U // 12.2 - XINT4 Interrupt +#define INT_XINT5 0x007A0C03U // 12.3 - XINT5 Interrupt +#define INT_PBIST 0x007B0C04U // 12.4 - PBIST Interrupt +#define INT_FMC 0x007C0C05U // 12.5 - Flash Wrapper Operation Done Interrupt +#define INT_VCU 0x007D0C06U // 12.6 - VCU Interrupt +#define INT_FPU_OVERFLOW 0x007E0C07U // 12.7 - FPU Overflow Interrupt +#define INT_FPU_UNDERFLOW 0x007F0C08U // 12.8 - FPU Underflow Interrupt + +// Upper PIE Group 1 +#define INT_IPC_0 0x0084010DU // 1.13 - IPC Interrupt 1 +#define INT_IPC_1 0x0085010EU // 1.14 - IPC Interrupt 2 +#define INT_IPC_2 0x0086010FU // 1.15 - IPC Interrupt 3 +#define INT_IPC_3 0x00870110U // 1.16 - IPC Interrupt 4 + +// Upper PIE Group 2 +#define INT_EPWM9_TZ 0x00880209U // 2.9 - ePWM9 Trip Zone Interrupt +#define INT_EPWM10_TZ 0x0089020AU // 2.10 - ePWM10 Trip Zone Interrupt +#define INT_EPWM11_TZ 0x008A020BU // 2.11 - ePWM11 Trip Zone Interrupt +#define INT_EPWM12_TZ 0x008B020CU // 2.12 - ePWM12 Trip Zone Interrupt + +// Upper PIE Group 3 +#define INT_EPWM9 0x00900309U // 3.9 - ePWM9 Interrupt +#define INT_EPWM10 0x0091030AU // 3.10 - ePWM10 Interrupt +#define INT_EPWM11 0x0092030BU // 3.11 - ePWM11 Interrupt +#define INT_EPWM12 0x0093030CU // 3.12 - ePWM12 Interrupt + +// Upper PIE Group 5 +#define INT_SD1 0x00A00509U // 5.9 - SD1 Interrupt +#define INT_SD2 0x00A1050AU // 5.10 - SD2 Interrupt + +// Upper PIE Group 6 +#define INT_SPIC_RX 0x00A80609U // 6.9 - SPIC Receive Interrupt +#define INT_SPIC_TX 0x00A9060AU // 6.10 - SPIC Transmit Interrupt + +// Upper PIE Group 8 +#define INT_UPPA 0x00BE080FU // 8.15 - uPPA Interrupt + +// Upper PIE Group 9 +#define INT_USBA 0x00C6090FU // 9.15 - USBA Interrupt + +// Upper PIE Group 10 +#define INT_ADCC_EVT 0x00C80A09U // 10.9 - ADCC Event Interrupt +#define INT_ADCC2 0x00C90A0AU // 10.10 - ADCC Interrupt 2 +#define INT_ADCC3 0x00CA0A0BU // 10.11 - ADCC Interrupt 3 +#define INT_ADCC4 0x00CB0A0CU // 10.12 - ADCC Interrupt 4 +#define INT_ADCD_EVT 0x00CC0A0DU // 10.13 - ADCD Event Interrupt +#define INT_ADCD2 0x00CD0A0EU // 10.14 - ADCD Interrupt 2 +#define INT_ADCD3 0x00CE0A0FU // 10.15 - ADCD Interrupt 3 +#define INT_ADCD4 0x00CF0A10U // 10.16 - ADCD Interrupt 4 + +// Upper PIE Group 12 +#define INT_EMIF_ERROR 0x00D80C09U // 12.9 - EMIF Error Interrupt +#define INT_RAM_CORR_ERR 0x00D90C0AU // 12.10 - RAM Correctable Error Interrupt +#define INT_FLASH_CORR_ERR 0x00DA0C0BU // 12.11 - Flash Correctable Error Interrupt +#define INT_RAM_ACC_VIOL 0x00DB0C0CU // 12.12 - RAM Access Violation Interrupt +#define INT_SYS_PLL_SLIP 0x00DC0C0DU // 12.13 - System PLL Slip Interrupt +#define INT_AUX_PLL_SLIP 0x00DD0C0EU // 12.14 - Auxiliary PLL Slip Interrupt +#define INT_CLA_OVERFLOW 0x00DE0C0FU // 12.15 - CLA Overflow Interrupt +#define INT_CLA_UNDERFLOW 0x00DF0C10U // 12.16 - CLA Underflow Interrupt + +// Other interrupts +#define INT_TIMER1 0x000D0000U // CPU Timer 1 Interrupt +#define INT_TIMER2 0x000E0000U // CPU Timer 2 Interrupt +#define INT_DATALOG 0x000F0000U // Datalogging Interrupt +#define INT_RTOS 0x00100000U // RTOS Interrupt +#define INT_EMU 0x00110000U // Emulation Interrupt +#define INT_NMI 0x00120000U // Non-Maskable Interrupt +#define INT_ILLEGAL 0x00130000U // Illegal Operation Trap +#define INT_USER1 0x00140000U // User Defined Trap 1 +#define INT_USER2 0x00150000U // User Defined Trap 2 +#define INT_USER3 0x00160000U // User Defined Trap 3 +#define INT_USER4 0x00170000U // User Defined Trap 4 +#define INT_USER5 0x00180000U // User Defined Trap 5 +#define INT_USER6 0x00190000U // User Defined Trap 6 +#define INT_USER7 0x001A0000U // User Defined Trap 7 +#define INT_USER8 0x001B0000U // User Defined Trap 8 +#define INT_USER9 0x001C0000U // User Defined Trap 9 +#define INT_USER10 0x001D0000U // User Defined Trap 10 +#define INT_USER11 0x001E0000U // User Defined Trap 11 +#define INT_USER12 0x001F0000U // User Defined Trap 12 + +#endif // HW_INTS_H diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_ipc.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ipc.h new file mode 100644 index 0000000..e99715f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_ipc.h @@ -0,0 +1,323 @@ +//########################################################################### +// +// FILE: hw_ipc.h +// +// TITLE: Definitions for the IPC registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_IPC_H +#define HW_IPC_H + +//***************************************************************************** +// +// The following are defines for the IPC register offsets +// +//***************************************************************************** +#define IPC_O_ACK 0x0U // IPC incoming flag clear + // (acknowledge) register +#define IPC_O_STS 0x2U // IPC incoming flag status + // register +#define IPC_O_SET 0x4U // IPC remote flag set register +#define IPC_O_CLR 0x6U // IPC remote flag clear + // register +#define IPC_O_FLG 0x8U // IPC remote flag status + // register +#define IPC_O_COUNTERL 0xCU // IPC Counter Low Register +#define IPC_O_COUNTERH 0xEU // IPC Counter High Register +#ifndef CPU2 +#define IPC_O_SENDCOM 0x10U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x12U // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x14U // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x16U // Remote to Local IPC Reply + // Data Register +#define IPC_O_RECVCOM 0x18U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x1AU // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x1CU // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x1EU // Local to Remote IPC Reply + // Data Register +#else +#define IPC_O_RECVCOM 0x10U // Remote to Local IPC Command + // Register +#define IPC_O_RECVADDR 0x12U // Remote to Local IPC Address + // Register +#define IPC_O_RECVDATA 0x14U // Remote to Local IPC Data + // Register +#define IPC_O_LOCALREPLY 0x16U // Local to Remote IPC Reply + // Data Register +#define IPC_O_SENDCOM 0x18U // Local to Remote IPC Command + // Register +#define IPC_O_SENDADDR 0x1AU // Local to Remote IPC Address + // Register +#define IPC_O_SENDDATA 0x1CU // Local to Remote IPC Data + // Register +#define IPC_O_REMOTEREPLY 0x1EU // Remote to Local IPC Reply + // Data Register +#endif +#define IPC_O_BOOTSTS 0x20U // CPU2 to CPU1 IPC Boot Status + // Register +#define IPC_O_BOOTMODE 0x22U // CPU1 to CPU2 IPC Boot Mode + // Register + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCACK register +// +//***************************************************************************** +#define IPC_ACK_IPC0 0x1U // Local IPC Flag 0 + // Acknowledgement +#define IPC_ACK_IPC1 0x2U // Local IPC Flag 1 + // Acknowledgement +#define IPC_ACK_IPC2 0x4U // Local IPC Flag 2 + // Acknowledgement +#define IPC_ACK_IPC3 0x8U // Local IPC Flag 3 + // Acknowledgement +#define IPC_ACK_IPC4 0x10U // Local IPC Flag 4 + // Acknowledgement +#define IPC_ACK_IPC5 0x20U // Local IPC Flag 5 + // Acknowledgement +#define IPC_ACK_IPC6 0x40U // Local IPC Flag 6 + // Acknowledgement +#define IPC_ACK_IPC7 0x80U // Local IPC Flag 7 + // Acknowledgement +#define IPC_ACK_IPC8 0x100U // Local IPC Flag 8 + // Acknowledgement +#define IPC_ACK_IPC9 0x200U // Local IPC Flag 9 + // Acknowledgement +#define IPC_ACK_IPC10 0x400U // Local IPC Flag 10 + // Acknowledgement +#define IPC_ACK_IPC11 0x800U // Local IPC Flag 11 + // Acknowledgement +#define IPC_ACK_IPC12 0x1000U // Local IPC Flag 12 + // Acknowledgement +#define IPC_ACK_IPC13 0x2000U // Local IPC Flag 13 + // Acknowledgement +#define IPC_ACK_IPC14 0x4000U // Local IPC Flag 14 + // Acknowledgement +#define IPC_ACK_IPC15 0x8000U // Local IPC Flag 15 + // Acknowledgement +#define IPC_ACK_IPC16 0x10000U // Local IPC Flag 16 + // Acknowledgement +#define IPC_ACK_IPC17 0x20000U // Local IPC Flag 17 + // Acknowledgement +#define IPC_ACK_IPC18 0x40000U // Local IPC Flag 18 + // Acknowledgement +#define IPC_ACK_IPC19 0x80000U // Local IPC Flag 19 + // Acknowledgement +#define IPC_ACK_IPC20 0x100000U // Local IPC Flag 20 + // Acknowledgement +#define IPC_ACK_IPC21 0x200000U // Local IPC Flag 21 + // Acknowledgement +#define IPC_ACK_IPC22 0x400000U // Local IPC Flag 22 + // Acknowledgement +#define IPC_ACK_IPC23 0x800000U // Local IPC Flag 23 + // Acknowledgement +#define IPC_ACK_IPC24 0x1000000U // Local IPC Flag 24 + // Acknowledgement +#define IPC_ACK_IPC25 0x2000000U // Local IPC Flag 25 + // Acknowledgement +#define IPC_ACK_IPC26 0x4000000U // Local IPC Flag 26 + // Acknowledgement +#define IPC_ACK_IPC27 0x8000000U // Local IPC Flag 27 + // Acknowledgement +#define IPC_ACK_IPC28 0x10000000U // Local IPC Flag 28 + // Acknowledgement +#define IPC_ACK_IPC29 0x20000000U // Local IPC Flag 29 + // Acknowledgement +#define IPC_ACK_IPC30 0x40000000U // Local IPC Flag 30 + // Acknowledgement +#define IPC_ACK_IPC31 0x80000000U // Local IPC Flag 31 + // Acknowledgement + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSTS register +// +//***************************************************************************** +#define IPC_STS_IPC0 0x1U // Local IPC Flag 0 Status +#define IPC_STS_IPC1 0x2U // Local IPC Flag 1 Status +#define IPC_STS_IPC2 0x4U // Local IPC Flag 2 Status +#define IPC_STS_IPC3 0x8U // Local IPC Flag 3 Status +#define IPC_STS_IPC4 0x10U // Local IPC Flag 4 Status +#define IPC_STS_IPC5 0x20U // Local IPC Flag 5 Status +#define IPC_STS_IPC6 0x40U // Local IPC Flag 6 Status +#define IPC_STS_IPC7 0x80U // Local IPC Flag 7 Status +#define IPC_STS_IPC8 0x100U // Local IPC Flag 8 Status +#define IPC_STS_IPC9 0x200U // Local IPC Flag 9 Status +#define IPC_STS_IPC10 0x400U // Local IPC Flag 10 Status +#define IPC_STS_IPC11 0x800U // Local IPC Flag 11 Status +#define IPC_STS_IPC12 0x1000U // Local IPC Flag 12 Status +#define IPC_STS_IPC13 0x2000U // Local IPC Flag 13 Status +#define IPC_STS_IPC14 0x4000U // Local IPC Flag 14 Status +#define IPC_STS_IPC15 0x8000U // Local IPC Flag 15 Status +#define IPC_STS_IPC16 0x10000U // Local IPC Flag 16 Status +#define IPC_STS_IPC17 0x20000U // Local IPC Flag 17 Status +#define IPC_STS_IPC18 0x40000U // Local IPC Flag 18 Status +#define IPC_STS_IPC19 0x80000U // Local IPC Flag 19 Status +#define IPC_STS_IPC20 0x100000U // Local IPC Flag 20 Status +#define IPC_STS_IPC21 0x200000U // Local IPC Flag 21 Status +#define IPC_STS_IPC22 0x400000U // Local IPC Flag 22 Status +#define IPC_STS_IPC23 0x800000U // Local IPC Flag 23 Status +#define IPC_STS_IPC24 0x1000000U // Local IPC Flag 24 Status +#define IPC_STS_IPC25 0x2000000U // Local IPC Flag 25 Status +#define IPC_STS_IPC26 0x4000000U // Local IPC Flag 26 Status +#define IPC_STS_IPC27 0x8000000U // Local IPC Flag 27 Status +#define IPC_STS_IPC28 0x10000000U // Local IPC Flag 28 Status +#define IPC_STS_IPC29 0x20000000U // Local IPC Flag 29 Status +#define IPC_STS_IPC30 0x40000000U // Local IPC Flag 30 Status +#define IPC_STS_IPC31 0x80000000U // Local IPC Flag 31 Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCSET register +// +//***************************************************************************** +#define IPC_SET_IPC0 0x1U // Set Remote IPC0 Flag +#define IPC_SET_IPC1 0x2U // Set Remote IPC1 Flag +#define IPC_SET_IPC2 0x4U // Set Remote IPC2 Flag +#define IPC_SET_IPC3 0x8U // Set Remote IPC3 Flag +#define IPC_SET_IPC4 0x10U // Set Remote IPC4 Flag +#define IPC_SET_IPC5 0x20U // Set Remote IPC5 Flag +#define IPC_SET_IPC6 0x40U // Set Remote IPC6 Flag +#define IPC_SET_IPC7 0x80U // Set Remote IPC7 Flag +#define IPC_SET_IPC8 0x100U // Set Remote IPC8 Flag +#define IPC_SET_IPC9 0x200U // Set Remote IPC9 Flag +#define IPC_SET_IPC10 0x400U // Set Remote IPC10 Flag +#define IPC_SET_IPC11 0x800U // Set Remote IPC11 Flag +#define IPC_SET_IPC12 0x1000U // Set Remote IPC12 Flag +#define IPC_SET_IPC13 0x2000U // Set Remote IPC13 Flag +#define IPC_SET_IPC14 0x4000U // Set Remote IPC14 Flag +#define IPC_SET_IPC15 0x8000U // Set Remote IPC15 Flag +#define IPC_SET_IPC16 0x10000U // Set Remote IPC16 Flag +#define IPC_SET_IPC17 0x20000U // Set Remote IPC17 Flag +#define IPC_SET_IPC18 0x40000U // Set Remote IPC18 Flag +#define IPC_SET_IPC19 0x80000U // Set Remote IPC19 Flag +#define IPC_SET_IPC20 0x100000U // Set Remote IPC20 Flag +#define IPC_SET_IPC21 0x200000U // Set Remote IPC21 Flag +#define IPC_SET_IPC22 0x400000U // Set Remote IPC22 Flag +#define IPC_SET_IPC23 0x800000U // Set Remote IPC23 Flag +#define IPC_SET_IPC24 0x1000000U // Set Remote IPC24 Flag +#define IPC_SET_IPC25 0x2000000U // Set Remote IPC25 Flag +#define IPC_SET_IPC26 0x4000000U // Set Remote IPC26 Flag +#define IPC_SET_IPC27 0x8000000U // Set Remote IPC27 Flag +#define IPC_SET_IPC28 0x10000000U // Set Remote IPC28 Flag +#define IPC_SET_IPC29 0x20000000U // Set Remote IPC29 Flag +#define IPC_SET_IPC30 0x40000000U // Set Remote IPC30 Flag +#define IPC_SET_IPC31 0x80000000U // Set Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCCLR register +// +//***************************************************************************** +#define IPC_CLR_IPC0 0x1U // Clear Remote IPC0 Flag +#define IPC_CLR_IPC1 0x2U // Clear Remote IPC1 Flag +#define IPC_CLR_IPC2 0x4U // Clear Remote IPC2 Flag +#define IPC_CLR_IPC3 0x8U // Clear Remote IPC3 Flag +#define IPC_CLR_IPC4 0x10U // Clear Remote IPC4 Flag +#define IPC_CLR_IPC5 0x20U // Clear Remote IPC5 Flag +#define IPC_CLR_IPC6 0x40U // Clear Remote IPC6 Flag +#define IPC_CLR_IPC7 0x80U // Clear Remote IPC7 Flag +#define IPC_CLR_IPC8 0x100U // Clear Remote IPC8 Flag +#define IPC_CLR_IPC9 0x200U // Clear Remote IPC9 Flag +#define IPC_CLR_IPC10 0x400U // Clear Remote IPC10 Flag +#define IPC_CLR_IPC11 0x800U // Clear Remote IPC11 Flag +#define IPC_CLR_IPC12 0x1000U // Clear Remote IPC12 Flag +#define IPC_CLR_IPC13 0x2000U // Clear Remote IPC13 Flag +#define IPC_CLR_IPC14 0x4000U // Clear Remote IPC14 Flag +#define IPC_CLR_IPC15 0x8000U // Clear Remote IPC15 Flag +#define IPC_CLR_IPC16 0x10000U // Clear Remote IPC16 Flag +#define IPC_CLR_IPC17 0x20000U // Clear Remote IPC17 Flag +#define IPC_CLR_IPC18 0x40000U // Clear Remote IPC18 Flag +#define IPC_CLR_IPC19 0x80000U // Clear Remote IPC19 Flag +#define IPC_CLR_IPC20 0x100000U // Clear Remote IPC20 Flag +#define IPC_CLR_IPC21 0x200000U // Clear Remote IPC21 Flag +#define IPC_CLR_IPC22 0x400000U // Clear Remote IPC22 Flag +#define IPC_CLR_IPC23 0x800000U // Clear Remote IPC23 Flag +#define IPC_CLR_IPC24 0x1000000U // Clear Remote IPC24 Flag +#define IPC_CLR_IPC25 0x2000000U // Clear Remote IPC25 Flag +#define IPC_CLR_IPC26 0x4000000U // Clear Remote IPC26 Flag +#define IPC_CLR_IPC27 0x8000000U // Clear Remote IPC27 Flag +#define IPC_CLR_IPC28 0x10000000U // Clear Remote IPC28 Flag +#define IPC_CLR_IPC29 0x20000000U // Clear Remote IPC29 Flag +#define IPC_CLR_IPC30 0x40000000U // Clear Remote IPC30 Flag +#define IPC_CLR_IPC31 0x80000000U // Clear Remote IPC31 Flag + +//***************************************************************************** +// +// The following are defines for the bit fields in the IPCFLG register +// +//***************************************************************************** +#define IPC_FLG_IPC0 0x1U // Remote IPC0 Flag Status +#define IPC_FLG_IPC1 0x2U // Remote IPC1 Flag Status +#define IPC_FLG_IPC2 0x4U // Remote IPC2 Flag Status +#define IPC_FLG_IPC3 0x8U // Remote IPC3 Flag Status +#define IPC_FLG_IPC4 0x10U // Remote IPC4 Flag Status +#define IPC_FLG_IPC5 0x20U // Remote IPC5 Flag Status +#define IPC_FLG_IPC6 0x40U // Remote IPC6 Flag Status +#define IPC_FLG_IPC7 0x80U // Remote IPC7 Flag Status +#define IPC_FLG_IPC8 0x100U // Remote IPC8 Flag Status +#define IPC_FLG_IPC9 0x200U // Remote IPC9 Flag Status +#define IPC_FLG_IPC10 0x400U // Remote IPC10 Flag Status +#define IPC_FLG_IPC11 0x800U // Remote IPC11 Flag Status +#define IPC_FLG_IPC12 0x1000U // Remote IPC12 Flag Status +#define IPC_FLG_IPC13 0x2000U // Remote IPC13 Flag Status +#define IPC_FLG_IPC14 0x4000U // Remote IPC14 Flag Status +#define IPC_FLG_IPC15 0x8000U // Remote IPC15 Flag Status +#define IPC_FLG_IPC16 0x10000U // Remote IPC16 Flag Status +#define IPC_FLG_IPC17 0x20000U // Remote IPC17 Flag Status +#define IPC_FLG_IPC18 0x40000U // Remote IPC18 Flag Status +#define IPC_FLG_IPC19 0x80000U // Remote IPC19 Flag Status +#define IPC_FLG_IPC20 0x100000U // Remote IPC20 Flag Status +#define IPC_FLG_IPC21 0x200000U // Remote IPC21 Flag Status +#define IPC_FLG_IPC22 0x400000U // Remote IPC22 Flag Status +#define IPC_FLG_IPC23 0x800000U // Remote IPC23 Flag Status +#define IPC_FLG_IPC24 0x1000000U // Remote IPC24 Flag Status +#define IPC_FLG_IPC25 0x2000000U // Remote IPC25 Flag Status +#define IPC_FLG_IPC26 0x4000000U // Remote IPC26 Flag Status +#define IPC_FLG_IPC27 0x8000000U // Remote IPC27 Flag Status +#define IPC_FLG_IPC28 0x10000000U // Remote IPC28 Flag Status +#define IPC_FLG_IPC29 0x20000000U // Remote IPC29 Flag Status +#define IPC_FLG_IPC30 0x40000000U // Remote IPC30 Flag Status +#define IPC_FLG_IPC31 0x80000000U // Remote IPC31 Flag Status +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_mcbsp.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_mcbsp.h new file mode 100644 index 0000000..814055f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_mcbsp.h @@ -0,0 +1,286 @@ +//########################################################################### +// +// FILE: hw_mcbsp.h +// +// TITLE: Definitions for the MCBSP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MCBSP_H +#define HW_MCBSP_H + +//************************************************************************************************* +// +// The following are defines for the MCBSP register offsets +// +//************************************************************************************************* +#define MCBSP_O_DRR2 0x0U // Data receive register bits 31-16 +#define MCBSP_O_DRR1 0x1U // Data receive register bits 15-0 +#define MCBSP_O_DXR2 0x2U // Data transmit register bits 31-16 +#define MCBSP_O_DXR1 0x3U // Data transmit register bits 15-0 +#define MCBSP_O_SPCR2 0x4U // Serial port control register 2 +#define MCBSP_O_SPCR1 0x5U // Serial port control register 1 +#define MCBSP_O_RCR2 0x6U // Receive Control register 2 +#define MCBSP_O_RCR1 0x7U // Receive Control register 1 +#define MCBSP_O_XCR2 0x8U // Transmit Control register 2 +#define MCBSP_O_XCR1 0x9U // Transmit Control register 1 +#define MCBSP_O_SRGR2 0xAU // Sample rate generator register 2 +#define MCBSP_O_SRGR1 0xBU // Sample rate generator register 1 +#define MCBSP_O_MCR2 0xCU // Multi-channel control register 2 +#define MCBSP_O_MCR1 0xDU // Multi-channel control register 1 +#define MCBSP_O_RCERA 0xEU // Receive channel enable partition A +#define MCBSP_O_RCERB 0xFU // Receive channel enable partition B +#define MCBSP_O_XCERA 0x10U // Transmit channel enable partition A +#define MCBSP_O_XCERB 0x11U // Transmit channel enable partition B +#define MCBSP_O_PCR 0x12U // Pin Control register +#define MCBSP_O_RCERC 0x13U // Receive channel enable partition C +#define MCBSP_O_RCERD 0x14U // Receive channel enable partition D +#define MCBSP_O_XCERC 0x15U // Transmit channel enable partition C +#define MCBSP_O_XCERD 0x16U // Transmit channel enable partition D +#define MCBSP_O_RCERE 0x17U // Receive channel enable partition E +#define MCBSP_O_RCERF 0x18U // Receive channel enable partition F +#define MCBSP_O_XCERE 0x19U // Transmit channel enable partition E +#define MCBSP_O_XCERF 0x1AU // Transmit channel enable partition F +#define MCBSP_O_RCERG 0x1BU // Receive channel enable partition G +#define MCBSP_O_RCERH 0x1CU // Receive channel enable partition H +#define MCBSP_O_XCERG 0x1DU // Transmit channel enable partition G +#define MCBSP_O_XCERH 0x1EU // Transmit channel enable partition H +#define MCBSP_O_MFFINT 0x23U // Interrupt enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR2 register +// +//************************************************************************************************* +#define MCBSP_DRR2_HWLB_S 0U +#define MCBSP_DRR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DRR2_HWHB_S 8U +#define MCBSP_DRR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DRR1 register +// +//************************************************************************************************* +#define MCBSP_DRR1_LWLB_S 0U +#define MCBSP_DRR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DRR1_LWHB_S 8U +#define MCBSP_DRR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR2 register +// +//************************************************************************************************* +#define MCBSP_DXR2_HWLB_S 0U +#define MCBSP_DXR2_HWLB_M 0xFFU // High word low byte +#define MCBSP_DXR2_HWHB_S 8U +#define MCBSP_DXR2_HWHB_M 0xFF00U // High word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DXR1 register +// +//************************************************************************************************* +#define MCBSP_DXR1_LWLB_S 0U +#define MCBSP_DXR1_LWLB_M 0xFFU // Low word low byte +#define MCBSP_DXR1_LWHB_S 8U +#define MCBSP_DXR1_LWHB_M 0xFF00U // Low word high byte + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR2 register +// +//************************************************************************************************* +#define MCBSP_SPCR2_XRST 0x1U // Transmitter reset +#define MCBSP_SPCR2_XRDY 0x2U // Transmitter ready +#define MCBSP_SPCR2_XEMPTY 0x4U // Transmitter empty +#define MCBSP_SPCR2_XSYNCERR 0x8U // Transmit sync error INT flag +#define MCBSP_SPCR2_XINTM_S 4U +#define MCBSP_SPCR2_XINTM_M 0x30U // Transmit Interupt mode bits +#define MCBSP_SPCR2_GRST 0x40U // Sample rate generator reset +#define MCBSP_SPCR2_FRST 0x80U // Frame sync logic reset +#define MCBSP_SPCR2_SOFT 0x100U // SOFT bit +#define MCBSP_SPCR2_FREE 0x200U // FREE bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPCR1 register +// +//************************************************************************************************* +#define MCBSP_SPCR1_RRST 0x1U // Receiver reset +#define MCBSP_SPCR1_RRDY 0x2U // Receiver ready +#define MCBSP_SPCR1_RFULL 0x4U // Receiver full +#define MCBSP_SPCR1_RSYNCERR 0x8U // Receive sync error INT flag +#define MCBSP_SPCR1_RINTM_S 4U +#define MCBSP_SPCR1_RINTM_M 0x30U // Receive Interupt mode bits +#define MCBSP_SPCR1_DXENA 0x80U // DX delay enable +#define MCBSP_SPCR1_CLKSTP_S 11U +#define MCBSP_SPCR1_CLKSTP_M 0x1800U // Clock stop mode +#define MCBSP_SPCR1_RJUST_S 13U +#define MCBSP_SPCR1_RJUST_M 0x6000U // Rx sign extension and justification mode +#define MCBSP_SPCR1_DLB 0x8000U // Digital loopback + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR2 register +// +//************************************************************************************************* +#define MCBSP_RCR2_RDATDLY_S 0U +#define MCBSP_RCR2_RDATDLY_M 0x3U // Receive data delay +#define MCBSP_RCR2_RFIG 0x4U // Receive frame sync ignore +#define MCBSP_RCR2_RCOMPAND_S 3U +#define MCBSP_RCR2_RCOMPAND_M 0x18U // Receive Companding Mode selects +#define MCBSP_RCR2_RWDLEN2_S 5U +#define MCBSP_RCR2_RWDLEN2_M 0xE0U // Receive word length 2 +#define MCBSP_RCR2_RFRLEN2_S 8U +#define MCBSP_RCR2_RFRLEN2_M 0x7F00U // Receive Frame length 2 +#define MCBSP_RCR2_RPHASE 0x8000U // Receive Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RCR1 register +// +//************************************************************************************************* +#define MCBSP_RCR1_RWDLEN1_S 5U +#define MCBSP_RCR1_RWDLEN1_M 0xE0U // Receive word length 1 +#define MCBSP_RCR1_RFRLEN1_S 8U +#define MCBSP_RCR1_RFRLEN1_M 0x7F00U // Receive Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR2 register +// +//************************************************************************************************* +#define MCBSP_XCR2_XDATDLY_S 0U +#define MCBSP_XCR2_XDATDLY_M 0x3U // Transmit data delay +#define MCBSP_XCR2_XFIG 0x4U // Transmit frame sync ignore +#define MCBSP_XCR2_XCOMPAND_S 3U +#define MCBSP_XCR2_XCOMPAND_M 0x18U // Transmit Companding Mode selects +#define MCBSP_XCR2_XWDLEN2_S 5U +#define MCBSP_XCR2_XWDLEN2_M 0xE0U // Transmit word length 2 +#define MCBSP_XCR2_XFRLEN2_S 8U +#define MCBSP_XCR2_XFRLEN2_M 0x7F00U // Transmit Frame length 2 +#define MCBSP_XCR2_XPHASE 0x8000U // Transmit Phase + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCR1 register +// +//************************************************************************************************* +#define MCBSP_XCR1_XWDLEN1_S 5U +#define MCBSP_XCR1_XWDLEN1_M 0xE0U // Transmit word length 1 +#define MCBSP_XCR1_XFRLEN1_S 8U +#define MCBSP_XCR1_XFRLEN1_M 0x7F00U // Transmit Frame length 1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR2 register +// +//************************************************************************************************* +#define MCBSP_SRGR2_FPER_S 0U +#define MCBSP_SRGR2_FPER_M 0xFFFU // Frame-sync period +#define MCBSP_SRGR2_FSGM 0x1000U // Frame sync generator mode +#define MCBSP_SRGR2_CLKSM 0x2000U // Sample rate generator mode +#define MCBSP_SRGR2_GSYNC 0x8000U // CLKG sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SRGR1 register +// +//************************************************************************************************* +#define MCBSP_SRGR1_CLKGDV_S 0U +#define MCBSP_SRGR1_CLKGDV_M 0xFFU // CLKG divider +#define MCBSP_SRGR1_FWID_S 8U +#define MCBSP_SRGR1_FWID_M 0xFF00U // Frame width + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR2 register +// +//************************************************************************************************* +#define MCBSP_MCR2_XMCM_S 0U +#define MCBSP_MCR2_XMCM_M 0x3U // Transmit data delay +#define MCBSP_MCR2_XCBLK_S 2U +#define MCBSP_MCR2_XCBLK_M 0x1CU // Transmit frame sync ignore +#define MCBSP_MCR2_XPABLK_S 5U +#define MCBSP_MCR2_XPABLK_M 0x60U // Transmit Companding Mode selects +#define MCBSP_MCR2_XPBBLK_S 7U +#define MCBSP_MCR2_XPBBLK_M 0x180U // Transmit word length 2 +#define MCBSP_MCR2_XMCME 0x200U // Transmit Frame length 2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCR1 register +// +//************************************************************************************************* +#define MCBSP_MCR1_RMCM 0x1U // Receive multichannel mode +#define MCBSP_MCR1_RCBLK_S 2U +#define MCBSP_MCR1_RCBLK_M 0x1CU // eceive current block +#define MCBSP_MCR1_RPABLK_S 5U +#define MCBSP_MCR1_RPABLK_M 0x60U // Receive partition A Block +#define MCBSP_MCR1_RPBBLK_S 7U +#define MCBSP_MCR1_RPBBLK_M 0x180U // Receive partition B Block +#define MCBSP_MCR1_RMCME 0x200U // Receive multi-channel enhance mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCR register +// +//************************************************************************************************* +#define MCBSP_PCR_CLKRP 0x1U // Receive Clock polarity +#define MCBSP_PCR_CLKXP 0x2U // Transmit clock polarity +#define MCBSP_PCR_FSRP 0x4U // Receive Frame synchronization polarity +#define MCBSP_PCR_FSXP 0x8U // Transmit Frame synchronization polarity +#define MCBSP_PCR_SCLKME 0x80U // Sample clock mode selection +#define MCBSP_PCR_CLKRM 0x100U // Receiver Clock Mode +#define MCBSP_PCR_CLKXM 0x200U // Transmit Clock Mode. +#define MCBSP_PCR_FSRM 0x400U // Receive Frame Synchronization Mode +#define MCBSP_PCR_FSXM 0x800U // Transmit Frame Synchronization Mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MFFINT register +// +//************************************************************************************************* +#define MCBSP_MFFINT_XINT 0x1U // Enable for Receive Interrupt +#define MCBSP_MFFINT_RINT 0x4U // Enable for transmit Interrupt + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_memcfg.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_memcfg.h new file mode 100644 index 0000000..d5d7e8c --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_memcfg.h @@ -0,0 +1,870 @@ +//########################################################################### +// +// FILE: hw_memcfg.h +// +// TITLE: Definitions for the MEMCFG registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMCFG_H +#define HW_MEMCFG_H + +//************************************************************************************************* +// +// The following are defines for the MEMCFG register offsets +// +//************************************************************************************************* +#define MEMCFG_O_DXLOCK 0x0U // Dedicated RAM Config Lock Register +#define MEMCFG_O_DXCOMMIT 0x2U // Dedicated RAM Config Lock Commit Register +#define MEMCFG_O_DXACCPROT0 0x8U // Dedicated RAM Config Register +#define MEMCFG_O_DXTEST 0x10U // Dedicated RAM TEST Register +#define MEMCFG_O_DXINIT 0x12U // Dedicated RAM Init Register +#define MEMCFG_O_DXINITDONE 0x14U // Dedicated RAM InitDone Status Register +#define MEMCFG_O_LSXLOCK 0x20U // Local Shared RAM Config Lock Register +#define MEMCFG_O_LSXCOMMIT 0x22U // Local Shared RAM Config Lock Commit Register +#define MEMCFG_O_LSXMSEL 0x24U // Local Shared RAM Master Sel Register +#define MEMCFG_O_LSXCLAPGM 0x26U // Local Shared RAM Prog/Exe control Register +#define MEMCFG_O_LSXACCPROT0 0x28U // Local Shared RAM Config Register 0 +#define MEMCFG_O_LSXACCPROT1 0x2AU // Local Shared RAM Config Register 1 +#define MEMCFG_O_LSXTEST 0x30U // Local Shared RAM TEST Register +#define MEMCFG_O_LSXINIT 0x32U // Local Shared RAM Init Register +#define MEMCFG_O_LSXINITDONE 0x34U // Local Shared RAM InitDone Status Register +#define MEMCFG_O_GSXLOCK 0x40U // Global Shared RAM Config Lock Register +#define MEMCFG_O_GSXCOMMIT 0x42U // Global Shared RAM Config Lock Commit Register +#define MEMCFG_O_GSXMSEL 0x44U // Global Shared RAM Master Sel Register +#define MEMCFG_O_GSXACCPROT0 0x48U // Global Shared RAM Config Register 0 +#define MEMCFG_O_GSXACCPROT1 0x4AU // Global Shared RAM Config Register 1 +#define MEMCFG_O_GSXACCPROT2 0x4CU // Global Shared RAM Config Register 2 +#define MEMCFG_O_GSXACCPROT3 0x4EU // Global Shared RAM Config Register 3 +#define MEMCFG_O_GSXTEST 0x50U // Global Shared RAM TEST Register +#define MEMCFG_O_GSXINIT 0x52U // Global Shared RAM Init Register +#define MEMCFG_O_GSXINITDONE 0x54U // Global Shared RAM InitDone Status Register +#define MEMCFG_O_MSGXTEST 0x70U // Message RAM TEST Register +#define MEMCFG_O_MSGXINIT 0x72U // Message RAM Init Register +#define MEMCFG_O_MSGXINITDONE 0x74U // Message RAM InitDone Status Register + +#define MEMCFG_O_EMIF1LOCK 0x0U // EMIF1 Config Lock Register +#define MEMCFG_O_EMIF1COMMIT 0x2U // EMIF1 Config Lock Commit Register +#define MEMCFG_O_EMIF1MSEL 0x4U // EMIF1 Master Sel Register +#define MEMCFG_O_EMIF1ACCPROT0 0x8U // EMIF1 Config Register 0 + +#define MEMCFG_O_EMIF2LOCK 0x0U // EMIF2 Config Lock Register +#define MEMCFG_O_EMIF2COMMIT 0x2U // EMIF2 Config Lock Commit Register +#define MEMCFG_O_EMIF2ACCPROT0 0x8U // EMIF2 Config Register 0 + +#define MEMCFG_O_NMAVFLG 0x0U // Non-Master Access Violation Flag Register +#define MEMCFG_O_NMAVSET 0x2U // Non-Master Access Violation Flag Set Register +#define MEMCFG_O_NMAVCLR 0x4U // Non-Master Access Violation Flag Clear Register +#define MEMCFG_O_NMAVINTEN 0x6U // Non-Master Access Violation Interrupt Enable Register +#define MEMCFG_O_NMCPURDAVADDR 0x8U // Non-Master CPU Read Access Violation Address +#define MEMCFG_O_NMCPUWRAVADDR 0xAU // Non-Master CPU Write Access Violation Address +#define MEMCFG_O_NMCPUFAVADDR 0xCU // Non-Master CPU Fetch Access Violation Address +#define MEMCFG_O_NMDMAWRAVADDR 0xEU // Non-Master DMA Write Access Violation Address +#define MEMCFG_O_NMCLA1RDAVADDR 0x10U // Non-Master CLA1 Read Access Violation Address +#define MEMCFG_O_NMCLA1WRAVADDR 0x12U // Non-Master CLA1 Write Access Violation Address +#define MEMCFG_O_NMCLA1FAVADDR 0x14U // Non-Master CLA1 Fetch Access Violation Address +#define MEMCFG_O_MAVFLG 0x20U // Master Access Violation Flag Register +#define MEMCFG_O_MAVSET 0x22U // Master Access Violation Flag Set Register +#define MEMCFG_O_MAVCLR 0x24U // Master Access Violation Flag Clear Register +#define MEMCFG_O_MAVINTEN 0x26U // Master Access Violation Interrupt Enable Register +#define MEMCFG_O_MCPUFAVADDR 0x28U // Master CPU Fetch Access Violation Address +#define MEMCFG_O_MCPUWRAVADDR 0x2AU // Master CPU Write Access Violation Address +#define MEMCFG_O_MDMAWRAVADDR 0x2CU // Master DMA Write Access Violation Address + +#define MEMCFG_O_UCERRFLG 0x0U // Uncorrectable Error Flag Register +#define MEMCFG_O_UCERRSET 0x2U // Uncorrectable Error Flag Set Register +#define MEMCFG_O_UCERRCLR 0x4U // Uncorrectable Error Flag Clear Register +#define MEMCFG_O_UCCPUREADDR 0x6U // Uncorrectable CPU Read Error Address +#define MEMCFG_O_UCDMAREADDR 0x8U // Uncorrectable DMA Read Error Address +#define MEMCFG_O_UCCLA1READDR 0xAU // Uncorrectable CLA1 Read Error Address +#define MEMCFG_O_CERRFLG 0x20U // Correctable Error Flag Register +#define MEMCFG_O_CERRSET 0x22U // Correctable Error Flag Set Register +#define MEMCFG_O_CERRCLR 0x24U // Correctable Error Flag Clear Register +#define MEMCFG_O_CCPUREADDR 0x26U // Correctable CPU Read Error Address +#define MEMCFG_O_CERRCNT 0x2EU // Correctable Error Count Register +#define MEMCFG_O_CERRTHRES 0x30U // Correctable Error Threshold Value Register +#define MEMCFG_O_CEINTFLG 0x32U // Correctable Error Interrupt Flag Status Register +#define MEMCFG_O_CEINTCLR 0x34U // Correctable Error Interrupt Flag Clear Register +#define MEMCFG_O_CEINTSET 0x36U // Correctable Error Interrupt Flag Set Register +#define MEMCFG_O_CEINTEN 0x38U // Correctable Error Interrupt Enable Register + +#define MEMCFG_O_ROMWAITSTATE 0x0U // ROM Wait State Configuration Register + +#define MEMCFG_O_ROMPREFETCH 0x0U // ROM Prefetch Configuration Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxLOCK register +// +//************************************************************************************************* +#define MEMCFG_DXLOCK_LOCK_D0 0x4U // D0 RAM access protection and master select fields lock + // bit +#define MEMCFG_DXLOCK_LOCK_D1 0x8U // D1 RAM access protection and master select fields lock + // bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_DXCOMMIT_COMMIT_D0 0x4U // D0 RAM access protection and master select permanent + // lock +#define MEMCFG_DXCOMMIT_COMMIT_D1 0x8U // D1 RAM access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_DXACCPROT0_FETCHPROT_D0 0x10000U // Fetch Protection For D0 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D0 0x20000U // CPU WR Protection For D0 RAM +#define MEMCFG_DXACCPROT0_FETCHPROT_D1 0x1000000U // Fetch Protection For D1 RAM +#define MEMCFG_DXACCPROT0_CPUWRPROT_D1 0x2000000U // CPU WR Protection For D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxTEST register +// +//************************************************************************************************* +#define MEMCFG_DXTEST_TEST_M0_S 0U +#define MEMCFG_DXTEST_TEST_M0_M 0x3U // Selects the different modes for M0 RAM +#define MEMCFG_DXTEST_TEST_M1_S 2U +#define MEMCFG_DXTEST_TEST_M1_M 0xCU // Selects the different modes for M1 RAM +#define MEMCFG_DXTEST_TEST_D0_S 4U +#define MEMCFG_DXTEST_TEST_D0_M 0x30U // Selects the different modes for D0 RAM +#define MEMCFG_DXTEST_TEST_D1_S 6U +#define MEMCFG_DXTEST_TEST_D1_M 0xC0U // Selects the different modes for D1 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINIT register +// +//************************************************************************************************* +#define MEMCFG_DXINIT_INIT_M0 0x1U // RAM Initialization control for M0 RAM. +#define MEMCFG_DXINIT_INIT_M1 0x2U // RAM Initialization control for M1 RAM. +#define MEMCFG_DXINIT_INIT_D0 0x4U // RAM Initialization control for D0 RAM. +#define MEMCFG_DXINIT_INIT_D1 0x8U // RAM Initialization control for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_DXINITDONE_INITDONE_M0 0x1U // RAM Initialization status for M0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_M1 0x2U // RAM Initialization status for M1 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D0 0x4U // RAM Initialization status for D0 RAM. +#define MEMCFG_DXINITDONE_INITDONE_D1 0x8U // RAM Initialization status for D1 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_LSXLOCK_LOCK_LS0 0x1U // LS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS1 0x2U // LS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS2 0x4U // LS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS3 0x8U // LS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS4 0x10U // LS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_LSXLOCK_LOCK_LS5 0x20U // LS5 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_LSXCOMMIT_COMMIT_LS0 0x1U // LS0 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS1 0x2U // LS1 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS2 0x4U // LS2 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS3 0x8U // LS3 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS4 0x10U // LS4 RAM access protection and master select + // permanent lock +#define MEMCFG_LSXCOMMIT_COMMIT_LS5 0x20U // LS5 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_LSXMSEL_MSEL_LS0_S 0U +#define MEMCFG_LSXMSEL_MSEL_LS0_M 0x3U // Master Select for LS0 RAM +#define MEMCFG_LSXMSEL_MSEL_LS1_S 2U +#define MEMCFG_LSXMSEL_MSEL_LS1_M 0xCU // Master Select for LS1 RAM +#define MEMCFG_LSXMSEL_MSEL_LS2_S 4U +#define MEMCFG_LSXMSEL_MSEL_LS2_M 0x30U // Master Select for LS2 RAM +#define MEMCFG_LSXMSEL_MSEL_LS3_S 6U +#define MEMCFG_LSXMSEL_MSEL_LS3_M 0xC0U // Master Select for LS3 RAM +#define MEMCFG_LSXMSEL_MSEL_LS4_S 8U +#define MEMCFG_LSXMSEL_MSEL_LS4_M 0x300U // Master Select for LS4 RAM +#define MEMCFG_LSXMSEL_MSEL_LS5_S 10U +#define MEMCFG_LSXMSEL_MSEL_LS5_M 0xC00U // Master Select for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxCLAPGM register +// +//************************************************************************************************* +#define MEMCFG_LSXCLAPGM_CLAPGM_LS0 0x1U // Selects LS0 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS1 0x2U // Selects LS1 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS2 0x4U // Selects LS2 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS3 0x8U // Selects LS3 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS4 0x10U // Selects LS4 RAM as program vs data memory for CLA +#define MEMCFG_LSXCLAPGM_CLAPGM_LS5 0x20U // Selects LS5 RAM as program vs data memory for CLA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS0 0x1U // Fetch Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS0 0x2U // CPU WR Protection For LS0 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS1 0x100U // Fetch Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS1 0x200U // CPU WR Protection For LS1 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS2 0x10000U // Fetch Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS2 0x20000U // CPU WR Protection For LS2 RAM +#define MEMCFG_LSXACCPROT0_FETCHPROT_LS3 0x1000000U // Fetch Protection For LS3 RAM +#define MEMCFG_LSXACCPROT0_CPUWRPROT_LS3 0x2000000U // CPU WR Protection For LS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS4 0x1U // Fetch Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS4 0x2U // CPU WR Protection For LS4 RAM +#define MEMCFG_LSXACCPROT1_FETCHPROT_LS5 0x100U // Fetch Protection For LS5 RAM +#define MEMCFG_LSXACCPROT1_CPUWRPROT_LS5 0x200U // CPU WR Protection For LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxTEST register +// +//************************************************************************************************* +#define MEMCFG_LSXTEST_TEST_LS0_S 0U +#define MEMCFG_LSXTEST_TEST_LS0_M 0x3U // Selects the different modes for LS0 RAM +#define MEMCFG_LSXTEST_TEST_LS1_S 2U +#define MEMCFG_LSXTEST_TEST_LS1_M 0xCU // Selects the different modes for LS1 RAM +#define MEMCFG_LSXTEST_TEST_LS2_S 4U +#define MEMCFG_LSXTEST_TEST_LS2_M 0x30U // Selects the different modes for LS2 RAM +#define MEMCFG_LSXTEST_TEST_LS3_S 6U +#define MEMCFG_LSXTEST_TEST_LS3_M 0xC0U // Selects the different modes for LS3 RAM +#define MEMCFG_LSXTEST_TEST_LS4_S 8U +#define MEMCFG_LSXTEST_TEST_LS4_M 0x300U // Selects the different modes for LS4 RAM +#define MEMCFG_LSXTEST_TEST_LS5_S 10U +#define MEMCFG_LSXTEST_TEST_LS5_M 0xC00U // Selects the different modes for LS5 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINIT register +// +//************************************************************************************************* +#define MEMCFG_LSXINIT_INIT_LS0 0x1U // RAM Initialization control for LS0 RAM. +#define MEMCFG_LSXINIT_INIT_LS1 0x2U // RAM Initialization control for LS1 RAM. +#define MEMCFG_LSXINIT_INIT_LS2 0x4U // RAM Initialization control for LS2 RAM. +#define MEMCFG_LSXINIT_INIT_LS3 0x8U // RAM Initialization control for LS3 RAM. +#define MEMCFG_LSXINIT_INIT_LS4 0x10U // RAM Initialization control for LS4 RAM. +#define MEMCFG_LSXINIT_INIT_LS5 0x20U // RAM Initialization control for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_LSXINITDONE_INITDONE_LS0 0x1U // RAM Initialization status for LS0 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS1 0x2U // RAM Initialization status for LS1 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS2 0x4U // RAM Initialization status for LS2 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS3 0x8U // RAM Initialization status for LS3 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS4 0x10U // RAM Initialization status for LS4 RAM. +#define MEMCFG_LSXINITDONE_INITDONE_LS5 0x20U // RAM Initialization status for LS5 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxLOCK register +// +//************************************************************************************************* +#define MEMCFG_GSXLOCK_LOCK_GS0 0x1U // GS0 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS1 0x2U // GS1 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS2 0x4U // GS2 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS3 0x8U // GS3 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS4 0x10U // GS4 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS5 0x20U // GS5 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS6 0x40U // GS6 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS7 0x80U // GS7 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS8 0x100U // GS8 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS9 0x200U // GS9 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS10 0x400U // GS10 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS11 0x800U // GS11 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS12 0x1000U // GS12 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS13 0x2000U // GS13 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS14 0x4000U // GS14 RAM access protection and master select fields + // lock bit +#define MEMCFG_GSXLOCK_LOCK_GS15 0x8000U // GS15 RAM access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxCOMMIT register +// +//************************************************************************************************* +#define MEMCFG_GSXCOMMIT_COMMIT_GS0 0x1U // GS0 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS1 0x2U // GS1 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS2 0x4U // GS2 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS3 0x8U // GS3 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS4 0x10U // GS4 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS5 0x20U // GS5 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS6 0x40U // GS6 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS7 0x80U // GS7 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS8 0x100U // GS8 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS9 0x200U // GS9 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS10 0x400U // GS10 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS11 0x800U // GS11 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS12 0x1000U // GS12 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS13 0x2000U // GS13 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS14 0x4000U // GS14 RAM access protection and master select + // permanent lock +#define MEMCFG_GSXCOMMIT_COMMIT_GS15 0x8000U // GS15 RAM access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxMSEL register +// +//************************************************************************************************* +#define MEMCFG_GSXMSEL_MSEL_GS0 0x1U // Master Select for GS0 RAM +#define MEMCFG_GSXMSEL_MSEL_GS1 0x2U // Master Select for GS1 RAM +#define MEMCFG_GSXMSEL_MSEL_GS2 0x4U // Master Select for GS2 RAM +#define MEMCFG_GSXMSEL_MSEL_GS3 0x8U // Master Select for GS3 RAM +#define MEMCFG_GSXMSEL_MSEL_GS4 0x10U // Master Select for GS4 RAM +#define MEMCFG_GSXMSEL_MSEL_GS5 0x20U // Master Select for GS5 RAM +#define MEMCFG_GSXMSEL_MSEL_GS6 0x40U // Master Select for GS6 RAM +#define MEMCFG_GSXMSEL_MSEL_GS7 0x80U // Master Select for GS7 RAM +#define MEMCFG_GSXMSEL_MSEL_GS8 0x100U // Master Select for GS8 RAM +#define MEMCFG_GSXMSEL_MSEL_GS9 0x200U // Master Select for GS9 RAM +#define MEMCFG_GSXMSEL_MSEL_GS10 0x400U // Master Select for GS10 RAM +#define MEMCFG_GSXMSEL_MSEL_GS11 0x800U // Master Select for GS11 RAM +#define MEMCFG_GSXMSEL_MSEL_GS12 0x1000U // Master Select for GS12 RAM +#define MEMCFG_GSXMSEL_MSEL_GS13 0x2000U // Master Select for GS13 RAM +#define MEMCFG_GSXMSEL_MSEL_GS14 0x4000U // Master Select for GS14 RAM +#define MEMCFG_GSXMSEL_MSEL_GS15 0x8000U // Master Select for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS0 0x1U // Fetch Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 0x2U // CPU WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS0 0x4U // DMA WR Protection For GS0 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS1 0x100U // Fetch Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS1 0x200U // CPU WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS1 0x400U // DMA WR Protection For GS1 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS2 0x10000U // Fetch Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS2 0x20000U // CPU WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS2 0x40000U // DMA WR Protection For GS2 RAM +#define MEMCFG_GSXACCPROT0_FETCHPROT_GS3 0x1000000U // Fetch Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_CPUWRPROT_GS3 0x2000000U // CPU WR Protection For GS3 RAM +#define MEMCFG_GSXACCPROT0_DMAWRPROT_GS3 0x4000000U // DMA WR Protection For GS3 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT1 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS4 0x1U // Fetch Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS4 0x2U // CPU WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS4 0x4U // DMA WR Protection For GS4 RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS5 0x100U // Fetch Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS5 0x200U // CPU WR Protection For GS5 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS5 0x400U // DMA WR Protection For GS5RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS6 0x10000U // Fetch Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS6 0x20000U // CPU WR Protection For GS6 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS6 0x40000U // DMA WR Protection For GS6RAM +#define MEMCFG_GSXACCPROT1_FETCHPROT_GS7 0x1000000U // Fetch Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_CPUWRPROT_GS7 0x2000000U // CPU WR Protection For GS7 RAM +#define MEMCFG_GSXACCPROT1_DMAWRPROT_GS7 0x4000000U // DMA WR Protection For GS7RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT2 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS8 0x1U // Fetch Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS8 0x2U // CPU WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS8 0x4U // DMA WR Protection For GS8 RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS9 0x100U // Fetch Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS9 0x200U // CPU WR Protection For GS9 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS9 0x400U // DMA WR Protection For GS9RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS10 0x10000U // Fetch Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS10 0x20000U // CPU WR Protection For GS10 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS10 0x40000U // DMA WR Protection For GS10RAM +#define MEMCFG_GSXACCPROT2_FETCHPROT_GS11 0x1000000U // Fetch Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_CPUWRPROT_GS11 0x2000000U // CPU WR Protection For GS11 RAM +#define MEMCFG_GSXACCPROT2_DMAWRPROT_GS11 0x4000000U // DMA WR Protection For GS11RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxACCPROT3 register +// +//************************************************************************************************* +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS12 0x1U // Fetch Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS12 0x2U // CPU WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS12 0x4U // DMA WR Protection For GS12 RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS13 0x100U // Fetch Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS13 0x200U // CPU WR Protection For GS13 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS13 0x400U // DMA WR Protection For GS13RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS14 0x10000U // Fetch Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS14 0x20000U // CPU WR Protection For GS14 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS14 0x40000U // DMA WR Protection For GS14RAM +#define MEMCFG_GSXACCPROT3_FETCHPROT_GS15 0x1000000U // Fetch Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_CPUWRPROT_GS15 0x2000000U // CPU WR Protection For GS15 RAM +#define MEMCFG_GSXACCPROT3_DMAWRPROT_GS15 0x4000000U // DMA WR Protection For GS15RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxTEST register +// +//************************************************************************************************* +#define MEMCFG_GSXTEST_TEST_GS0_S 0U +#define MEMCFG_GSXTEST_TEST_GS0_M 0x3U // Selects the different modes for GS0 RAM +#define MEMCFG_GSXTEST_TEST_GS1_S 2U +#define MEMCFG_GSXTEST_TEST_GS1_M 0xCU // Selects the different modes for GS1 RAM +#define MEMCFG_GSXTEST_TEST_GS2_S 4U +#define MEMCFG_GSXTEST_TEST_GS2_M 0x30U // Selects the different modes for GS2 RAM +#define MEMCFG_GSXTEST_TEST_GS3_S 6U +#define MEMCFG_GSXTEST_TEST_GS3_M 0xC0U // Selects the different modes for GS3 RAM +#define MEMCFG_GSXTEST_TEST_GS4_S 8U +#define MEMCFG_GSXTEST_TEST_GS4_M 0x300U // Selects the different modes for GS4 RAM +#define MEMCFG_GSXTEST_TEST_GS5_S 10U +#define MEMCFG_GSXTEST_TEST_GS5_M 0xC00U // Selects the different modes for GS5 RAM +#define MEMCFG_GSXTEST_TEST_GS6_S 12U +#define MEMCFG_GSXTEST_TEST_GS6_M 0x3000U // Selects the different modes for GS6 RAM +#define MEMCFG_GSXTEST_TEST_GS7_S 14U +#define MEMCFG_GSXTEST_TEST_GS7_M 0xC000U // Selects the different modes for GS7 RAM +#define MEMCFG_GSXTEST_TEST_GS8_S 16U +#define MEMCFG_GSXTEST_TEST_GS8_M 0x30000U // Selects the different modes for GS8 RAM +#define MEMCFG_GSXTEST_TEST_GS9_S 18U +#define MEMCFG_GSXTEST_TEST_GS9_M 0xC0000U // Selects the different modes for GS9 RAM +#define MEMCFG_GSXTEST_TEST_GS10_S 20U +#define MEMCFG_GSXTEST_TEST_GS10_M 0x300000U // Selects the different modes for GS10 RAM +#define MEMCFG_GSXTEST_TEST_GS11_S 22U +#define MEMCFG_GSXTEST_TEST_GS11_M 0xC00000U // Selects the different modes for GS11 RAM +#define MEMCFG_GSXTEST_TEST_GS12_S 24U +#define MEMCFG_GSXTEST_TEST_GS12_M 0x3000000U // Selects the different modes for GS12 RAM +#define MEMCFG_GSXTEST_TEST_GS13_S 26U +#define MEMCFG_GSXTEST_TEST_GS13_M 0xC000000U // Selects the different modes for GS13 RAM +#define MEMCFG_GSXTEST_TEST_GS14_S 28U +#define MEMCFG_GSXTEST_TEST_GS14_M 0x30000000U // Selects the different modes for GS14 RAM +#define MEMCFG_GSXTEST_TEST_GS15_S 30U +#define MEMCFG_GSXTEST_TEST_GS15_M 0xC0000000U // Selects the different modes for GS15 RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINIT register +// +//************************************************************************************************* +#define MEMCFG_GSXINIT_INIT_GS0 0x1U // RAM Initialization control for GS0 RAM. +#define MEMCFG_GSXINIT_INIT_GS1 0x2U // RAM Initialization control for GS1 RAM. +#define MEMCFG_GSXINIT_INIT_GS2 0x4U // RAM Initialization control for GS2 RAM. +#define MEMCFG_GSXINIT_INIT_GS3 0x8U // RAM Initialization control for GS3 RAM. +#define MEMCFG_GSXINIT_INIT_GS4 0x10U // RAM Initialization control for GS4 RAM. +#define MEMCFG_GSXINIT_INIT_GS5 0x20U // RAM Initialization control for GS5 RAM. +#define MEMCFG_GSXINIT_INIT_GS6 0x40U // RAM Initialization control for GS6 RAM. +#define MEMCFG_GSXINIT_INIT_GS7 0x80U // RAM Initialization control for GS7 RAM. +#define MEMCFG_GSXINIT_INIT_GS8 0x100U // RAM Initialization control for GS8 RAM. +#define MEMCFG_GSXINIT_INIT_GS9 0x200U // RAM Initialization control for GS9 RAM. +#define MEMCFG_GSXINIT_INIT_GS10 0x400U // RAM Initialization control for GS10 RAM. +#define MEMCFG_GSXINIT_INIT_GS11 0x800U // RAM Initialization control for GS11 RAM. +#define MEMCFG_GSXINIT_INIT_GS12 0x1000U // RAM Initialization control for GS12 RAM. +#define MEMCFG_GSXINIT_INIT_GS13 0x2000U // RAM Initialization control for GS13 RAM. +#define MEMCFG_GSXINIT_INIT_GS14 0x4000U // RAM Initialization control for GS14 RAM. +#define MEMCFG_GSXINIT_INIT_GS15 0x8000U // RAM Initialization control for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GSxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_GSXINITDONE_INITDONE_GS0 0x1U // RAM Initialization status for GS0 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS1 0x2U // RAM Initialization status for GS1 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS2 0x4U // RAM Initialization status for GS2 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS3 0x8U // RAM Initialization status for GS3 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS4 0x10U // RAM Initialization status for GS4 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS5 0x20U // RAM Initialization status for GS5 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS6 0x40U // RAM Initialization status for GS6 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS7 0x80U // RAM Initialization status for GS7 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS8 0x100U // RAM Initialization status for GS8 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS9 0x200U // RAM Initialization status for GS9 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS10 0x400U // RAM Initialization status for GS10 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS11 0x800U // RAM Initialization status for GS11 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS12 0x1000U // RAM Initialization status for GS12 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS13 0x2000U // RAM Initialization status for GS13 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS14 0x4000U // RAM Initialization status for GS14 RAM. +#define MEMCFG_GSXINITDONE_INITDONE_GS15 0x8000U // RAM Initialization status for GS15 RAM. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxTEST register +// +//************************************************************************************************* +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_S 0U +#define MEMCFG_MSGXTEST_TEST_CPUTOCPU_M 0x3U // CPU to CPU Mode Select +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_S 2U +#define MEMCFG_MSGXTEST_TEST_CPUTOCLA1_M 0xCU // CPU to CLA1 MSG RAM Mode Select +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_S 4U +#define MEMCFG_MSGXTEST_TEST_CLA1TOCPU_M 0x30U // CLA1 to CPU MSG RAM Mode Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINIT register +// +//************************************************************************************************* +#define MEMCFG_MSGXINIT_INIT_CPUTOCPU 0x1U // Initialization control for CPU to CPU MSG RAM +#define MEMCFG_MSGXINIT_INIT_CPUTOCLA1 0x2U // Initialization control for CPUTOCLA1 MSG RAM +#define MEMCFG_MSGXINIT_INIT_CLA1TOCPU 0x4U // Initialization control for CLA1TOCPU MSG RAM + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MSGxINITDONE register +// +//************************************************************************************************* +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCPU 0x1U // Initialization status for CPU to CPU MSG + // RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CPUTOCLA1 0x2U // Initialization status for CPU to CLA1 + // MSG RAM +#define MEMCFG_MSGXINITDONE_INITDONE_CLA1TOCPU 0x4U // Initialization status for CLA1 to CPU + // MSG RAM + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF1LOCK_LOCK_EMIF1 0x1U // EMIF1 access protection and master select fields + // lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF1COMMIT_COMMIT_EMIF1 0x1U // EMIF1 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1MSEL register +// +//************************************************************************************************* +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_S 0U +#define MEMCFG_EMIF1MSEL_MSEL_EMIF1_M 0x3U // Master Select for EMIF1. +#define MEMCFG_EMIF1MSEL_KEY_S 4U +#define MEMCFG_EMIF1MSEL_KEY_M 0xFFFFFFF0U // KEY to enable the write into MSEL_EMIF1 + // bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF1ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF1ACCPROT0_FETCHPROT_EMIF1 0x1U // Fetch Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_CPUWRPROT_EMIF1 0x2U // CPU WR Protection For EMIF1 +#define MEMCFG_EMIF1ACCPROT0_DMAWRPROT_EMIF1 0x4U // DMA WR Protection For EMIF1 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2LOCK register +// +//************************************************************************************************* +#define MEMCFG_EMIF2LOCK_LOCK_EMIF2 0x1U // EMIF2 access protection and master select permanent + // lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2COMMIT register +// +//************************************************************************************************* +#define MEMCFG_EMIF2COMMIT_COMMIT_EMIF2 0x1U // EMIF2 access protection and master select + // permanent lock + +//************************************************************************************************* +// +// The following are defines for the bit fields in the EMIF2ACCPROT0 register +// +//************************************************************************************************* +#define MEMCFG_EMIF2ACCPROT0_FETCHPROT_EMIF2 0x1U // Fetch Protection For EMIF2 +#define MEMCFG_EMIF2ACCPROT0_CPUWRPROT_EMIF2 0x2U // CPU WR Protection For EMIF2 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVFLG register +// +//************************************************************************************************* +#define MEMCFG_NMAVFLG_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag +#define MEMCFG_NMAVFLG_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag +#define MEMCFG_NMAVFLG_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag +#define MEMCFG_NMAVFLG_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag +#define MEMCFG_NMAVFLG_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVSET register +// +//************************************************************************************************* +#define MEMCFG_NMAVSET_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Set +#define MEMCFG_NMAVSET_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Set +#define MEMCFG_NMAVSET_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVCLR register +// +//************************************************************************************************* +#define MEMCFG_NMAVCLR_CPUREAD 0x1U // Non Master CPU Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUWRITE 0x2U // Non Master CPU Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_NMAVCLR_DMAWRITE 0x8U // Non Master DMA Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Flag Clear +#define MEMCFG_NMAVCLR_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_NMAVINTEN_CPUREAD 0x1U // Non Master CPU Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUWRITE 0x2U // Non Master CPU Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CPUFETCH 0x4U // Non Master CPU Fetch Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_DMAWRITE 0x8U // Non Master DMA Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1READ 0x10U // Non Master CLA1 Read Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1WRITE 0x20U // Non Master CLA1 Write Access Violation Interrupt + // Enable +#define MEMCFG_NMAVINTEN_CLA1FETCH 0x40U // Non Master CLA1 Fetch Access Violation Interrupt + // Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVFLG register +// +//************************************************************************************************* +#define MEMCFG_MAVFLG_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag +#define MEMCFG_MAVFLG_CPUWRITE 0x2U // Master CPU Write Access Violation Flag +#define MEMCFG_MAVFLG_DMAWRITE 0x4U // Master DMA Write Access Violation Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVSET register +// +//************************************************************************************************* +#define MEMCFG_MAVSET_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Set +#define MEMCFG_MAVSET_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Set +#define MEMCFG_MAVSET_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVCLR register +// +//************************************************************************************************* +#define MEMCFG_MAVCLR_CPUFETCH 0x1U // Master CPU Fetch Access Violation Flag Clear +#define MEMCFG_MAVCLR_CPUWRITE 0x2U // Master CPU Write Access Violation Flag Clear +#define MEMCFG_MAVCLR_DMAWRITE 0x4U // Master DMA Write Access Violation Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MAVINTEN register +// +//************************************************************************************************* +#define MEMCFG_MAVINTEN_CPUFETCH 0x1U // Master CPU Fetch Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_CPUWRITE 0x2U // Master CPU Write Access Violation Interrupt Enable +#define MEMCFG_MAVINTEN_DMAWRITE 0x4U // Master DMA Write Access Violation Interrupt Enable + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRFLG register +// +//************************************************************************************************* +#define MEMCFG_UCERRFLG_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag +#define MEMCFG_UCERRFLG_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRSET register +// +//************************************************************************************************* +#define MEMCFG_UCERRSET_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Set +#define MEMCFG_UCERRSET_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the UCERRCLR register +// +//************************************************************************************************* +#define MEMCFG_UCERRCLR_CPURDERR 0x1U // CPU Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_DMARDERR 0x2U // DMA Uncorrectable Read Error Flag Clear +#define MEMCFG_UCERRCLR_CLA1RDERR 0x4U // CLA1 Uncorrectable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRFLG register +// +//************************************************************************************************* +#define MEMCFG_CERRFLG_CPURDERR 0x1U // CPU Correctable Read Error Flag +#define MEMCFG_CERRFLG_DMARDERR 0x2U // DMA Correctable Read Error Flag +#define MEMCFG_CERRFLG_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRSET register +// +//************************************************************************************************* +#define MEMCFG_CERRSET_CPURDERR 0x1U // CPU Correctable Read Error Flag Set +#define MEMCFG_CERRSET_DMARDERR 0x2U // DMA Correctable Read Error Flag Set +#define MEMCFG_CERRSET_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Set + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CERRCLR register +// +//************************************************************************************************* +#define MEMCFG_CERRCLR_CPURDERR 0x1U // CPU Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_DMARDERR 0x2U // DMA Correctable Read Error Flag Clear +#define MEMCFG_CERRCLR_CLA1RDERR 0x4U // CLA1 Correctable Read Error Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTFLG register +// +//************************************************************************************************* +#define MEMCFG_CEINTFLG_CEINTFLAG 0x1U // Total corrected error count exceeded threshold flag. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTCLR register +// +//************************************************************************************************* +#define MEMCFG_CEINTCLR_CEINTCLR 0x1U // CPU Corrected Error Threshold Exceeded Error Clear. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTSET register +// +//************************************************************************************************* +#define MEMCFG_CEINTSET_CEINTSET 0x1U // Total corrected error count exceeded flag set. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CEINTEN register +// +//************************************************************************************************* +#define MEMCFG_CEINTEN_CEINTEN 0x1U // CPU/DMA Correctable Error Interrupt Enable. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMWAITSTATE register +// +//************************************************************************************************* +#define MEMCFG_ROMWAITSTATE_WSDISABLE 0x1U // C28x ROM Wait State Enable/Disable Control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ROMPREFETCH register +// +//************************************************************************************************* +#define MEMCFG_ROMPREFETCH_PFENABLE 0x1U // ROM Prefetch Enable/Disable Control + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_memmap.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_memmap.h new file mode 100644 index 0000000..ba0b5e5 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_memmap.h @@ -0,0 +1,208 @@ +//########################################################################### +// +// FILE: hw_memmap.h +// +// TITLE: Macros defining the memory map of the C28x. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_MEMMAP_H +#define HW_MEMMAP_H + +//***************************************************************************** +// +// The following are defines for the base address of the memories and +// peripherals. +// +//***************************************************************************** +#define M0_RAM_BASE 0x00000000U +#define M1_RAM_BASE 0x00000400U +#define ADCARESULT_BASE 0x00000B00U +#define ADCBRESULT_BASE 0x00000B20U +#define ADCCRESULT_BASE 0x00000B40U +#define ADCDRESULT_BASE 0x00000B60U +#define CPUTIMER0_BASE 0x00000C00U +#define CPUTIMER1_BASE 0x00000C08U +#define CPUTIMER2_BASE 0x00000C10U +#define CLA1_SOFTINT_BASE 0x00000CE0U +#define PIECTRL_BASE 0x00000CE0U +#define PIEVECTTABLE_BASE 0x00000D00U +#define DMA_BASE 0x00001000U +#define DMA_CH1_BASE 0x00001020U +#define DMA_CH2_BASE 0x00001040U +#define DMA_CH3_BASE 0x00001060U +#define DMA_CH4_BASE 0x00001080U +#define DMA_CH5_BASE 0x000010A0U +#define DMA_CH6_BASE 0x000010C0U +#define CLA1_BASE 0x00001400U +#define CLATOCPU_RAM_BASE 0x00001480U +#define CPUTOCLA_RAM_BASE 0x00001500U +#define CLB1_BASE 0x00003000U +#define CLB1_LOGICCFG_BASE 0x00003000U +#define CLB1_LOGICCTL_BASE 0x00003100U +#define CLB1_DATAEXCH_BASE 0x00003200U +#define CLB2_BASE 0x00003400U +#define CLB2_LOGICCFG_BASE 0x00003400U +#define CLB2_LOGICCTL_BASE 0x00003500U +#define CLB2_DATAEXCH_BASE 0x00003600U +#define CLB3_BASE 0x00003800U +#define CLB3_LOGICCFG_BASE 0x00003800U +#define CLB3_LOGICCTL_BASE 0x00003900U +#define CLB3_DATAEXCH_BASE 0x00003A00U +#define CLB4_BASE 0x00003C00U +#define CLB4_LOGICCFG_BASE 0x00003C00U +#define CLB4_LOGICCTL_BASE 0x00003D00U +#define CLB4_DATAEXCH_BASE 0x00003E00U +#define EPWM1_BASE 0x00004000U +#define EPWM2_BASE 0x00004100U +#define EPWM3_BASE 0x00004200U +#define EPWM4_BASE 0x00004300U +#define EPWM5_BASE 0x00004400U +#define EPWM6_BASE 0x00004500U +#define EPWM7_BASE 0x00004600U +#define EPWM8_BASE 0x00004700U +#define EPWM9_BASE 0x00004800U +#define EPWM10_BASE 0x00004900U +#define EPWM11_BASE 0x00004A00U +#define EPWM12_BASE 0x00004B00U +#define ECAP1_BASE 0x00005000U +#define ECAP2_BASE 0x00005020U +#define ECAP3_BASE 0x00005040U +#define ECAP4_BASE 0x00005060U +#define ECAP5_BASE 0x00005080U +#define ECAP6_BASE 0x000050A0U +#define EQEP1_BASE 0x00005100U +#define EQEP2_BASE 0x00005140U +#define EQEP3_BASE 0x00005180U +#define DACA_BASE 0x00005C00U +#define DACB_BASE 0x00005C10U +#define DACC_BASE 0x00005C20U +#define CMPSS1_BASE 0x00005C80U +#define CMPSS2_BASE 0x00005CA0U +#define CMPSS3_BASE 0x00005CC0U +#define CMPSS4_BASE 0x00005CE0U +#define CMPSS5_BASE 0x00005D00U +#define CMPSS6_BASE 0x00005D20U +#define CMPSS7_BASE 0x00005D40U +#define CMPSS8_BASE 0x00005D60U +#define SDFM1_BASE 0x00005E00U +#define SDFM2_BASE 0x00005E80U +#define MCBSPA_BASE 0x00006000U +#define MCBSPB_BASE 0x00006040U +#define SPIA_BASE 0x00006100U +#define SPIB_BASE 0x00006110U +#define SPIC_BASE 0x00006120U +#define UPP_BASE 0x00006200U +#define UPP_TX_MSG_RAM_BASE 0x00006C00U +#define UPP_RX_MSG_RAM_BASE 0x00006E00U +#define WD_BASE 0x00007000U +#define NMI_BASE 0x00007060U +#define XINT_BASE 0x00007070U +#define SCIA_BASE 0x00007200U +#define SCIB_BASE 0x00007210U +#define SCIC_BASE 0x00007220U +#define SCID_BASE 0x00007230U +#define I2CA_BASE 0x00007300U +#define I2CB_BASE 0x00007340U +#define ADCA_BASE 0x00007400U +#define ADCB_BASE 0x00007480U +#define ADCC_BASE 0x00007500U +#define ADCD_BASE 0x00007580U +#define INPUTXBAR_BASE 0x00007900U +#define XBAR_BASE 0x00007920U +#define SYNCSOC_BASE 0x00007940U +#define DMACLASRCSEL_BASE 0x00007980U +#define EPWMXBAR_BASE 0x00007A00U +#define CLBXBAR_BASE 0x00007A40U +#define OUTPUTXBAR_BASE 0x00007A80U +#define GPIOCTRL_BASE 0x00007C00U +#define GPIODATA_BASE 0x00007F00U +#define LS0_RAM_BASE 0x00008000U +#define LS1_RAM_BASE 0x00008800U +#define LS2_RAM_BASE 0x00009000U +#define LS3_RAM_BASE 0x00009800U +#define LS4_RAM_BASE 0x0000A000U +#define LS5_RAM_BASE 0x0000A800U +#define D0_RAM_BASE 0x0000B000U +#define D1_RAM_BASE 0x0000B800U +#define GS0_RAM_BASE 0x0000C000U +#define GS1_RAM_BASE 0x0000D000U +#define GS2_RAM_BASE 0x0000E000U +#define GS3_RAM_BASE 0x0000F000U +#define GS4_RAM_BASE 0x00010000U +#define GS5_RAM_BASE 0x00011000U +#define GS6_RAM_BASE 0x00012000U +#define GS7_RAM_BASE 0x00013000U +#define GS8_RAM_BASE 0x00014000U +#define GS9_RAM_BASE 0x00015000U +#define GS10_RAM_BASE 0x00016000U +#define GS11_RAM_BASE 0x00017000U +#define GS12_RAM_BASE 0x00018000U +#define GS13_RAM_BASE 0x00019000U +#define GS14_RAM_BASE 0x0001A000U +#define GS15_RAM_BASE 0x0001B000U +#define CPU2_TO_CPU1_MSG_RAM_BASE 0x0003F800U +#define CPU1_TO_CPU2_MSG_RAM_BASE 0x0003FC00U +#define USBA_BASE 0x00040000U +#define EMIF1_BASE 0x00047000U +#define EMIF2_BASE 0x00047800U +#define CANA_BASE 0x00048000U +#define CANA_MSG_RAM_BASE 0x00049000U +#define CANB_BASE 0x0004A000U +#define CANB_MSG_RAM_BASE 0x0004B000U +#define IPC_BASE 0x00050000U +#define FLASHPUMPSEMAPHORE_BASE 0x00050024U +#define DEVCFG_BASE 0x0005D000U +#define ANALOGSUBSYS_BASE 0x0005D180U +#define CLKCFG_BASE 0x0005D200U +#define CPUSYS_BASE 0x0005D300U +#define ROMPREFETCH_BASE 0x0005E608U +#define DCSM_Z1_BASE 0x0005F000U +#define DCSM_Z2_BASE 0x0005F040U +#define DCSMCOMMON_BASE 0x0005F070U +#define MEMCFG_BASE 0x0005F400U +#define EMIF1CONFIG_BASE 0x0005F480U +#define EMIF2CONFIG_BASE 0x0005F4A0U +#define ACCESSPROTECTION_BASE 0x0005F4C0U +#define MEMORYERROR_BASE 0x0005F500U +#define ROMWAITSTATE_BASE 0x0005F540U +#define FLASH0CTRL_BASE 0x0005F800U +#define FLASH0ECC_BASE 0x0005FB00U +#define DCSM_Z1OTP_BASE 0x00078000U +#define DCSM_Z2OTP_BASE 0x00078200U +#define UID_BASE 0x000703C0U +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_nmi.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_nmi.h new file mode 100644 index 0000000..efd8157 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_nmi.h @@ -0,0 +1,134 @@ +//########################################################################### +// +// FILE: hw_nmi.h +// +// TITLE: Definitions for the NMI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_NMI_H +#define HW_NMI_H + +//************************************************************************************************* +// +// The following are defines for the NMI register offsets +// +//************************************************************************************************* +#define NMI_O_CFG 0x0U // NMI Configuration Register +#define NMI_O_FLG 0x1U // NMI Flag Register (XRSn Clear) +#define NMI_O_FLGCLR 0x2U // NMI Flag Clear Register +#define NMI_O_FLGFRC 0x3U // NMI Flag Force Register +#define NMI_O_WDCNT 0x4U // NMI Watchdog Counter Register +#define NMI_O_WDPRD 0x5U // NMI Watchdog Period Register +#define NMI_O_SHDFLG 0x6U // NMI Shadow Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMICFG register +// +//************************************************************************************************* +#define NMI_CFG_NMIE 0x1U // Global NMI Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLG register +// +//************************************************************************************************* +#define NMI_FLG_NMIINT 0x1U // NMI Interrupt Flag +#define NMI_FLG_CLOCKFAIL 0x2U // Clock Fail Interrupt Flag +#define NMI_FLG_RAMUNCERR 0x4U // RAM Uncorrectable Error NMI Flag +#define NMI_FLG_FLUNCERR 0x8U // Flash Uncorrectable Error NMI Flag +#define NMI_FLG_CPU1HWBISTERR 0x10U // HW BIST Error NMI Flag +#define NMI_FLG_CPU2HWBISTERR 0x20U // HW BIST Error NMI Flag +#define NMI_FLG_PIEVECTERR 0x40U // PIE Vector Fetch Error Flag +#define NMI_FLG_CLBNMI 0x100U // Configurable Logic Block NMI Flag +#define NMI_FLG_CPU2WDRSN 0x200U // CPU2 WDRSn Reset Indication Flag +#define NMI_FLG_CPU2NMIWDRSN 0x400U // CPU2 NMIWDRSn Reset Indication Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGCLR register +// +//************************************************************************************************* +#define NMI_FLGCLR_NMIINT 0x1U // NMIINT Flag Clear +#define NMI_FLGCLR_CLOCKFAIL 0x2U // CLOCKFAIL Flag Clear +#define NMI_FLGCLR_RAMUNCERR 0x4U // RAMUNCERR Flag Clear +#define NMI_FLGCLR_FLUNCERR 0x8U // FLUNCERR Flag Clear +#define NMI_FLGCLR_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Clear +#define NMI_FLGCLR_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Clear +#define NMI_FLGCLR_PIEVECTERR 0x40U // PIEVECTERR Flag Clear +#define NMI_FLGCLR_CLBNMI 0x100U // CLBNMI Flag Clear +#define NMI_FLGCLR_CPU2WDRSN 0x200U // CPU2WDRSn Flag Clear +#define NMI_FLGCLR_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Clear +#define NMI_FLGCLR_OVF 0x800U // OVF Flag Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMIFLGFRC register +// +//************************************************************************************************* +#define NMI_FLGFRC_CLOCKFAIL 0x2U // CLOCKFAIL Flag Force +#define NMI_FLGFRC_RAMUNCERR 0x4U // RAMUNCERR Flag Force +#define NMI_FLGFRC_FLUNCERR 0x8U // FLUNCERR Flag Force +#define NMI_FLGFRC_CPU1HWBISTERR 0x10U // CPU1HWBISTERR Flag Force +#define NMI_FLGFRC_CPU2HWBISTERR 0x20U // CPU2HWBISTERR Flag Force +#define NMI_FLGFRC_PIEVECTERR 0x40U // PIEVECTERR Flag Force +#define NMI_FLGFRC_CLBNMI 0x100U // CLBNMI Flag Force +#define NMI_FLGFRC_CPU2WDRSN 0x200U // CPU2WDRSn Flag Force +#define NMI_FLGFRC_CPU2NMIWDRSN 0x400U // CPU2NMIWDRSn Flag Force +#define NMI_FLGFRC_OVF 0x800U // OVF Flag Force + +//************************************************************************************************* +// +// The following are defines for the bit fields in the NMISHDFLG register +// +//************************************************************************************************* +#define NMI_SHDFLG_CLOCKFAIL 0x2U // Shadow CLOCKFAIL Flag +#define NMI_SHDFLG_RAMUNCERR 0x4U // Shadow RAMUNCERR Flag +#define NMI_SHDFLG_FLUNCERR 0x8U // Shadow FLUNCERR Flag +#define NMI_SHDFLG_CPU1HWBISTERR 0x10U // Shadow CPU1HWBISTERR Flag +#define NMI_SHDFLG_CPU2HWBISTERR 0x20U // Shadow CPU2HWBISTERR Flag +#define NMI_SHDFLG_PIEVECTERR 0x40U // Shadow PIEVECTERR Flag +#define NMI_SHDFLG_CLBNMI 0x100U // Shadow CLBNMI Flag +#define NMI_SHDFLG_CPU2WDRSN 0x200U // Shadow CPU2WDRSn Flag +#define NMI_SHDFLG_CPU2NMIWDRSN 0x400U // Shadow CPU2NMIWDRSn Flag +#define NMI_SHDFLG_OVF 0x800U // Shadow OVF Flag + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_otp.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_otp.h new file mode 100644 index 0000000..d074499 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_otp.h @@ -0,0 +1,63 @@ +//########################################################################### +// +// FILE: hw_otp.h +// +// TITLE: Definitions for the OTP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OTP_H +#define HW_OTP_H + +//************************************************************************************************* +// +// The following are defines for the OTP register offsets +// +//************************************************************************************************* +#define OTP_O_UID_PSRAND0 0x0U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND1 0x2U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND2 0x4U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND3 0x6U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND4 0x8U // UID Psuedo-random 160 bit number +#define OTP_O_UID_PSRAND5 0xAU // UID Psuedo-random 160 bit number +#define OTP_O_UID_UNIQUE 0xCU // UID UID Unique 32 bit number +#define OTP_O_UID_CHECKSUM 0xEU // UID Checksum + + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_outputxbar.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_outputxbar.h new file mode 100644 index 0000000..30a10e9 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_outputxbar.h @@ -0,0 +1,1340 @@ +//########################################################################### +// +// FILE: hw_outputxbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_OUTPUTXBAR_H +#define HW_OUTPUTXBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_OUTPUT1MUX0TO15CFG 0x0U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT1MUX16TO31CFG 0x2U // Output X-BAR Mux Configuration for Output 1 +#define XBAR_O_OUTPUT2MUX0TO15CFG 0x4U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT2MUX16TO31CFG 0x6U // Output X-BAR Mux Configuration for Output 2 +#define XBAR_O_OUTPUT3MUX0TO15CFG 0x8U // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT3MUX16TO31CFG 0xAU // Output X-BAR Mux Configuration for Output 3 +#define XBAR_O_OUTPUT4MUX0TO15CFG 0xCU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT4MUX16TO31CFG 0xEU // Output X-BAR Mux Configuration for Output 4 +#define XBAR_O_OUTPUT5MUX0TO15CFG 0x10U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT5MUX16TO31CFG 0x12U // Output X-BAR Mux Configuration for Output 5 +#define XBAR_O_OUTPUT6MUX0TO15CFG 0x14U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT6MUX16TO31CFG 0x16U // Output X-BAR Mux Configuration for Output 6 +#define XBAR_O_OUTPUT7MUX0TO15CFG 0x18U // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT7MUX16TO31CFG 0x1AU // Output X-BAR Mux Configuration for Output 7 +#define XBAR_O_OUTPUT8MUX0TO15CFG 0x1CU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT8MUX16TO31CFG 0x1EU // Output X-BAR Mux Configuration for Output 8 +#define XBAR_O_OUTPUT1MUXENABLE 0x20U // Output X-BAR Mux Enable for Output 1 +#define XBAR_O_OUTPUT2MUXENABLE 0x22U // Output X-BAR Mux Enable for Output 2 +#define XBAR_O_OUTPUT3MUXENABLE 0x24U // Output X-BAR Mux Enable for Output 3 +#define XBAR_O_OUTPUT4MUXENABLE 0x26U // Output X-BAR Mux Enable for Output 4 +#define XBAR_O_OUTPUT5MUXENABLE 0x28U // Output X-BAR Mux Enable for Output 5 +#define XBAR_O_OUTPUT6MUXENABLE 0x2AU // Output X-BAR Mux Enable for Output 6 +#define XBAR_O_OUTPUT7MUXENABLE 0x2CU // Output X-BAR Mux Enable for Output 7 +#define XBAR_O_OUTPUT8MUXENABLE 0x2EU // Output X-BAR Mux Enable for Output 8 +#define XBAR_O_OUTPUTLATCH 0x30U // Output X-BAR Output Latch +#define XBAR_O_OUTPUTLATCHCLR 0x32U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHFRC 0x34U // Output X-BAR Output Latch Clear +#define XBAR_O_OUTPUTLATCHENABLE 0x36U // Output X-BAR Output Latch Enable +#define XBAR_O_OUTPUTINV 0x38U // Output X-BAR Output Inversion +#define XBAR_O_OUTPUTLOCK 0x3EU // Output X-BAR Configuration Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT1MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT1 of + // OUTPUT-XBAR +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT1MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT1 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT2MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT2 of + // OUTPUT-XBAR +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT2MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT2 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT3MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT3 of + // OUTPUT-XBAR +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT3MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT3 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT4MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT4 of + // OUTPUT-XBAR +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT4MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT4 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT5MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT5 of + // OUTPUT-XBAR +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT5MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT5 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT6MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT6 of + // OUTPUT-XBAR +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT6MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT6 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT7MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT7 of + // OUTPUT-XBAR +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT7MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT7 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX0TO15CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_S 0U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX0_M 0x3U // Mux0 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_S 2U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX1_M 0xCU // Mux1 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_S 4U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX2_M 0x30U // Mux2 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_S 6U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX3_M 0xC0U // Mux3 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_S 8U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX4_M 0x300U // Mux4 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_S 10U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX5_M 0xC00U // Mux5 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_S 12U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX6_M 0x3000U // Mux6 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_S 14U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX7_M 0xC000U // Mux7 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_S 16U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX8_M 0x30000U // Mux8 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_S 18U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX9_M 0xC0000U // Mux9 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_S 20U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX10_M 0x300000U // Mux10 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_S 22U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX11_M 0xC00000U // Mux11 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_S 24U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX12_M 0x3000000U // Mux12 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_S 26U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX13_M 0xC000000U // Mux13 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_S 28U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX14_M 0x30000000U // Mux14 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_S 30U +#define XBAR_OUTPUT8MUX0TO15CFG_MUX15_M 0xC0000000U // Mux15 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUX16TO31CFG register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_S 0U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX16_M 0x3U // Mux16 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_S 2U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX17_M 0xCU // Mux17 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_S 4U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX18_M 0x30U // Mux18 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_S 6U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX19_M 0xC0U // Mux19 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_S 8U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX20_M 0x300U // Mux20 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_S 10U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX21_M 0xC00U // Mux21 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_S 12U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX22_M 0x3000U // Mux22 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_S 14U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX23_M 0xC000U // Mux23 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_S 16U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX24_M 0x30000U // Mux24 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_S 18U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX25_M 0xC0000U // Mux25 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_S 20U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX26_M 0x300000U // Mux26 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_S 22U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX27_M 0xC00000U // Mux27 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_S 24U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX28_M 0x3000000U // Mux28 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_S 26U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX29_M 0xC000000U // Mux29 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_S 28U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX30_M 0x30000000U // Mux30 Configuration for OUTPUT8 of + // OUTPUT-XBAR +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_S 30U +#define XBAR_OUTPUT8MUX16TO31CFG_MUX31_M 0xC0000000U // Mux31 Configuration for OUTPUT8 of + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT1MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT1MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUT1MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT1 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT2MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT2MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUT2MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT2 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT3MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT3MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUT3MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT3 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT4MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT4MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUT4MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT4 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT5MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT5MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUT5MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT5 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT6MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT6MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUT6MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT6 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT7MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT7MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUT7MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT7 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUT8MUXENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUT8MUXENABLE_MUX0 0x1U // Mux0 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX1 0x2U // Mux1 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX2 0x4U // Mux2 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX3 0x8U // Mux3 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX4 0x10U // Mux4 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX5 0x20U // Mux5 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX6 0x40U // Mux6 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX7 0x80U // Mux7 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX8 0x100U // Mux8 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX9 0x200U // Mux9 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX10 0x400U // Mux10 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX11 0x800U // Mux11 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX12 0x1000U // Mux12 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX13 0x2000U // Mux13 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX14 0x4000U // Mux14 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX15 0x8000U // Mux15 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX16 0x10000U // Mux16 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX17 0x20000U // Mux17 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX18 0x40000U // Mux18 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX19 0x80000U // Mux19 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX20 0x100000U // Mux20 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX21 0x200000U // Mux21 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX22 0x400000U // Mux22 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX23 0x800000U // Mux23 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX24 0x1000000U // Mux24 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX25 0x2000000U // Mux25 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX26 0x4000000U // Mux26 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX27 0x8000000U // Mux27 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX28 0x10000000U // Mux28 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX29 0x20000000U // Mux29 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX30 0x40000000U // Mux30 to drive OUTPUT8 of OUTPUT-XBAR +#define XBAR_OUTPUT8MUXENABLE_MUX31 0x80000000U // Mux31 to drive OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCH register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCH_OUTPUT1 0x1U // Records the OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT2 0x2U // Records the OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT3 0x4U // Records the OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT4 0x8U // Records the OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT5 0x10U // Records the OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT6 0x20U // Records the OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT7 0x40U // Records the OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCH_OUTPUT8 0x80U // Records the OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHCLR register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHCLR_OUTPUT1 0x1U // Clears the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT2 0x2U // Clears the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT3 0x4U // Clears the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT4 0x8U // Clears the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT5 0x10U // Clears the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT6 0x20U // Clears the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT7 0x40U // Clears the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHCLR_OUTPUT8 0x80U // Clears the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHFRC register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHFRC_OUTPUT1 0x1U // Sets the Output-Latch for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT2 0x2U // Sets the Output-Latch for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT3 0x4U // Sets the Output-Latch for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT4 0x8U // Sets the Output-Latch for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT5 0x10U // Sets the Output-Latch for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT6 0x20U // Sets the Output-Latch for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT7 0x40U // Sets the Output-Latch for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTLATCHFRC_OUTPUT8 0x80U // Sets the Output-Latch for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLATCHENABLE register +// +//************************************************************************************************* +#define XBAR_OUTPUTLATCHENABLE_OUTPUT1 0x1U // Selects the output latch to drive OUTPUT1 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT2 0x2U // Selects the output latch to drive OUTPUT2 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT3 0x4U // Selects the output latch to drive OUTPUT3 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT4 0x8U // Selects the output latch to drive OUTPUT4 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT5 0x10U // Selects the output latch to drive OUTPUT5 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT6 0x20U // Selects the output latch to drive OUTPUT6 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT7 0x40U // Selects the output latch to drive OUTPUT7 for + // OUTPUT-XBAR +#define XBAR_OUTPUTLATCHENABLE_OUTPUT8 0x80U // Selects the output latch to drive OUTPUT8 for + // OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTINV register +// +//************************************************************************************************* +#define XBAR_OUTPUTINV_OUTPUT1 0x1U // Selects polarity for OUTPUT1 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT2 0x2U // Selects polarity for OUTPUT2 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT3 0x4U // Selects polarity for OUTPUT3 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT4 0x8U // Selects polarity for OUTPUT4 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT5 0x10U // Selects polarity for OUTPUT5 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT6 0x20U // Selects polarity for OUTPUT6 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT7 0x40U // Selects polarity for OUTPUT7 of OUTPUT-XBAR +#define XBAR_OUTPUTINV_OUTPUT8 0x80U // Selects polarity for OUTPUT8 of OUTPUT-XBAR + +//************************************************************************************************* +// +// The following are defines for the bit fields in the OUTPUTLOCK register +// +//************************************************************************************************* +#define XBAR_OUTPUTLOCK_LOCK 0x1U // Locks the configuration for OUTPUT-XBAR +#define XBAR_OUTPUTLOCK_KEY_S 16U +#define XBAR_OUTPUTLOCK_KEY_M 0xFFFF0000U // Write Protection KEY + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_pie.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_pie.h new file mode 100644 index 0000000..9a4f09f --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_pie.h @@ -0,0 +1,636 @@ +//########################################################################### +// +// FILE: hw_pie.h +// +// TITLE: Definitions for the PIE registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_PIE_H +#define HW_PIE_H + +//************************************************************************************************* +// +// The following are defines for the PIE register offsets +// +//************************************************************************************************* +#define PIE_O_CTRL 0x0U // ePIE Control Register +#define PIE_O_ACK 0x1U // Interrupt Acknowledge Register +#define PIE_O_IER1 0x2U // Interrupt Group 1 Enable Register +#define PIE_O_IFR1 0x3U // Interrupt Group 1 Flag Register +#define PIE_O_IER2 0x4U // Interrupt Group 2 Enable Register +#define PIE_O_IFR2 0x5U // Interrupt Group 2 Flag Register +#define PIE_O_IER3 0x6U // Interrupt Group 3 Enable Register +#define PIE_O_IFR3 0x7U // Interrupt Group 3 Flag Register +#define PIE_O_IER4 0x8U // Interrupt Group 4 Enable Register +#define PIE_O_IFR4 0x9U // Interrupt Group 4 Flag Register +#define PIE_O_IER5 0xAU // Interrupt Group 5 Enable Register +#define PIE_O_IFR5 0xBU // Interrupt Group 5 Flag Register +#define PIE_O_IER6 0xCU // Interrupt Group 6 Enable Register +#define PIE_O_IFR6 0xDU // Interrupt Group 6 Flag Register +#define PIE_O_IER7 0xEU // Interrupt Group 7 Enable Register +#define PIE_O_IFR7 0xFU // Interrupt Group 7 Flag Register +#define PIE_O_IER8 0x10U // Interrupt Group 8 Enable Register +#define PIE_O_IFR8 0x11U // Interrupt Group 8 Flag Register +#define PIE_O_IER9 0x12U // Interrupt Group 9 Enable Register +#define PIE_O_IFR9 0x13U // Interrupt Group 9 Flag Register +#define PIE_O_IER10 0x14U // Interrupt Group 10 Enable Register +#define PIE_O_IFR10 0x15U // Interrupt Group 10 Flag Register +#define PIE_O_IER11 0x16U // Interrupt Group 11 Enable Register +#define PIE_O_IFR11 0x17U // Interrupt Group 11 Flag Register +#define PIE_O_IER12 0x18U // Interrupt Group 12 Enable Register +#define PIE_O_IFR12 0x19U // Interrupt Group 12 Flag Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIECTRL register +// +//************************************************************************************************* +#define PIE_CTRL_ENPIE 0x1U // PIE Enable +#define PIE_CTRL_PIEVECT_S 1U +#define PIE_CTRL_PIEVECT_M 0xFFFEU // PIE Vector Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEACK register +// +//************************************************************************************************* +#define PIE_ACK_ACK1 0x1U // Acknowledge PIE Interrupt Group 1 +#define PIE_ACK_ACK2 0x2U // Acknowledge PIE Interrupt Group 2 +#define PIE_ACK_ACK3 0x4U // Acknowledge PIE Interrupt Group 3 +#define PIE_ACK_ACK4 0x8U // Acknowledge PIE Interrupt Group 4 +#define PIE_ACK_ACK5 0x10U // Acknowledge PIE Interrupt Group 5 +#define PIE_ACK_ACK6 0x20U // Acknowledge PIE Interrupt Group 6 +#define PIE_ACK_ACK7 0x40U // Acknowledge PIE Interrupt Group 7 +#define PIE_ACK_ACK8 0x80U // Acknowledge PIE Interrupt Group 8 +#define PIE_ACK_ACK9 0x100U // Acknowledge PIE Interrupt Group 9 +#define PIE_ACK_ACK10 0x200U // Acknowledge PIE Interrupt Group 10 +#define PIE_ACK_ACK11 0x400U // Acknowledge PIE Interrupt Group 11 +#define PIE_ACK_ACK12 0x800U // Acknowledge PIE Interrupt Group 12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER1 register +// +//************************************************************************************************* +#define PIE_IER1_INTX1 0x1U // Enable for Interrupt 1.1 +#define PIE_IER1_INTX2 0x2U // Enable for Interrupt 1.2 +#define PIE_IER1_INTX3 0x4U // Enable for Interrupt 1.3 +#define PIE_IER1_INTX4 0x8U // Enable for Interrupt 1.4 +#define PIE_IER1_INTX5 0x10U // Enable for Interrupt 1.5 +#define PIE_IER1_INTX6 0x20U // Enable for Interrupt 1.6 +#define PIE_IER1_INTX7 0x40U // Enable for Interrupt 1.7 +#define PIE_IER1_INTX8 0x80U // Enable for Interrupt 1.8 +#define PIE_IER1_INTX9 0x100U // Enable for Interrupt 1.9 +#define PIE_IER1_INTX10 0x200U // Enable for Interrupt 1.10 +#define PIE_IER1_INTX11 0x400U // Enable for Interrupt 1.11 +#define PIE_IER1_INTX12 0x800U // Enable for Interrupt 1.12 +#define PIE_IER1_INTX13 0x1000U // Enable for Interrupt 1.13 +#define PIE_IER1_INTX14 0x2000U // Enable for Interrupt 1.14 +#define PIE_IER1_INTX15 0x4000U // Enable for Interrupt 1.15 +#define PIE_IER1_INTX16 0x8000U // Enable for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR1 register +// +//************************************************************************************************* +#define PIE_IFR1_INTX1 0x1U // Flag for Interrupt 1.1 +#define PIE_IFR1_INTX2 0x2U // Flag for Interrupt 1.2 +#define PIE_IFR1_INTX3 0x4U // Flag for Interrupt 1.3 +#define PIE_IFR1_INTX4 0x8U // Flag for Interrupt 1.4 +#define PIE_IFR1_INTX5 0x10U // Flag for Interrupt 1.5 +#define PIE_IFR1_INTX6 0x20U // Flag for Interrupt 1.6 +#define PIE_IFR1_INTX7 0x40U // Flag for Interrupt 1.7 +#define PIE_IFR1_INTX8 0x80U // Flag for Interrupt 1.8 +#define PIE_IFR1_INTX9 0x100U // Flag for Interrupt 1.9 +#define PIE_IFR1_INTX10 0x200U // Flag for Interrupt 1.10 +#define PIE_IFR1_INTX11 0x400U // Flag for Interrupt 1.11 +#define PIE_IFR1_INTX12 0x800U // Flag for Interrupt 1.12 +#define PIE_IFR1_INTX13 0x1000U // Flag for Interrupt 1.13 +#define PIE_IFR1_INTX14 0x2000U // Flag for Interrupt 1.14 +#define PIE_IFR1_INTX15 0x4000U // Flag for Interrupt 1.15 +#define PIE_IFR1_INTX16 0x8000U // Flag for Interrupt 1.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER2 register +// +//************************************************************************************************* +#define PIE_IER2_INTX1 0x1U // Enable for Interrupt 2.1 +#define PIE_IER2_INTX2 0x2U // Enable for Interrupt 2.2 +#define PIE_IER2_INTX3 0x4U // Enable for Interrupt 2.3 +#define PIE_IER2_INTX4 0x8U // Enable for Interrupt 2.4 +#define PIE_IER2_INTX5 0x10U // Enable for Interrupt 2.5 +#define PIE_IER2_INTX6 0x20U // Enable for Interrupt 2.6 +#define PIE_IER2_INTX7 0x40U // Enable for Interrupt 2.7 +#define PIE_IER2_INTX8 0x80U // Enable for Interrupt 2.8 +#define PIE_IER2_INTX9 0x100U // Enable for Interrupt 2.9 +#define PIE_IER2_INTX10 0x200U // Enable for Interrupt 2.10 +#define PIE_IER2_INTX11 0x400U // Enable for Interrupt 2.11 +#define PIE_IER2_INTX12 0x800U // Enable for Interrupt 2.12 +#define PIE_IER2_INTX13 0x1000U // Enable for Interrupt 2.13 +#define PIE_IER2_INTX14 0x2000U // Enable for Interrupt 2.14 +#define PIE_IER2_INTX15 0x4000U // Enable for Interrupt 2.15 +#define PIE_IER2_INTX16 0x8000U // Enable for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR2 register +// +//************************************************************************************************* +#define PIE_IFR2_INTX1 0x1U // Flag for Interrupt 2.1 +#define PIE_IFR2_INTX2 0x2U // Flag for Interrupt 2.2 +#define PIE_IFR2_INTX3 0x4U // Flag for Interrupt 2.3 +#define PIE_IFR2_INTX4 0x8U // Flag for Interrupt 2.4 +#define PIE_IFR2_INTX5 0x10U // Flag for Interrupt 2.5 +#define PIE_IFR2_INTX6 0x20U // Flag for Interrupt 2.6 +#define PIE_IFR2_INTX7 0x40U // Flag for Interrupt 2.7 +#define PIE_IFR2_INTX8 0x80U // Flag for Interrupt 2.8 +#define PIE_IFR2_INTX9 0x100U // Flag for Interrupt 2.9 +#define PIE_IFR2_INTX10 0x200U // Flag for Interrupt 2.10 +#define PIE_IFR2_INTX11 0x400U // Flag for Interrupt 2.11 +#define PIE_IFR2_INTX12 0x800U // Flag for Interrupt 2.12 +#define PIE_IFR2_INTX13 0x1000U // Flag for Interrupt 2.13 +#define PIE_IFR2_INTX14 0x2000U // Flag for Interrupt 2.14 +#define PIE_IFR2_INTX15 0x4000U // Flag for Interrupt 2.15 +#define PIE_IFR2_INTX16 0x8000U // Flag for Interrupt 2.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER3 register +// +//************************************************************************************************* +#define PIE_IER3_INTX1 0x1U // Enable for Interrupt 3.1 +#define PIE_IER3_INTX2 0x2U // Enable for Interrupt 3.2 +#define PIE_IER3_INTX3 0x4U // Enable for Interrupt 3.3 +#define PIE_IER3_INTX4 0x8U // Enable for Interrupt 3.4 +#define PIE_IER3_INTX5 0x10U // Enable for Interrupt 3.5 +#define PIE_IER3_INTX6 0x20U // Enable for Interrupt 3.6 +#define PIE_IER3_INTX7 0x40U // Enable for Interrupt 3.7 +#define PIE_IER3_INTX8 0x80U // Enable for Interrupt 3.8 +#define PIE_IER3_INTX9 0x100U // Enable for Interrupt 3.9 +#define PIE_IER3_INTX10 0x200U // Enable for Interrupt 3.10 +#define PIE_IER3_INTX11 0x400U // Enable for Interrupt 3.11 +#define PIE_IER3_INTX12 0x800U // Enable for Interrupt 3.12 +#define PIE_IER3_INTX13 0x1000U // Enable for Interrupt 3.13 +#define PIE_IER3_INTX14 0x2000U // Enable for Interrupt 3.14 +#define PIE_IER3_INTX15 0x4000U // Enable for Interrupt 3.15 +#define PIE_IER3_INTX16 0x8000U // Enable for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR3 register +// +//************************************************************************************************* +#define PIE_IFR3_INTX1 0x1U // Flag for Interrupt 3.1 +#define PIE_IFR3_INTX2 0x2U // Flag for Interrupt 3.2 +#define PIE_IFR3_INTX3 0x4U // Flag for Interrupt 3.3 +#define PIE_IFR3_INTX4 0x8U // Flag for Interrupt 3.4 +#define PIE_IFR3_INTX5 0x10U // Flag for Interrupt 3.5 +#define PIE_IFR3_INTX6 0x20U // Flag for Interrupt 3.6 +#define PIE_IFR3_INTX7 0x40U // Flag for Interrupt 3.7 +#define PIE_IFR3_INTX8 0x80U // Flag for Interrupt 3.8 +#define PIE_IFR3_INTX9 0x100U // Flag for Interrupt 3.9 +#define PIE_IFR3_INTX10 0x200U // Flag for Interrupt 3.10 +#define PIE_IFR3_INTX11 0x400U // Flag for Interrupt 3.11 +#define PIE_IFR3_INTX12 0x800U // Flag for Interrupt 3.12 +#define PIE_IFR3_INTX13 0x1000U // Flag for Interrupt 3.13 +#define PIE_IFR3_INTX14 0x2000U // Flag for Interrupt 3.14 +#define PIE_IFR3_INTX15 0x4000U // Flag for Interrupt 3.15 +#define PIE_IFR3_INTX16 0x8000U // Flag for Interrupt 3.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER4 register +// +//************************************************************************************************* +#define PIE_IER4_INTX1 0x1U // Enable for Interrupt 4.1 +#define PIE_IER4_INTX2 0x2U // Enable for Interrupt 4.2 +#define PIE_IER4_INTX3 0x4U // Enable for Interrupt 4.3 +#define PIE_IER4_INTX4 0x8U // Enable for Interrupt 4.4 +#define PIE_IER4_INTX5 0x10U // Enable for Interrupt 4.5 +#define PIE_IER4_INTX6 0x20U // Enable for Interrupt 4.6 +#define PIE_IER4_INTX7 0x40U // Enable for Interrupt 4.7 +#define PIE_IER4_INTX8 0x80U // Enable for Interrupt 4.8 +#define PIE_IER4_INTX9 0x100U // Enable for Interrupt 4.9 +#define PIE_IER4_INTX10 0x200U // Enable for Interrupt 4.10 +#define PIE_IER4_INTX11 0x400U // Enable for Interrupt 4.11 +#define PIE_IER4_INTX12 0x800U // Enable for Interrupt 4.12 +#define PIE_IER4_INTX13 0x1000U // Enable for Interrupt 4.13 +#define PIE_IER4_INTX14 0x2000U // Enable for Interrupt 4.14 +#define PIE_IER4_INTX15 0x4000U // Enable for Interrupt 4.15 +#define PIE_IER4_INTX16 0x8000U // Enable for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR4 register +// +//************************************************************************************************* +#define PIE_IFR4_INTX1 0x1U // Flag for Interrupt 4.1 +#define PIE_IFR4_INTX2 0x2U // Flag for Interrupt 4.2 +#define PIE_IFR4_INTX3 0x4U // Flag for Interrupt 4.3 +#define PIE_IFR4_INTX4 0x8U // Flag for Interrupt 4.4 +#define PIE_IFR4_INTX5 0x10U // Flag for Interrupt 4.5 +#define PIE_IFR4_INTX6 0x20U // Flag for Interrupt 4.6 +#define PIE_IFR4_INTX7 0x40U // Flag for Interrupt 4.7 +#define PIE_IFR4_INTX8 0x80U // Flag for Interrupt 4.8 +#define PIE_IFR4_INTX9 0x100U // Flag for Interrupt 4.9 +#define PIE_IFR4_INTX10 0x200U // Flag for Interrupt 4.10 +#define PIE_IFR4_INTX11 0x400U // Flag for Interrupt 4.11 +#define PIE_IFR4_INTX12 0x800U // Flag for Interrupt 4.12 +#define PIE_IFR4_INTX13 0x1000U // Flag for Interrupt 4.13 +#define PIE_IFR4_INTX14 0x2000U // Flag for Interrupt 4.14 +#define PIE_IFR4_INTX15 0x4000U // Flag for Interrupt 4.15 +#define PIE_IFR4_INTX16 0x8000U // Flag for Interrupt 4.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER5 register +// +//************************************************************************************************* +#define PIE_IER5_INTX1 0x1U // Enable for Interrupt 5.1 +#define PIE_IER5_INTX2 0x2U // Enable for Interrupt 5.2 +#define PIE_IER5_INTX3 0x4U // Enable for Interrupt 5.3 +#define PIE_IER5_INTX4 0x8U // Enable for Interrupt 5.4 +#define PIE_IER5_INTX5 0x10U // Enable for Interrupt 5.5 +#define PIE_IER5_INTX6 0x20U // Enable for Interrupt 5.6 +#define PIE_IER5_INTX7 0x40U // Enable for Interrupt 5.7 +#define PIE_IER5_INTX8 0x80U // Enable for Interrupt 5.8 +#define PIE_IER5_INTX9 0x100U // Enable for Interrupt 5.9 +#define PIE_IER5_INTX10 0x200U // Enable for Interrupt 5.10 +#define PIE_IER5_INTX11 0x400U // Enable for Interrupt 5.11 +#define PIE_IER5_INTX12 0x800U // Enable for Interrupt 5.12 +#define PIE_IER5_INTX13 0x1000U // Enable for Interrupt 5.13 +#define PIE_IER5_INTX14 0x2000U // Enable for Interrupt 5.14 +#define PIE_IER5_INTX15 0x4000U // Enable for Interrupt 5.15 +#define PIE_IER5_INTX16 0x8000U // Enable for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR5 register +// +//************************************************************************************************* +#define PIE_IFR5_INTX1 0x1U // Flag for Interrupt 5.1 +#define PIE_IFR5_INTX2 0x2U // Flag for Interrupt 5.2 +#define PIE_IFR5_INTX3 0x4U // Flag for Interrupt 5.3 +#define PIE_IFR5_INTX4 0x8U // Flag for Interrupt 5.4 +#define PIE_IFR5_INTX5 0x10U // Flag for Interrupt 5.5 +#define PIE_IFR5_INTX6 0x20U // Flag for Interrupt 5.6 +#define PIE_IFR5_INTX7 0x40U // Flag for Interrupt 5.7 +#define PIE_IFR5_INTX8 0x80U // Flag for Interrupt 5.8 +#define PIE_IFR5_INTX9 0x100U // Flag for Interrupt 5.9 +#define PIE_IFR5_INTX10 0x200U // Flag for Interrupt 5.10 +#define PIE_IFR5_INTX11 0x400U // Flag for Interrupt 5.11 +#define PIE_IFR5_INTX12 0x800U // Flag for Interrupt 5.12 +#define PIE_IFR5_INTX13 0x1000U // Flag for Interrupt 5.13 +#define PIE_IFR5_INTX14 0x2000U // Flag for Interrupt 5.14 +#define PIE_IFR5_INTX15 0x4000U // Flag for Interrupt 5.15 +#define PIE_IFR5_INTX16 0x8000U // Flag for Interrupt 5.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER6 register +// +//************************************************************************************************* +#define PIE_IER6_INTX1 0x1U // Enable for Interrupt 6.1 +#define PIE_IER6_INTX2 0x2U // Enable for Interrupt 6.2 +#define PIE_IER6_INTX3 0x4U // Enable for Interrupt 6.3 +#define PIE_IER6_INTX4 0x8U // Enable for Interrupt 6.4 +#define PIE_IER6_INTX5 0x10U // Enable for Interrupt 6.5 +#define PIE_IER6_INTX6 0x20U // Enable for Interrupt 6.6 +#define PIE_IER6_INTX7 0x40U // Enable for Interrupt 6.7 +#define PIE_IER6_INTX8 0x80U // Enable for Interrupt 6.8 +#define PIE_IER6_INTX9 0x100U // Enable for Interrupt 6.9 +#define PIE_IER6_INTX10 0x200U // Enable for Interrupt 6.10 +#define PIE_IER6_INTX11 0x400U // Enable for Interrupt 6.11 +#define PIE_IER6_INTX12 0x800U // Enable for Interrupt 6.12 +#define PIE_IER6_INTX13 0x1000U // Enable for Interrupt 6.13 +#define PIE_IER6_INTX14 0x2000U // Enable for Interrupt 6.14 +#define PIE_IER6_INTX15 0x4000U // Enable for Interrupt 6.15 +#define PIE_IER6_INTX16 0x8000U // Enable for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR6 register +// +//************************************************************************************************* +#define PIE_IFR6_INTX1 0x1U // Flag for Interrupt 6.1 +#define PIE_IFR6_INTX2 0x2U // Flag for Interrupt 6.2 +#define PIE_IFR6_INTX3 0x4U // Flag for Interrupt 6.3 +#define PIE_IFR6_INTX4 0x8U // Flag for Interrupt 6.4 +#define PIE_IFR6_INTX5 0x10U // Flag for Interrupt 6.5 +#define PIE_IFR6_INTX6 0x20U // Flag for Interrupt 6.6 +#define PIE_IFR6_INTX7 0x40U // Flag for Interrupt 6.7 +#define PIE_IFR6_INTX8 0x80U // Flag for Interrupt 6.8 +#define PIE_IFR6_INTX9 0x100U // Flag for Interrupt 6.9 +#define PIE_IFR6_INTX10 0x200U // Flag for Interrupt 6.10 +#define PIE_IFR6_INTX11 0x400U // Flag for Interrupt 6.11 +#define PIE_IFR6_INTX12 0x800U // Flag for Interrupt 6.12 +#define PIE_IFR6_INTX13 0x1000U // Flag for Interrupt 6.13 +#define PIE_IFR6_INTX14 0x2000U // Flag for Interrupt 6.14 +#define PIE_IFR6_INTX15 0x4000U // Flag for Interrupt 6.15 +#define PIE_IFR6_INTX16 0x8000U // Flag for Interrupt 6.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER7 register +// +//************************************************************************************************* +#define PIE_IER7_INTX1 0x1U // Enable for Interrupt 7.1 +#define PIE_IER7_INTX2 0x2U // Enable for Interrupt 7.2 +#define PIE_IER7_INTX3 0x4U // Enable for Interrupt 7.3 +#define PIE_IER7_INTX4 0x8U // Enable for Interrupt 7.4 +#define PIE_IER7_INTX5 0x10U // Enable for Interrupt 7.5 +#define PIE_IER7_INTX6 0x20U // Enable for Interrupt 7.6 +#define PIE_IER7_INTX7 0x40U // Enable for Interrupt 7.7 +#define PIE_IER7_INTX8 0x80U // Enable for Interrupt 7.8 +#define PIE_IER7_INTX9 0x100U // Enable for Interrupt 7.9 +#define PIE_IER7_INTX10 0x200U // Enable for Interrupt 7.10 +#define PIE_IER7_INTX11 0x400U // Enable for Interrupt 7.11 +#define PIE_IER7_INTX12 0x800U // Enable for Interrupt 7.12 +#define PIE_IER7_INTX13 0x1000U // Enable for Interrupt 7.13 +#define PIE_IER7_INTX14 0x2000U // Enable for Interrupt 7.14 +#define PIE_IER7_INTX15 0x4000U // Enable for Interrupt 7.15 +#define PIE_IER7_INTX16 0x8000U // Enable for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR7 register +// +//************************************************************************************************* +#define PIE_IFR7_INTX1 0x1U // Flag for Interrupt 7.1 +#define PIE_IFR7_INTX2 0x2U // Flag for Interrupt 7.2 +#define PIE_IFR7_INTX3 0x4U // Flag for Interrupt 7.3 +#define PIE_IFR7_INTX4 0x8U // Flag for Interrupt 7.4 +#define PIE_IFR7_INTX5 0x10U // Flag for Interrupt 7.5 +#define PIE_IFR7_INTX6 0x20U // Flag for Interrupt 7.6 +#define PIE_IFR7_INTX7 0x40U // Flag for Interrupt 7.7 +#define PIE_IFR7_INTX8 0x80U // Flag for Interrupt 7.8 +#define PIE_IFR7_INTX9 0x100U // Flag for Interrupt 7.9 +#define PIE_IFR7_INTX10 0x200U // Flag for Interrupt 7.10 +#define PIE_IFR7_INTX11 0x400U // Flag for Interrupt 7.11 +#define PIE_IFR7_INTX12 0x800U // Flag for Interrupt 7.12 +#define PIE_IFR7_INTX13 0x1000U // Flag for Interrupt 7.13 +#define PIE_IFR7_INTX14 0x2000U // Flag for Interrupt 7.14 +#define PIE_IFR7_INTX15 0x4000U // Flag for Interrupt 7.15 +#define PIE_IFR7_INTX16 0x8000U // Flag for Interrupt 7.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER8 register +// +//************************************************************************************************* +#define PIE_IER8_INTX1 0x1U // Enable for Interrupt 8.1 +#define PIE_IER8_INTX2 0x2U // Enable for Interrupt 8.2 +#define PIE_IER8_INTX3 0x4U // Enable for Interrupt 8.3 +#define PIE_IER8_INTX4 0x8U // Enable for Interrupt 8.4 +#define PIE_IER8_INTX5 0x10U // Enable for Interrupt 8.5 +#define PIE_IER8_INTX6 0x20U // Enable for Interrupt 8.6 +#define PIE_IER8_INTX7 0x40U // Enable for Interrupt 8.7 +#define PIE_IER8_INTX8 0x80U // Enable for Interrupt 8.8 +#define PIE_IER8_INTX9 0x100U // Enable for Interrupt 8.9 +#define PIE_IER8_INTX10 0x200U // Enable for Interrupt 8.10 +#define PIE_IER8_INTX11 0x400U // Enable for Interrupt 8.11 +#define PIE_IER8_INTX12 0x800U // Enable for Interrupt 8.12 +#define PIE_IER8_INTX13 0x1000U // Enable for Interrupt 8.13 +#define PIE_IER8_INTX14 0x2000U // Enable for Interrupt 8.14 +#define PIE_IER8_INTX15 0x4000U // Enable for Interrupt 8.15 +#define PIE_IER8_INTX16 0x8000U // Enable for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR8 register +// +//************************************************************************************************* +#define PIE_IFR8_INTX1 0x1U // Flag for Interrupt 8.1 +#define PIE_IFR8_INTX2 0x2U // Flag for Interrupt 8.2 +#define PIE_IFR8_INTX3 0x4U // Flag for Interrupt 8.3 +#define PIE_IFR8_INTX4 0x8U // Flag for Interrupt 8.4 +#define PIE_IFR8_INTX5 0x10U // Flag for Interrupt 8.5 +#define PIE_IFR8_INTX6 0x20U // Flag for Interrupt 8.6 +#define PIE_IFR8_INTX7 0x40U // Flag for Interrupt 8.7 +#define PIE_IFR8_INTX8 0x80U // Flag for Interrupt 8.8 +#define PIE_IFR8_INTX9 0x100U // Flag for Interrupt 8.9 +#define PIE_IFR8_INTX10 0x200U // Flag for Interrupt 8.10 +#define PIE_IFR8_INTX11 0x400U // Flag for Interrupt 8.11 +#define PIE_IFR8_INTX12 0x800U // Flag for Interrupt 8.12 +#define PIE_IFR8_INTX13 0x1000U // Flag for Interrupt 8.13 +#define PIE_IFR8_INTX14 0x2000U // Flag for Interrupt 8.14 +#define PIE_IFR8_INTX15 0x4000U // Flag for Interrupt 8.15 +#define PIE_IFR8_INTX16 0x8000U // Flag for Interrupt 8.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER9 register +// +//************************************************************************************************* +#define PIE_IER9_INTX1 0x1U // Enable for Interrupt 9.1 +#define PIE_IER9_INTX2 0x2U // Enable for Interrupt 9.2 +#define PIE_IER9_INTX3 0x4U // Enable for Interrupt 9.3 +#define PIE_IER9_INTX4 0x8U // Enable for Interrupt 9.4 +#define PIE_IER9_INTX5 0x10U // Enable for Interrupt 9.5 +#define PIE_IER9_INTX6 0x20U // Enable for Interrupt 9.6 +#define PIE_IER9_INTX7 0x40U // Enable for Interrupt 9.7 +#define PIE_IER9_INTX8 0x80U // Enable for Interrupt 9.8 +#define PIE_IER9_INTX9 0x100U // Enable for Interrupt 9.9 +#define PIE_IER9_INTX10 0x200U // Enable for Interrupt 9.10 +#define PIE_IER9_INTX11 0x400U // Enable for Interrupt 9.11 +#define PIE_IER9_INTX12 0x800U // Enable for Interrupt 9.12 +#define PIE_IER9_INTX13 0x1000U // Enable for Interrupt 9.13 +#define PIE_IER9_INTX14 0x2000U // Enable for Interrupt 9.14 +#define PIE_IER9_INTX15 0x4000U // Enable for Interrupt 9.15 +#define PIE_IER9_INTX16 0x8000U // Enable for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR9 register +// +//************************************************************************************************* +#define PIE_IFR9_INTX1 0x1U // Flag for Interrupt 9.1 +#define PIE_IFR9_INTX2 0x2U // Flag for Interrupt 9.2 +#define PIE_IFR9_INTX3 0x4U // Flag for Interrupt 9.3 +#define PIE_IFR9_INTX4 0x8U // Flag for Interrupt 9.4 +#define PIE_IFR9_INTX5 0x10U // Flag for Interrupt 9.5 +#define PIE_IFR9_INTX6 0x20U // Flag for Interrupt 9.6 +#define PIE_IFR9_INTX7 0x40U // Flag for Interrupt 9.7 +#define PIE_IFR9_INTX8 0x80U // Flag for Interrupt 9.8 +#define PIE_IFR9_INTX9 0x100U // Flag for Interrupt 9.9 +#define PIE_IFR9_INTX10 0x200U // Flag for Interrupt 9.10 +#define PIE_IFR9_INTX11 0x400U // Flag for Interrupt 9.11 +#define PIE_IFR9_INTX12 0x800U // Flag for Interrupt 9.12 +#define PIE_IFR9_INTX13 0x1000U // Flag for Interrupt 9.13 +#define PIE_IFR9_INTX14 0x2000U // Flag for Interrupt 9.14 +#define PIE_IFR9_INTX15 0x4000U // Flag for Interrupt 9.15 +#define PIE_IFR9_INTX16 0x8000U // Flag for Interrupt 9.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER10 register +// +//************************************************************************************************* +#define PIE_IER10_INTX1 0x1U // Enable for Interrupt 10.1 +#define PIE_IER10_INTX2 0x2U // Enable for Interrupt 10.2 +#define PIE_IER10_INTX3 0x4U // Enable for Interrupt 10.3 +#define PIE_IER10_INTX4 0x8U // Enable for Interrupt 10.4 +#define PIE_IER10_INTX5 0x10U // Enable for Interrupt 10.5 +#define PIE_IER10_INTX6 0x20U // Enable for Interrupt 10.6 +#define PIE_IER10_INTX7 0x40U // Enable for Interrupt 10.7 +#define PIE_IER10_INTX8 0x80U // Enable for Interrupt 10.8 +#define PIE_IER10_INTX9 0x100U // Enable for Interrupt 10.9 +#define PIE_IER10_INTX10 0x200U // Enable for Interrupt 10.10 +#define PIE_IER10_INTX11 0x400U // Enable for Interrupt 10.11 +#define PIE_IER10_INTX12 0x800U // Enable for Interrupt 10.12 +#define PIE_IER10_INTX13 0x1000U // Enable for Interrupt 10.13 +#define PIE_IER10_INTX14 0x2000U // Enable for Interrupt 10.14 +#define PIE_IER10_INTX15 0x4000U // Enable for Interrupt 10.15 +#define PIE_IER10_INTX16 0x8000U // Enable for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR10 register +// +//************************************************************************************************* +#define PIE_IFR10_INTX1 0x1U // Flag for Interrupt 10.1 +#define PIE_IFR10_INTX2 0x2U // Flag for Interrupt 10.2 +#define PIE_IFR10_INTX3 0x4U // Flag for Interrupt 10.3 +#define PIE_IFR10_INTX4 0x8U // Flag for Interrupt 10.4 +#define PIE_IFR10_INTX5 0x10U // Flag for Interrupt 10.5 +#define PIE_IFR10_INTX6 0x20U // Flag for Interrupt 10.6 +#define PIE_IFR10_INTX7 0x40U // Flag for Interrupt 10.7 +#define PIE_IFR10_INTX8 0x80U // Flag for Interrupt 10.8 +#define PIE_IFR10_INTX9 0x100U // Flag for Interrupt 10.9 +#define PIE_IFR10_INTX10 0x200U // Flag for Interrupt 10.10 +#define PIE_IFR10_INTX11 0x400U // Flag for Interrupt 10.11 +#define PIE_IFR10_INTX12 0x800U // Flag for Interrupt 10.12 +#define PIE_IFR10_INTX13 0x1000U // Flag for Interrupt 10.13 +#define PIE_IFR10_INTX14 0x2000U // Flag for Interrupt 10.14 +#define PIE_IFR10_INTX15 0x4000U // Flag for Interrupt 10.15 +#define PIE_IFR10_INTX16 0x8000U // Flag for Interrupt 10.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER11 register +// +//************************************************************************************************* +#define PIE_IER11_INTX1 0x1U // Enable for Interrupt 11.1 +#define PIE_IER11_INTX2 0x2U // Enable for Interrupt 11.2 +#define PIE_IER11_INTX3 0x4U // Enable for Interrupt 11.3 +#define PIE_IER11_INTX4 0x8U // Enable for Interrupt 11.4 +#define PIE_IER11_INTX5 0x10U // Enable for Interrupt 11.5 +#define PIE_IER11_INTX6 0x20U // Enable for Interrupt 11.6 +#define PIE_IER11_INTX7 0x40U // Enable for Interrupt 11.7 +#define PIE_IER11_INTX8 0x80U // Enable for Interrupt 11.8 +#define PIE_IER11_INTX9 0x100U // Enable for Interrupt 11.9 +#define PIE_IER11_INTX10 0x200U // Enable for Interrupt 11.10 +#define PIE_IER11_INTX11 0x400U // Enable for Interrupt 11.11 +#define PIE_IER11_INTX12 0x800U // Enable for Interrupt 11.12 +#define PIE_IER11_INTX13 0x1000U // Enable for Interrupt 11.13 +#define PIE_IER11_INTX14 0x2000U // Enable for Interrupt 11.14 +#define PIE_IER11_INTX15 0x4000U // Enable for Interrupt 11.15 +#define PIE_IER11_INTX16 0x8000U // Enable for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR11 register +// +//************************************************************************************************* +#define PIE_IFR11_INTX1 0x1U // Flag for Interrupt 11.1 +#define PIE_IFR11_INTX2 0x2U // Flag for Interrupt 11.2 +#define PIE_IFR11_INTX3 0x4U // Flag for Interrupt 11.3 +#define PIE_IFR11_INTX4 0x8U // Flag for Interrupt 11.4 +#define PIE_IFR11_INTX5 0x10U // Flag for Interrupt 11.5 +#define PIE_IFR11_INTX6 0x20U // Flag for Interrupt 11.6 +#define PIE_IFR11_INTX7 0x40U // Flag for Interrupt 11.7 +#define PIE_IFR11_INTX8 0x80U // Flag for Interrupt 11.8 +#define PIE_IFR11_INTX9 0x100U // Flag for Interrupt 11.9 +#define PIE_IFR11_INTX10 0x200U // Flag for Interrupt 11.10 +#define PIE_IFR11_INTX11 0x400U // Flag for Interrupt 11.11 +#define PIE_IFR11_INTX12 0x800U // Flag for Interrupt 11.12 +#define PIE_IFR11_INTX13 0x1000U // Flag for Interrupt 11.13 +#define PIE_IFR11_INTX14 0x2000U // Flag for Interrupt 11.14 +#define PIE_IFR11_INTX15 0x4000U // Flag for Interrupt 11.15 +#define PIE_IFR11_INTX16 0x8000U // Flag for Interrupt 11.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIER12 register +// +//************************************************************************************************* +#define PIE_IER12_INTX1 0x1U // Enable for Interrupt 12.1 +#define PIE_IER12_INTX2 0x2U // Enable for Interrupt 12.2 +#define PIE_IER12_INTX3 0x4U // Enable for Interrupt 12.3 +#define PIE_IER12_INTX4 0x8U // Enable for Interrupt 12.4 +#define PIE_IER12_INTX5 0x10U // Enable for Interrupt 12.5 +#define PIE_IER12_INTX6 0x20U // Enable for Interrupt 12.6 +#define PIE_IER12_INTX7 0x40U // Enable for Interrupt 12.7 +#define PIE_IER12_INTX8 0x80U // Enable for Interrupt 12.8 +#define PIE_IER12_INTX9 0x100U // Enable for Interrupt 12.9 +#define PIE_IER12_INTX10 0x200U // Enable for Interrupt 12.10 +#define PIE_IER12_INTX11 0x400U // Enable for Interrupt 12.11 +#define PIE_IER12_INTX12 0x800U // Enable for Interrupt 12.12 +#define PIE_IER12_INTX13 0x1000U // Enable for Interrupt 12.13 +#define PIE_IER12_INTX14 0x2000U // Enable for Interrupt 12.14 +#define PIE_IER12_INTX15 0x4000U // Enable for Interrupt 12.15 +#define PIE_IER12_INTX16 0x8000U // Enable for Interrupt 12.16 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEIFR12 register +// +//************************************************************************************************* +#define PIE_IFR12_INTX1 0x1U // Flag for Interrupt 12.1 +#define PIE_IFR12_INTX2 0x2U // Flag for Interrupt 12.2 +#define PIE_IFR12_INTX3 0x4U // Flag for Interrupt 12.3 +#define PIE_IFR12_INTX4 0x8U // Flag for Interrupt 12.4 +#define PIE_IFR12_INTX5 0x10U // Flag for Interrupt 12.5 +#define PIE_IFR12_INTX6 0x20U // Flag for Interrupt 12.6 +#define PIE_IFR12_INTX7 0x40U // Flag for Interrupt 12.7 +#define PIE_IFR12_INTX8 0x80U // Flag for Interrupt 12.8 +#define PIE_IFR12_INTX9 0x100U // Flag for Interrupt 12.9 +#define PIE_IFR12_INTX10 0x200U // Flag for Interrupt 12.10 +#define PIE_IFR12_INTX11 0x400U // Flag for Interrupt 12.11 +#define PIE_IFR12_INTX12 0x800U // Flag for Interrupt 12.12 +#define PIE_IFR12_INTX13 0x1000U // Flag for Interrupt 12.13 +#define PIE_IFR12_INTX14 0x2000U // Flag for Interrupt 12.14 +#define PIE_IFR12_INTX15 0x4000U // Flag for Interrupt 12.15 +#define PIE_IFR12_INTX16 0x8000U // Flag for Interrupt 12.16 + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_sci.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sci.h new file mode 100644 index 0000000..2fc9680 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sci.h @@ -0,0 +1,209 @@ +//########################################################################### +// +// FILE: hw_sci.h +// +// TITLE: Definitions for the SCI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SCI_H +#define HW_SCI_H + +//************************************************************************************************* +// +// The following are defines for the SCI register offsets +// +//************************************************************************************************* +#define SCI_O_CCR 0x0U // Communications control register +#define SCI_O_CTL1 0x1U // Control register 1 +#define SCI_O_HBAUD 0x2U // Baud rate (high) register +#define SCI_O_LBAUD 0x3U // Baud rate (low) register +#define SCI_O_CTL2 0x4U // Control register 2 +#define SCI_O_RXST 0x5U // Receive status register +#define SCI_O_RXEMU 0x6U // Receive emulation buffer register +#define SCI_O_RXBUF 0x7U // Receive data buffer +#define SCI_O_TXBUF 0x9U // Transmit data buffer +#define SCI_O_FFTX 0xAU // FIFO transmit register +#define SCI_O_FFRX 0xBU // FIFO receive register +#define SCI_O_FFCT 0xCU // FIFO control register +#define SCI_O_PRI 0xFU // SCI priority control + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICCR register +// +//************************************************************************************************* +#define SCI_CCR_SCICHAR_S 0U +#define SCI_CCR_SCICHAR_M 0x7U // Character length control +#define SCI_CCR_ADDRIDLE_MODE 0x8U // ADDR/IDLE Mode control +#define SCI_CCR_LOOPBKENA 0x10U // Loop Back enable +#define SCI_CCR_PARITYENA 0x20U // Parity enable +#define SCI_CCR_PARITY 0x40U // Even or Odd Parity +#define SCI_CCR_STOPBITS 0x80U // Number of Stop Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL1 register +// +//************************************************************************************************* +#define SCI_CTL1_RXENA 0x1U // SCI receiver enable +#define SCI_CTL1_TXENA 0x2U // SCI transmitter enable +#define SCI_CTL1_SLEEP 0x4U // SCI sleep +#define SCI_CTL1_TXWAKE 0x8U // Transmitter wakeup method +#define SCI_CTL1_SWRESET 0x20U // Software reset +#define SCI_CTL1_RXERRINTENA 0x40U // Receive error interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIHBAUD register +// +//************************************************************************************************* +#define SCI_HBAUD_BAUD_S 0U +#define SCI_HBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCIHBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCILBAUD register +// +//************************************************************************************************* +#define SCI_LBAUD_BAUD_S 0U +#define SCI_LBAUD_BAUD_M 0xFFU // SCI 16-bit baud selection Registers SCILBAUD + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCICTL2 register +// +//************************************************************************************************* +#define SCI_CTL2_TXINTENA 0x1U // Transmit __interrupt enable +#define SCI_CTL2_RXBKINTENA 0x2U // Receiver-buffer break enable +#define SCI_CTL2_TXEMPTY 0x40U // Transmitter empty flag +#define SCI_CTL2_TXRDY 0x80U // Transmitter ready flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXST register +// +//************************************************************************************************* +#define SCI_RXST_RXWAKE 0x2U // Receiver wakeup detect flag +#define SCI_RXST_PE 0x4U // Parity error flag +#define SCI_RXST_OE 0x8U // Overrun error flag +#define SCI_RXST_FE 0x10U // Framing error flag +#define SCI_RXST_BRKDT 0x20U // Break-detect flag +#define SCI_RXST_RXRDY 0x40U // Receiver ready flag +#define SCI_RXST_RXERROR 0x80U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXEMU register +// +//************************************************************************************************* +#define SCI_RXEMU_ERXDT_S 0U +#define SCI_RXEMU_ERXDT_M 0xFFU // Receive emulation buffer data + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIRXBUF register +// +//************************************************************************************************* +#define SCI_RXBUF_SAR_S 0U +#define SCI_RXBUF_SAR_M 0xFFU // Receive Character bits +#define SCI_RXBUF_SCIFFPE 0x4000U // Receiver error flag +#define SCI_RXBUF_SCIFFFE 0x8000U // Receiver error flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCITXBUF register +// +//************************************************************************************************* +#define SCI_TXBUF_TXDT_S 0U +#define SCI_TXBUF_TXDT_M 0xFFU // Transmit data buffer + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFTX register +// +//************************************************************************************************* +#define SCI_FFTX_TXFFIL_S 0U +#define SCI_FFTX_TXFFIL_M 0x1FU // Interrupt level +#define SCI_FFTX_TXFFIENA 0x20U // Interrupt enable +#define SCI_FFTX_TXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFTX_TXFFINT 0x80U // INT flag +#define SCI_FFTX_TXFFST_S 8U +#define SCI_FFTX_TXFFST_M 0x1F00U // FIFO status +#define SCI_FFTX_TXFIFORESET 0x2000U // FIFO reset +#define SCI_FFTX_SCIFFENA 0x4000U // Enhancement enable +#define SCI_FFTX_SCIRST 0x8000U // SCI reset rx/tx channels + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFRX register +// +//************************************************************************************************* +#define SCI_FFRX_RXFFIL_S 0U +#define SCI_FFRX_RXFFIL_M 0x1FU // Interrupt level +#define SCI_FFRX_RXFFIENA 0x20U // Interrupt enable +#define SCI_FFRX_RXFFINTCLR 0x40U // Clear INT flag +#define SCI_FFRX_RXFFINT 0x80U // INT flag +#define SCI_FFRX_RXFFST_S 8U +#define SCI_FFRX_RXFFST_M 0x1F00U // FIFO status +#define SCI_FFRX_RXFIFORESET 0x2000U // FIFO reset +#define SCI_FFRX_RXFFOVRCLR 0x4000U // Clear overflow +#define SCI_FFRX_RXFFOVF 0x8000U // FIFO overflow + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIFFCT register +// +//************************************************************************************************* +#define SCI_FFCT_FFTXDLY_S 0U +#define SCI_FFCT_FFTXDLY_M 0xFFU // FIFO transmit delay +#define SCI_FFCT_CDC 0x2000U // Auto baud mode enable +#define SCI_FFCT_ABDCLR 0x4000U // Auto baud clear +#define SCI_FFCT_ABD 0x8000U // Auto baud detect + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCIPRI register +// +//************************************************************************************************* +#define SCI_PRI_FREESOFT_S 3U +#define SCI_PRI_FREESOFT_M 0x18U // Emulation modes + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_sdfm.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sdfm.h new file mode 100644 index 0000000..d2ba146 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sdfm.h @@ -0,0 +1,431 @@ +//########################################################################### +// +// FILE: hw_sdfm.h +// +// TITLE: Definitions for the SDFM registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SDFM_H +#define HW_SDFM_H + +//************************************************************************************************* +// +// The following are defines for the SDFM register offsets +// +//************************************************************************************************* +#define SDFM_O_SDIFLG 0x0U // Interrupt Flag Register +#define SDFM_O_SDIFLGCLR 0x2U // Interrupt Flag Clear Register +#define SDFM_O_SDCTL 0x4U // SD Control Register +#define SDFM_O_SDMFILEN 0x6U // SD Master Filter Enable +#define SDFM_O_SDCTLPARM1 0x10U // Control Parameter Register for Ch1 +#define SDFM_O_SDDFPARM1 0x11U // Data Filter Parameter Register for Ch1 +#define SDFM_O_SDDPARM1 0x12U // Integer Parameter Register for Ch1 +#define SDFM_O_SDCMPH1 0x13U // High-level Threshold Register for Ch1 +#define SDFM_O_SDCMPL1 0x14U // Low-level Threshold Register for Ch1 +#define SDFM_O_SDCPARM1 0x15U // Comparator Parameter Register for Ch1 +#define SDFM_O_SDDATA1 0x16U // Filter Data Register (16 or 32bit) for Ch1 +#define SDFM_O_SDCTLPARM2 0x20U // Control Parameter Register for Ch2 +#define SDFM_O_SDDFPARM2 0x21U // Data Filter Parameter Register for Ch2 +#define SDFM_O_SDDPARM2 0x22U // Integer Parameter Register for Ch2 +#define SDFM_O_SDCMPH2 0x23U // High-level Threshold Register for Ch2 +#define SDFM_O_SDCMPL2 0x24U // Low-level Threshold Register for Ch2 +#define SDFM_O_SDCPARM2 0x25U // Comparator Parameter Register for Ch2 +#define SDFM_O_SDDATA2 0x26U // Filter Data Register (16 or 32bit) for Ch2 +#define SDFM_O_SDCTLPARM3 0x30U // Control Parameter Register for Ch3 +#define SDFM_O_SDDFPARM3 0x31U // Data Filter Parameter Register for Ch3 +#define SDFM_O_SDDPARM3 0x32U // Integer Parameter Register for Ch3 +#define SDFM_O_SDCMPH3 0x33U // High-level Threshold Register for Ch3 +#define SDFM_O_SDCMPL3 0x34U // Low-level Threshold Register for Ch3 +#define SDFM_O_SDCPARM3 0x35U // Comparator Parameter Register for Ch3 +#define SDFM_O_SDDATA3 0x36U // Filter Data Register (16 or 32bit) for Ch3 +#define SDFM_O_SDCTLPARM4 0x40U // Control Parameter Register for Ch4 +#define SDFM_O_SDDFPARM4 0x41U // Data Filter Parameter Register for Ch4 +#define SDFM_O_SDDPARM4 0x42U // Integer Parameter Register for Ch4 +#define SDFM_O_SDCMPH4 0x43U // High-level Threshold Register for Ch4 +#define SDFM_O_SDCMPL4 0x44U // Low-level Threshold Register for Ch4 +#define SDFM_O_SDCPARM4 0x45U // Comparator Parameter Register for Ch4 +#define SDFM_O_SDDATA4 0x46U // Filter Data Register (16 or 32bit) for Ch4 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLG register +// +//************************************************************************************************* +#define SDFM_SDIFLG_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLG_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLG_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLG_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLG_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLG_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLG_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLG_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLG_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLG_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLG_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLG_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLG_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLG_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDIFLGCLR register +// +//************************************************************************************************* +#define SDFM_SDIFLGCLR_IFH1 0x1U // High-level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFL1 0x2U // Low-Level Interrupt flag Filter 1 +#define SDFM_SDIFLGCLR_IFH2 0x4U // High-level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFL2 0x8U // Low-Level Interrupt flag Filter 2 +#define SDFM_SDIFLGCLR_IFH3 0x10U // High-level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFL3 0x20U // Low-Level Interrupt flag Filter 3 +#define SDFM_SDIFLGCLR_IFH4 0x40U // High-level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_IFL4 0x80U // Low-Level Interrupt flag Filter 4 +#define SDFM_SDIFLGCLR_MF1 0x100U // Modulator Failure for Filter 1 +#define SDFM_SDIFLGCLR_MF2 0x200U // Modulator Failure for Filter 2 +#define SDFM_SDIFLGCLR_MF3 0x400U // Modulator Failure for Filter 3 +#define SDFM_SDIFLGCLR_MF4 0x800U // Modulator Failure for Filter 4 +#define SDFM_SDIFLGCLR_AF1 0x1000U // Acknowledge flag for Filter 1 +#define SDFM_SDIFLGCLR_AF2 0x2000U // Acknowledge flag for Filter 2 +#define SDFM_SDIFLGCLR_AF3 0x4000U // Acknowledge flag for Filter 3 +#define SDFM_SDIFLGCLR_AF4 0x8000U // Acknowledge flag for Filter 4 +#define SDFM_SDIFLGCLR_MIF 0x80000000U // Master Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTL register +// +//************************************************************************************************* +#define SDFM_SDCTL_MIE 0x2000U // Master Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDMFILEN register +// +//************************************************************************************************* +#define SDFM_SDMFILEN_MFE 0x800U // Master Filter Enable. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM1_MOD_S 0U +#define SDFM_SDCTLPARM1_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM1_DOSR_S 0U +#define SDFM_SDDFPARM1_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM1_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM1_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM1_SST_S 10U +#define SDFM_SDDFPARM1_SST_M 0xC00U // Data Filter Structure (DataFast/1/2/3) +#define SDFM_SDDFPARM1_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM1 register +// +//************************************************************************************************* +#define SDFM_SDDPARM1_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM1_SH_S 11U +#define SDFM_SDDPARM1_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH1 register +// +//************************************************************************************************* +#define SDFM_SDCMPH1_HLT_S 0U +#define SDFM_SDCMPH1_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL1 register +// +//************************************************************************************************* +#define SDFM_SDCMPL1_LLT_S 0U +#define SDFM_SDCMPL1_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM1 register +// +//************************************************************************************************* +#define SDFM_SDCPARM1_COSR_S 0U +#define SDFM_SDCPARM1_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM1_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM1_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM1_CS1_CS0_S 7U +#define SDFM_SDCPARM1_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM1_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA1 register +// +//************************************************************************************************* +#define SDFM_SDDATA1_DATA16_S 0U +#define SDFM_SDDATA1_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA1_DATA32HI_S 16U +#define SDFM_SDDATA1_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM2_MOD_S 0U +#define SDFM_SDCTLPARM2_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM2_DOSR_S 0U +#define SDFM_SDDFPARM2_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM2_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM2_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM2_SST_S 10U +#define SDFM_SDDFPARM2_SST_M 0xC00U // Data Filter Structure (SincFast/1/2/3) +#define SDFM_SDDFPARM2_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM2 register +// +//************************************************************************************************* +#define SDFM_SDDPARM2_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM2_SH_S 11U +#define SDFM_SDDPARM2_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH2 register +// +//************************************************************************************************* +#define SDFM_SDCMPH2_HLT_S 0U +#define SDFM_SDCMPH2_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL2 register +// +//************************************************************************************************* +#define SDFM_SDCMPL2_LLT_S 0U +#define SDFM_SDCMPL2_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM2 register +// +//************************************************************************************************* +#define SDFM_SDCPARM2_COSR_S 0U +#define SDFM_SDCPARM2_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM2_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM2_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM2_CS1_CS0_S 7U +#define SDFM_SDCPARM2_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM2_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA2 register +// +//************************************************************************************************* +#define SDFM_SDDATA2_DATA16_S 0U +#define SDFM_SDDATA2_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA2_DATA32HI_S 16U +#define SDFM_SDDATA2_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM3_MOD_S 0U +#define SDFM_SDCTLPARM3_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM3_DOSR_S 0U +#define SDFM_SDDFPARM3_DOSR_M 0xFFU // Data Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM3_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM3_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM3_SST_S 10U +#define SDFM_SDDFPARM3_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM3_SDSYNCEN 0x1000U // Data FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM3 register +// +//************************************************************************************************* +#define SDFM_SDDPARM3_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM3_SH_S 11U +#define SDFM_SDDPARM3_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH3 register +// +//************************************************************************************************* +#define SDFM_SDCMPH3_HLT_S 0U +#define SDFM_SDCMPH3_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL3 register +// +//************************************************************************************************* +#define SDFM_SDCMPL3_LLT_S 0U +#define SDFM_SDCMPL3_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM3 register +// +//************************************************************************************************* +#define SDFM_SDCPARM3_COSR_S 0U +#define SDFM_SDCPARM3_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM3_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM3_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM3_CS1_CS0_S 7U +#define SDFM_SDCPARM3_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM3_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA3 register +// +//************************************************************************************************* +#define SDFM_SDDATA3_DATA16_S 0U +#define SDFM_SDDATA3_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA3_DATA32HI_S 16U +#define SDFM_SDDATA3_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCTLPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCTLPARM4_MOD_S 0U +#define SDFM_SDCTLPARM4_MOD_M 0x3U // Delta-Sigma Modulator mode + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDFPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDFPARM4_DOSR_S 0U +#define SDFM_SDDFPARM4_DOSR_M 0xFFU // SINC Filter Oversample Ratio= DOSR+1 +#define SDFM_SDDFPARM4_FEN 0x100U // Filter Enable +#define SDFM_SDDFPARM4_AE 0x200U // Ack Enable +#define SDFM_SDDFPARM4_SST_S 10U +#define SDFM_SDDFPARM4_SST_M 0xC00U // Data filter structure (SincFast/1/2/3) +#define SDFM_SDDFPARM4_SDSYNCEN 0x1000U // SINC FILTER Reset Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDPARM4 register +// +//************************************************************************************************* +#define SDFM_SDDPARM4_DR 0x400U // Data Representation (0/1 = 16/32b 2's complement) +#define SDFM_SDDPARM4_SH_S 11U +#define SDFM_SDDPARM4_SH_M 0xF800U // Shift Control (# bits to shift in 16b mode) + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPH4 register +// +//************************************************************************************************* +#define SDFM_SDCMPH4_HLT_S 0U +#define SDFM_SDCMPH4_HLT_M 0x7FFFU // High-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCMPL4 register +// +//************************************************************************************************* +#define SDFM_SDCMPL4_LLT_S 0U +#define SDFM_SDCMPL4_LLT_M 0x7FFFU // Low-level threshold for the comparator filter output. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDCPARM4 register +// +//************************************************************************************************* +#define SDFM_SDCPARM4_COSR_S 0U +#define SDFM_SDCPARM4_COSR_M 0x1FU // Comparator Oversample Ratio = COSR + 1 +#define SDFM_SDCPARM4_IEH 0x20U // High-level interrupt enable +#define SDFM_SDCPARM4_IEL 0x40U // Low-level interrupt enable +#define SDFM_SDCPARM4_CS1_CS0_S 7U +#define SDFM_SDCPARM4_CS1_CS0_M 0x180U // Comparator filter structure + // (Sincfast/Sinc1/Sinc2/Sinc3 +#define SDFM_SDCPARM4_MFIE 0x200U // Modulator Failure Interrupt enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SDDATA4 register +// +//************************************************************************************************* +#define SDFM_SDDATA4_DATA16_S 0U +#define SDFM_SDDATA4_DATA16_M 0xFFFFU // 16-bit Data in 16b mode, Lo-order 16b in 32b + // mode +#define SDFM_SDDATA4_DATA32HI_S 16U +#define SDFM_SDDATA4_DATA32HI_M 0xFFFF0000U // Hi-order 16b in 32b mode + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_spi.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_spi.h new file mode 100644 index 0000000..c4907aa --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_spi.h @@ -0,0 +1,157 @@ +//########################################################################### +// +// FILE: hw_spi.h +// +// TITLE: Definitions for the SPI registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SPI_H +#define HW_SPI_H + +//************************************************************************************************* +// +// The following are defines for the SPI register offsets +// +//************************************************************************************************* +#define SPI_O_CCR 0x0U // SPI Configuration Control Register +#define SPI_O_CTL 0x1U // SPI Operation Control Register +#define SPI_O_STS 0x2U // SPI Status Register +#define SPI_O_BRR 0x4U // SPI Baud Rate Register +#define SPI_O_RXEMU 0x6U // SPI Emulation Buffer Register +#define SPI_O_RXBUF 0x7U // SPI Serial Input Buffer Register +#define SPI_O_TXBUF 0x8U // SPI Serial Output Buffer Register +#define SPI_O_DAT 0x9U // SPI Serial Data Register +#define SPI_O_FFTX 0xAU // SPI FIFO Transmit Register +#define SPI_O_FFRX 0xBU // SPI FIFO Receive Register +#define SPI_O_FFCT 0xCU // SPI FIFO Control Register +#define SPI_O_PRI 0xFU // SPI Priority Control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICCR register +// +//************************************************************************************************* +#define SPI_CCR_SPICHAR_S 0U +#define SPI_CCR_SPICHAR_M 0xFU // Character Length Control +#define SPI_CCR_SPILBK 0x10U // SPI Loopback +#define SPI_CCR_HS_MODE 0x20U // High Speed mode control +#define SPI_CCR_CLKPOLARITY 0x40U // Shift Clock Polarity +#define SPI_CCR_SPISWRESET 0x80U // SPI Software Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPICTL register +// +//************************************************************************************************* +#define SPI_CTL_SPIINTENA 0x1U // SPI Interupt Enable +#define SPI_CTL_TALK 0x2U // Master/Slave Transmit Enable +#define SPI_CTL_MASTER_SLAVE 0x4U // SPI Network Mode Control +#define SPI_CTL_CLK_PHASE 0x8U // SPI Clock Phase +#define SPI_CTL_OVERRUNINTENA 0x10U // Overrun Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPISTS register +// +//************************************************************************************************* +#define SPI_STS_BUFFULL_FLAG 0x20U // SPI Transmit Buffer Full Flag +#define SPI_STS_INT_FLAG 0x40U // SPI Interrupt Flag +#define SPI_STS_OVERRUN_FLAG 0x80U // SPI Receiver Overrun Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIBRR register +// +//************************************************************************************************* +#define SPI_BRR_SPI_BIT_RATE_S 0U +#define SPI_BRR_SPI_BIT_RATE_M 0x7FU // SPI Bit Rate Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFTX register +// +//************************************************************************************************* +#define SPI_FFTX_TXFFIL_S 0U +#define SPI_FFTX_TXFFIL_M 0x1FU // TXFIFO Interrupt Level +#define SPI_FFTX_TXFFIENA 0x20U // TXFIFO Interrupt Enable +#define SPI_FFTX_TXFFINTCLR 0x40U // TXFIFO Interrupt Clear +#define SPI_FFTX_TXFFINT 0x80U // TXFIFO Interrupt Flag +#define SPI_FFTX_TXFFST_S 8U +#define SPI_FFTX_TXFFST_M 0x1F00U // Transmit FIFO Status +#define SPI_FFTX_TXFIFO 0x2000U // TXFIFO Reset +#define SPI_FFTX_SPIFFENA 0x4000U // FIFO Enhancements Enable +#define SPI_FFTX_SPIRST 0x8000U // SPI Reset + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFRX register +// +//************************************************************************************************* +#define SPI_FFRX_RXFFIL_S 0U +#define SPI_FFRX_RXFFIL_M 0x1FU // RXFIFO Interrupt Level +#define SPI_FFRX_RXFFIENA 0x20U // RXFIFO Interrupt Enable +#define SPI_FFRX_RXFFINTCLR 0x40U // RXFIFO Interupt Clear +#define SPI_FFRX_RXFFINT 0x80U // RXFIFO Interrupt Flag +#define SPI_FFRX_RXFFST_S 8U +#define SPI_FFRX_RXFFST_M 0x1F00U // Receive FIFO Status +#define SPI_FFRX_RXFIFORESET 0x2000U // RXFIFO Reset +#define SPI_FFRX_RXFFOVFCLR 0x4000U // Receive FIFO Overflow Clear +#define SPI_FFRX_RXFFOVF 0x8000U // Receive FIFO Overflow Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIFFCT register +// +//************************************************************************************************* +#define SPI_FFCT_TXDLY_S 0U +#define SPI_FFCT_TXDLY_M 0xFFU // FIFO Transmit Delay Bits + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SPIPRI register +// +//************************************************************************************************* +#define SPI_PRI_TRIWIRE 0x1U // 3-wire mode select bit +#define SPI_PRI_STEINV 0x2U // SPISTE inversion bit +#define SPI_PRI_FREE 0x10U // Free emulation mode +#define SPI_PRI_SOFT 0x20U // Soft emulation mode + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_sysctl.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sysctl.h new file mode 100644 index 0000000..11df8d3 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_sysctl.h @@ -0,0 +1,1428 @@ +//########################################################################### +// +// FILE: hw_sysctl.h +// +// TITLE: Definitions for the SYSCTL registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_SYSCTL_H +#define HW_SYSCTL_H + +//************************************************************************************************* +// +// The following are defines for the SYSCTL register offsets +// +//************************************************************************************************* +#define SYSCTL_O_DEVCFGLOCK1 0x0U // Lock bit for CPUSELx registers +#define SYSCTL_O_PARTIDL 0x8U // Lower 32-bit of Device PART Identification Number +#define SYSCTL_O_PARTIDH 0xAU // Upper 32-bit of Device PART Identification Number +#define SYSCTL_O_REVID 0xCU // Device Revision Number +#define SYSCTL_O_DC0 0x10U // Device Capability: Device Information +#define SYSCTL_O_DC1 0x12U // Device Capability: Processing Block Customization +#define SYSCTL_O_DC2 0x14U // Device Capability: EMIF Customization +#define SYSCTL_O_DC3 0x16U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC4 0x18U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC5 0x1AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC6 0x1CU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC7 0x1EU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC8 0x20U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC9 0x22U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC10 0x24U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC11 0x26U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC12 0x28U // Device Capability: Peripheral Customization +#define SYSCTL_O_DC13 0x2AU // Device Capability: Peripheral Customization +#define SYSCTL_O_DC14 0x2CU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC15 0x2EU // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC17 0x32U // Device Capability: Analog Modules Customization +#define SYSCTL_O_DC18 0x34U // Device Capability: CPU1 Lx SRAM Customization +#define SYSCTL_O_DC19 0x36U // Device Capability: CPU2 Lx SRAM Customization +#define SYSCTL_O_DC20 0x38U // Device Capability: GSx SRAM Customization +#define SYSCTL_O_PERCNF1 0x60U // Peripheral Configuration register +#define SYSCTL_O_FUSEERR 0x74U // e-Fuse error Status register +#define SYSCTL_O_SOFTPRES0 0x82U // Processing Block Software Reset register +#define SYSCTL_O_SOFTPRES1 0x84U // EMIF Software Reset register +#define SYSCTL_O_SOFTPRES2 0x86U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES3 0x88U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES4 0x8AU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES6 0x8EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES7 0x90U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES8 0x92U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES9 0x94U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES11 0x98U // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES13 0x9CU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES14 0x9EU // Peripheral Software Reset register +#define SYSCTL_O_SOFTPRES16 0xA2U // Peripheral Software Reset register +#define SYSCTL_O_CPUSEL0 0xD6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL1 0xD8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL2 0xDAU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL4 0xDEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL5 0xE0U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL6 0xE2U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL7 0xE4U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL8 0xE6U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL9 0xE8U // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL11 0xECU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL12 0xEEU // CPU Select register for common peripherals +#define SYSCTL_O_CPUSEL14 0xF2U // CPU Select register for common peripherals +#define SYSCTL_O_CPU2RESCTL 0x122U // CPU2 Reset Control Register +#define SYSCTL_O_RSTSTAT 0x124U // Reset Status register for secondary C28x CPUs +#define SYSCTL_O_LPMSTAT 0x125U // LPM Status Register for secondary C28x CPUs +#define SYSCTL_O_SYSDBGCTL 0x12CU // System Debug Control register + +#define SYSCTL_O_CLKSEM 0x0U // Clock Control Semaphore Register +#define SYSCTL_O_CLKCFGLOCK1 0x2U // Lock bit for CLKCFG registers +#define SYSCTL_O_CLKSRCCTL1 0x8U // Clock Source Control register-1 +#define SYSCTL_O_CLKSRCCTL2 0xAU // Clock Source Control register-2 +#define SYSCTL_O_CLKSRCCTL3 0xCU // Clock Source Control register-3 +#define SYSCTL_O_SYSPLLCTL1 0xEU // SYSPLL Control register-1 +#define SYSCTL_O_SYSPLLMULT 0x14U // SYSPLL Multiplier register +#define SYSCTL_O_SYSPLLSTS 0x16U // SYSPLL Status register +#define SYSCTL_O_AUXPLLCTL1 0x18U // AUXPLL Control register-1 +#define SYSCTL_O_AUXPLLMULT 0x1EU // AUXPLL Multiplier register +#define SYSCTL_O_AUXPLLSTS 0x20U // AUXPLL Status register +#define SYSCTL_O_SYSCLKDIVSEL 0x22U // System Clock Divider Select register +#define SYSCTL_O_AUXCLKDIVSEL 0x24U // Auxillary Clock Divider Select register +#define SYSCTL_O_PERCLKDIVSEL 0x26U // Peripheral Clock Divider Selet register +#define SYSCTL_O_XCLKOUTDIVSEL 0x28U // XCLKOUT Divider Select register +#define SYSCTL_O_LOSPCP 0x2CU // Low Speed Clock Source Prescalar +#define SYSCTL_O_MCDCR 0x2EU // Missing Clock Detect Control Register +#define SYSCTL_O_X1CNT 0x30U // 10-bit Counter on X1 Clock + +#define SYSCTL_O_CPUSYSLOCK1 0x0U // Lock bit for CPUSYS registers +#define SYSCTL_O_HIBBOOTMODE 0x6U // HIB Boot Mode Register +#define SYSCTL_O_IORESTOREADDR 0x8U // IORestore() routine Address Register +#define SYSCTL_O_PIEVERRADDR 0xAU // PIE Vector Fetch Error Address register +#define SYSCTL_O_PCLKCR0 0x22U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR1 0x24U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR2 0x26U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR3 0x28U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR4 0x2AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR6 0x2EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR7 0x30U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR8 0x32U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR9 0x34U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR10 0x36U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR11 0x38U // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR12 0x3AU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR13 0x3CU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR14 0x3EU // Peripheral Clock Gating Registers +#define SYSCTL_O_PCLKCR16 0x42U // Peripheral Clock Gating Registers +#define SYSCTL_O_SECMSEL 0x74U // Secondary Master Select register for common + // peripherals: Selects between CLA & DMA +#define SYSCTL_O_LPMCR 0x76U // LPM Control Register +#define SYSCTL_O_GPIOLPMSEL0 0x78U // GPIO LPM Wakeup select registers +#define SYSCTL_O_GPIOLPMSEL1 0x7AU // GPIO LPM Wakeup select registers +#define SYSCTL_O_TMR2CLKCTL 0x7CU // Timer2 Clock Measurement functionality control register +#define SYSCTL_O_RESC 0x80U // Reset Cause register + +#define SYSCTL_O_SCSR 0x22U // System Control & Status Register +#define SYSCTL_O_WDCNTR 0x23U // Watchdog Counter Register +#define SYSCTL_O_WDKEY 0x25U // Watchdog Reset Key Register +#define SYSCTL_O_WDCR 0x29U // Watchdog Control Register +#define SYSCTL_O_WDWCR 0x2AU // Watchdog Windowed Control Register + +#define SYSCTL_O_CLA1TASKSRCSELLOCK 0x0U // CLA1 Task Trigger Source Select Lock Register +#define SYSCTL_O_DMACHSRCSELLOCK 0x4U // DMA Channel Triger Source Select Lock Register +#define SYSCTL_O_CLA1TASKSRCSEL1 0x6U // CLA1 Task Trigger Source Select Register-1 +#define SYSCTL_O_CLA1TASKSRCSEL2 0x8U // CLA1 Task Trigger Source Select Register-2 +#define SYSCTL_O_DMACHSRCSEL1 0x16U // DMA Channel Trigger Source Select Register-1 +#define SYSCTL_O_DMACHSRCSEL2 0x18U // DMA Channel Trigger Source Select Register-2 + +#define SYSCTL_O_SYNCSELECT 0x0U // Sync Input and Output Select Register +#define SYSCTL_O_ADCSOCOUTSELECT 0x2U // External ADC (Off Chip) SOC Select Register +#define SYSCTL_O_SYNCSOCLOCK 0x4U // SYNCSEL and EXTADCSOC Select Lock register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DEVCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_DEVCFGLOCK1_CPUSEL0 0x1U // Lock bit for CPUSEL0 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL1 0x2U // Lock bit for CPUSEL1 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL2 0x4U // Lock bit for CPUSEL2 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL3 0x8U // Lock bit for CPUSEL3 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL4 0x10U // Lock bit for CPUSEL4 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL5 0x20U // Lock bit for CPUSEL5 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL6 0x40U // Lock bit for CPUSEL6 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL7 0x80U // Lock bit for CPUSEL7 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL8 0x100U // Lock bit for CPUSEL8 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL9 0x200U // Lock bit for CPUSEL9 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL10 0x400U // Lock bit for CPUSEL10 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL11 0x800U // Lock bit for CPUSEL11 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL12 0x1000U // Lock bit for CPUSEL12 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL13 0x2000U // Lock bit for CPUSEL13 register +#define SYSCTL_DEVCFGLOCK1_CPUSEL14 0x4000U // Lock bit for CPUSEL14 register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDL register +// +//************************************************************************************************* +#define SYSCTL_PARTIDL_QUAL_S 6U +#define SYSCTL_PARTIDL_QUAL_M 0xC0U // Qualification Status +#define SYSCTL_PARTIDL_PIN_COUNT_S 8U +#define SYSCTL_PARTIDL_PIN_COUNT_M 0x700U // Device Pin Count +#define SYSCTL_PARTIDL_INSTASPIN_S 13U +#define SYSCTL_PARTIDL_INSTASPIN_M 0x6000U // Motorware feature set +#define SYSCTL_PARTIDL_FLASH_SIZE_S 16U +#define SYSCTL_PARTIDL_FLASH_SIZE_M 0xFF0000U // Flash size in KB +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S 28U +#define SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M 0xF0000000U // Revision of the PARTID format + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PARTIDH register +// +//************************************************************************************************* +#define SYSCTL_PARTIDH_FAMILY_S 8U +#define SYSCTL_PARTIDH_FAMILY_M 0xFF00U // Device family +#define SYSCTL_PARTIDH_PARTNO_S 16U +#define SYSCTL_PARTIDH_PARTNO_M 0xFF0000U // Device part number +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_S 24U +#define SYSCTL_PARTIDH_DEVICE_CLASS_ID_M 0xFF000000U // Device class ID + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC0 register +// +//************************************************************************************************* +#define SYSCTL_DC0_SINGLE_CORE 0x1U // Single Core vs Dual Core + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC1 register +// +//************************************************************************************************* +#define SYSCTL_DC1_CPU1_FPU_TMU 0x1U // CPU1's FPU1+TMU1 +#define SYSCTL_DC1_CPU2_FPU_TMU 0x2U // CPU2's FPU2+TMU2 +#define SYSCTL_DC1_CPU1_VCU 0x4U // CPU1's VCU +#define SYSCTL_DC1_CPU2_VCU 0x8U // CPU2's VCU +#define SYSCTL_DC1_CPU1_CLA1 0x40U // CPU1.CLA1 +#define SYSCTL_DC1_CPU2_CLA1 0x100U // CPU2.CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC2 register +// +//************************************************************************************************* +#define SYSCTL_DC2_EMIF1 0x1U // EMIF1 +#define SYSCTL_DC2_EMIF2 0x2U // EMIF2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC3 register +// +//************************************************************************************************* +#define SYSCTL_DC3_EPWM1 0x1U // EPWM1 +#define SYSCTL_DC3_EPWM2 0x2U // EPWM2 +#define SYSCTL_DC3_EPWM3 0x4U // EPWM3 +#define SYSCTL_DC3_EPWM4 0x8U // EPWM4 +#define SYSCTL_DC3_EPWM5 0x10U // EPWM5 +#define SYSCTL_DC3_EPWM6 0x20U // EPWM6 +#define SYSCTL_DC3_EPWM7 0x40U // EPWM7 +#define SYSCTL_DC3_EPWM8 0x80U // EPWM8 +#define SYSCTL_DC3_EPWM9 0x100U // EPWM9 +#define SYSCTL_DC3_EPWM10 0x200U // EPWM10 +#define SYSCTL_DC3_EPWM11 0x400U // EPWM11 +#define SYSCTL_DC3_EPWM12 0x800U // EPWM12 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC4 register +// +//************************************************************************************************* +#define SYSCTL_DC4_ECAP1 0x1U // ECAP1 +#define SYSCTL_DC4_ECAP2 0x2U // ECAP2 +#define SYSCTL_DC4_ECAP3 0x4U // ECAP3 +#define SYSCTL_DC4_ECAP4 0x8U // ECAP4 +#define SYSCTL_DC4_ECAP5 0x10U // ECAP5 +#define SYSCTL_DC4_ECAP6 0x20U // ECAP6 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC5 register +// +//************************************************************************************************* +#define SYSCTL_DC5_EQEP1 0x1U // EQEP1 +#define SYSCTL_DC5_EQEP2 0x2U // EQEP2 +#define SYSCTL_DC5_EQEP3 0x4U // EQEP3 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC6 register +// +//************************************************************************************************* +#define SYSCTL_DC6_CLB1 0x1U // CLB1 +#define SYSCTL_DC6_CLB2 0x2U // CLB2 +#define SYSCTL_DC6_CLB3 0x4U // CLB3 +#define SYSCTL_DC6_CLB4 0x8U // CLB4 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC7 register +// +//************************************************************************************************* +#define SYSCTL_DC7_SD1 0x1U // SD1 +#define SYSCTL_DC7_SD2 0x2U // SD2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC8 register +// +//************************************************************************************************* +#define SYSCTL_DC8_SCI_A 0x1U // SCI_A +#define SYSCTL_DC8_SCI_B 0x2U // SCI_B +#define SYSCTL_DC8_SCI_C 0x4U // SCI_C +#define SYSCTL_DC8_SCI_D 0x8U // SCI_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC9 register +// +//************************************************************************************************* +#define SYSCTL_DC9_SPI_A 0x1U // SPI_A +#define SYSCTL_DC9_SPI_B 0x2U // SPI_B +#define SYSCTL_DC9_SPI_C 0x4U // SPI_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC10 register +// +//************************************************************************************************* +#define SYSCTL_DC10_I2C_A 0x1U // I2C_A +#define SYSCTL_DC10_I2C_B 0x2U // I2C_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC11 register +// +//************************************************************************************************* +#define SYSCTL_DC11_CAN_A 0x1U // CAN_A +#define SYSCTL_DC11_CAN_B 0x2U // CAN_B + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC12 register +// +//************************************************************************************************* +#define SYSCTL_DC12_MCBSP_A 0x1U // McBSP_A +#define SYSCTL_DC12_MCBSP_B 0x2U // McBSP_B +#define SYSCTL_DC12_USB_A_S 16U +#define SYSCTL_DC12_USB_A_M 0x30000U // Decides the capability of the USB_A Module + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC13 register +// +//************************************************************************************************* +#define SYSCTL_DC13_UPP_A 0x1U // uPP_A + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC14 register +// +//************************************************************************************************* +#define SYSCTL_DC14_ADC_A 0x1U // ADC_A +#define SYSCTL_DC14_ADC_B 0x2U // ADC_B +#define SYSCTL_DC14_ADC_C 0x4U // ADC_C +#define SYSCTL_DC14_ADC_D 0x8U // ADC_D + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC15 register +// +//************************************************************************************************* +#define SYSCTL_DC15_CMPSS1 0x1U // CMPSS1 +#define SYSCTL_DC15_CMPSS2 0x2U // CMPSS2 +#define SYSCTL_DC15_CMPSS3 0x4U // CMPSS3 +#define SYSCTL_DC15_CMPSS4 0x8U // CMPSS4 +#define SYSCTL_DC15_CMPSS5 0x10U // CMPSS5 +#define SYSCTL_DC15_CMPSS6 0x20U // CMPSS6 +#define SYSCTL_DC15_CMPSS7 0x40U // CMPSS7 +#define SYSCTL_DC15_CMPSS8 0x80U // CMPSS8 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC17 register +// +//************************************************************************************************* +#define SYSCTL_DC17_DAC_A 0x10000U // Buffered-DAC_A +#define SYSCTL_DC17_DAC_B 0x20000U // Buffered-DAC_B +#define SYSCTL_DC17_DAC_C 0x40000U // Buffered-DAC_C + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC18 register +// +//************************************************************************************************* +#define SYSCTL_DC18_LS0_1 0x1U // LS0_1 +#define SYSCTL_DC18_LS1_1 0x2U // LS1_1 +#define SYSCTL_DC18_LS2_1 0x4U // LS2_1 +#define SYSCTL_DC18_LS3_1 0x8U // LS3_1 +#define SYSCTL_DC18_LS4_1 0x10U // LS4_1 +#define SYSCTL_DC18_LS5_1 0x20U // LS5_1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC19 register +// +//************************************************************************************************* +#define SYSCTL_DC19_LS0_2 0x1U // LS0_2 +#define SYSCTL_DC19_LS1_2 0x2U // LS1_2 +#define SYSCTL_DC19_LS2_2 0x4U // LS2_2 +#define SYSCTL_DC19_LS3_2 0x8U // LS3_2 +#define SYSCTL_DC19_LS4_2 0x10U // LS4_2 +#define SYSCTL_DC19_LS5_2 0x20U // LS5_2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DC20 register +// +//************************************************************************************************* +#define SYSCTL_DC20_GS0 0x1U // GS0 +#define SYSCTL_DC20_GS1 0x2U // GS1 +#define SYSCTL_DC20_GS2 0x4U // GS2 +#define SYSCTL_DC20_GS3 0x8U // GS3 +#define SYSCTL_DC20_GS4 0x10U // GS4 +#define SYSCTL_DC20_GS5 0x20U // GS5 +#define SYSCTL_DC20_GS6 0x40U // GS6 +#define SYSCTL_DC20_GS7 0x80U // GS7 +#define SYSCTL_DC20_GS8 0x100U // GS8 +#define SYSCTL_DC20_GS9 0x200U // GS9 +#define SYSCTL_DC20_GS10 0x400U // GS10 +#define SYSCTL_DC20_GS11 0x800U // GS11 +#define SYSCTL_DC20_GS12 0x1000U // GS12 +#define SYSCTL_DC20_GS13 0x2000U // GS13 +#define SYSCTL_DC20_GS14 0x4000U // GS14 +#define SYSCTL_DC20_GS15 0x8000U // GS15 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCNF1 register +// +//************************************************************************************************* +#define SYSCTL_PERCNF1_ADC_A_MODE 0x1U // ADC_A mode setting bit +#define SYSCTL_PERCNF1_ADC_B_MODE 0x2U // ADC_B mode setting bit +#define SYSCTL_PERCNF1_ADC_C_MODE 0x4U // ADC_C mode setting bit +#define SYSCTL_PERCNF1_ADC_D_MODE 0x8U // ADC_D mode setting bit +#define SYSCTL_PERCNF1_USB_A_PHY 0x10000U // USB_A_PHY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the FUSEERR register +// +//************************************************************************************************* +#define SYSCTL_FUSEERR_ALERR_S 0U +#define SYSCTL_FUSEERR_ALERR_M 0x1FU // Efuse Autoload Error Status +#define SYSCTL_FUSEERR_ERR 0x20U // Efuse Self Test Error Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES0 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES0_CPU1_CLA1 0x1U // CPU1_CLA1 software reset bit +#define SYSCTL_SOFTPRES0_CPU2_CLA1 0x4U // CPU2_CLA1 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES1 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES1_EMIF1 0x1U // EMIF1 software reset bit +#define SYSCTL_SOFTPRES1_EMIF2 0x2U // EMIF2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES2 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES2_EPWM1 0x1U // EPWM1 software reset bit +#define SYSCTL_SOFTPRES2_EPWM2 0x2U // EPWM2 software reset bit +#define SYSCTL_SOFTPRES2_EPWM3 0x4U // EPWM3 software reset bit +#define SYSCTL_SOFTPRES2_EPWM4 0x8U // EPWM4 software reset bit +#define SYSCTL_SOFTPRES2_EPWM5 0x10U // EPWM5 software reset bit +#define SYSCTL_SOFTPRES2_EPWM6 0x20U // EPWM6 software reset bit +#define SYSCTL_SOFTPRES2_EPWM7 0x40U // EPWM7 software reset bit +#define SYSCTL_SOFTPRES2_EPWM8 0x80U // EPWM8 software reset bit +#define SYSCTL_SOFTPRES2_EPWM9 0x100U // EPWM9 software reset bit +#define SYSCTL_SOFTPRES2_EPWM10 0x200U // EPWM10 software reset bit +#define SYSCTL_SOFTPRES2_EPWM11 0x400U // EPWM11 software reset bit +#define SYSCTL_SOFTPRES2_EPWM12 0x800U // EPWM12 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES3 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES3_ECAP1 0x1U // ECAP1 software reset bit +#define SYSCTL_SOFTPRES3_ECAP2 0x2U // ECAP2 software reset bit +#define SYSCTL_SOFTPRES3_ECAP3 0x4U // ECAP3 software reset bit +#define SYSCTL_SOFTPRES3_ECAP4 0x8U // ECAP4 software reset bit +#define SYSCTL_SOFTPRES3_ECAP5 0x10U // ECAP5 software reset bit +#define SYSCTL_SOFTPRES3_ECAP6 0x20U // ECAP6 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES4 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES4_EQEP1 0x1U // EQEP1 software reset bit +#define SYSCTL_SOFTPRES4_EQEP2 0x2U // EQEP2 software reset bit +#define SYSCTL_SOFTPRES4_EQEP3 0x4U // EQEP3 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES6 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES6_SD1 0x1U // SD1 software reset bit +#define SYSCTL_SOFTPRES6_SD2 0x2U // SD2 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES7 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES7_SCI_A 0x1U // SCI_A software reset bit +#define SYSCTL_SOFTPRES7_SCI_B 0x2U // SCI_B software reset bit +#define SYSCTL_SOFTPRES7_SCI_C 0x4U // SCI_C software reset bit +#define SYSCTL_SOFTPRES7_SCI_D 0x8U // SCI_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES8 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES8_SPI_A 0x1U // SPI_A software reset bit +#define SYSCTL_SOFTPRES8_SPI_B 0x2U // SPI_B software reset bit +#define SYSCTL_SOFTPRES8_SPI_C 0x4U // SPI_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES9 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES9_I2C_A 0x1U // I2C_A software reset bit +#define SYSCTL_SOFTPRES9_I2C_B 0x2U // I2C_B software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES11 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES11_MCBSP_A 0x1U // McBSP_A software reset bit +#define SYSCTL_SOFTPRES11_MCBSP_B 0x2U // McBSP_B software reset bit +#define SYSCTL_SOFTPRES11_USB_A 0x10000U // USB_A software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES13 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES13_ADC_A 0x1U // ADC_A software reset bit +#define SYSCTL_SOFTPRES13_ADC_B 0x2U // ADC_B software reset bit +#define SYSCTL_SOFTPRES13_ADC_C 0x4U // ADC_C software reset bit +#define SYSCTL_SOFTPRES13_ADC_D 0x8U // ADC_D software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES14 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES14_CMPSS1 0x1U // CMPSS1 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS2 0x2U // CMPSS2 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS3 0x4U // CMPSS3 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS4 0x8U // CMPSS4 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS5 0x10U // CMPSS5 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS6 0x20U // CMPSS6 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS7 0x40U // CMPSS7 software reset bit +#define SYSCTL_SOFTPRES14_CMPSS8 0x80U // CMPSS8 software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SOFTPRES16 register +// +//************************************************************************************************* +#define SYSCTL_SOFTPRES16_DAC_A 0x10000U // Buffered_DAC_A software reset bit +#define SYSCTL_SOFTPRES16_DAC_B 0x20000U // Buffered_DAC_B software reset bit +#define SYSCTL_SOFTPRES16_DAC_C 0x40000U // Buffered_DAC_C software reset bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL0 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL0_EPWM1 0x1U // EPWM1 CPU select bit +#define SYSCTL_CPUSEL0_EPWM2 0x2U // EPWM2 CPU select bit +#define SYSCTL_CPUSEL0_EPWM3 0x4U // EPWM3 CPU select bit +#define SYSCTL_CPUSEL0_EPWM4 0x8U // EPWM4 CPU select bit +#define SYSCTL_CPUSEL0_EPWM5 0x10U // EPWM5 CPU select bit +#define SYSCTL_CPUSEL0_EPWM6 0x20U // EPWM6 CPU select bit +#define SYSCTL_CPUSEL0_EPWM7 0x40U // EPWM7 CPU select bit +#define SYSCTL_CPUSEL0_EPWM8 0x80U // EPWM8 CPU select bit +#define SYSCTL_CPUSEL0_EPWM9 0x100U // EPWM9 CPU select bit +#define SYSCTL_CPUSEL0_EPWM10 0x200U // EPWM10 CPU select bit +#define SYSCTL_CPUSEL0_EPWM11 0x400U // EPWM11 CPU select bit +#define SYSCTL_CPUSEL0_EPWM12 0x800U // EPWM12 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL1_ECAP1 0x1U // ECAP1 CPU select bit +#define SYSCTL_CPUSEL1_ECAP2 0x2U // ECAP2 CPU select bit +#define SYSCTL_CPUSEL1_ECAP3 0x4U // ECAP3 CPU select bit +#define SYSCTL_CPUSEL1_ECAP4 0x8U // ECAP4 CPU select bit +#define SYSCTL_CPUSEL1_ECAP5 0x10U // ECAP5 CPU select bit +#define SYSCTL_CPUSEL1_ECAP6 0x20U // ECAP6 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL2_EQEP1 0x1U // EQEP1 CPU select bit +#define SYSCTL_CPUSEL2_EQEP2 0x2U // EQEP2 CPU select bit +#define SYSCTL_CPUSEL2_EQEP3 0x4U // EQEP3 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL4 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL4_SD1 0x1U // SD1 CPU select bit +#define SYSCTL_CPUSEL4_SD2 0x2U // SD2 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL5 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL5_SCI_A 0x1U // SCI_A CPU select bit +#define SYSCTL_CPUSEL5_SCI_B 0x2U // SCI_B CPU select bit +#define SYSCTL_CPUSEL5_SCI_C 0x4U // SCI_C CPU select bit +#define SYSCTL_CPUSEL5_SCI_D 0x8U // SCI_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL6 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL6_SPI_A 0x1U // SPI_A CPU select bit +#define SYSCTL_CPUSEL6_SPI_B 0x2U // SPI_B CPU select bit +#define SYSCTL_CPUSEL6_SPI_C 0x4U // SPI_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL7 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL7_I2C_A 0x1U // I2C_A CPU select bit +#define SYSCTL_CPUSEL7_I2C_B 0x2U // I2C_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL8 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL8_CAN_A 0x1U // CAN_A CPU select bit +#define SYSCTL_CPUSEL8_CAN_B 0x2U // CAN_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL9 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL9_MCBSP_A 0x1U // McBSP_A CPU select bit +#define SYSCTL_CPUSEL9_MCBSP_B 0x2U // McBSP_B CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL11 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL11_ADC_A 0x1U // ADC_A CPU select bit +#define SYSCTL_CPUSEL11_ADC_B 0x2U // ADC_B CPU select bit +#define SYSCTL_CPUSEL11_ADC_C 0x4U // ADC_C CPU select bit +#define SYSCTL_CPUSEL11_ADC_D 0x8U // ADC_D CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL12 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL12_CMPSS1 0x1U // CMPSS1 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS2 0x2U // CMPSS2 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS3 0x4U // CMPSS3 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS4 0x8U // CMPSS4 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS5 0x10U // CMPSS5 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS6 0x20U // CMPSS6 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS7 0x40U // CMPSS7 CPU select bit +#define SYSCTL_CPUSEL12_CMPSS8 0x80U // CMPSS8 CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSEL14 register +// +//************************************************************************************************* +#define SYSCTL_CPUSEL14_DAC_A 0x10000U // Buffered_DAC_A CPU select bit +#define SYSCTL_CPUSEL14_DAC_B 0x20000U // Buffered_DAC_B CPU select bit +#define SYSCTL_CPUSEL14_DAC_C 0x40000U // Buffered_DAC_C CPU select bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPU2RESCTL register +// +//************************************************************************************************* +#define SYSCTL_CPU2RESCTL_RESET 0x1U // CPU2 Reset Control bit +#define SYSCTL_CPU2RESCTL_KEY_S 16U +#define SYSCTL_CPU2RESCTL_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RSTSTAT register +// +//************************************************************************************************* +#define SYSCTL_RSTSTAT_CPU2RES 0x1U // CPU2 Reset Status bit +#define SYSCTL_RSTSTAT_CPU2NMIWDRST 0x2U // Indicates whether a CPU2.NMIWD reset was issued + // to CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST0 0x4U // Indicates whether a HWBIST reset was issued to + // CPU2 +#define SYSCTL_RSTSTAT_CPU2HWBISTRST1 0x8U // Indicates whether a HWBIST reset was issued to + // CPU2 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMSTAT register +// +//************************************************************************************************* +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_S 0U +#define SYSCTL_LPMSTAT_CPU2LPMSTAT_M 0x3U // CPU2 LPM Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSDBGCTL register +// +//************************************************************************************************* +#define SYSCTL_SYSDBGCTL_BIT_0 0x1U // Used in PLL startup. Only reset by POR. + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSEM register +// +//************************************************************************************************* +#define SYSCTL_CLKSEM_SEM_S 0U +#define SYSCTL_CLKSEM_SEM_M 0x3U // Semaphore for CLKCFG Ownership by CPU1 or CPU2 +#define SYSCTL_CLKSEM_KEY_S 16U +#define SYSCTL_CLKSEM_KEY_M 0xFFFF0000U // Key Qualifier for writes to this register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKCFGLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL1 0x1U // Lock bit for CLKSRCCTL1 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL2 0x2U // Lock bit for CLKSRCCTL2 register +#define SYSCTL_CLKCFGLOCK1_CLKSRCCTL3 0x4U // Lock bit for CLKSRCCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL1 0x8U // Lock bit for SYSPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL2 0x10U // Lock bit for SYSPLLCTL2 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLCTL3 0x20U // Lock bit for SYSPLLCTL3 register +#define SYSCTL_CLKCFGLOCK1_SYSPLLMULT 0x40U // Lock bit for SYSPLLMULT register +#define SYSCTL_CLKCFGLOCK1_AUXPLLCTL1 0x80U // Lock bit for AUXPLLCTL1 register +#define SYSCTL_CLKCFGLOCK1_AUXPLLMULT 0x400U // Lock bit for AUXPLLMULT register +#define SYSCTL_CLKCFGLOCK1_SYSCLKDIVSEL 0x800U // Lock bit for SYSCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_AUXCLKDIVSEL 0x1000U // Lock bit for AUXCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_PERCLKDIVSEL 0x2000U // Lock bit for PERCLKDIVSEL register +#define SYSCTL_CLKCFGLOCK1_LOSPCP 0x8000U // Lock bit for LOSPCP register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL1 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M 0x3U // OSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL1_INTOSC2OFF 0x8U // Internal Oscillator 2 Off Bit +#define SYSCTL_CLKSRCCTL1_XTALOFF 0x10U // Crystal (External) Oscillator Off Bit +#define SYSCTL_CLKSRCCTL1_WDHALTI 0x20U // Watchdog HALT Mode Ignore Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL2 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S 0U +#define SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M 0x3U // AUXOSCCLK Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_S 2U +#define SYSCTL_CLKSRCCTL2_CANABCLKSEL_M 0xCU // CANA Bit Clock Source Select Bit +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_S 4U +#define SYSCTL_CLKSRCCTL2_CANBBCLKSEL_M 0x30U // CANB Bit Clock Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLKSRCCTL3 register +// +//************************************************************************************************* +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_S 0U +#define SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M 0x7U // XCLKOUT Source Select Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLCTL1_PLLEN 0x1U // SYSPLL enable/disable bit +#define SYSCTL_SYSPLLCTL1_PLLCLKEN 0x2U // SYSPLL bypassed or included in the PLLSYSCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLMULT_IMULT_S 0U +#define SYSCTL_SYSPLLMULT_IMULT_M 0x7FU // SYSPLL Integer Multiplier +#define SYSCTL_SYSPLLMULT_FMULT_S 8U +#define SYSCTL_SYSPLLMULT_FMULT_M 0x300U // SYSPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_SYSPLLSTS_LOCKS 0x1U // SYSPLL Lock Status Bit +#define SYSCTL_SYSPLLSTS_SLIPS 0x2U // SYSPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLCTL1 register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLCTL1_PLLEN 0x1U // AUXPLL enable/disable bit +#define SYSCTL_AUXPLLCTL1_PLLCLKEN 0x2U // AUXPLL bypassed or included in the AUXPLLCLK path + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLMULT register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLMULT_IMULT_S 0U +#define SYSCTL_AUXPLLMULT_IMULT_M 0x7FU // AUXPLL Integer Multiplier +#define SYSCTL_AUXPLLMULT_FMULT_S 8U +#define SYSCTL_AUXPLLMULT_FMULT_M 0x300U // AUXPLL Fractional Multiplier + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXPLLSTS register +// +//************************************************************************************************* +#define SYSCTL_AUXPLLSTS_LOCKS 0x1U // AUXPLL Lock Status Bit +#define SYSCTL_AUXPLLSTS_SLIPS 0x2U // AUXPLL Slip Status Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYSCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_S 0U +#define SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M 0x3FU // PLLSYSCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the AUXCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_S 0U +#define SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M 0x3U // AUXPLLCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCLKDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_S 0U +#define SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M 0x3U // EPWM Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV 0x10U // EMIF1 Clock Divide Select +#define SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV 0x40U // EMIF2 Clock Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XCLKOUTDIVSEL register +// +//************************************************************************************************* +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_S 0U +#define SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M 0x3U // XCLKOUT Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LOSPCP register +// +//************************************************************************************************* +#define SYSCTL_LOSPCP_LSPCLKDIV_S 0U +#define SYSCTL_LOSPCP_LSPCLKDIV_M 0x7U // LSPCLK Divide Select + +//************************************************************************************************* +// +// The following are defines for the bit fields in the MCDCR register +// +//************************************************************************************************* +#define SYSCTL_MCDCR_MCLKSTS 0x1U // Missing Clock Status Bit +#define SYSCTL_MCDCR_MCLKCLR 0x2U // Missing Clock Clear Bit +#define SYSCTL_MCDCR_MCLKOFF 0x4U // Missing Clock Detect Off Bit +#define SYSCTL_MCDCR_OSCOFF 0x8U // Oscillator Clock Off Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the X1CNT register +// +//************************************************************************************************* +#define SYSCTL_X1CNT_X1CNT_S 0U +#define SYSCTL_X1CNT_X1CNT_M 0x3FFU // X1 Counter + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CPUSYSLOCK1 register +// +//************************************************************************************************* +#define SYSCTL_CPUSYSLOCK1_HIBBOOTMODE 0x1U // Lock bit for HIBBOOTMODE register +#define SYSCTL_CPUSYSLOCK1_IORESTOREADDR 0x2U // Lock bit for IORESTOREADDR Register +#define SYSCTL_CPUSYSLOCK1_PIEVERRADDR 0x4U // Lock bit for PIEVERRADDR Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR0 0x8U // Lock bit for PCLKCR0 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR1 0x10U // Lock bit for PCLKCR1 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR2 0x20U // Lock bit for PCLKCR2 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR3 0x40U // Lock bit for PCLKCR3 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR4 0x80U // Lock bit for PCLKCR4 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR5 0x100U // Lock bit for PCLKCR5 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR6 0x200U // Lock bit for PCLKCR6 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR7 0x400U // Lock bit for PCLKCR7 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR8 0x800U // Lock bit for PCLKCR8 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR9 0x1000U // Lock bit for PCLKCR9 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR10 0x2000U // Lock bit for PCLKCR10 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR11 0x4000U // Lock bit for PCLKCR11 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR12 0x8000U // Lock bit for PCLKCR12 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR13 0x10000U // Lock bit for PCLKCR13 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR14 0x20000U // Lock bit for PCLKCR14 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR15 0x40000U // Lock bit for PCLKCR15 Register +#define SYSCTL_CPUSYSLOCK1_PCLKCR16 0x80000U // Lock bit for PCLKCR16 Register +#define SYSCTL_CPUSYSLOCK1_SECMSEL 0x100000U // Lock bit for SECMSEL Register +#define SYSCTL_CPUSYSLOCK1_LPMCR 0x200000U // Lock bit for LPMCR Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL0 0x400000U // Lock bit for GPIOLPMSEL0 Register +#define SYSCTL_CPUSYSLOCK1_GPIOLPMSEL1 0x800000U // Lock bit for GPIOLPMSEL1 Register + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IORESTOREADDR register +// +//************************************************************************************************* +#define SYSCTL_IORESTOREADDR_ADDR_S 0U +#define SYSCTL_IORESTOREADDR_ADDR_M 0x3FFFFFU // restoreIO() routine address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PIEVERRADDR register +// +//************************************************************************************************* +#define SYSCTL_PIEVERRADDR_ADDR_S 0U +#define SYSCTL_PIEVERRADDR_ADDR_M 0x3FFFFFU // PIE Vector Fetch Error Handler Routine Address + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR0 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR0_CLA1 0x1U // CLA1 Clock Enable Bit +#define SYSCTL_PCLKCR0_DMA 0x4U // DMA Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER0 0x8U // CPUTIMER0 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER1 0x10U // CPUTIMER1 Clock Enable bit +#define SYSCTL_PCLKCR0_CPUTIMER2 0x20U // CPUTIMER2 Clock Enable bit +#define SYSCTL_PCLKCR0_HRPWM 0x10000U // HRPWM Clock Enable Bit +#define SYSCTL_PCLKCR0_TBCLKSYNC 0x40000U // EPWM Time Base Clock sync +#define SYSCTL_PCLKCR0_GTBCLKSYNC 0x80000U // EPWM Time Base Clock Global sync + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR1 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR1_EMIF1 0x1U // EMIF1 Clock Enable bit +#define SYSCTL_PCLKCR1_EMIF2 0x2U // EMIF2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR2 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR2_EPWM1 0x1U // EPWM1 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM2 0x2U // EPWM2 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM3 0x4U // EPWM3 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM4 0x8U // EPWM4 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM5 0x10U // EPWM5 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM6 0x20U // EPWM6 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM7 0x40U // EPWM7 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM8 0x80U // EPWM8 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM9 0x100U // EPWM9 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM10 0x200U // EPWM10 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM11 0x400U // EPWM11 Clock Enable bit +#define SYSCTL_PCLKCR2_EPWM12 0x800U // EPWM12 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR3 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR3_ECAP1 0x1U // ECAP1 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP2 0x2U // ECAP2 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP3 0x4U // ECAP3 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP4 0x8U // ECAP4 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP5 0x10U // ECAP5 Clock Enable bit +#define SYSCTL_PCLKCR3_ECAP6 0x20U // ECAP6 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR4 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR4_EQEP1 0x1U // EQEP1 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP2 0x2U // EQEP2 Clock Enable bit +#define SYSCTL_PCLKCR4_EQEP3 0x4U // EQEP3 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR6 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR6_SD1 0x1U // SD1 Clock Enable bit +#define SYSCTL_PCLKCR6_SD2 0x2U // SD2 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR7 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR7_SCI_A 0x1U // SCI_A Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_B 0x2U // SCI_B Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_C 0x4U // SCI_C Clock Enable bit +#define SYSCTL_PCLKCR7_SCI_D 0x8U // SCI_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR8 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR8_SPI_A 0x1U // SPI_A Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_B 0x2U // SPI_B Clock Enable bit +#define SYSCTL_PCLKCR8_SPI_C 0x4U // SPI_C Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR9 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR9_I2C_A 0x1U // I2C_A Clock Enable bit +#define SYSCTL_PCLKCR9_I2C_B 0x2U // I2C_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR10 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR10_CAN_A 0x1U // CAN_A Clock Enable bit +#define SYSCTL_PCLKCR10_CAN_B 0x2U // CAN_B Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR11 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR11_MCBSP_A 0x1U // McBSP_A Clock Enable bit +#define SYSCTL_PCLKCR11_MCBSP_B 0x2U // McBSP_B Clock Enable bit +#define SYSCTL_PCLKCR11_USB_A 0x10000U // USB_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR12 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR12_UPP_A 0x1U // uPP_A Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR13 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR13_ADC_A 0x1U // ADC_A Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_B 0x2U // ADC_B Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_C 0x4U // ADC_C Clock Enable bit +#define SYSCTL_PCLKCR13_ADC_D 0x8U // ADC_D Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR14 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR14_CMPSS1 0x1U // CMPSS1 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS2 0x2U // CMPSS2 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS3 0x4U // CMPSS3 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS4 0x8U // CMPSS4 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS5 0x10U // CMPSS5 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS6 0x20U // CMPSS6 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS7 0x40U // CMPSS7 Clock Enable bit +#define SYSCTL_PCLKCR14_CMPSS8 0x80U // CMPSS8 Clock Enable bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PCLKCR16 register +// +//************************************************************************************************* +#define SYSCTL_PCLKCR16_DAC_A 0x10000U // Buffered_DAC_A Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_B 0x20000U // Buffered_DAC_B Clock Enable Bit +#define SYSCTL_PCLKCR16_DAC_C 0x40000U // Buffered_DAC_C Clock Enable Bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SECMSEL register +// +//************************************************************************************************* +#define SYSCTL_SECMSEL_PF1SEL_S 0U +#define SYSCTL_SECMSEL_PF1SEL_M 0x3U // Secondary Master Select for VBUS32_1 Bridge +#define SYSCTL_SECMSEL_PF2SEL_S 2U +#define SYSCTL_SECMSEL_PF2SEL_M 0xCU // Secondary Master Select for VBUS32_2 Bridge + +//************************************************************************************************* +// +// The following are defines for the bit fields in the LPMCR register +// +//************************************************************************************************* +#define SYSCTL_LPMCR_LPM_S 0U +#define SYSCTL_LPMCR_LPM_M 0x3U // Low Power Mode setting +#define SYSCTL_LPMCR_QUALSTDBY_S 2U +#define SYSCTL_LPMCR_QUALSTDBY_M 0xFCU // STANDBY Wakeup Pin Qualification Setting +#define SYSCTL_LPMCR_WDINTE 0x8000U // Enable for WDINT wakeup from STANDBY +#define SYSCTL_LPMCR_M0M1MODE_S 16U +#define SYSCTL_LPMCR_M0M1MODE_M 0x30000U // Configuration for M0 and M1 mode during HIB +#define SYSCTL_LPMCR_IOISODIS 0x80000000U // IO Isolation Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL0 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL0_GPIO0 0x1U // GPIO0 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO1 0x2U // GPIO1 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO2 0x4U // GPIO2 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO3 0x8U // GPIO3 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO4 0x10U // GPIO4 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO5 0x20U // GPIO5 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO6 0x40U // GPIO6 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO7 0x80U // GPIO7 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO8 0x100U // GPIO8 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO9 0x200U // GPIO9 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO10 0x400U // GPIO10 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO11 0x800U // GPIO11 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO12 0x1000U // GPIO12 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO13 0x2000U // GPIO13 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO14 0x4000U // GPIO14 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO15 0x8000U // GPIO15 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO16 0x10000U // GPIO16 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO17 0x20000U // GPIO17 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO18 0x40000U // GPIO18 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO19 0x80000U // GPIO19 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO20 0x100000U // GPIO20 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO21 0x200000U // GPIO21 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO22 0x400000U // GPIO22 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO23 0x800000U // GPIO23 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO24 0x1000000U // GPIO24 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO25 0x2000000U // GPIO25 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO26 0x4000000U // GPIO26 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO27 0x8000000U // GPIO27 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO28 0x10000000U // GPIO28 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO29 0x20000000U // GPIO29 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO30 0x40000000U // GPIO30 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL0_GPIO31 0x80000000U // GPIO31 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GPIOLPMSEL1 register +// +//************************************************************************************************* +#define SYSCTL_GPIOLPMSEL1_GPIO32 0x1U // GPIO32 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO33 0x2U // GPIO33 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO34 0x4U // GPIO34 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO35 0x8U // GPIO35 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO36 0x10U // GPIO36 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO37 0x20U // GPIO37 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO38 0x40U // GPIO38 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO39 0x80U // GPIO39 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO40 0x100U // GPIO40 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO41 0x200U // GPIO41 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO42 0x400U // GPIO42 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO43 0x800U // GPIO43 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO44 0x1000U // GPIO44 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO45 0x2000U // GPIO45 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO46 0x4000U // GPIO46 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO47 0x8000U // GPIO47 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO48 0x10000U // GPIO48 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO49 0x20000U // GPIO49 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO50 0x40000U // GPIO50 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO51 0x80000U // GPIO51 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO52 0x100000U // GPIO52 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO53 0x200000U // GPIO53 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO54 0x400000U // GPIO54 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO55 0x800000U // GPIO55 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO56 0x1000000U // GPIO56 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO57 0x2000000U // GPIO57 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO58 0x4000000U // GPIO58 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO59 0x8000000U // GPIO59 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO60 0x10000000U // GPIO60 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO61 0x20000000U // GPIO61 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO62 0x40000000U // GPIO62 Enable for LPM Wakeup +#define SYSCTL_GPIOLPMSEL1_GPIO63 0x80000000U // GPIO63 Enable for LPM Wakeup + +//************************************************************************************************* +// +// The following are defines for the bit fields in the TMR2CLKCTL register +// +//************************************************************************************************* +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S 0U +#define SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M 0x7U // CPU Timer 2 Clock Source Select Bit +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S 3U +#define SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M 0x38U // CPU Timer 2 Clock Pre-Scale Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RESC register +// +//************************************************************************************************* +#define SYSCTL_RESC_POR 0x1U // POR Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN 0x2U // XRSn Reset Cause Indication Bit +#define SYSCTL_RESC_WDRSN 0x4U // WDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_NMIWDRSN 0x8U // NMIWDRSn Reset Cause Indication Bit +#define SYSCTL_RESC_HWBISTN 0x20U // HWBISTn Reset Cause Indication Bit +#define SYSCTL_RESC_HIBRESETN 0x40U // HIBRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_SCCRESETN 0x100U // SCCRESETn Reset Cause Indication Bit +#define SYSCTL_RESC_XRSN_PIN_STATUS 0x40000000U // XRSN Pin Status +#define SYSCTL_RESC_TRSTN_PIN_STATUS 0x80000000U // TRSTn Status + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SCSR register +// +//************************************************************************************************* +#define SYSCTL_SCSR_WDOVERRIDE 0x1U // WD Override for WDDIS bit +#define SYSCTL_SCSR_WDENINT 0x2U // WD Interrupt Enable +#define SYSCTL_SCSR_WDINTS 0x4U // WD Interrupt Status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCNTR register +// +//************************************************************************************************* +#define SYSCTL_WDCNTR_WDCNTR_S 0U +#define SYSCTL_WDCNTR_WDCNTR_M 0xFFU // WD Counter + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDKEY register +// +//************************************************************************************************* +#define SYSCTL_WDKEY_WDKEY_S 0U +#define SYSCTL_WDKEY_WDKEY_M 0xFFU // WD KEY + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDCR register +// +//************************************************************************************************* +#define SYSCTL_WDCR_WDPS_S 0U +#define SYSCTL_WDCR_WDPS_M 0x7U // WD Clock Prescalar +#define SYSCTL_WDCR_WDCHK_S 3U +#define SYSCTL_WDCR_WDCHK_M 0x38U // WD Check Bits +#define SYSCTL_WDCR_WDDIS 0x40U // WD Disable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the WDWCR register +// +//************************************************************************************************* +#define SYSCTL_WDWCR_MIN_S 0U +#define SYSCTL_WDWCR_MIN_M 0xFFU // WD Min Threshold setting for Windowed Watchdog + // functionality +#define SYSCTL_WDWCR_FIRSTKEY 0x100U // First Key Detect Flag + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL1 0x1U // CLA1TASKSRCSEL1 Register Lock bit +#define SYSCTL_CLA1TASKSRCSELLOCK_CLA1TASKSRCSEL2 0x2U // CLA1TASKSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSELLOCK register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL1 0x1U // DMACHSRCSEL1 Register Lock bit +#define SYSCTL_DMACHSRCSELLOCK_DMACHSRCSEL2 0x2U // DMACHSRCSEL2 Register Lock bit + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_S 0U +#define SYSCTL_CLA1TASKSRCSEL1_TASK1_M 0xFFU // Selects the Trigger Source for TASK1 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_S 8U +#define SYSCTL_CLA1TASKSRCSEL1_TASK2_M 0xFF00U // Selects the Trigger Source for TASK2 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_S 16U +#define SYSCTL_CLA1TASKSRCSEL1_TASK3_M 0xFF0000U // Selects the Trigger Source for TASK3 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_S 24U +#define SYSCTL_CLA1TASKSRCSEL1_TASK4_M 0xFF000000U // Selects the Trigger Source for TASK4 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CLA1TASKSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_S 0U +#define SYSCTL_CLA1TASKSRCSEL2_TASK5_M 0xFFU // Selects the Trigger Source for TASK5 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_S 8U +#define SYSCTL_CLA1TASKSRCSEL2_TASK6_M 0xFF00U // Selects the Trigger Source for TASK6 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_S 16U +#define SYSCTL_CLA1TASKSRCSEL2_TASK7_M 0xFF0000U // Selects the Trigger Source for TASK7 of + // CLA1 +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_S 24U +#define SYSCTL_CLA1TASKSRCSEL2_TASK8_M 0xFF000000U // Selects the Trigger Source for TASK8 of + // CLA1 + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL1 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL1_CH1_S 0U +#define SYSCTL_DMACHSRCSEL1_CH1_M 0xFFU // Selects the Trigger and Sync Source CH1 of DMA +#define SYSCTL_DMACHSRCSEL1_CH2_S 8U +#define SYSCTL_DMACHSRCSEL1_CH2_M 0xFF00U // Selects the Trigger and Sync Source CH2 of DMA +#define SYSCTL_DMACHSRCSEL1_CH3_S 16U +#define SYSCTL_DMACHSRCSEL1_CH3_M 0xFF0000U // Selects the Trigger and Sync Source CH3 of DMA +#define SYSCTL_DMACHSRCSEL1_CH4_S 24U +#define SYSCTL_DMACHSRCSEL1_CH4_M 0xFF000000U // Selects the Trigger and Sync Source CH4 of DMA + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DMACHSRCSEL2 register +// +//************************************************************************************************* +#define SYSCTL_DMACHSRCSEL2_CH5_S 0U +#define SYSCTL_DMACHSRCSEL2_CH5_M 0xFFU // Selects the Trigger and Sync Source CH5 of DMA +#define SYSCTL_DMACHSRCSEL2_CH6_S 8U +#define SYSCTL_DMACHSRCSEL2_CH6_M 0xFF00U // Selects the Trigger and Sync Source CH6 of DMA + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSELECT register +// +//************************************************************************************************* +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_S 0U +#define SYSCTL_SYNCSELECT_EPWM4SYNCIN_M 0x7U // Selects Sync Input Source for EPWM4 +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_S 3U +#define SYSCTL_SYNCSELECT_EPWM7SYNCIN_M 0x38U // Selects Sync Input Source for EPWM7 +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_S 6U +#define SYSCTL_SYNCSELECT_EPWM10SYNCIN_M 0x1C0U // Selects Sync Input Source for EPWM10 +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_S 9U +#define SYSCTL_SYNCSELECT_ECAP1SYNCIN_M 0xE00U // Selects Sync Input Source for ECAP1 +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_S 12U +#define SYSCTL_SYNCSELECT_ECAP4SYNCIN_M 0x7000U // Selects Sync Input Source for ECAP4 +#define SYSCTL_SYNCSELECT_SYNCOUT_S 27U +#define SYSCTL_SYNCSELECT_SYNCOUT_M 0x18000000U // Select Syncout Source + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ADCSOCOUTSELECT register +// +//************************************************************************************************* +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCAEN 0x1U // PWM1SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCAEN 0x2U // PWM2SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCAEN 0x4U // PWM3SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCAEN 0x8U // PWM4SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCAEN 0x10U // PWM5SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCAEN 0x20U // PWM6SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCAEN 0x40U // PWM7SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCAEN 0x80U // PWM8SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCAEN 0x100U // PWM9SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCAEN 0x200U // PWM10SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCAEN 0x400U // PWM11SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCAEN 0x800U // PWM12SOCAEN Enable for ADCSOCAO +#define SYSCTL_ADCSOCOUTSELECT_PWM1SOCBEN 0x10000U // PWM1SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM2SOCBEN 0x20000U // PWM2SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM3SOCBEN 0x40000U // PWM3SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM4SOCBEN 0x80000U // PWM4SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM5SOCBEN 0x100000U // PWM5SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM6SOCBEN 0x200000U // PWM6SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM7SOCBEN 0x400000U // PWM7SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM8SOCBEN 0x800000U // PWM8SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM9SOCBEN 0x1000000U // PWM9SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM10SOCBEN 0x2000000U // PWM10SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM11SOCBEN 0x4000000U // PWM11SOCBEN Enable for ADCSOCBO +#define SYSCTL_ADCSOCOUTSELECT_PWM12SOCBEN 0x8000000U // PWM12SOCBEN Enable for ADCSOCBO + +//************************************************************************************************* +// +// The following are defines for the bit fields in the SYNCSOCLOCK register +// +//************************************************************************************************* +#define SYSCTL_SYNCSOCLOCK_SYNCSELECT 0x1U // SYNCSEL Register Lock bit +#define SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT 0x2U // ADCSOCOUTSELECT Register Lock bit + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_types.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_types.h new file mode 100644 index 0000000..8c1b32d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_types.h @@ -0,0 +1,166 @@ +//########################################################################### +// +// FILE: hw_types.h +// +// TITLE: Type definitions used in driverlib functions. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_TYPES_H +#define HW_TYPES_H + +//***************************************************************************** +// +// Macros for hardware access +// +//***************************************************************************** +#if defined(__TMS320C28XX_CLA__) + #define HWREG(x) \ + (*((volatile uint32_t *)((uintptr_t)(x)))) + #define HWREGH(x) \ + (*((volatile uint16_t *)((uintptr_t)(x)))) +#else + #define HWREG(x) \ + (*((volatile uint32_t *)(x))) + #define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#endif + +#define HWREG_BP(x) \ + __byte_peripheral_32((uint32_t *)(x)) +#define HWREGB(x) \ + __byte((int *)(x),0) + +//***************************************************************************** +// +// SUCCESS and FAILURE for API return value +// +//***************************************************************************** +#define STATUS_S_SUCCESS (0) +#define STATUS_E_FAILURE (-1) + +//***************************************************************************** +// +// Definition of 8 bit types for USB Driver code to maintain portability +// between byte and word addressable cores of C2000 Devices. +// +//***************************************************************************** +typedef uint16_t uint8_t; +typedef int16_t int8_t; + +//**************************************************************************** +// +// For checking NULL pointers +// +//**************************************************************************** +#ifndef NULL +#define NULL ((void *)0x0) +#endif + +//***************************************************************************** +// +// 32-bit & 64-bit float type +// +//***************************************************************************** +#ifndef C2000_IEEE754_TYPES +#define C2000_IEEE754_TYPES +#ifdef __TI_EABI__ +typedef float float32_t; +typedef double float64_t; +#else // TI COFF +typedef float float32_t; +typedef long double float64_t; +#endif // __TI_EABI__ +#endif // C2000_IEEE754_TYPES + + +//***************************************************************************** +// +// Emulated Bitbanded write +// +//***************************************************************************** +#define HWREGBITW(address, mask, value) \ + (*(volatile uint32_t *)(address)) = \ + ((*(volatile uint32_t *)(address)) & ~((uint32_t)1 << mask)) \ + | ((uint32_t)value << mask) + +#define HWREGBITHW(address, mask, value) \ + (*(volatile uint16_t *)(address)) = \ + ((*(volatile uint16_t *)(address)) & ~((uint16_t)1 << mask)) \ + | ((uint16_t)value << mask) + +//***************************************************************************** +// +// Emulated Bitbanded read +// +//***************************************************************************** +#define HWREGBITR(address, mask) \ + (((*(volatile uint32_t *)(address)) & ((uint32_t)1 << mask)) >> mask) + +#define HWREGBITHR(address, mask) \ + (((*(volatile uint16_t *)(address)) & ((uint16_t)1 << mask)) >> mask) + +//***************************************************************************** +// +// Extern compiler intrinsic prototypes. See compiler User's Guide for details. +// These are provided to satisfy static analysis tools. The #ifndef is required +// because the '&' is for a C++-style reference, and although it is the correct +// prototype, it will not build in C code. +// +//***************************************************************************** +#if(defined(__TMS320C28XX__) || defined(__TMS320C28XX_CLA__)) +#else +extern int16_t &__byte(int16_t *array, uint16_t byte_index); +extern uint32_t &__byte_peripheral_32(uint32_t *x); +#endif + +// +// C++ Bool Compatibility +// +#if defined(__cplusplus) +typedef bool _Bool; +#endif + +/* To fix Misra-C errors */ +#ifndef TRUE +#define TRUE 1 +#endif +#ifndef FALSE +#define FALSE 0 +#endif + +#endif // HW_TYPES_H diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_upp.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_upp.h new file mode 100644 index 0000000..9f73e9b --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_upp.h @@ -0,0 +1,306 @@ +//########################################################################### +// +// FILE: hw_upp.h +// +// TITLE: Definitions for the UPP registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_UPP_H +#define HW_UPP_H + +//************************************************************************************************* +// +// The following are defines for the UPP register offsets +// +//************************************************************************************************* +#define UPP_O_PID 0x0U // Peripheral ID Register +#define UPP_O_PERCTL 0x2U // Peripheral Control Register +#define UPP_O_CHCTL 0x8U // General Control Register +#define UPP_O_IFCFG 0xAU // Interface Configuration Register +#define UPP_O_IFIVAL 0xCU // Interface Idle Value Register +#define UPP_O_THCFG 0xEU // Threshold Configuration Register +#define UPP_O_RAWINTST 0x10U // Raw Interrupt Status Register +#define UPP_O_ENINTST 0x12U // Enable Interrupt Status Register +#define UPP_O_INTENSET 0x14U // Interrupt Enable Set Register +#define UPP_O_INTENCLR 0x16U // Interrupt Enable Clear Register +#define UPP_O_CHIDESC0 0x20U // DMA Channel I Descriptor 0 Register +#define UPP_O_CHIDESC1 0x22U // DMA Channel I Descriptor 1 Register +#define UPP_O_CHIDESC2 0x24U // DMA Channel I Descriptor 2 Register +#define UPP_O_CHIST0 0x28U // DMA Channel I Status 0 Register +#define UPP_O_CHIST1 0x2AU // DMA Channel I Status 1 Register +#define UPP_O_CHIST2 0x2CU // DMA Channel I Status 2 Register +#define UPP_O_CHQDESC0 0x30U // DMA Channel Q Descriptor 0 Register +#define UPP_O_CHQDESC1 0x32U // DMA Channel Q Descriptor 1 Register +#define UPP_O_CHQDESC2 0x34U // DMA Channel Q Descriptor 2 Register +#define UPP_O_CHQST0 0x38U // DMA Channel Q Status 0 Register +#define UPP_O_CHQST1 0x3AU // DMA Channel Q Status 1 Register +#define UPP_O_CHQST2 0x3CU // DMA Channel Q Status 2 Register +#define UPP_O_GINTEN 0x40U // Global Peripheral Interrupt Enable Register +#define UPP_O_GINTFLG 0x42U // Global Peripheral Interrupt Flag Register +#define UPP_O_GINTCLR 0x44U // Global Peripheral Interrupt Clear Register +#define UPP_O_DLYCTL 0x46U // IO clock data skew control Register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the PERCTL register +// +//************************************************************************************************* +#define UPP_PERCTL_FREE 0x1U // Emulation control. +#define UPP_PERCTL_SOFT 0x2U // Emulation control. +#define UPP_PERCTL_RTEMU 0x4U // Realtime emulation control. +#define UPP_PERCTL_PEREN 0x8U // Peripheral Enable +#define UPP_PERCTL_SOFTRST 0x10U // Software Reset +#define UPP_PERCTL_DMAST 0x80U // DMA Burst transaction status + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHCTL register +// +//************************************************************************************************* +#define UPP_CHCTL_MODE_S 0U +#define UPP_CHCTL_MODE_M 0x3U // Operating mode +#define UPP_CHCTL_SDRTXILA 0x8U // SDR TX Interleve mode +#define UPP_CHCTL_DEMUXA 0x10U // DDR de-multiplexing mode +#define UPP_CHCTL_DRA 0x10000U // Data rate + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFCFG register +// +//************************************************************************************************* +#define UPP_IFCFG_STARTPOLA 0x1U // Polarity of START(SELECT) signal +#define UPP_IFCFG_ENAPOLA 0x2U // Polarity of ENABLE(WRITE) signal +#define UPP_IFCFG_WAITPOLA 0x4U // Polarity of WAIT signal. +#define UPP_IFCFG_STARTA 0x8U // Enable Usage of START (SELECT) signal +#define UPP_IFCFG_ENAA 0x10U // Enable Usage of ENABLE (WRITE) signal +#define UPP_IFCFG_WAITA 0x20U // Enable Usage of WAIT signal +#define UPP_IFCFG_CLKDIVA_S 8U +#define UPP_IFCFG_CLKDIVA_M 0xF00U // Clock divider for tx mode +#define UPP_IFCFG_CLKINVA 0x1000U // Clock inversion +#define UPP_IFCFG_TRISENA 0x2000U // Pin Tri-state Control + +//************************************************************************************************* +// +// The following are defines for the bit fields in the IFIVAL register +// +//************************************************************************************************* +#define UPP_IFIVAL_VALA_S 0U +#define UPP_IFIVAL_VALA_M 0x1FFU // Idle Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the THCFG register +// +//************************************************************************************************* +#define UPP_THCFG_RDSIZEI_S 0U +#define UPP_THCFG_RDSIZEI_M 0x3U // DMA Read Threshold for DMA Channel I +#define UPP_THCFG_RDSIZEQ_S 8U +#define UPP_THCFG_RDSIZEQ_M 0x300U // DMA Read Threshold for DMA Channel Q +#define UPP_THCFG_TXSIZEA_S 16U +#define UPP_THCFG_TXSIZEA_M 0x30000U // I/O Transmit Threshold Value + +//************************************************************************************************* +// +// The following are defines for the bit fields in the RAWINTST register +// +//************************************************************************************************* +#define UPP_RAWINTST_DPEI 0x1U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEI 0x2U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWI 0x8U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLI 0x10U // Interrupt raw status for end-of-line condition +#define UPP_RAWINTST_DPEQ 0x100U // Interrupt raw status for DMA programming error +#define UPP_RAWINTST_UOEQ 0x200U // Interrupt raw status for DMA under-run or over-run +#define UPP_RAWINTST_EOWQ 0x800U // Interrupt raw status for end-of window condition +#define UPP_RAWINTST_EOLQ 0x1000U // Interrupt raw status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the ENINTST register +// +//************************************************************************************************* +#define UPP_ENINTST_DPEI 0x1U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEI 0x2U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWI 0x8U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLI 0x10U // Interrupt enable status for end-of-line condition +#define UPP_ENINTST_DPEQ 0x100U // Interrupt enable status for DMA programming error +#define UPP_ENINTST_UOEQ 0x200U // Interrupt enable status for DMA under-run or over-run +#define UPP_ENINTST_EOWQ 0x800U // Interrupt enable status for end-of window condition +#define UPP_ENINTST_EOLQ 0x1000U // Interrupt enable status for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENSET register +// +//************************************************************************************************* +#define UPP_INTENSET_DPEI 0x1U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEI 0x2U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWI 0x8U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLI 0x10U // Interrupt enable for end-of-line condition +#define UPP_INTENSET_DPEQ 0x100U // Interrupt enable for DMA programming error +#define UPP_INTENSET_UOEQ 0x200U // Interrupt enable for DMA under-run or over-run +#define UPP_INTENSET_EOWQ 0x800U // Interrupt enable for end-of window condition +#define UPP_INTENSET_EOLQ 0x1000U // Interrupt enable for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the INTENCLR register +// +//************************************************************************************************* +#define UPP_INTENCLR_DPEI 0x1U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEI 0x2U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWI 0x8U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLI 0x10U // Interrupt clear for end-of-line condition +#define UPP_INTENCLR_DPEQ 0x100U // Interrupt clear for DMA programming error +#define UPP_INTENCLR_UOEQ 0x200U // Interrupt clear for DMA under-run or over-run +#define UPP_INTENCLR_EOWQ 0x800U // Interrupt clear for end-of window condition +#define UPP_INTENCLR_EOLQ 0x1000U // Interrupt clear for end-of-line condition + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC1 register +// +//************************************************************************************************* +#define UPP_CHIDESC1_BCNT_S 0U +#define UPP_CHIDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel I + // transfer. +#define UPP_CHIDESC1_LCNT_S 16U +#define UPP_CHIDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel I + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIDESC2 register +// +//************************************************************************************************* +#define UPP_CHIDESC2_LOFFSET_S 0U +#define UPP_CHIDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST1 register +// +//************************************************************************************************* +#define UPP_CHIST1_BCNT_S 0U +#define UPP_CHIST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHIST1_LCNT_S 16U +#define UPP_CHIST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHIST2 register +// +//************************************************************************************************* +#define UPP_CHIST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHIST2_PEND 0x2U // Status of DMA. +#define UPP_CHIST2_WM_S 4U +#define UPP_CHIST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel I tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC1 register +// +//************************************************************************************************* +#define UPP_CHQDESC1_BCNT_S 0U +#define UPP_CHQDESC1_BCNT_M 0xFFFFU // Number of bytes in a line for DMA Channel Q + // transfer. +#define UPP_CHQDESC1_LCNT_S 16U +#define UPP_CHQDESC1_LCNT_M 0xFFFF0000U // Number of lines in a window for DMA Channel Q + // transfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQDESC2 register +// +//************************************************************************************************* +#define UPP_CHQDESC2_LOFFSET_S 0U +#define UPP_CHQDESC2_LOFFSET_M 0xFFFFU // Current start address to next start address offset. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST1 register +// +//************************************************************************************************* +#define UPP_CHQST1_BCNT_S 0U +#define UPP_CHQST1_BCNT_M 0xFFFFU // Current byte number. +#define UPP_CHQST1_LCNT_S 16U +#define UPP_CHQST1_LCNT_M 0xFFFF0000U // Current line number. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the CHQST2 register +// +//************************************************************************************************* +#define UPP_CHQST2_ACT 0x1U // Status of DMA descriptor. +#define UPP_CHQST2_PEND 0x2U // Status of DMA. +#define UPP_CHQST2_WM_S 4U +#define UPP_CHQST2_WM_M 0xF0U // Watermark for FIFO block count for DMA Channel Q tranfer. + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTEN register +// +//************************************************************************************************* +#define UPP_GINTEN_GINTEN 0x1U // Global Interrupt Enable + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTFLG register +// +//************************************************************************************************* +#define UPP_GINTFLG_GINTFLG 0x1U // Global Interrupt Flag + +//************************************************************************************************* +// +// The following are defines for the bit fields in the GINTCLR register +// +//************************************************************************************************* +#define UPP_GINTCLR_GINTCLR 0x1U // Global Interrupt Clear + +//************************************************************************************************* +// +// The following are defines for the bit fields in the DLYCTL register +// +//************************************************************************************************* +#define UPP_DLYCTL_DLYDIS 0x1U // IO dealy control disable. +#define UPP_DLYCTL_DLYCTL_S 1U +#define UPP_DLYCTL_DLYCTL_M 0x6U // IO delay control. + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_usb.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_usb.h new file mode 100644 index 0000000..27907eb --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_usb.h @@ -0,0 +1,4614 @@ +//########################################################################### +// +// FILE: hw_usb.h +// +// TITLE: Definitions for the USB registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_USB_H +#define HW_USB_H + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_FIFO8 0x00000040 // USB FIFO Endpoint 8 +#define USB_O_FIFO9 0x00000044 // USB FIFO Endpoint 9 +#define USB_O_FIFO10 0x00000048 // USB FIFO Endpoint 10 +#define USB_O_FIFO11 0x0000004C // USB FIFO Endpoint 11 +#define USB_O_FIFO12 0x00000050 // USB FIFO Endpoint 12 +#define USB_O_FIFO13 0x00000054 // USB FIFO Endpoint 13 +#define USB_O_FIFO14 0x00000058 // USB FIFO Endpoint 14 +#define USB_O_FIFO15 0x0000005C // USB FIFO Endpoint 15 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_TXFUNCADDR8 0x000000C0 // USB Transmit Functional Address + // Endpoint 8 +#define USB_O_TXHUBADDR8 0x000000C2 // USB Transmit Hub Address + // Endpoint 8 +#define USB_O_TXHUBPORT8 0x000000C3 // USB Transmit Hub Port Endpoint 8 +#define USB_O_RXFUNCADDR8 0x000000C4 // USB Receive Functional Address + // Endpoint 8 +#define USB_O_RXHUBADDR8 0x000000C6 // USB Receive Hub Address Endpoint + // 8 +#define USB_O_RXHUBPORT8 0x000000C7 // USB Receive Hub Port Endpoint 8 +#define USB_O_TXFUNCADDR9 0x000000C8 // USB Transmit Functional Address + // Endpoint 9 +#define USB_O_TXHUBADDR9 0x000000CA // USB Transmit Hub Address + // Endpoint 9 +#define USB_O_TXHUBPORT9 0x000000CB // USB Transmit Hub Port Endpoint 9 +#define USB_O_RXFUNCADDR9 0x000000CC // USB Receive Functional Address + // Endpoint 9 +#define USB_O_RXHUBADDR9 0x000000CE // USB Receive Hub Address Endpoint + // 9 +#define USB_O_RXHUBPORT9 0x000000CF // USB Receive Hub Port Endpoint 9 +#define USB_O_TXFUNCADDR10 0x000000D0 // USB Transmit Functional Address + // Endpoint 10 +#define USB_O_TXHUBADDR10 0x000000D2 // USB Transmit Hub Address + // Endpoint 10 +#define USB_O_TXHUBPORT10 0x000000D3 // USB Transmit Hub Port Endpoint + // 10 +#define USB_O_RXFUNCADDR10 0x000000D4 // USB Receive Functional Address + // Endpoint 10 +#define USB_O_RXHUBADDR10 0x000000D6 // USB Receive Hub Address Endpoint + // 10 +#define USB_O_RXHUBPORT10 0x000000D7 // USB Receive Hub Port Endpoint 10 +#define USB_O_TXFUNCADDR11 0x000000D8 // USB Transmit Functional Address + // Endpoint 11 +#define USB_O_TXHUBADDR11 0x000000DA // USB Transmit Hub Address + // Endpoint 11 +#define USB_O_TXHUBPORT11 0x000000DB // USB Transmit Hub Port Endpoint + // 11 +#define USB_O_RXFUNCADDR11 0x000000DC // USB Receive Functional Address + // Endpoint 11 +#define USB_O_RXHUBADDR11 0x000000DE // USB Receive Hub Address Endpoint + // 11 +#define USB_O_RXHUBPORT11 0x000000DF // USB Receive Hub Port Endpoint 11 +#define USB_O_TXFUNCADDR12 0x000000E0 // USB Transmit Functional Address + // Endpoint 12 +#define USB_O_TXHUBADDR12 0x000000E2 // USB Transmit Hub Address + // Endpoint 12 +#define USB_O_TXHUBPORT12 0x000000E3 // USB Transmit Hub Port Endpoint + // 12 +#define USB_O_RXFUNCADDR12 0x000000E4 // USB Receive Functional Address + // Endpoint 12 +#define USB_O_RXHUBADDR12 0x000000E6 // USB Receive Hub Address Endpoint + // 12 +#define USB_O_RXHUBPORT12 0x000000E7 // USB Receive Hub Port Endpoint 12 +#define USB_O_TXFUNCADDR13 0x000000E8 // USB Transmit Functional Address + // Endpoint 13 +#define USB_O_TXHUBADDR13 0x000000EA // USB Transmit Hub Address + // Endpoint 13 +#define USB_O_TXHUBPORT13 0x000000EB // USB Transmit Hub Port Endpoint + // 13 +#define USB_O_RXFUNCADDR13 0x000000EC // USB Receive Functional Address + // Endpoint 13 +#define USB_O_RXHUBADDR13 0x000000EE // USB Receive Hub Address Endpoint + // 13 +#define USB_O_RXHUBPORT13 0x000000EF // USB Receive Hub Port Endpoint 13 +#define USB_O_TXFUNCADDR14 0x000000F0 // USB Transmit Functional Address + // Endpoint 14 +#define USB_O_TXHUBADDR14 0x000000F2 // USB Transmit Hub Address + // Endpoint 14 +#define USB_O_TXHUBPORT14 0x000000F3 // USB Transmit Hub Port Endpoint + // 14 +#define USB_O_RXFUNCADDR14 0x000000F4 // USB Receive Functional Address + // Endpoint 14 +#define USB_O_RXHUBADDR14 0x000000F6 // USB Receive Hub Address Endpoint + // 14 +#define USB_O_RXHUBPORT14 0x000000F7 // USB Receive Hub Port Endpoint 14 +#define USB_O_TXFUNCADDR15 0x000000F8 // USB Transmit Functional Address + // Endpoint 15 +#define USB_O_TXHUBADDR15 0x000000FA // USB Transmit Hub Address + // Endpoint 15 +#define USB_O_TXHUBPORT15 0x000000FB // USB Transmit Hub Port Endpoint + // 15 +#define USB_O_RXFUNCADDR15 0x000000FC // USB Receive Functional Address + // Endpoint 15 +#define USB_O_RXHUBADDR15 0x000000FE // USB Receive Hub Address Endpoint + // 15 +#define USB_O_RXHUBPORT15 0x000000FF // USB Receive Hub Port Endpoint 15 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_TXMAXP8 0x00000180 // USB Maximum Transmit Data + // Endpoint 8 +#define USB_O_TXCSRL8 0x00000182 // USB Transmit Control and Status + // Endpoint 8 Low +#define USB_O_TXCSRH8 0x00000183 // USB Transmit Control and Status + // Endpoint 8 High +#define USB_O_RXMAXP8 0x00000184 // USB Maximum Receive Data + // Endpoint 8 +#define USB_O_RXCSRL8 0x00000186 // USB Receive Control and Status + // Endpoint 8 Low +#define USB_O_RXCSRH8 0x00000187 // USB Receive Control and Status + // Endpoint 8 High +#define USB_O_RXCOUNT8 0x00000188 // USB Receive Byte Count Endpoint + // 8 +#define USB_O_TXTYPE8 0x0000018A // USB Host Transmit Configure Type + // Endpoint 8 +#define USB_O_TXINTERVAL8 0x0000018B // USB Host Transmit Interval + // Endpoint 8 +#define USB_O_RXTYPE8 0x0000018C // USB Host Configure Receive Type + // Endpoint 8 +#define USB_O_RXINTERVAL8 0x0000018D // USB Host Receive Polling + // Interval Endpoint 8 +#define USB_O_TXMAXP9 0x00000190 // USB Maximum Transmit Data + // Endpoint 9 +#define USB_O_TXCSRL9 0x00000192 // USB Transmit Control and Status + // Endpoint 9 Low +#define USB_O_TXCSRH9 0x00000193 // USB Transmit Control and Status + // Endpoint 9 High +#define USB_O_RXMAXP9 0x00000194 // USB Maximum Receive Data + // Endpoint 9 +#define USB_O_RXCSRL9 0x00000196 // USB Receive Control and Status + // Endpoint 9 Low +#define USB_O_RXCSRH9 0x00000197 // USB Receive Control and Status + // Endpoint 9 High +#define USB_O_RXCOUNT9 0x00000198 // USB Receive Byte Count Endpoint + // 9 +#define USB_O_TXTYPE9 0x0000019A // USB Host Transmit Configure Type + // Endpoint 9 +#define USB_O_TXINTERVAL9 0x0000019B // USB Host Transmit Interval + // Endpoint 9 +#define USB_O_RXTYPE9 0x0000019C // USB Host Configure Receive Type + // Endpoint 9 +#define USB_O_RXINTERVAL9 0x0000019D // USB Host Receive Polling + // Interval Endpoint 9 +#define USB_O_TXMAXP10 0x000001A0 // USB Maximum Transmit Data + // Endpoint 10 +#define USB_O_TXCSRL10 0x000001A2 // USB Transmit Control and Status + // Endpoint 10 Low +#define USB_O_TXCSRH10 0x000001A3 // USB Transmit Control and Status + // Endpoint 10 High +#define USB_O_RXMAXP10 0x000001A4 // USB Maximum Receive Data + // Endpoint 10 +#define USB_O_RXCSRL10 0x000001A6 // USB Receive Control and Status + // Endpoint 10 Low +#define USB_O_RXCSRH10 0x000001A7 // USB Receive Control and Status + // Endpoint 10 High +#define USB_O_RXCOUNT10 0x000001A8 // USB Receive Byte Count Endpoint + // 10 +#define USB_O_TXTYPE10 0x000001AA // USB Host Transmit Configure Type + // Endpoint 10 +#define USB_O_TXINTERVAL10 0x000001AB // USB Host Transmit Interval + // Endpoint 10 +#define USB_O_RXTYPE10 0x000001AC // USB Host Configure Receive Type + // Endpoint 10 +#define USB_O_RXINTERVAL10 0x000001AD // USB Host Receive Polling + // Interval Endpoint 10 +#define USB_O_TXMAXP11 0x000001B0 // USB Maximum Transmit Data + // Endpoint 11 +#define USB_O_TXCSRL11 0x000001B2 // USB Transmit Control and Status + // Endpoint 11 Low +#define USB_O_TXCSRH11 0x000001B3 // USB Transmit Control and Status + // Endpoint 11 High +#define USB_O_RXMAXP11 0x000001B4 // USB Maximum Receive Data + // Endpoint 11 +#define USB_O_RXCSRL11 0x000001B6 // USB Receive Control and Status + // Endpoint 11 Low +#define USB_O_RXCSRH11 0x000001B7 // USB Receive Control and Status + // Endpoint 11 High +#define USB_O_RXCOUNT11 0x000001B8 // USB Receive Byte Count Endpoint + // 11 +#define USB_O_TXTYPE11 0x000001BA // USB Host Transmit Configure Type + // Endpoint 11 +#define USB_O_TXINTERVAL11 0x000001BB // USB Host Transmit Interval + // Endpoint 11 +#define USB_O_RXTYPE11 0x000001BC // USB Host Configure Receive Type + // Endpoint 11 +#define USB_O_RXINTERVAL11 0x000001BD // USB Host Receive Polling + // Interval Endpoint 11 +#define USB_O_TXMAXP12 0x000001C0 // USB Maximum Transmit Data + // Endpoint 12 +#define USB_O_TXCSRL12 0x000001C2 // USB Transmit Control and Status + // Endpoint 12 Low +#define USB_O_TXCSRH12 0x000001C3 // USB Transmit Control and Status + // Endpoint 12 High +#define USB_O_RXMAXP12 0x000001C4 // USB Maximum Receive Data + // Endpoint 12 +#define USB_O_RXCSRL12 0x000001C6 // USB Receive Control and Status + // Endpoint 12 Low +#define USB_O_RXCSRH12 0x000001C7 // USB Receive Control and Status + // Endpoint 12 High +#define USB_O_RXCOUNT12 0x000001C8 // USB Receive Byte Count Endpoint + // 12 +#define USB_O_TXTYPE12 0x000001CA // USB Host Transmit Configure Type + // Endpoint 12 +#define USB_O_TXINTERVAL12 0x000001CB // USB Host Transmit Interval + // Endpoint 12 +#define USB_O_RXTYPE12 0x000001CC // USB Host Configure Receive Type + // Endpoint 12 +#define USB_O_RXINTERVAL12 0x000001CD // USB Host Receive Polling + // Interval Endpoint 12 +#define USB_O_TXMAXP13 0x000001D0 // USB Maximum Transmit Data + // Endpoint 13 +#define USB_O_TXCSRL13 0x000001D2 // USB Transmit Control and Status + // Endpoint 13 Low +#define USB_O_TXCSRH13 0x000001D3 // USB Transmit Control and Status + // Endpoint 13 High +#define USB_O_RXMAXP13 0x000001D4 // USB Maximum Receive Data + // Endpoint 13 +#define USB_O_RXCSRL13 0x000001D6 // USB Receive Control and Status + // Endpoint 13 Low +#define USB_O_RXCSRH13 0x000001D7 // USB Receive Control and Status + // Endpoint 13 High +#define USB_O_RXCOUNT13 0x000001D8 // USB Receive Byte Count Endpoint + // 13 +#define USB_O_TXTYPE13 0x000001DA // USB Host Transmit Configure Type + // Endpoint 13 +#define USB_O_TXINTERVAL13 0x000001DB // USB Host Transmit Interval + // Endpoint 13 +#define USB_O_RXTYPE13 0x000001DC // USB Host Configure Receive Type + // Endpoint 13 +#define USB_O_RXINTERVAL13 0x000001DD // USB Host Receive Polling + // Interval Endpoint 13 +#define USB_O_TXMAXP14 0x000001E0 // USB Maximum Transmit Data + // Endpoint 14 +#define USB_O_TXCSRL14 0x000001E2 // USB Transmit Control and Status + // Endpoint 14 Low +#define USB_O_TXCSRH14 0x000001E3 // USB Transmit Control and Status + // Endpoint 14 High +#define USB_O_RXMAXP14 0x000001E4 // USB Maximum Receive Data + // Endpoint 14 +#define USB_O_RXCSRL14 0x000001E6 // USB Receive Control and Status + // Endpoint 14 Low +#define USB_O_RXCSRH14 0x000001E7 // USB Receive Control and Status + // Endpoint 14 High +#define USB_O_RXCOUNT14 0x000001E8 // USB Receive Byte Count Endpoint + // 14 +#define USB_O_TXTYPE14 0x000001EA // USB Host Transmit Configure Type + // Endpoint 14 +#define USB_O_TXINTERVAL14 0x000001EB // USB Host Transmit Interval + // Endpoint 14 +#define USB_O_RXTYPE14 0x000001EC // USB Host Configure Receive Type + // Endpoint 14 +#define USB_O_RXINTERVAL14 0x000001ED // USB Host Receive Polling + // Interval Endpoint 14 +#define USB_O_TXMAXP15 0x000001F0 // USB Maximum Transmit Data + // Endpoint 15 +#define USB_O_TXCSRL15 0x000001F2 // USB Transmit Control and Status + // Endpoint 15 Low +#define USB_O_TXCSRH15 0x000001F3 // USB Transmit Control and Status + // Endpoint 15 High +#define USB_O_RXMAXP15 0x000001F4 // USB Maximum Receive Data + // Endpoint 15 +#define USB_O_RXCSRL15 0x000001F6 // USB Receive Control and Status + // Endpoint 15 Low +#define USB_O_RXCSRH15 0x000001F7 // USB Receive Control and Status + // Endpoint 15 High +#define USB_O_RXCOUNT15 0x000001F8 // USB Receive Byte Count Endpoint + // 15 +#define USB_O_TXTYPE15 0x000001FA // USB Host Transmit Configure Type + // Endpoint 15 +#define USB_O_TXINTERVAL15 0x000001FB // USB Host Transmit Interval + // Endpoint 15 +#define USB_O_RXTYPE15 0x000001FC // USB Host Configure Receive Type + // Endpoint 15 +#define USB_O_RXINTERVAL15 0x000001FD // USB Host Receive Polling + // Interval Endpoint 15 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RQPKTCOUNT8 0x00000320 // USB Request Packet Count in + // Block Transfer Endpoint 8 +#define USB_O_RQPKTCOUNT9 0x00000324 // USB Request Packet Count in + // Block Transfer Endpoint 9 +#define USB_O_RQPKTCOUNT10 0x00000328 // USB Request Packet Count in + // Block Transfer Endpoint 10 +#define USB_O_RQPKTCOUNT11 0x0000032C // USB Request Packet Count in + // Block Transfer Endpoint 11 +#define USB_O_RQPKTCOUNT12 0x00000330 // USB Request Packet Count in + // Block Transfer Endpoint 12 +#define USB_O_RQPKTCOUNT13 0x00000334 // USB Request Packet Count in + // Block Transfer Endpoint 13 +#define USB_O_RQPKTCOUNT14 0x00000338 // USB Request Packet Count in + // Block Transfer Endpoint 14 +#define USB_O_RQPKTCOUNT15 0x0000033C // USB Request Packet Count in + // Block Transfer Endpoint 15 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_DMASEL 0x00000450 // USB DMA Select +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP15 0x00008000 // TX Endpoint 15 Interrupt +#define USB_TXIS_EP14 0x00004000 // TX Endpoint 14 Interrupt +#define USB_TXIS_EP13 0x00002000 // TX Endpoint 13 Interrupt +#define USB_TXIS_EP12 0x00001000 // TX Endpoint 12 Interrupt +#define USB_TXIS_EP11 0x00000800 // TX Endpoint 11 Interrupt +#define USB_TXIS_EP10 0x00000400 // TX Endpoint 10 Interrupt +#define USB_TXIS_EP9 0x00000200 // TX Endpoint 9 Interrupt +#define USB_TXIS_EP8 0x00000100 // TX Endpoint 8 Interrupt +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP15 0x00008000 // RX Endpoint 15 Interrupt +#define USB_RXIS_EP14 0x00004000 // RX Endpoint 14 Interrupt +#define USB_RXIS_EP13 0x00002000 // RX Endpoint 13 Interrupt +#define USB_RXIS_EP12 0x00001000 // RX Endpoint 12 Interrupt +#define USB_RXIS_EP11 0x00000800 // RX Endpoint 11 Interrupt +#define USB_RXIS_EP10 0x00000400 // RX Endpoint 10 Interrupt +#define USB_RXIS_EP9 0x00000200 // RX Endpoint 9 Interrupt +#define USB_RXIS_EP8 0x00000100 // RX Endpoint 8 Interrupt +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP15 0x00008000 // TX Endpoint 15 Interrupt Enable +#define USB_TXIE_EP14 0x00004000 // TX Endpoint 14 Interrupt Enable +#define USB_TXIE_EP13 0x00002000 // TX Endpoint 13 Interrupt Enable +#define USB_TXIE_EP12 0x00001000 // TX Endpoint 12 Interrupt Enable +#define USB_TXIE_EP11 0x00000800 // TX Endpoint 11 Interrupt Enable +#define USB_TXIE_EP10 0x00000400 // TX Endpoint 10 Interrupt Enable +#define USB_TXIE_EP9 0x00000200 // TX Endpoint 9 Interrupt Enable +#define USB_TXIE_EP8 0x00000100 // TX Endpoint 8 Interrupt Enable +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP15 0x00008000 // RX Endpoint 15 Interrupt Enable +#define USB_RXIE_EP14 0x00004000 // RX Endpoint 14 Interrupt Enable +#define USB_RXIE_EP13 0x00002000 // RX Endpoint 13 Interrupt Enable +#define USB_RXIE_EP12 0x00001000 // RX Endpoint 12 Interrupt Enable +#define USB_RXIE_EP11 0x00000800 // RX Endpoint 11 Interrupt Enable +#define USB_RXIE_EP10 0x00000400 // RX Endpoint 10 Interrupt Enable +#define USB_RXIE_EP9 0x00000200 // RX Endpoint 9 Interrupt Enable +#define USB_RXIE_EP8 0x00000100 // RX Endpoint 8 Interrupt Enable +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST +#define USB_IS_DISCON 0x00000020 // Session Disconnect +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt +#define USB_IE_SESREQ 0x00000040 // Enable Session Request +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO8 register. +// +//***************************************************************************** +#define USB_FIFO8_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO8_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO9 register. +// +//***************************************************************************** +#define USB_FIFO9_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO9_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO10 register. +// +//***************************************************************************** +#define USB_FIFO10_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO10_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO11 register. +// +//***************************************************************************** +#define USB_FIFO11_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO11_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO12 register. +// +//***************************************************************************** +#define USB_FIFO12_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO12_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO13 register. +// +//***************************************************************************** +#define USB_FIFO13_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO13_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO14 register. +// +//***************************************************************************** +#define USB_FIFO14_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO14_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO15 register. +// +//***************************************************************************** +#define USB_FIFO15_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO15_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR8 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR8_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR8 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR8_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR8_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT8 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT8_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT8_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR9 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR9_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR9 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR9_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR9_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT9 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT9_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT9_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR10 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR10_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR10 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR10_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR10_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT10 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT10_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT10_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR11 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR11_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR11 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR11_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR11_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT11 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT11_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT11_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR12 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR12_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR12 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR12_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR12_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT12 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT12_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT12_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR13 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR13_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR13 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR13_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR13_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT13 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT13_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT13_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR14 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR14_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR14 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR14_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR14_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT14 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT14_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT14_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR15 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR15_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR15 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR15_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR15_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT15 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT15_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT15_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP8 register. +// +//***************************************************************************** +#define USB_TXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL8 register. +// +//***************************************************************************** +#define USB_TXCSRL8_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL8_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL8_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL8_STALL 0x00000010 // Send STALL +#define USB_TXCSRL8_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL8_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL8_ERROR 0x00000004 // Error +#define USB_TXCSRL8_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL8_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL8_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH8 register. +// +//***************************************************************************** +#define USB_TXCSRH8_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH8_MODE 0x00000020 // Mode +#define USB_TXCSRH8_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH8_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH8_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH8_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH8_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP8 register. +// +//***************************************************************************** +#define USB_RXMAXP8_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP8_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL8 register. +// +//***************************************************************************** +#define USB_RXCSRL8_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL8_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL8_STALL 0x00000020 // Send STALL +#define USB_RXCSRL8_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL8_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL8_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL8_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL8_OVER 0x00000004 // Overrun +#define USB_RXCSRL8_ERROR 0x00000004 // Error +#define USB_RXCSRL8_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL8_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH8 register. +// +//***************************************************************************** +#define USB_RXCSRH8_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH8_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH8_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH8_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH8_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH8_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH8_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH8_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH8_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT8 register. +// +//***************************************************************************** +#define USB_RXCOUNT8_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE8 register. +// +//***************************************************************************** +#define USB_TXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL8_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL8_NAKLMT_S \ + 0 +#define USB_TXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE8 register. +// +//***************************************************************************** +#define USB_RXTYPE8_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE8_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE8_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE8_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE8_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE8_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE8_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE8_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE8_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE8_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE8_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL8 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL8_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL8_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL8_NAKLMT_S \ + 0 +#define USB_RXINTERVAL8_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP9 register. +// +//***************************************************************************** +#define USB_TXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL9 register. +// +//***************************************************************************** +#define USB_TXCSRL9_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL9_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL9_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL9_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL9_STALL 0x00000010 // Send STALL +#define USB_TXCSRL9_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL9_ERROR 0x00000004 // Error +#define USB_TXCSRL9_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL9_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL9_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH9 register. +// +//***************************************************************************** +#define USB_TXCSRH9_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH9_MODE 0x00000020 // Mode +#define USB_TXCSRH9_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH9_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH9_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH9_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH9_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP9 register. +// +//***************************************************************************** +#define USB_RXMAXP9_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP9_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL9 register. +// +//***************************************************************************** +#define USB_RXCSRL9_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL9_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL9_STALL 0x00000020 // Send STALL +#define USB_RXCSRL9_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL9_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL9_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL9_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL9_ERROR 0x00000004 // Error +#define USB_RXCSRL9_OVER 0x00000004 // Overrun +#define USB_RXCSRL9_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL9_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH9 register. +// +//***************************************************************************** +#define USB_RXCSRH9_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH9_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH9_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH9_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH9_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH9_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH9_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH9_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH9_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT9 register. +// +//***************************************************************************** +#define USB_RXCOUNT9_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE9 register. +// +//***************************************************************************** +#define USB_TXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL9_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL9_TXPOLL_S \ + 0 +#define USB_TXINTERVAL9_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE9 register. +// +//***************************************************************************** +#define USB_RXTYPE9_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE9_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE9_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE9_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE9_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE9_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE9_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE9_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE9_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE9_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE9_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL9 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL9_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL9_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL9_NAKLMT_S \ + 0 +#define USB_RXINTERVAL9_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP10 register. +// +//***************************************************************************** +#define USB_TXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL10 register. +// +//***************************************************************************** +#define USB_TXCSRL10_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL10_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL10_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL10_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL10_STALL 0x00000010 // Send STALL +#define USB_TXCSRL10_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL10_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL10_ERROR 0x00000004 // Error +#define USB_TXCSRL10_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL10_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH10 register. +// +//***************************************************************************** +#define USB_TXCSRH10_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH10_MODE 0x00000020 // Mode +#define USB_TXCSRH10_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH10_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH10_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH10_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH10_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP10 register. +// +//***************************************************************************** +#define USB_RXMAXP10_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP10_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL10 register. +// +//***************************************************************************** +#define USB_RXCSRL10_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL10_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL10_STALL 0x00000020 // Send STALL +#define USB_RXCSRL10_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL10_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL10_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL10_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL10_OVER 0x00000004 // Overrun +#define USB_RXCSRL10_ERROR 0x00000004 // Error +#define USB_RXCSRL10_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL10_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH10 register. +// +//***************************************************************************** +#define USB_RXCSRH10_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH10_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH10_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH10_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH10_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH10_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH10_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH10_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH10_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT10_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT10_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE10 register. +// +//***************************************************************************** +#define USB_TXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL10_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL10_TXPOLL_S \ + 0 +#define USB_TXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE10 register. +// +//***************************************************************************** +#define USB_RXTYPE10_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE10_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE10_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE10_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE10_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE10_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE10_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE10_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE10_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE10_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE10_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL10 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL10_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL10_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL10_TXPOLL_S \ + 0 +#define USB_RXINTERVAL10_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP11 register. +// +//***************************************************************************** +#define USB_TXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL11 register. +// +//***************************************************************************** +#define USB_TXCSRL11_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL11_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL11_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL11_STALL 0x00000010 // Send STALL +#define USB_TXCSRL11_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL11_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL11_ERROR 0x00000004 // Error +#define USB_TXCSRL11_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL11_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL11_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH11 register. +// +//***************************************************************************** +#define USB_TXCSRH11_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH11_MODE 0x00000020 // Mode +#define USB_TXCSRH11_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH11_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH11_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH11_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH11_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP11 register. +// +//***************************************************************************** +#define USB_RXMAXP11_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP11_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL11 register. +// +//***************************************************************************** +#define USB_RXCSRL11_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL11_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL11_STALL 0x00000020 // Send STALL +#define USB_RXCSRL11_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL11_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL11_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL11_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL11_OVER 0x00000004 // Overrun +#define USB_RXCSRL11_ERROR 0x00000004 // Error +#define USB_RXCSRL11_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL11_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH11 register. +// +//***************************************************************************** +#define USB_RXCSRH11_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH11_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH11_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH11_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH11_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH11_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH11_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH11_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH11_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT11_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT11_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE11 register. +// +//***************************************************************************** +#define USB_TXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL11_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL11_NAKLMT_S \ + 0 +#define USB_TXINTERVAL11_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE11 register. +// +//***************************************************************************** +#define USB_RXTYPE11_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE11_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE11_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE11_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE11_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE11_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE11_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE11_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE11_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE11_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE11_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL11 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL11_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL11_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL11_TXPOLL_S \ + 0 +#define USB_RXINTERVAL11_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP12 register. +// +//***************************************************************************** +#define USB_TXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL12 register. +// +//***************************************************************************** +#define USB_TXCSRL12_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL12_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL12_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL12_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL12_STALL 0x00000010 // Send STALL +#define USB_TXCSRL12_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL12_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL12_ERROR 0x00000004 // Error +#define USB_TXCSRL12_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL12_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH12 register. +// +//***************************************************************************** +#define USB_TXCSRH12_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH12_MODE 0x00000020 // Mode +#define USB_TXCSRH12_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH12_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH12_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH12_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH12_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP12 register. +// +//***************************************************************************** +#define USB_RXMAXP12_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP12_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL12 register. +// +//***************************************************************************** +#define USB_RXCSRL12_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL12_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL12_STALL 0x00000020 // Send STALL +#define USB_RXCSRL12_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL12_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL12_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL12_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL12_ERROR 0x00000004 // Error +#define USB_RXCSRL12_OVER 0x00000004 // Overrun +#define USB_RXCSRL12_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL12_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH12 register. +// +//***************************************************************************** +#define USB_RXCSRH12_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH12_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH12_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH12_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH12_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH12_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH12_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH12_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH12_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT12_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT12_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE12 register. +// +//***************************************************************************** +#define USB_TXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL12_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL12_TXPOLL_S \ + 0 +#define USB_TXINTERVAL12_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE12 register. +// +//***************************************************************************** +#define USB_RXTYPE12_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE12_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE12_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE12_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE12_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE12_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE12_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE12_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE12_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE12_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE12_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL12 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL12_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL12_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL12_NAKLMT_S \ + 0 +#define USB_RXINTERVAL12_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP13 register. +// +//***************************************************************************** +#define USB_TXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL13 register. +// +//***************************************************************************** +#define USB_TXCSRL13_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL13_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL13_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL13_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL13_STALL 0x00000010 // Send STALL +#define USB_TXCSRL13_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL13_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL13_ERROR 0x00000004 // Error +#define USB_TXCSRL13_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL13_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH13 register. +// +//***************************************************************************** +#define USB_TXCSRH13_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH13_MODE 0x00000020 // Mode +#define USB_TXCSRH13_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH13_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH13_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH13_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH13_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP13 register. +// +//***************************************************************************** +#define USB_RXMAXP13_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP13_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL13 register. +// +//***************************************************************************** +#define USB_RXCSRL13_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL13_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL13_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL13_STALL 0x00000020 // Send STALL +#define USB_RXCSRL13_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL13_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL13_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL13_OVER 0x00000004 // Overrun +#define USB_RXCSRL13_ERROR 0x00000004 // Error +#define USB_RXCSRL13_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL13_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH13 register. +// +//***************************************************************************** +#define USB_RXCSRH13_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH13_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH13_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH13_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH13_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH13_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH13_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH13_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH13_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT13_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT13_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE13 register. +// +//***************************************************************************** +#define USB_TXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL13_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL13_TXPOLL_S \ + 0 +#define USB_TXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE13 register. +// +//***************************************************************************** +#define USB_RXTYPE13_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE13_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE13_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE13_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE13_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE13_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE13_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE13_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE13_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE13_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE13_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL13 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL13_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL13_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL13_TXPOLL_S \ + 0 +#define USB_RXINTERVAL13_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP14 register. +// +//***************************************************************************** +#define USB_TXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL14 register. +// +//***************************************************************************** +#define USB_TXCSRL14_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL14_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL14_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL14_STALL 0x00000010 // Send STALL +#define USB_TXCSRL14_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL14_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL14_ERROR 0x00000004 // Error +#define USB_TXCSRL14_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL14_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL14_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH14 register. +// +//***************************************************************************** +#define USB_TXCSRH14_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH14_MODE 0x00000020 // Mode +#define USB_TXCSRH14_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH14_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH14_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH14_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH14_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP14 register. +// +//***************************************************************************** +#define USB_RXMAXP14_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP14_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL14 register. +// +//***************************************************************************** +#define USB_RXCSRL14_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL14_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL14_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL14_STALL 0x00000020 // Send STALL +#define USB_RXCSRL14_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL14_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL14_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL14_OVER 0x00000004 // Overrun +#define USB_RXCSRL14_ERROR 0x00000004 // Error +#define USB_RXCSRL14_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL14_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH14 register. +// +//***************************************************************************** +#define USB_RXCSRH14_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH14_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH14_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH14_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH14_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH14_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH14_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH14_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH14_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT14_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT14_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE14 register. +// +//***************************************************************************** +#define USB_TXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL14_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL14_TXPOLL_S \ + 0 +#define USB_TXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE14 register. +// +//***************************************************************************** +#define USB_RXTYPE14_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE14_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE14_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE14_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE14_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE14_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE14_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE14_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE14_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE14_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE14_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL14 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL14_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL14_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL14_TXPOLL_S \ + 0 +#define USB_RXINTERVAL14_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP15 register. +// +//***************************************************************************** +#define USB_TXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL15 register. +// +//***************************************************************************** +#define USB_TXCSRL15_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL15_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL15_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL15_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL15_STALL 0x00000010 // Send STALL +#define USB_TXCSRL15_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL15_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL15_ERROR 0x00000004 // Error +#define USB_TXCSRL15_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL15_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH15 register. +// +//***************************************************************************** +#define USB_TXCSRH15_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH15_MODE 0x00000020 // Mode +#define USB_TXCSRH15_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH15_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH15_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH15_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH15_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP15 register. +// +//***************************************************************************** +#define USB_RXMAXP15_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP15_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL15 register. +// +//***************************************************************************** +#define USB_RXCSRL15_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL15_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL15_STALL 0x00000020 // Send STALL +#define USB_RXCSRL15_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL15_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL15_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL15_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL15_ERROR 0x00000004 // Error +#define USB_RXCSRL15_OVER 0x00000004 // Overrun +#define USB_RXCSRL15_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL15_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH15 register. +// +//***************************************************************************** +#define USB_RXCSRH15_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH15_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH15_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH15_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH15_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH15_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH15_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH15_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH15_DT 0x00000002 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RXCOUNT15_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT15_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE15 register. +// +//***************************************************************************** +#define USB_TXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL15_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL15_NAKLMT_S \ + 0 +#define USB_TXINTERVAL15_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE15 register. +// +//***************************************************************************** +#define USB_RXTYPE15_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE15_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE15_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE15_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE15_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE15_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE15_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE15_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE15_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE15_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE15_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL15 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL15_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL15_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL15_TXPOLL_S \ + 0 +#define USB_RXINTERVAL15_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT8 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT8_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT8_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT9 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT9_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT9_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT10 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT10_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT10_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT11 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT11_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT11_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT12 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT12_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT12_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT13 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT13_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT13_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT14 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT14_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT14_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT15 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT15_COUNT_M \ + 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT15_COUNT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP15 0x00008000 // EP15 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP14 0x00004000 // EP14 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP13 0x00002000 // EP13 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP12 0x00001000 // EP12 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP11 0x00000800 // EP11 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP10 0x00000400 // EP10 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP9 0x00000200 // EP9 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP8 0x00000100 // EP8 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP15 0x00008000 // EP15 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP14 0x00004000 // EP14 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP13 0x00002000 // EP13 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP12 0x00001000 // EP12 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP11 0x00000800 // EP11 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP10 0x00000400 // EP10 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP9 0x00000200 // EP9 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP8 0x00000100 // EP8 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMASEL register. +// +//***************************************************************************** +#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select +#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select +#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select +#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select +#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select +#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select +#define USB_DMASEL_DMACTX_S 20 +#define USB_DMASEL_DMACRX_S 16 +#define USB_DMASEL_DMABTX_S 12 +#define USB_DMASEL_DMABRX_S 8 +#define USB_DMASEL_DMAATX_S 4 +#define USB_DMASEL_DMAARX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_PHY 0x00000010 // PHY Present +#define USB_PP_TYPE_M 0x0000000F // Controller Type +#define USB_PP_TYPE_0 0x00000000 // The first-generation USB + // controller +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following definitions are deprecated. +// +//***************************************************************************** +#ifndef DEPRECATED + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_TXFIFOADD register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_TXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_TXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_TXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_TXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_TXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_TXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_TXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_TXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_TXFIFOADD_ADDR_0 0x00000000 // 0 + +//***************************************************************************** +// +// The following are deprecated defines for the bit fields in the +// USB_O_RXFIFOADD register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_2048 0x00000009 // 2048 +#define USB_RXFIFOADD_ADDR_1024 0x00000008 // 1024 +#define USB_RXFIFOADD_ADDR_512 0x00000007 // 512 +#define USB_RXFIFOADD_ADDR_256 0x00000006 // 256 +#define USB_RXFIFOADD_ADDR_128 0x00000005 // 128 +#define USB_RXFIFOADD_ADDR_64 0x00000004 // 64 +#define USB_RXFIFOADD_ADDR_32 0x00000003 // 32 +#define USB_RXFIFOADD_ADDR_16 0x00000002 // 16 +#define USB_RXFIFOADD_ADDR_8 0x00000001 // 8 +#define USB_RXFIFOADD_ADDR_0 0x00000000 // 0 + +#endif + +#endif // __HW_USB_H__ diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_xbar.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_xbar.h new file mode 100644 index 0000000..7869257 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_xbar.h @@ -0,0 +1,271 @@ +//########################################################################### +// +// FILE: hw_xbar.h +// +// TITLE: Definitions for the XBAR registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XBAR_H +#define HW_XBAR_H + +//************************************************************************************************* +// +// The following are defines for the XBAR register offsets +// +//************************************************************************************************* +#define XBAR_O_FLG1 0x0U // X-Bar Input Flag Register 1 +#define XBAR_O_FLG2 0x2U // X-Bar Input Flag Register 2 +#define XBAR_O_FLG3 0x4U // X-Bar Input Flag Register 3 +#define XBAR_O_CLR1 0x8U // X-Bar Input Flag Clear Register 1 +#define XBAR_O_CLR2 0xAU // X-Bar Input Flag Clear Register 2 +#define XBAR_O_CLR3 0xCU // X-Bar Input Flag Clear Register 3 + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG1 register +// +//************************************************************************************************* +#define XBAR_FLG1_CMPSS1_CTRIPL 0x1U // Input Flag for CMPSS1.CTRIPL Signal +#define XBAR_FLG1_CMPSS1_CTRIPH 0x2U // Input Flag for CMPSS1.CTRIPH Signal +#define XBAR_FLG1_CMPSS2_CTRIPL 0x4U // Input Flag for CMPSS2.CTRIPL Signal +#define XBAR_FLG1_CMPSS2_CTRIPH 0x8U // Input Flag for CMPSS2.CTRIPH Signal +#define XBAR_FLG1_CMPSS3_CTRIPL 0x10U // Input Flag for CMPSS3.CTRIPL Signal +#define XBAR_FLG1_CMPSS3_CTRIPH 0x20U // Input Flag for CMPSS3.CTRIPH Signal +#define XBAR_FLG1_CMPSS4_CTRIPL 0x40U // Input Flag for CMPSS4.CTRIPL Signal +#define XBAR_FLG1_CMPSS4_CTRIPH 0x80U // Input Flag for CMPSS4.CTRIPH Signal +#define XBAR_FLG1_CMPSS5_CTRIPL 0x100U // Input Flag for CMPSS5.CTRIPL Signal +#define XBAR_FLG1_CMPSS5_CTRIPH 0x200U // Input Flag for CMPSS5.CTRIPH Signal +#define XBAR_FLG1_CMPSS6_CTRIPL 0x400U // Input Flag for CMPSS6.CTRIPL Signal +#define XBAR_FLG1_CMPSS6_CTRIPH 0x800U // Input Flag for CMPSS6.CTRIPH Signal +#define XBAR_FLG1_CMPSS7_CTRIPL 0x1000U // Input Flag for CMPSS7.CTRIPL Signal +#define XBAR_FLG1_CMPSS7_CTRIPH 0x2000U // Input Flag for CMPSS7.CTRIPH Signal +#define XBAR_FLG1_CMPSS8_CTRIPL 0x4000U // Input Flag for CMPSS8.CTRIPL Signal +#define XBAR_FLG1_CMPSS8_CTRIPH 0x8000U // Input Flag for CMPSS8.CTRIPH Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag for CMPSS1.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag for CMPSS1.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag for CMPSS2.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag for CMPSS2.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag for CMPSS3.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag for CMPSS3.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag for CMPSS4.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag for CMPSS4.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag for CMPSS5.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag for CMPSS5.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag for CMPSS6.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag for CMPSS6.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag for CMPSS7.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag for CMPSS7.CTRIPOUTH Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag for CMPSS8.CTRIPOUTL Signal +#define XBAR_FLG1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG2 register +// +//************************************************************************************************* +#define XBAR_FLG2_INPUT1 0x1U // Input Flag for INPUT1 Signal +#define XBAR_FLG2_INPUT2 0x2U // Input Flag for INPUT2 Signal +#define XBAR_FLG2_INPUT3 0x4U // Input Flag for INPUT3 Signal +#define XBAR_FLG2_INPUT4 0x8U // Input Flag for INPUT4 Signal +#define XBAR_FLG2_INPUT5 0x10U // Input Flag for INPUT5 Signal +#define XBAR_FLG2_INPUT6 0x20U // Input Flag for INPUT6 Signal +#define XBAR_FLG2_ADCSOCAO 0x40U // Input Flag for ADCSOCAO Signal +#define XBAR_FLG2_ADCSOCBO 0x80U // Input Flag for ADCSOCBO Signal +#define XBAR_FLG2_CLB1_OUT4 0x100U // Input Flag for CLB1_OUT4 Signal +#define XBAR_FLG2_CLB1_OUT5 0x200U // Input Flag for CLB1_OUT5 Signal +#define XBAR_FLG2_CLB2_OUT4 0x400U // Input Flag for CLB2_OUT4 Signal +#define XBAR_FLG2_CLB2_OUT5 0x800U // Input Flag for CLB2_OUT5 Signal +#define XBAR_FLG2_CLB3_OUT4 0x1000U // Input Flag for CLB3_OUT4 Signal +#define XBAR_FLG2_CLB3_OUT5 0x2000U // Input Flag for CLB3_OUT5 Signal +#define XBAR_FLG2_CLB4_OUT4 0x4000U // Input Flag for CLB4_OUT4 Signal +#define XBAR_FLG2_CLB4_OUT5 0x8000U // Input Flag for CLB4_OUT5 Signal +#define XBAR_FLG2_ECAP1_OUT 0x10000U // Input Flag for ECAP1.OUT Signal +#define XBAR_FLG2_ECAP2_OUT 0x20000U // Input Flag for ECAP2.OUT Signal +#define XBAR_FLG2_ECAP3_OUT 0x40000U // Input Flag for ECAP3.OUT Signal +#define XBAR_FLG2_ECAP4_OUT 0x80000U // Input Flag for ECAP4.OUT Signal +#define XBAR_FLG2_ECAP5_OUT 0x100000U // Input Flag for ECAP5.OUT Signal +#define XBAR_FLG2_ECAP6_OUT 0x200000U // Input Flag for ECAP6.OUT Signal +#define XBAR_FLG2_EXTSYNCOUT 0x400000U // Input Flag for EXTSYNCOUT Signal +#define XBAR_FLG2_ADCAEVT1 0x800000U // Input Flag for ADCAEVT1 Signal +#define XBAR_FLG2_ADCAEVT2 0x1000000U // Input Flag for ADCAEVT2 Signal +#define XBAR_FLG2_ADCAEVT3 0x2000000U // Input Flag for ADCAEVT3 Signal +#define XBAR_FLG2_ADCAEVT4 0x4000000U // Input Flag for ADCAEVT4 Signal +#define XBAR_FLG2_ADCBEVT1 0x8000000U // Input Flag for ADCBEVT1 Signal +#define XBAR_FLG2_ADCBEVT2 0x10000000U // Input Flag for ADCBEVT2 Signal +#define XBAR_FLG2_ADCBEVT3 0x20000000U // Input Flag for ADCBEVT3 Signal +#define XBAR_FLG2_ADCBEVT4 0x40000000U // Input Flag for ADCBEVT4 Signal +#define XBAR_FLG2_ADCCEVT1 0x80000000U // Input Flag for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARFLG3 register +// +//************************************************************************************************* +#define XBAR_FLG3_ADCCEVT2 0x1U // Input Flag for ADCCEVT2 Signal +#define XBAR_FLG3_ADCCEVT3 0x2U // Input Flag for ADCCEVT3 Signal +#define XBAR_FLG3_ADCCEVT4 0x4U // Input Flag for ADCCEVT4 Signal +#define XBAR_FLG3_ADCDEVT1 0x8U // Input Flag for ADCDEVT1 Signal +#define XBAR_FLG3_ADCDEVT2 0x10U // Input Flag for ADCDEVT2 Signal +#define XBAR_FLG3_ADCDEVT3 0x20U // Input Flag for ADCDEVT3 Signal +#define XBAR_FLG3_ADCDEVT4 0x40U // Input Flag for ADCDEVT4 Signal +#define XBAR_FLG3_SD1FLT1_COMPL 0x80U // Input Flag for SD1FLT1.COMPL Signal +#define XBAR_FLG3_SD1FLT1_COMPH 0x100U // Input Flag for SD1FLT1.COMPH Signal +#define XBAR_FLG3_SD1FLT2_COMPL 0x200U // Input Flag for SD1FLT2.COMPL Signal +#define XBAR_FLG3_SD1FLT2_COMPH 0x400U // Input Flag for SD1FLT2.COMPH Signal +#define XBAR_FLG3_SD1FLT3_COMPL 0x800U // Input Flag for SD1FLT3.COMPL Signal +#define XBAR_FLG3_SD1FLT3_COMPH 0x1000U // Input Flag for SD1FLT3.COMPH Signal +#define XBAR_FLG3_SD1FLT4_COMPL 0x2000U // Input Flag for SD1FLT4.COMPL Signal +#define XBAR_FLG3_SD1FLT4_COMPH 0x4000U // Input Flag for SD1FLT4.COMPH Signal +#define XBAR_FLG3_SD2FLT1_COMPL 0x8000U // Input Flag for SD2FLT1.COMPL Signal +#define XBAR_FLG3_SD2FLT1_COMPH 0x10000U // Input Flag for SD2FLT1.COMPH Signal +#define XBAR_FLG3_SD2FLT2_COMPL 0x20000U // Input Flag for SD2FLT2.COMPL Signal +#define XBAR_FLG3_SD2FLT2_COMPH 0x40000U // Input Flag for SD2FLT2.COMPH Signal +#define XBAR_FLG3_SD2FLT3_COMPL 0x80000U // Input Flag for SD2FLT3.COMPL Signal +#define XBAR_FLG3_SD2FLT3_COMPH 0x100000U // Input Flag for SD2FLT3.COMPH Signal +#define XBAR_FLG3_SD2FLT4_COMPL 0x200000U // Input Flag for SD2FLT4.COMPL Signal +#define XBAR_FLG3_SD2FLT4_COMPH 0x400000U // Input Flag for SD2FLT4.COMPH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR1 register +// +//************************************************************************************************* +#define XBAR_CLR1_CMPSS1_CTRIPL 0x1U // Input Flag Clear for CMPSS1.CTRIPL Signal +#define XBAR_CLR1_CMPSS1_CTRIPH 0x2U // Input Flag Clear for CMPSS1.CTRIPH Signal +#define XBAR_CLR1_CMPSS2_CTRIPL 0x4U // Input Flag Clear for CMPSS2.CTRIPL Signal +#define XBAR_CLR1_CMPSS2_CTRIPH 0x8U // Input Flag Clear for CMPSS2.CTRIPH Signal +#define XBAR_CLR1_CMPSS3_CTRIPL 0x10U // Input Flag Clear for CMPSS3.CTRIPL Signal +#define XBAR_CLR1_CMPSS3_CTRIPH 0x20U // Input Flag Clear for CMPSS3.CTRIPH Signal +#define XBAR_CLR1_CMPSS4_CTRIPL 0x40U // Input Flag Clear for CMPSS4.CTRIPL Signal +#define XBAR_CLR1_CMPSS4_CTRIPH 0x80U // Input Flag Clear for CMPSS4.CTRIPH Signal +#define XBAR_CLR1_CMPSS5_CTRIPL 0x100U // Input Flag Clear for CMPSS5.CTRIPL Signal +#define XBAR_CLR1_CMPSS5_CTRIPH 0x200U // Input Flag Clear for CMPSS5.CTRIPH Signal +#define XBAR_CLR1_CMPSS6_CTRIPL 0x400U // Input Flag Clear for CMPSS6.CTRIPL Signal +#define XBAR_CLR1_CMPSS6_CTRIPH 0x800U // Input Flag Clear for CMPSS6.CTRIPH Signal +#define XBAR_CLR1_CMPSS7_CTRIPL 0x1000U // Input Flag Clear for CMPSS7.CTRIPL Signal +#define XBAR_CLR1_CMPSS7_CTRIPH 0x2000U // Input Flag Clear for CMPSS7.CTRIPH Signal +#define XBAR_CLR1_CMPSS8_CTRIPL 0x4000U // Input Flag Clear for CMPSS8.CTRIPL Signal +#define XBAR_CLR1_CMPSS8_CTRIPH 0x8000U // Input Flag Clear for CMPSS8.CTRIPH Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTL 0x10000U // Input Flag Clear for CMPSS1.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS1_CTRIPOUTH 0x20000U // Input Flag Clear for CMPSS1.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTL 0x40000U // Input Flag Clear for CMPSS2.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS2_CTRIPOUTH 0x80000U // Input Flag Clear for CMPSS2.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTL 0x100000U // Input Flag Clear for CMPSS3.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS3_CTRIPOUTH 0x200000U // Input Flag Clear for CMPSS3.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTL 0x400000U // Input Flag Clear for CMPSS4.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS4_CTRIPOUTH 0x800000U // Input Flag Clear for CMPSS4.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTL 0x1000000U // Input Flag Clear for CMPSS5.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS5_CTRIPOUTH 0x2000000U // Input Flag Clear for CMPSS5.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTL 0x4000000U // Input Flag Clear for CMPSS6.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS6_CTRIPOUTH 0x8000000U // Input Flag Clear for CMPSS6.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTL 0x10000000U // Input Flag Clear for CMPSS7.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS7_CTRIPOUTH 0x20000000U // Input Flag Clear for CMPSS7.CTRIPOUTH Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTL 0x40000000U // Input Flag Clear for CMPSS8.CTRIPOUTL Signal +#define XBAR_CLR1_CMPSS8_CTRIPOUTH 0x80000000U // Input Flag Clear for CMPSS8.CTRIPOUTH Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR2 register +// +//************************************************************************************************* +#define XBAR_CLR2_INPUT1 0x1U // Input Flag Clear for INPUT1 Signal +#define XBAR_CLR2_INPUT2 0x2U // Input Flag Clear for INPUT2 Signal +#define XBAR_CLR2_INPUT3 0x4U // Input Flag Clear for INPUT3 Signal +#define XBAR_CLR2_INPUT4 0x8U // Input Flag Clear for INPUT4 Signal +#define XBAR_CLR2_INPUT5 0x10U // Input Flag Clear for INPUT5 Signal +#define XBAR_CLR2_INPUT7 0x20U // Input Flag Clear for INPUT7 Signal +#define XBAR_CLR2_ADCSOCAO 0x40U // Input Flag Clear for ADCSOCAO Signal +#define XBAR_CLR2_ADCSOCBO 0x80U // Input Flag Clear for ADCSOCBO Signal +#define XBAR_CLR2_CLB1_OUT4 0x100U // Input Flag Clear for CLB1_OUT4 Signal +#define XBAR_CLR2_CLB1_OUT5 0x200U // Input Flag Clear for CLB1_OUT5 Signal +#define XBAR_CLR2_CLB2_OUT4 0x400U // Input Flag Clear for CLB2_OUT4 Signal +#define XBAR_CLR2_CLB2_OUT5 0x800U // Input Flag Clear for CLB2_OUT5 Signal +#define XBAR_CLR2_CLB3_OUT4 0x1000U // Input Flag Clear for CLB3_OUT4 Signal +#define XBAR_CLR2_CLB3_OUT5 0x2000U // Input Flag Clear for CLB3_OUT5 Signal +#define XBAR_CLR2_CLB4_OUT4 0x4000U // Input Flag Clear for CLB4_OUT4 Signal +#define XBAR_CLR2_CLB4_OUT5 0x8000U // Input Flag Clear for CLB4_OUT5 Signal +#define XBAR_CLR2_ECAP1_OUT 0x10000U // Input Flag Clear for ECAP1.OUT Signal +#define XBAR_CLR2_ECAP2_OUT 0x20000U // Input Flag Clear for ECAP2.OUT Signal +#define XBAR_CLR2_ECAP3_OUT 0x40000U // Input Flag Clear for ECAP3.OUT Signal +#define XBAR_CLR2_ECAP4_OUT 0x80000U // Input Flag Clear for ECAP4.OUT Signal +#define XBAR_CLR2_ECAP5_OUT 0x100000U // Input Flag Clear for ECAP5.OUT Signal +#define XBAR_CLR2_ECAP6_OUT 0x200000U // Input Flag Clear for ECAP6.OUT Signal +#define XBAR_CLR2_EXTSYNCOUT 0x400000U // Input Flag Clear for EXTSYNCOUT Signal +#define XBAR_CLR2_ADCAEVT1 0x800000U // Input Flag Clear for ADCAEVT1 Signal +#define XBAR_CLR2_ADCAEVT2 0x1000000U // Input Flag Clear for ADCAEVT2 Signal +#define XBAR_CLR2_ADCAEVT3 0x2000000U // Input Flag Clear for ADCAEVT3 Signal +#define XBAR_CLR2_ADCAEVT4 0x4000000U // Input Flag Clear for ADCAEVT4 Signal +#define XBAR_CLR2_ADCBEVT1 0x8000000U // Input Flag Clear for ADCBEVT1 Signal +#define XBAR_CLR2_ADCBEVT2 0x10000000U // Input Flag Clear for ADCBEVT2 Signal +#define XBAR_CLR2_ADCBEVT3 0x20000000U // Input Flag Clear for ADCBEVT3 Signal +#define XBAR_CLR2_ADCBEVT4 0x40000000U // Input Flag Clear for ADCBEVT4 Signal +#define XBAR_CLR2_ADCCEVT1 0x80000000U // Input Flag Clear for ADCCEVT1 Signal + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XBARCLR3 register +// +//************************************************************************************************* +#define XBAR_CLR3_ADCCEVT2 0x1U // Input Flag Clear for ADCCEVT2 Signal +#define XBAR_CLR3_ADCCEVT3 0x2U // Input Flag Clear for ADCCEVT3 Signal +#define XBAR_CLR3_ADCCEVT4 0x4U // Input Flag Clear for ADCCEVT4 Signal +#define XBAR_CLR3_ADCDEVT1 0x8U // Input Flag Clear for ADCDEVT1 Signal +#define XBAR_CLR3_ADCDEVT2 0x10U // Input Flag Clear for ADCDEVT2 Signal +#define XBAR_CLR3_ADCDEVT3 0x20U // Input Flag Clear for ADCDEVT3 Signal +#define XBAR_CLR3_ADCDEVT4 0x40U // Input Flag Clear for ADCDEVT4 Signal +#define XBAR_CLR3_SD1FLT1_COMPL 0x80U // Input Flag Clear for SD1FLT1.COMPL Signal +#define XBAR_CLR3_SD1FLT1_COMPH 0x100U // Input Flag Clear for SD1FLT1.COMPH Signal +#define XBAR_CLR3_SD1FLT2_COMPL 0x200U // Input Flag Clear for SD1FLT2.COMPL Signal +#define XBAR_CLR3_SD1FLT2_COMPH 0x400U // Input Flag Clear for SD1FLT2.COMPH Signal +#define XBAR_CLR3_SD1FLT3_COMPL 0x800U // Input Flag Clear for SD1FLT3.COMPL Signal +#define XBAR_CLR3_SD1FLT3_COMPH 0x1000U // Input Flag Clear for SD1FLT3.COMPH Signal +#define XBAR_CLR3_SD1FLT4_COMPL 0x2000U // Input Flag Clear for SD1FLT4.COMPL Signal +#define XBAR_CLR3_SD1FLT4_COMPH 0x4000U // Input Flag Clear for SD1FLT4.COMPH Signal +#define XBAR_CLR3_SD2FLT1_COMPL 0x8000U // Input Flag Clear for SD2FLT1.COMPL Signal +#define XBAR_CLR3_SD2FLT1_COMPH 0x10000U // Input Flag Clear for SD2FLT1.COMPH Signal +#define XBAR_CLR3_SD2FLT2_COMPL 0x20000U // Input Flag Clear for SD2FLT2.COMPL Signal +#define XBAR_CLR3_SD2FLT2_COMPH 0x40000U // Input Flag Clear for SD2FLT2.COMPH Signal +#define XBAR_CLR3_SD2FLT3_COMPL 0x80000U // Input Flag Clear for SD2FLT3.COMPL Signal +#define XBAR_CLR3_SD2FLT3_COMPH 0x100000U // Input Flag Clear for SD2FLT3.COMPH Signal +#define XBAR_CLR3_SD2FLT4_COMPL 0x200000U // Input Flag Clear for SD2FLT4.COMPL Signal +#define XBAR_CLR3_SD2FLT4_COMPH 0x400000U // Input Flag Clear for SD2FLT4.COMPH Signal + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/inc/hw_xint.h b/gpio_driverlib_cpu1/device/driverlib/inc/hw_xint.h new file mode 100644 index 0000000..677c2f9 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/inc/hw_xint.h @@ -0,0 +1,108 @@ +//########################################################################### +// +// FILE: hw_xint.h +// +// TITLE: Definitions for the XINT registers. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef HW_XINT_H +#define HW_XINT_H + +//************************************************************************************************* +// +// The following are defines for the XINT register offsets +// +//************************************************************************************************* +#define XINT_O_1CR 0x0U // XINT1 configuration register +#define XINT_O_2CR 0x1U // XINT2 configuration register +#define XINT_O_3CR 0x2U // XINT3 configuration register +#define XINT_O_4CR 0x3U // XINT4 configuration register +#define XINT_O_5CR 0x4U // XINT5 configuration register +#define XINT_O_1CTR 0x8U // XINT1 counter register +#define XINT_O_2CTR 0x9U // XINT2 counter register +#define XINT_O_3CTR 0xAU // XINT3 counter register + + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT1CR register +// +//************************************************************************************************* +#define XINT_1CR_ENABLE 0x1U // XINT1 Enable +#define XINT_1CR_POLARITY_S 2U +#define XINT_1CR_POLARITY_M 0xCU // XINT1 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT2CR register +// +//************************************************************************************************* +#define XINT_2CR_ENABLE 0x1U // XINT2 Enable +#define XINT_2CR_POLARITY_S 2U +#define XINT_2CR_POLARITY_M 0xCU // XINT2 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT3CR register +// +//************************************************************************************************* +#define XINT_3CR_ENABLE 0x1U // XINT3 Enable +#define XINT_3CR_POLARITY_S 2U +#define XINT_3CR_POLARITY_M 0xCU // XINT3 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT4CR register +// +//************************************************************************************************* +#define XINT_4CR_ENABLE 0x1U // XINT4 Enable +#define XINT_4CR_POLARITY_S 2U +#define XINT_4CR_POLARITY_M 0xCU // XINT4 Polarity + +//************************************************************************************************* +// +// The following are defines for the bit fields in the XINT5CR register +// +//************************************************************************************************* +#define XINT_5CR_ENABLE 0x1U // XINT5 Enable +#define XINT_5CR_POLARITY_S 2U +#define XINT_5CR_POLARITY_M 0xCU // XINT5 Polarity + + + +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/interrupt.c b/gpio_driverlib_cpu1/device/driverlib/interrupt.c new file mode 100644 index 0000000..4d628ce --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/interrupt.c @@ -0,0 +1,425 @@ +//########################################################################### +// +// FILE: interrupt.c +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "interrupt.h" + +//***************************************************************************** +// +//! \internal +//! Clears the IFR flag in the CPU. +//! +//! \param group specifies the interrupt group to be cleared. +//! +//! This function clears the IFR flag. This switch is needed because the +//! clearing of the IFR can only be done with a constant. +// +//***************************************************************************** +static void Interrupt_clearIFR(uint16_t group) +{ + switch(group) + { + case 0x0001U: + IFR &= ~(uint16_t)0x0001U; + break; + case 0x0002U: + IFR &= ~(uint16_t)0x0002U; + break; + case 0x0004U: + IFR &= ~(uint16_t)0x0004U; + break; + case 0x0008U: + IFR &= ~(uint16_t)0x0008U; + break; + case 0x0010U: + IFR &= ~(uint16_t)0x0010U; + break; + case 0x0020U: + IFR &= ~(uint16_t)0x0020U; + break; + case 0x0040U: + IFR &= ~(uint16_t)0x0040U; + break; + case 0x0080U: + IFR &= ~(uint16_t)0x0080U; + break; + case 0x0100U: + IFR &= ~(uint16_t)0x0100U; + break; + case 0x0200U: + IFR &= ~(uint16_t)0x0200U; + break; + case 0x0400U: + IFR &= ~(uint16_t)0x0400U; + break; + case 0x0800U: + IFR &= ~(uint16_t)0x0800U; + break; + case 0x1000U: + IFR &= ~(uint16_t)0x1000U; + break; + case 0x2000U: + IFR &= ~(uint16_t)0x2000U; + break; + case 0x4000U: + IFR &= ~(uint16_t)0x4000U; + break; + case 0x8000U: + IFR &= ~(uint16_t)0x8000U; + break; + default: + // + // Invalid group mask. + // + ASSERT((bool)false); + break; + } +} + +//***************************************************************************** +// +// Interrupt_initModule +// +//***************************************************************************** +void +Interrupt_initModule(void) +{ + // + // Disable and clear all interrupts at the CPU + // + (void)Interrupt_disableGlobal(); + IER = 0x0000U; + IFR = 0x0000U; + + // + // Clear all PIEIER registers + // + HWREGH(PIECTRL_BASE + PIE_O_IER1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IER12) = 0U; + + // + // Clear all PIEIFR registers + // + HWREGH(PIECTRL_BASE + PIE_O_IFR1) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR2) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR3) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR4) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR5) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR6) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR7) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR8) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR9) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR10) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR11) = 0U; + HWREGH(PIECTRL_BASE + PIE_O_IFR12) = 0U; + + // + // Enable vector fetching from PIE block + // + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; + +} + +//***************************************************************************** +// +//! The default interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_defaultHandler(void) +{ + uint16_t pieVect; + uint16_t vectID; + + // + // Calculate the vector ID. If the vector is in the lower PIE, it's the + // offset of the vector that was fetched (bits 7:1 of PIECTRL.PIEVECT) + // divided by two. + // + pieVect = HWREGH(PIECTRL_BASE + PIE_O_CTRL); + vectID = (pieVect & 0xFEU) >> 1U; + + // + // If the vector is in the upper PIE, the vector ID is 128 or higher. + // + if(pieVect >= 0x0E00U) + { + vectID += 128U; + } + + // + // Something has gone wrong. An interrupt without a proper registered + // handler function has occurred. To help you debug the issue, local + // variable vectID contains the vector ID of the interrupt that occurred. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default illegal instruction trap interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_illegalOperationHandler(void) +{ + // + // Something has gone wrong. The CPU has tried to execute an illegal + // instruction, generating an illegal instruction trap (ITRAP). + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +//! The default non-maskable interrupt handler. +//! +//! \return None. +// +//***************************************************************************** +__interrupt void Interrupt_nmiHandler(void) +{ + // + // A non-maskable interrupt has occurred, indicating that a hardware error + // has occurred in the system. You can use SysCtl_getNMIFlagStatus() to + // to read the NMIFLG register and determine what caused the NMI. + // + ESTOP0; + for(;;) + { + ; + } +} + +//***************************************************************************** +// +// Interrupt_initVectorTable +// +//***************************************************************************** +void +Interrupt_initVectorTable(void) +{ + uint16_t i; + + EALLOW; + + // + // We skip the first three locations because they are initialized by Boot + // ROM with boot variables. + // + for(i = 3U; i < 224U; i++) + { + HWREG(PIEVECTTABLE_BASE + (2U * i)) = + (uint32_t)Interrupt_defaultHandler; + } + + // + // NMI and ITRAP get their own handlers. + // + HWREG(PIEVECTTABLE_BASE + ((INT_NMI >> 16U) * 2U)) = + (uint32_t)Interrupt_nmiHandler; + HWREG(PIEVECTTABLE_BASE + ((INT_ILLEGAL >> 16U) * 2U)) = + (uint32_t)Interrupt_illegalOperationHandler; + + EDIS; +} + +//***************************************************************************** +// +//Interrupt_enable +// +//***************************************************************************** +void +Interrupt_enable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + // + // Globally disable interrupts but save status + // + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) |= + (uint16_t)1U << ((interruptNumber & 0xFFU) - 1U); + + // + // Enable PIE Group Interrupt + // + IER |= groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER |= (uint16_t)1U << (vectID - 1U); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} + +//***************************************************************************** +// +// Interrupt_disable +// +//***************************************************************************** +void +Interrupt_disable(uint32_t interruptNumber) +{ + bool intsDisabled; + uint16_t intGroup; + uint16_t groupMask; + uint16_t vectID; + + vectID = (uint16_t)(interruptNumber >> 16U); + + intsDisabled = Interrupt_disableGlobal(); + + // + // PIE Interrupts + // + if(vectID >= 0x20U) + { + intGroup = (uint16_t)(((interruptNumber & 0xFF00UL) >> 8U) - 1U); + groupMask = (uint16_t)1U << intGroup; + + // + // Disable individual PIE interrupt + // + HWREGH((PIECTRL_BASE + PIE_O_IER1 + (intGroup * 2U))) &= + ~(1U << ((interruptNumber & 0xFFUL) - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR(groupMask); + + // + // Acknowledge any interrupts + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = groupMask; + } + + // + // INT13, INT14, DLOGINT, & RTOSINT + // + else if((vectID >= 0x0DU) && (vectID <= 0x10U)) + { + IER &= ~((uint16_t)1U << (vectID - 1U)); + + // + // Wait for any pending interrupts to get to the CPU + // + NOP; + NOP; + NOP; + NOP; + NOP; + + Interrupt_clearIFR((uint16_t)1U << (vectID - 1U)); + } + else + { + // + // Other interrupts + // + } + + // + // Re-enable interrupts if they were enabled + // + if(!intsDisabled) + { + (void)Interrupt_enableGlobal(); + } +} diff --git a/gpio_driverlib_cpu1/device/driverlib/interrupt.h b/gpio_driverlib_cpu1/device/driverlib/interrupt.h new file mode 100644 index 0000000..05a555a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/interrupt.h @@ -0,0 +1,497 @@ +//########################################################################### +// +// FILE: interrupt.h +// +// TITLE: C28x Interrupt (PIE) driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef INTERRUPT_H +#define INTERRUPT_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +#ifdef __TMS320C28XX__ + +//***************************************************************************** +// +//! \addtogroup interrupt_api Interrupt +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_ints.h" +#include "inc/hw_memmap.h" +#include "inc/hw_pie.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_enableInCPU() +// and Interrupt_disableInCPU() functions as the cpuInterrupt parameter. +// +//***************************************************************************** +#define INTERRUPT_CPU_INT1 0x1U //!< CPU Interrupt Number 1 +#define INTERRUPT_CPU_INT2 0x2U //!< CPU Interrupt Number 2 +#define INTERRUPT_CPU_INT3 0x4U //!< CPU Interrupt Number 3 +#define INTERRUPT_CPU_INT4 0x8U //!< CPU Interrupt Number 4 +#define INTERRUPT_CPU_INT5 0x10U //!< CPU Interrupt Number 5 +#define INTERRUPT_CPU_INT6 0x20U //!< CPU Interrupt Number 6 +#define INTERRUPT_CPU_INT7 0x40U //!< CPU Interrupt Number 7 +#define INTERRUPT_CPU_INT8 0x80U //!< CPU Interrupt Number 8 +#define INTERRUPT_CPU_INT9 0x100U //!< CPU Interrupt Number 9 +#define INTERRUPT_CPU_INT10 0x200U //!< CPU Interrupt Number 10 +#define INTERRUPT_CPU_INT11 0x400U //!< CPU Interrupt Number 11 +#define INTERRUPT_CPU_INT12 0x800U //!< CPU Interrupt Number 12 +#define INTERRUPT_CPU_INT13 0x1000U //!< CPU Interrupt Number 13 +#define INTERRUPT_CPU_INT14 0x2000U //!< CPU Interrupt Number 14 +#define INTERRUPT_CPU_DLOGINT 0x4000U //!< CPU Data Log Interrupt +#define INTERRUPT_CPU_RTOSINT 0x8000U //!< CPU RTOS Interrupt + +//***************************************************************************** +// +// The following are values that can be passed to the Interrupt_clearACKGroup() +// function as the group parameter. +// +//***************************************************************************** +#define INTERRUPT_ACK_GROUP1 0x1U //!< Acknowledge PIE Interrupt Group 1 +#define INTERRUPT_ACK_GROUP2 0x2U //!< Acknowledge PIE Interrupt Group 2 +#define INTERRUPT_ACK_GROUP3 0x4U //!< Acknowledge PIE Interrupt Group 3 +#define INTERRUPT_ACK_GROUP4 0x8U //!< Acknowledge PIE Interrupt Group 4 +#define INTERRUPT_ACK_GROUP5 0x10U //!< Acknowledge PIE Interrupt Group 5 +#define INTERRUPT_ACK_GROUP6 0x20U //!< Acknowledge PIE Interrupt Group 6 +#define INTERRUPT_ACK_GROUP7 0x40U //!< Acknowledge PIE Interrupt Group 7 +#define INTERRUPT_ACK_GROUP8 0x80U //!< Acknowledge PIE Interrupt Group 8 +#define INTERRUPT_ACK_GROUP9 0x100U //!< Acknowledge PIE Interrupt Group 9 +#define INTERRUPT_ACK_GROUP10 0x200U //!< Acknowledge PIE Interrupt Group 10 +#define INTERRUPT_ACK_GROUP11 0x400U //!< Acknowledge PIE Interrupt Group 11 +#define INTERRUPT_ACK_GROUP12 0x800U //!< Acknowledge PIE Interrupt Group 12 +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! The default interrupt handler. +//! +//! This is the default interrupt handler. The Interrupt_initVectorTable() +//! function sets all vectors to this function. Also, when an interrupt is +//! unregistered using the Interrupt_unregister() function, this handler takes +//! its place. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_defaultHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default illegal instruction trap interrupt handler. +//! +//! This is the default interrupt handler for an illegal instruction trap +//! (ITRAP). The Interrupt_initVectorTable() function sets the appropriate +//! vector to this function. This should never be called during normal +//! operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with +//! an appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_illegalOperationHandler(void); + +//***************************************************************************** +// +//! \internal +//! The default non-maskable interrupt handler. +//! +//! This is the default interrupt handler for a non-maskable interrupt (NMI). +//! The Interrupt_initVectorTable() function sets the appropriate vector to +//! this function. This should never be called during normal operation. +//! +//! The ESTOP0 statement is for debug purposes only. Remove and replace with an +//! appropriate error handling routine for your program. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_nmiHandler(void); + +//***************************************************************************** +// +//! Allows the CPU to process interrupts. +//! +//! This function clears the global interrupt mask bit (INTM) in the CPU, +//! allowing the processor to respond to interrupts. +//! +//! \return Returns \b true if interrupts were disabled when the function was +//! called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_enableGlobal(void) +{ + // + // Enable processor interrupts. + // + return(((__enable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Stops the CPU from processing interrupts. +//! +//! This function sets the global interrupt mask bit (INTM) in the CPU, +//! preventing the processor from receiving maskable interrupts. +//! +//! \return Returns \b true if interrupts were already disabled when the +//! function was called or \b false if they were initially enabled. +// +//***************************************************************************** +static inline bool +Interrupt_disableGlobal(void) +{ + // + // Disable processor interrupts. + // + return(((__disable_interrupts() & 0x1U) != 0U) ? true : false); +} + +//***************************************************************************** +// +//! Registers a function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! \param handler is a pointer to the function to be called. +//! +//! This function is used to specify the handler function to be called when the +//! given interrupt is asserted to the processor. When the interrupt occurs, +//! if it is enabled (via Interrupt_enable()), the handler function will be +//! called in interrupt context. Since the handler function can preempt other +//! code, care must be taken to protect memory or peripherals that are accessed +//! by the handler and other non-handler code. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \note This function assumes that the PIE has been enabled. See +//! Interrupt_initModule(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_register(uint32_t interruptNumber, void (*handler)(void)) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)handler; + EDIS; +} + +//***************************************************************************** +// +//! Unregisters the function to be called when an interrupt occurs. +//! +//! \param interruptNumber specifies the interrupt in question. +//! +//! This function is used to indicate that a default handler +//! Interrupt_defaultHandler() should be called when the given interrupt is +//! asserted to the processor. Call Interrupt_disable() to disable +//! the interrupt before calling this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \sa Interrupt_register() for important information about registering +//! interrupt handlers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_unregister(uint32_t interruptNumber) +{ + uint32_t address; + + // + // Calculate appropriate address for the interrupt number + // + address = (uint32_t)PIEVECTTABLE_BASE + + (((interruptNumber & 0xFFFF0000U) >> 16U) * 2U); + + // + // Copy default ISR address into PIE table + // + EALLOW; + HWREG(address) = (uint32_t)Interrupt_defaultHandler; + EDIS; +} + +//***************************************************************************** +// +//! Enables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be enabled. +//! +//! This function enables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enableInCPU(uint16_t cpuInterrupt) +{ + // + // Set the interrupt bits in the CPU. + // + IER |= cpuInterrupt; +} + +//***************************************************************************** +// +//! Disables CPU interrupt channels +//! +//! \param cpuInterrupt specifies the CPU interrupts to be disabled. +//! +//! This function disables the specified interrupts in the CPU. The +//! \e cpuInterrupt parameter is a logical OR of the values +//! \b INTERRUPT_CPU_INTx where x is the interrupt number between 1 and 14, +//! \b INTERRUPT_CPU_DLOGINT, and \b INTERRUPT_CPU_RTOSINT. +//! +//! \note Note that interrupts 1-12 correspond to the PIE groups with those +//! same numbers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disableInCPU(uint16_t cpuInterrupt) +{ + // + // Clear the interrupt bits in the CPU. + // + IER &= ~cpuInterrupt; +} + +//***************************************************************************** +// +//! Acknowledges PIE Interrupt Group +//! +//! \param group specifies the interrupt group to be acknowledged. +//! +//! The specified interrupt group is acknowledged and clears any interrupt +//! flag within that respective group. +//! +//! The \e group parameter must be a logical OR of the following: +//! \b INTERRUPT_ACK_GROUP1, \b INTERRUPT_ACK_GROUP2, \b INTERRUPT_ACK_GROUP3 +//! \b INTERRUPT_ACK_GROUP4, \b INTERRUPT_ACK_GROUP5, \b INTERRUPT_ACK_GROUP6 +//! \b INTERRUPT_ACK_GROUP7, \b INTERRUPT_ACK_GROUP8, \b INTERRUPT_ACK_GROUP9 +//! \b INTERRUPT_ACK_GROUP10, \b INTERRUPT_ACK_GROUP11, +//! \b INTERRUPT_ACK_GROUP12. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_clearACKGroup(uint16_t group) +{ + // + // Set interrupt group acknowledge bits + // + HWREGH(PIECTRL_BASE + PIE_O_ACK) = group; +} + +//***************************************************************************** +// +//! Enables the PIE block. +//! +//! This function enables the vector fetching for the peripheral interrupts by +//! enabling the PIE block. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_enablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) |= PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Disables the PIE block. +//! +//! This function disables the vector fetching for the peripheral interrupts by +//! disabling the PIE block. PIEACK, PIEIFR, and PIEIER registers can be +//! accessed even when the PIE block is disabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +Interrupt_disablePIE(void) +{ + HWREGH(PIECTRL_BASE + PIE_O_CTRL) &= ~PIE_CTRL_ENPIE; +} + +//***************************************************************************** +// +//! Initializes the PIE control registers by setting them to a known state. +//! +//! This function initializes the PIE control registers. After globally +//! disabling interrupts and enabling the PIE, it clears all of the PIE +//! interrupt enable bits and interrupt flags. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initModule(void); + +//***************************************************************************** +// +//! Initializes the PIE vector table by setting all vectors to a default +//! handler function. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_initVectorTable(void); + +//***************************************************************************** +// +//! Enables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be enabled. +//! +//! The specified interrupt is enabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_enable(uint32_t interruptNumber); + +//***************************************************************************** +// +//! Disables an interrupt. +//! +//! \param interruptNumber specifies the interrupt to be disabled. +//! +//! The specified interrupt is disabled in the interrupt controller. Other +//! enables for the interrupt (such as at the peripheral level) are unaffected +//! by this function. +//! +//! The available \e interruptNumber values are supplied in +//! inc/hw_ints.h. +//! +//! \return None. +// +//***************************************************************************** +extern void +Interrupt_disable(uint32_t interruptNumber); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +#endif // #ifdef __TMS320C28XX__ + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // INTERRUPT_H diff --git a/gpio_driverlib_cpu1/device/driverlib/ipc.c b/gpio_driverlib_cpu1/device/driverlib/ipc.c new file mode 100644 index 0000000..8d6982e --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/ipc.c @@ -0,0 +1,445 @@ +//########################################################################### +// +// FILE: ipc.c +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "ipc.h" + +// +// Macros internal to the IPC driver +// + +#define IPC_ADDR_OFFSET_NOCHANGE 2U +#define IPC_ADDR_OFFSET_MUL2 4U +#define IPC_ADDR_OFFSET_DIV2 1U + +#define IPC_ADDR_OFFSET_CORR(addr, corr) (((addr) * (corr)) / 2U) + +#if IPC_MSGQ_SUPPORT == 1U + +// +// Global Circular Buffer Definitions +// + + +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_PutBuffer, "MSGRAM_CPU1_TO_CPU2") +#pragma DATA_SECTION(IPC_CPU1_To_CPU2_GetBuffer, "MSGRAM_CPU2_TO_CPU1") + +// +// IPC_CPU1_To_CPU2_PutBuffer acts as IPC_CPU2_To_CPU1_GetBuffer and +// IPC_CPU1_To_CPU2_GetBuffer acts as IPC_CPU2_To_CPU1_PutBuffer +// +IPC_PutBuffer_t IPC_CPU1_To_CPU2_PutBuffer; +IPC_GetBuffer_t IPC_CPU1_To_CPU2_GetBuffer; +#endif + +const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM] = { + + /* IPC_CPU1_L_CPU2_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = &IPC_CPU1_To_CPU2_PutBuffer, + .IPC_GetBuffer = &IPC_CPU1_To_CPU2_GetBuffer +#endif + }, + + /* IPC_CPU2_L_CPU1_R */ + { + .IPC_Flag_Ctr_Reg = (volatile IPC_Flag_Ctr_Reg_t *) IPC_BASE, + .IPC_SendCmd_Reg = (volatile IPC_SendCmd_Reg_t *) + (IPC_BASE + 0x18U), + .IPC_RecvCmd_Reg = (volatile IPC_RecvCmd_Reg_t *) + (IPC_BASE + 0x10U), + .IPC_Boot_Pump_Reg = (volatile IPC_Boot_Pump_Reg_t *) + (IPC_BASE + 0x20U), + .IPC_IntNum = {INT_IPC_0, INT_IPC_1, INT_IPC_2, INT_IPC_3, + 0U, 0U, 0U, 0U}, + .IPC_MsgRam_LtoR = CPU2_TO_CPU1_MSG_RAM_BASE, + .IPC_MsgRam_RtoL = CPU1_TO_CPU2_MSG_RAM_BASE, + .IPC_Offset_Corr = IPC_ADDR_OFFSET_NOCHANGE +#if IPC_MSGQ_SUPPORT == 1U + , + .IPC_PutBuffer = (IPC_PutBuffer_t *)&IPC_CPU1_To_CPU2_GetBuffer, + .IPC_GetBuffer = (IPC_GetBuffer_t *)&IPC_CPU1_To_CPU2_PutBuffer +#endif + } +}; + +//***************************************************************************** +// +// IPC_sendCommand +// +//***************************************************************************** +bool IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data) +{ + bool ret; + + // + // Check whether the flags are not busy + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) == 0U) + { + ret = true; + + if(addrCorrEnable) + { + // + // Update the command registers. ADDR register holds the offset + // from the base address of the MSG RAM + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = + addr - IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + else + { + // + // Update the command registers. addr param remains as is. + // + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDCOM = command; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDDATA = data; + IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_SENDADDR = addr; + } + + // + // Set the flags to indicate the remote core + // + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; + } + else + { + ret = false; + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readCommand +// +//***************************************************************************** +bool IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data) +{ + bool ret; + uint32_t addrReg; + + // + // Check whether the flags are not empty + // + if((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U) + { + ret = true; + + // + // Read the command registers + // + *command = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVCOM; + addrReg = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVADDR; + *data = IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_RECVDATA; + + if(addrCorrEnable) + { + // + // Calculate the address form the offset + // + *addr = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(addrReg, + IPC_Instance[ipcType].IPC_Offset_Corr); + + } + else + { + *addr = addrReg; + } + + } + else + { + ret = false; + } + + return(ret); +} + + +//***************************************************************************** +// +// IPC_registerInterrupt +// +//***************************************************************************** +void IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Register the interrupt handler + // + + Interrupt_register(intNum, pfnHandler); + + // + // Enable the interrupt + // + Interrupt_enable(intNum); +} + +//***************************************************************************** +// +// IPC_unregisterInterrupt +// +//***************************************************************************** +void IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt) +{ + // + // Check for arguments + // + + ASSERT(ipcInt <= IPC_INT3); + + // + // Get the corresponding interrupt number + // + uint32_t intNum = IPC_Instance[ipcType].IPC_IntNum[ipcInt]; + + // + // Disable the interrupt. + // + Interrupt_disable(intNum); + + // + // Unregister the interrupt handler. + // + + Interrupt_unregister(intNum); +} + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// IPCinitMessageQueue +// +//***************************************************************************** +void IPC_initMessageQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(ipcInt_L < IPC_NUM_OF_INTERRUPTS); + ASSERT(ipcInt_R < IPC_NUM_OF_INTERRUPTS); + + IPC_PutBuffer_t *putBuffer = IPC_Instance[ipcType].IPC_PutBuffer; + IPC_GetBuffer_t *getBuffer = IPC_Instance[ipcType].IPC_GetBuffer; + + // + // L->R Put Buffer and Index Initialization + // + msgQueue->PutBuffer = putBuffer->Buffer[ipcInt_R]; + msgQueue->PutWriteIndex = &(putBuffer->PutWriteIndex[ipcInt_R]); + msgQueue->GetReadIndex = &(putBuffer->GetReadIndex[ipcInt_L]); + msgQueue->PutFlag = (uint32_t)1U << ipcInt_R; + + // + // L->R Get Buffer and Index Initialization + // + msgQueue->GetBuffer = getBuffer->Buffer[ipcInt_L]; + msgQueue->GetWriteIndex = &(getBuffer->GetWriteIndex[ipcInt_L]); + msgQueue->PutReadIndex = &(getBuffer->PutReadIndex[ipcInt_R]); + + // + // Initialize PutBuffer WriteIndex = 0 and GetBuffer ReadIndex = 0 + // + *(msgQueue->PutWriteIndex) = 0U; + *(msgQueue->GetReadIndex) = 0U; +} + +//***************************************************************************** +// +// IPC_sendMessageToQueue +// +//***************************************************************************** +bool IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->PutWriteIndex); + readIndex = *(msgQueue->PutReadIndex); + + // + // Wait until Put Buffer slot is free + // + while(((writeIndex + 1U) & IPC_MAX_BUFFER_INDEX) == readIndex) + { + // + // If designated as a "Blocking" function, and Put buffer is full, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + readIndex = *(msgQueue->PutReadIndex); + } + + if(ret != false) + { + // + // When slot is free, Write Message to PutBuffer, update PutWriteIndex, + // and set the CPU IPC INT Flag + // + msgQueue->PutBuffer[writeIndex] = *msg; + + if(addrCorrEnable) + { + msgQueue->PutBuffer[writeIndex].address -= + IPC_Instance[ipcType].IPC_MsgRam_LtoR; + } + + writeIndex = (writeIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->PutWriteIndex) = writeIndex; + + IPC_setFlagLtoR(ipcType, msgQueue->PutFlag); + } + + return(ret); +} + +//***************************************************************************** +// +// IPC_readMessageFromQueue +// +//***************************************************************************** +bool IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block) +{ + // + // Check for arguments + // + ASSERT(msgQueue != NULL); + ASSERT(msg != NULL); + + uint16_t writeIndex; + uint16_t readIndex; + bool ret = true; + + writeIndex = *(msgQueue->GetWriteIndex); + readIndex = *(msgQueue->GetReadIndex); + + // + // Loop while GetBuffer is empty + // + while(writeIndex == readIndex) + { + // + // If designated as a "Blocking" function, and Get buffer is empty, + // return immediately with fail status. + // + if(!block) + { + ret = false; + break; + } + + writeIndex = *(msgQueue->GetWriteIndex); + } + + if(ret != false) + { + // + // If there is a message in GetBuffer, Read Message and update + // the ReadIndex + // + *msg = msgQueue->GetBuffer[readIndex]; + if(addrCorrEnable) + { + msg->address = IPC_Instance[ipcType].IPC_MsgRam_RtoL + + IPC_ADDR_OFFSET_CORR(msg->address, + IPC_Instance[ipcType].IPC_Offset_Corr); + } + + readIndex = (readIndex + 1U) & IPC_MAX_BUFFER_INDEX; + *(msgQueue->GetReadIndex) = readIndex; + } + + return(ret); +} +#endif diff --git a/gpio_driverlib_cpu1/device/driverlib/ipc.h b/gpio_driverlib_cpu1/device/driverlib/ipc.h new file mode 100644 index 0000000..8da7688 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/ipc.h @@ -0,0 +1,880 @@ +//########################################################################### +// +// FILE: ipc.h +// +// TITLE: C28x IPC driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef IPC_H +#define IPC_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup ipc_api IPC +//! \brief This module is used for inter-processor communications. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "debug.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_ipc.h" +#include "inc/hw_ints.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the APIs +// +//***************************************************************************** +//***************************************************************************** +// +// Driver configuration macros +// +//***************************************************************************** +#define IPC_MSGQ_SUPPORT 1U + +// +// Number of IPC messages in circular buffer (must be interval of 2) +// +#define IPC_BUFFER_SIZE 4U + +// +// Number of IPC interrupts using circular buffer (must be same number on both +// CPUs) +// +#define IPC_NUM_OF_INTERRUPTS 4U + +//***************************************************************************** +// +// Values that can be passed as parameter flags in all the IPC API functions. +// +//***************************************************************************** +#ifndef IPC_FLAGS_DEFINED +#define IPC_FLAGS_DEFINED +#define IPC_NO_FLAG 0x00000000U //!< NO FLAG +#define IPC_FLAG0 0x00000001U //!< IPC FLAG 0 +#define IPC_FLAG1 0x00000002U //!< IPC FLAG 1 +#define IPC_FLAG2 0x00000004U //!< IPC FLAG 2 +#define IPC_FLAG3 0x00000008U //!< IPC FLAG 3 +#define IPC_FLAG4 0x00000010U //!< IPC FLAG 4 +#define IPC_FLAG5 0x00000020U //!< IPC FLAG 5 +#define IPC_FLAG6 0x00000040U //!< IPC FLAG 6 +#define IPC_FLAG7 0x00000080U //!< IPC FLAG 7 +#define IPC_FLAG8 0x00000100U //!< IPC FLAG 8 +#define IPC_FLAG9 0x00000200U //!< IPC FLAG 9 +#define IPC_FLAG10 0x00000400U //!< IPC FLAG 10 +#define IPC_FLAG11 0x00000800U //!< IPC FLAG 11 +#define IPC_FLAG12 0x00001000U //!< IPC FLAG 12 +#define IPC_FLAG13 0x00002000U //!< IPC FLAG 13 +#define IPC_FLAG14 0x00004000U //!< IPC FLAG 14 +#define IPC_FLAG15 0x00008000U //!< IPC FLAG 15 +#define IPC_FLAG16 0x00010000U //!< IPC FLAG 16 +#define IPC_FLAG17 0x00020000U //!< IPC FLAG 17 +#define IPC_FLAG18 0x00040000U //!< IPC FLAG 18 +#define IPC_FLAG19 0x00080000U //!< IPC FLAG 19 +#define IPC_FLAG20 0x00100000U //!< IPC FLAG 20 +#define IPC_FLAG21 0x00200000U //!< IPC FLAG 21 +#define IPC_FLAG22 0x00400000U //!< IPC FLAG 22 +#define IPC_FLAG23 0x00800000U //!< IPC FLAG 23 +#define IPC_FLAG24 0x01000000U //!< IPC FLAG 24 +#define IPC_FLAG25 0x02000000U //!< IPC FLAG 25 +#define IPC_FLAG26 0x04000000U //!< IPC FLAG 26 +#define IPC_FLAG27 0x08000000U //!< IPC FLAG 27 +#define IPC_FLAG28 0x10000000U //!< IPC FLAG 28 +#define IPC_FLAG29 0x20000000U //!< IPC FLAG 29 +#define IPC_FLAG30 0x40000000U //!< IPC FLAG 30 +#define IPC_FLAG31 0x80000000U //!< IPC FLAG 31 +#define IPC_FLAG_ALL 0xFFFFFFFFU //!< All IPC flags +#endif + +//***************************************************************************** +// +// Values that can be passed as parameter ipcInt in +// IPC_registerInterrupt and IPC_unregisterInterrupt functions. +// Please refer to the datasheet for the actual number of interrupts available +// for each IPC instance +// +//***************************************************************************** +#define IPC_INT0 0x0U //!< IPC Interrupt 0 +#define IPC_INT1 0x1U //!< IPC Interrupt 1 +#define IPC_INT2 0x2U //!< IPC Interrupt 2 +#define IPC_INT3 0x3U //!< IPC Interrupt 3 +#define IPC_INT4 0x4U //!< IPC Interrupt 4 +#define IPC_INT5 0x5U //!< IPC Interrupt 5 +#define IPC_INT6 0x6U //!< IPC Interrupt 6 +#define IPC_INT7 0x7U //!< IPC Interrupt 7 + +//***************************************************************************** +// +// Values that can be passed as parameter addrCorrEnable in +// IPC_sendCommand, IPC_readCommand, IPC_sendMessageToQueue and +// IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_ADDR_CORRECTION_ENABLE true +#define IPC_ADDR_CORRECTION_DISABLE false + +//***************************************************************************** +// +// Values that can be passed as parameter block in +// IPC_sendMessageToQueue and IPC_readMessageFromQueue functions. +// +//***************************************************************************** +#define IPC_BLOCKING_CALL true +#define IPC_NONBLOCKING_CALL false + + + +//***************************************************************************** +// +// Internal macros used for message queue implementation +// +//***************************************************************************** +#define IPC_MAX_BUFFER_INDEX (IPC_BUFFER_SIZE - 1U) + +//***************************************************************************** +// +// Enums for the APIs +// +//***************************************************************************** + +//***************************************************************************** +// +//! Values that can be passed as parameter \e ipcType in all the driver +//! functions +// +//***************************************************************************** +typedef enum +{ + IPC_CPU1_L_CPU2_R, //!< CPU1 - Local core, CPU2 - Remote core + IPC_CPU2_L_CPU1_R, //!< CPU2 - Local core, CPU1 - Remote core + IPC_TOTAL_NUM +}IPC_Type_t; + +//***************************************************************************** +// +// Internal structs for register and messaage queue accesses +// +//***************************************************************************** +typedef struct +{ + uint32_t IPC_ACK; + uint32_t IPC_STS; + uint32_t IPC_SET; + uint32_t IPC_CLR; + uint32_t IPC_FLG; + uint32_t IPC_RSVDREG; + uint32_t IPC_COUNTERL; + uint32_t IPC_COUNTERH; +}IPC_Flag_Ctr_Reg_t; + +typedef struct +{ + uint32_t IPC_SENDCOM; + uint32_t IPC_SENDADDR; + uint32_t IPC_SENDDATA; + uint32_t IPC_REMOTEREPLY; +}IPC_SendCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_RECVCOM; + uint32_t IPC_RECVADDR; + uint32_t IPC_RECVDATA; + uint32_t IPC_LOCALREPLY; +}IPC_RecvCmd_Reg_t; + +typedef struct +{ + uint32_t IPC_BOOTSTS; + uint32_t IPC_BOOTMODE; +}IPC_Boot_Pump_Reg_t; + +#if IPC_MSGQ_SUPPORT == 1U +typedef struct +{ + uint32_t command; + uint32_t address; + uint32_t dataw1; + uint32_t dataw2; +}IPC_Message_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t PutWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t GetReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_PutBuffer_t; + +typedef struct +{ + IPC_Message_t Buffer[IPC_NUM_OF_INTERRUPTS][IPC_BUFFER_SIZE]; + uint16_t GetWriteIndex[IPC_NUM_OF_INTERRUPTS]; + uint16_t PutReadIndex[IPC_NUM_OF_INTERRUPTS]; +}IPC_GetBuffer_t; +#endif + +//***************************************************************************** +// +// Internal struct used to store the required information regarding an IPC +// instance +// +//***************************************************************************** +typedef struct +{ + volatile IPC_Flag_Ctr_Reg_t *IPC_Flag_Ctr_Reg; + volatile IPC_SendCmd_Reg_t *IPC_SendCmd_Reg; + volatile IPC_RecvCmd_Reg_t *IPC_RecvCmd_Reg; + volatile IPC_Boot_Pump_Reg_t *IPC_Boot_Pump_Reg; + uint32_t IPC_IntNum[8U]; + uint32_t IPC_MsgRam_LtoR; + uint32_t IPC_MsgRam_RtoL; + uint32_t IPC_Offset_Corr; +#if IPC_MSGQ_SUPPORT == 1U + IPC_PutBuffer_t *IPC_PutBuffer; + IPC_GetBuffer_t *IPC_GetBuffer; +#endif +}IPC_Instance_t; + +extern const IPC_Instance_t IPC_Instance[IPC_TOTAL_NUM]; + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +// A structure that defines an IPC message queue. These +// fields are used by the IPC drivers, and normally it is not necessary for +// user software to directly read or write fields in the table. +// +//***************************************************************************** + +typedef struct +{ + IPC_Message_t * PutBuffer; + uint32_t PutFlag; + uint16_t * PutWriteIndex; + uint16_t * PutReadIndex; + IPC_Message_t * GetBuffer; + uint16_t * GetWriteIndex; + uint16_t * GetReadIndex; +} IPC_MessageQueue_t; +#endif + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** + +//***************************************************************************** +// +//! Local core sets Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being set +//! +//! This function will allow the Local core system to set the designated IPC +//! flags to send to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_SET = flags; +} + +//***************************************************************************** +// +//! Local core clears Local to Remote IPC Flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being cleared +//! +//! This function will allow the Local core system to clear the designated IPC +//! flags sent to the Remote core system. The \e flags parameter can be any +//! of the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_clearFlagLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_CLR = flags; +} + +//***************************************************************************** +// +//! Local core acknowledges Remote to Local IPC Flag. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags being acknowledged. +//! +//! This function will allow the Local core system to acknowledge/clear the IPC +//! flag set by the Remote core system. The \e flags parameter can be any of +//! the IPC flag values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_ackFlagRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_ACK = flags; +} + +//***************************************************************************** +// +//! Determines whether the given IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Local to Remote IPC flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Local to Remote +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyLtoR(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flags) != 0U); +} + +//***************************************************************************** +// +//! Determines whether the given Remote to Local IPC flags are busy or not. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the Remote to Local IPC Flag masks to check the status of +//! +//! Allows the caller to determine whether the designated Remote to Local +//! IPC flags are pending. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return Returns \b true if the any of the designated IPC flags are busy +//! or \b false if all the designated IPC flags are free. +// +//***************************************************************************** +static inline bool +IPC_isFlagBusyRtoL(IPC_Type_t ipcType, uint32_t flags) +{ + return((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flags) != 0U); +} + +//***************************************************************************** +// +//! Wait for the remote core to send a flag +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the Remote to Local IPC flag mask to wait for +//! +//! Allows the caller to wait for the Remote to Local flag to be send by +//! the remote core. The \e flags parameter can be any of the IPC flag +//! values: \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForFlag(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_STS & flag) == 0U) + { + } +} + +//***************************************************************************** +// +//! Wait for the IPC flag to be acknowledged +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask for which ack is pending +//! +//! Allows the caller to wait for the IPC flag to be acknowledged by the +//! remote core. The \e flagsparameter can be any of the IPC flag values: +//! \b IPC_FLAG0 - \b IPC_FLAG31. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_waitForAck(IPC_Type_t ipcType, uint32_t flag) +{ + while((IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_FLG & flag) != 0U) + { + } +} + +//***************************************************************************** +// +//! Synchronises the two cores +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flag is the IPC flag mask with which synchronisation is done +//! +//! Allows the local and remote cores to synchronise. Neither core will return +//! from this function call before the other core enters it. +//! +//! \note Must be called with same flag mask on both the cores +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_sync(IPC_Type_t ipcType, uint32_t flag) +{ + IPC_setFlagLtoR(ipcType, flag); + IPC_waitForFlag(ipcType, flag); + IPC_ackFlagRtoL(ipcType, flag); + IPC_waitForAck(ipcType, flag); +} + +//***************************************************************************** +// +//! Initialize IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +// +//! This function initializes IPC by clearing all the flags +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_init(IPC_Type_t ipcType) +{ + IPC_clearFlagLtoR(ipcType, IPC_FLAG_ALL); +} + +//***************************************************************************** +// +//! Sends a command to the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags to be set +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit command value +//! \param addr is the 32-bit address to be sent as part of command +//! \param data is the 32-bit data to be sent as part of command +//! +//! Allows the caller to send a command to the remote core. A command consists +//! of a unique command value, a 32-bit address and a 32-bit data. The function +//! also sends the designated flags to the remote core. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! The application shall use the function IPC_getResponse to read the response +//! sent by the remote core. +//! +//! \note The application is expected to wait until the the response is +//! received before sending another command. +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is sent properly and \b false if +//! the designated flags were busy and hence command was not sent. +// +//***************************************************************************** +extern bool +IPC_sendCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t command, uint32_t addr, uint32_t data); + +//***************************************************************************** +// +//! Reads a command sent by the Remote core +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param flags is the IPC flag mask for the flags sent by the remote core +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param command is the 32-bit pointer at which the command value is read to +//! \param addr is the 32-bit pointer at which address value is read to +//! \param data is the 32-bit pointer at which the data is read to +//! +//! Allows the caller to read a command sent by the remote core. A command +//! consists of a unique command value, a 32-bit address and a 32-bit data. +//! There may be differences in the address spaces of Local and Remote core. +//! For example in case of F2838X device, the address spaces of C28x core and +//! CM core are different. In case the \e addr refers to an address in the IPC +//! MSG RAM, \e addrCorrEnable param may be used to correct the address mismatch +//! +//! The \e flags parameter can be any of the IPC flag values: \b IPC_FLAG0 - +//! \b IPC_FLAG31. +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! +//! \note The application is expected to acknowledge the flag and send a +//! response (if needed) after reading the command +//! +//! \note \e addrCorrEnable parameter must be kept same on the sending and +//! receiving cores +//! +//! \return Returns \b true if the command is read properly and \b false if +//! the designated flags were empty and hence command was not read. +// +//***************************************************************************** +extern bool +IPC_readCommand(IPC_Type_t ipcType, uint32_t flags, bool addrCorrEnable, + uint32_t *command, uint32_t *addr, uint32_t *data); + +//***************************************************************************** +// +//! Sends the response to the command sent by remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param data is the 32-bit value of the response to be sent +//! +//! Allows the caller to send a response to the command previously sent by the +//! remote core +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_sendResponse(IPC_Type_t ipcType, uint32_t data) +{ + IPC_Instance[ipcType].IPC_RecvCmd_Reg->IPC_LOCALREPLY = data; +} + +//***************************************************************************** +// +//! Reads the response from the remote core. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the response sent by the remote core to the +//! command previously sent by the local core +//! +//! \return the 32-bit value of the response. +// +//***************************************************************************** +static inline uint32_t +IPC_getResponse(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_SendCmd_Reg->IPC_REMOTEREPLY); +} + +//***************************************************************************** +// +//! Sets the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param mode is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! \note This function shall be called by CPU1 only. +//! +//! \return None +// +//***************************************************************************** +static inline void +IPC_setBootMode(IPC_Type_t ipcType, uint32_t mode) +{ + ASSERT(ipcType == IPC_CPU1_L_CPU2_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE = mode; +} + +//***************************************************************************** +// +//! Reads the BOOTMODE register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTMODE register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootMode(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTMODE); +} + +//***************************************************************************** +// +//! Sets the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param status is the 32-bit value to be set +//! +//! Allows the caller to set the BOOTSTS register. +//! +//! \note This function shall be called by CPU2 and CM only +//! +//! \note This function shall be called by CPU2 only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +IPC_setBootStatus(IPC_Type_t ipcType, uint32_t status) +{ + ASSERT(ipcType == IPC_CPU2_L_CPU1_R); + + IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS = status; +} + +//***************************************************************************** +// +//! Reads the BOOTSTS register. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to set the BOOTMODE register. +//! +//! +//! \return 32-bit value of the BOOOTSTS register +// +//***************************************************************************** +static inline uint32_t +IPC_getBootStatus(IPC_Type_t ipcType) +{ + return(IPC_Instance[ipcType].IPC_Boot_Pump_Reg->IPC_BOOTSTS); +} + +//***************************************************************************** +// +//! Reads the timestamp counter value. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! +//! Allows the caller to read the IPC timestamp counter value. +//! +//! \return 64-bit counter value. +// +//***************************************************************************** +static inline uint64_t +IPC_getCounter(IPC_Type_t ipcType) +{ + // + // Get the Counter High and Low values. Read to the Counter low register + // saves the value of Counter High register. + // + uint32_t ctrL = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERL; + uint32_t ctrH = IPC_Instance[ipcType].IPC_Flag_Ctr_Reg->IPC_COUNTERH; + + // + // Return the 64-bit value of the counter + // + return(((uint64_t)ctrH << 32) | ((uint64_t)ctrL)); +} + +//***************************************************************************** +// +//! Registers an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being registered +//! \param pfnHandler is the pointer to ISR function +//! +//! This function registers the handler to be called when an IPC interrupt +//! occurs. This function enables the global interrupt in the interrupt +//! controller. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_registerInterrupt(IPC_Type_t ipcType, uint32_t ipcInt, + void (*pfnHandler)(void)); + +//***************************************************************************** +// +//! Unregisters an interrupt handler for IPC +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param ipcInt is the Flag number for which interrupt is being unregistered +//! +//! This function clears the handler to be called when an IPC interrupt +//! occurs. This function also masks off the interrupt in the interrupt +//! controller so that the interrupt handler no longer is called. +//! The \e ipcInt parameter can be any of the IPC flag values:\b IPC_INT0 - +//! \b IPC_INT7. IPC_INT0 corresponds to IPC Flag 0 interrupt and so on. +// +//***************************************************************************** +extern void +IPC_unregisterInterrupt(IPC_Type_t ipcType, uint32_t ipcInt); + +#if IPC_MSGQ_SUPPORT == 1U +//***************************************************************************** +// +//! Initializes the IPC message queue +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param ipcInt_L specifies the interrupt number on the local core used by +//! the message queue . +//! \param ipcInt_R specifies the interrupt number on the remote core used by +//! the message queue. +//! +//! This function initializes the IPC message queue with circular buffer +//! and index addresses for an IPC interrupt pair. The +//! \e ipcInt_L and \e ipcInt_R parameters can be one of the following values: +//! \b IPC_INT0, \b IPC_INT1, \b IPC_INT2, \b IPC_INT3. +//! +//! \note If an interrupt is currently in use by an \e IPC_MessageQueue_t +//! instance, that particular interrupt should not be tied to a second +//! \e IPC_MessageQueue_t instance. +//! +//! \note For a particular ipcInt_L - ipcInt_R pair, there must be an instance +//! of IPC_MessageQueue_t defined and initialized on both the locakl and remote +//! systems. +//! +//! \return None. +// +//***************************************************************************** +extern void +IPC_initMessageQueue(IPC_Type_t ipcType, volatile IPC_MessageQueue_t *msgQueue, + uint32_t ipcInt_L, uint32_t ipcInt_R); + +//***************************************************************************** +// +//! Sends a message into the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to be +//! sent to message queue. +//! \param block specifies whether to allow function to block until the buffer +//! has a free slot +//! +//! This function checks if there is a free slot in the message queue. If so, it +//! puts the message pointed to by \e msg into the free and sets the +//! appropriate IPC interrupt flag +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is full. \b true if the message is +//! successfully sent. +// +//***************************************************************************** +extern bool +IPC_sendMessageToQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); + +//***************************************************************************** +// +//! Reads a message from the messageQueue. +//! +//! \param ipcType is the enum corresponding to the IPC instance used +//! \param msgQueue specifies the address of a \e IPC_MessageQueue_t instance +//! \param addrCorrEnable is the flag used to determine whether or not to +//! convert the addr parameter to remote core's address space +//! \param msg specifies the address of the \e IPC_Message_t instance to which +//! the message needs to be read +//! \param block specifies whether to allow function to block until a message +//! is available in the message queue +//! +//! This function checks if there is a message in the message queue. If so, it +//! reads the message and writes to the address pointed to by \e msg into. +//! +//! The \e addrCorrEnable parameter can take values IPC_ADDR_CORRECTION_ENABLE +//! (converts the address to remote core's address space) or +//! IPC_ADDR_CORRECTION_DISABLE(does not modify the addr parmeter) +//! The \e block parameter can be one of the following values: +//! \b IPC_BLOCKING_CALL or \b IPC_NONBLOCKING_CALL. +//! +//! \return \b false if the queue is empty. \b true if the message successfully +//! read. +// +//***************************************************************************** +extern bool +IPC_readMessageFromQueue(IPC_Type_t ipcType, + volatile IPC_MessageQueue_t *msgQueue, + bool addrCorrEnable, IPC_Message_t *msg, bool block); +#endif +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // IPC_H diff --git a/gpio_driverlib_cpu1/device/driverlib/mcbsp.c b/gpio_driverlib_cpu1/device/driverlib/mcbsp.c new file mode 100644 index 0000000..4b23940 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/mcbsp.c @@ -0,0 +1,1621 @@ +//########################################################################### +// +// FILE: mcbsp.c +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "mcbsp.h" + +//***************************************************************************** +// +// McBSP_transmit16BitdataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit16BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write16bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_transmit32BitdataBlocking +// +//***************************************************************************** +void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Check if Transmitter buffer is ready. + // + while(!McBSP_isTxReady(base)) + { + } + + // + // Write data. + // + McBSP_write32bitData(base, data); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive16BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read16bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataNonBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_receive32BitDataBlocking +// +//***************************************************************************** +void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Wait until new data arrives. + // + while(!McBSP_isRxReady(base)) + { + } + + // + // Read the data. + // + *receiveData = McBSP_read32bitData(base); +} + +//***************************************************************************** +// +// McBSP_setRxDataSize +// +//***************************************************************************** +void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word , write to RWDLEN1 and words per frame , write to + // RFRLEN1. + // + HWREGH(base + MCBSP_O_RCR1) = + ((HWREGH(base + MCBSP_O_RCR1) & ~MCBSP_RCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR1_RFRLEN1_S))); + } + else + { + // + // Set bits per word , write to RWDLEN2 and words per frame, write to + // RFRLEN2. + // + HWREGH(base + MCBSP_O_RCR2) = + ((HWREGH(base + MCBSP_O_RCR2) & ~MCBSP_RCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_RCR2_RFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_setTxDataSize +// +//***************************************************************************** +void +McBSP_setTxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(wordsPerFrame < 128U); + + if(dataFrame == MCBSP_PHASE_ONE_FRAME) + { + // + // Set bits per word XWDLEN1 and words per frame XFRLEN1. + // + HWREGH(base + MCBSP_O_XCR1) = + ((HWREGH(base + MCBSP_O_XCR1) & ~MCBSP_XCR1_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR1_XFRLEN1_S))); + } + else + { + // + // Set bits per word XWDLEN2 and words per frame XFRLEN2. + // + HWREGH(base + MCBSP_O_XCR2) = + ((HWREGH(base + MCBSP_O_XCR2) & ~MCBSP_XCR2_M) | + ((uint16_t)bitsPerWord | (wordsPerFrame << MCBSP_XCR2_XFRLEN2_S))); + } +} + +//***************************************************************************** +// +// McBSP_disableRxChannel +// +//***************************************************************************** +void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableRxChannel +// +//***************************************************************************** +void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is RCERA or RCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is RCERC or RCERD or RCERE or RCERF or + // RCERG or RCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is RCERA or RCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_RCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_disableTxChannel +// +//***************************************************************************** +void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine whether it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) &= ~(1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_enableTxChannel +// +//***************************************************************************** +void McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel) +{ + uint16_t block; + uint16_t bitOffset; + uint16_t registerOffset; + uint16_t oddBlock; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + ASSERT(channel < 128U); + + // + // Determine channel block. + // + block = channel >> 4U; + + // + // Determine bit location. + // + bitOffset = channel - (block * 16U); + + // + // Determine register offset for Eight partition. + // + if(partition == MCBSP_MULTICHANNEL_EIGHT_PARTITION) + { + // + // For channel number 0 - 31. + // + if(channel < 32U) + { + // + // Determines whether it is XCERA or XCERB. + // + registerOffset = channel >> 4U; + } + + // + // For channel number 32 - 127. + // + else + { + // + // Determines whether it is XCERC or XCERD or XCERE or XCERF or + // XCERG or XCERH. + // + oddBlock = (block & 1U); + registerOffset = oddBlock + (2U * (block - (2U + oddBlock))) + + 0x5U; + } + } + + // + // Determine register offset for Two partition. + // + else + { + // + // Determine wheter it is XCERA or XCERB. + // + registerOffset = block & 0x1U; + } + + HWREGH(base + MCBSP_O_XCERA + registerOffset) |= (1U << bitOffset); +} + +//***************************************************************************** +// +// McBSP_configureTxClock +// +//***************************************************************************** +void +McBSP_configureTxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select TX clock source as SRG or External. + // + McBSP_setTxClockSource(base, + (McBSP_TxClockSource)ptrClockParams->clockSourceTx); + + // + // Check if using SRG to drive Transmitter clock. + // + if((McBSP_TxClockSource)ptrClockParams->clockSourceTx == + MCBSP_INTERNAL_TX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setTxSRGClockSource(base, + (McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource); + + // + // Check if SRG is clocked from MCLKR pin. GSYNC feature can be enabled + // in this case as SRG input clock source is MCLKR pin. + // + if((McBSP_SRGTxClockSource)ptrClockParams->clockTxSRGSource == + MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); + + // + // Check if SRG is to be synced with FSR that is GSYNC is to be + // enabled or not. + // + if(ptrClockParams->clockSRGSyncFlag) + { + McBSP_enableSRGSyncFSR(base); + } + else + { + McBSP_disableSRGSyncFSR(base); + } + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKX. + // Output polarity if using SRG as clock source. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); +} + +//***************************************************************************** +// +// McBSP_configureRxClock +// +//***************************************************************************** +void +McBSP_configureRxClock(uint32_t base, const McBSP_ClockParams *ptrClockParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select RX clock source as SRG or External. + // + McBSP_setRxClockSource(base, + (McBSP_RxClockSource)ptrClockParams->clockSourceRx); + + // + // Check if using SRG to drive Receiver clock. + // + if((McBSP_RxClockSource)ptrClockParams->clockSourceRx == + MCBSP_INTERNAL_RX_CLOCK_SOURCE) + { + // + // Set the SRG clock source. + // + McBSP_setRxSRGClockSource(base, + (McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource); + + // + // Check if SRG is clocked from MCLKX pin. GSYNC cannot be enabled in + // this case as GSYNC feature can be used only when SRG clock source is + // MCLKR pin. + // + if((McBSP_SRGRxClockSource)ptrClockParams->clockRxSRGSource == + MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN) + { + // + // Set the input clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrClockParams->clockMCLKXPolarity); + } + + // + // Set SRG clock divider. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrClockParams->clockSRGDivider); + } + + // + // Input polarity if using external clock on MCLKR. + // Output polarity if using SRG as clock source. + // + McBSP_setRxClockPolarity(base, + (McBSP_RxClockPolarity)ptrClockParams->clockMCLKRPolarity); +} + +//***************************************************************************** +// +// McBSP_configureTxFrameSync +// +//***************************************************************************** +void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setTxFrameSyncSource(base, + (McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx); + + // + // Check if using internal frame-sync source. + // + if((McBSP_TxFrameSyncSource)ptrFsyncParams->syncSourceTx == + MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Select the internal frame-sync trigger source. + // + McBSP_setTxInternalFrameSyncSource(base, + (McBSP_TxInternalFrameSyncSource)ptrFsyncParams->syncIntSource); + + // + // Check if using SRG FSG to trigger frame-sync pulse and GSYNC feature + // is disabled that is FSG is not derived from external MCLKR pin. + // + if((ptrFsyncParams->syncIntSource == + MCBSP_TX_INTERNAL_FRAME_SYNC_SRG) && + (ptrFsyncParams->syncSRGSyncFSRFlag == false)) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setTxFrameSyncPolarity(base, + (McBSP_TxFrameSyncPolarity)ptrFsyncParams->syncFSXPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableTxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureRxFrameSync +// +//***************************************************************************** +void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams *ptrFsyncParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Select frame-sync signal source. + // + McBSP_setRxFrameSyncSource(base, + (McBSP_RxFrameSyncSource)ptrFsyncParams->syncSourceRx); + + // + // If using internal frame-sync source. + // + if(ptrFsyncParams->syncSourceRx == MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE) + { + // + // Check if GSYNC feature is disabled that is FSG is not derived + // from external MCLKR pin. + // + if(ptrFsyncParams->syncSRGSyncFSRFlag == false) + { + // + // Set the frame-sync pulse period and width dividers. + // + McBSP_setFrameSyncPulsePeriod(base, + ptrFsyncParams->syncClockDivider); + McBSP_setFrameSyncPulseWidthDivider(base, + ptrFsyncParams->syncPulseDivider); + } + } + + // + // Set the frame-sync polarity. + // + McBSP_setRxFrameSyncPolarity(base, + (McBSP_RxFrameSyncPolarity)ptrFsyncParams->syncFSRPolarity); + + // + // Configure frame-sync error detect flag. + // + if(ptrFsyncParams->syncErrorDetect) + { + McBSP_enableRxFrameSyncErrorDetection(base); + } + else + { + McBSP_disableTxFrameSyncErrorDetection(base); + } +} + +//***************************************************************************** +// +// McBSP_configureTxDataFormat +// +//***************************************************************************** +void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - a TX must at least has a single phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseTx(base); + + // + // Check if second phase is being used. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseTx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the Tx companding mode. + // + McBSP_setTxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set Tx data delay in bits. + // + McBSP_setTxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set DX pin delay. + // + if(ptrDataParams->pinDelayEnableFlag) + { + McBSP_enableDxPinDelay(base); + } + else + { + McBSP_disableDxPinDelay(base); + } + + // + // Set the transmitter interrupt source. + // + McBSP_setTxInterruptSource(base, + (McBSP_TxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureRxDataFormat +// +//***************************************************************************** +void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams *ptrDataParams) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set loop back mode. + // + if(ptrDataParams->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure the module to work in McBSP mode. + // + McBSP_setClockStopMode(base, MCBSP_CLOCK_MCBSP_MODE); + + // + // Start with single phase - an RX must at least have a single phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase1WordLength, + ptrDataParams->phase1FrameLength); + + // + // Disable second phase by default. + // + McBSP_disableTwoPhaseRx(base); + + // + // Check if second phase is to be enabled. + // + if(ptrDataParams->twoPhaseModeFlag) + { + // + // Enable second phase. + // + McBSP_enableTwoPhaseRx(base); + + // + // Set the parameters for the second phase. + // + McBSP_setRxDataSize(base, MCBSP_PHASE_TWO_FRAME, + (McBSP_DataBitsPerWord)ptrDataParams->phase2WordLength, + ptrDataParams->phase2FrameLength); + } + + // + // Set the receiver companding mode. + // + McBSP_setRxCompandingMode(base, + (McBSP_CompandingMode)ptrDataParams->compandingMode); + + // + // Set receiver data delay in bits. + // + McBSP_setRxDataDelayBits(base, + (McBSP_DataDelayBits)ptrDataParams->dataDelayBits); + + // + // Set receiver sign-extension and justification mode. + // + McBSP_setRxSignExtension(base, + (McBSP_RxSignExtensionMode)ptrDataParams->signExtMode); + + // + // Set the receiver interrupt source. + // + McBSP_setRxInterruptSource(base, + (McBSP_RxInterruptSource)ptrDataParams->interruptMode); +} + +//***************************************************************************** +// +// McBSP_configureTxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorTx; + + errorTx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setTxChannelMode(base, + (McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx); + + // + // Configuration for multichannel selections that is for + // MCBSP_TX_CHANNEL_SELECTION_ENABLED, + // MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or + // MCBSP_SYMMERTIC_RX_TX_SELECTION. + // + if(((McBSP_TxChannelMode)ptrMchnParams->multichannelModeTx) != + MCBSP_ALL_TX_CHANNELS_ENABLED) + { + // + // Select 2 partition or 8 partition. + // + McBSP_setTxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionTx); + + // + // Disable dual phase transmission mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionTx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if(((uint16_t)ptrMchnParams->channelCountTx) > 32U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*(ptrMchnParams->ptrChannelsListTx) + + index)); + } + else + { + errorTx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setTxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition B. + // + McBSP_enableTxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + else + { + errorTx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if((uint16_t)ptrMchnParams->channelCountTx > 128U) + { + errorTx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountTx; + index++) + { + // + // Enable the Tx channels. + // + McBSP_enableTxChannel(base, MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListTx) + + index))); + } + } + } + return(errorTx); +} + +//***************************************************************************** +// +// McBSP_configureRxMultichannel +// +//***************************************************************************** +uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams *ptrMchnParams) +{ + uint16_t index; + uint16_t block; + uint16_t partitionAblock; + uint16_t partitionBblock; + uint16_t partitionAflag; + uint16_t partitionBflag; + uint16_t errorRx; + + errorRx = 0U; + partitionAblock = 0U; + partitionBblock = 0U; + + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Configure Tx Channel Selection mode. + // + McBSP_setRxChannelMode(base, + (McBSP_RxChannelMode)ptrMchnParams->multichannelModeRx); + + // + // Select 2 partition or 8 partition. + // + McBSP_setRxMultichannelPartition(base, + (McBSP_MultichannelPartition)ptrMchnParams->partitionRx); + + // + // Configuration for multichannel selections that is for + // MCBSP_RX_CHANNEL_SELECTION_ENABLED. + // + if((ptrMchnParams->multichannelModeRx) == + MCBSP_RX_CHANNEL_SELECTION_ENABLED) + { + // + // Disable dual phase reception mode. + // + McBSP_disableTwoPhaseRx(base); + + // + // Multichannel configuration for 2 partition mode. + // + if((McBSP_MultichannelPartition)ptrMchnParams->partitionRx == + MCBSP_MULTICHANNEL_TWO_PARTITION) + { + if((uint16_t)ptrMchnParams->channelCountRx > 32U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + partitionAflag = 0U; + partitionBflag = 0U; + + // + // Assign blocks to partition for the provided channels and + // enable the channels. Only the channels which belong to the + // block currently assigned to partition A or B can be enabled. + // + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Get the block to which channel belongs. + // + block = (*((ptrMchnParams->ptrChannelsListRx) + index)) >> 4U; + + // + // Check if channel block can be assigned to partition A. Only + // even numbered blocks can be assigned to partition A. + // + if((block & 0x1U) == 0U) + { + // + // Check if block is yet to be assigned to partition A. + // + if(partitionAflag == 0U) + { + // + // Assign block to partition A. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + + // + // Set flag to indicate that a block is now assigned + // to partition A. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionAflag = 1U; + partitionAblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition A. + // + if(partitionAblock == block) + { + // + // Enable the channel belonging to the block assigned + // to partition A. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx = MCBSP_ERROR_2_PARTITION_A; + } + } + + // + // Check if channel block can be assigned to partition B. Only + // odd numbered blocks can be assigned to partition B. + // + else + { + // + // Check if block is yet to be assigned to partition B. + // + if(partitionBflag == 0U) + { + // + // Assign block to partition B. + // + McBSP_setRxTwoPartitionBlock(base, + (McBSP_PartitionBlock)block); + // + // Set flag to indicate that a block is now assigned + // to partition B. Only one block can be assigned to + // a partition at a time in 2 partition mode. + // + partitionBflag = 1U; + partitionBblock = block; + } + + // + // Check if the channel to be enabled belong to the block + // assigned to partition B. + // + if(partitionBblock == block) + { + // + // Enable the Rx channel belonging to the block + // assigned to partition B. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_TWO_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + + index))); + } + else + { + errorRx |= MCBSP_ERROR_2_PARTITION_B; + } + } + } + } + + // + // Multichannel configuration for 8 partition mode. + // + else + { + if(ptrMchnParams->channelCountRx > 128U) + { + errorRx = MCBSP_ERROR_EXCEEDED_CHANNELS; + } + for(index = 0U; index < (uint16_t)ptrMchnParams->channelCountRx; + index++) + { + // + // Enable the Rx channels. + // + McBSP_enableRxChannel(base, + MCBSP_MULTICHANNEL_EIGHT_PARTITION, + (uint16_t)(*((ptrMchnParams->ptrChannelsListRx) + index))); + } + } + } + return(errorRx); +} + +//***************************************************************************** +// +// McBSP_configureSPIMasterMode +// +//***************************************************************************** +void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams *ptrSPIMasterMode) +{ + // + // Configure clock stop mode. + // + if(((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPIMasterMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPIMasterMode->clockStopMode); + + // + // Set loop back mode. + // + if(ptrSPIMasterMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as master. Use SRG as clock source for driving + // master clock. MCLKX pin will be the master clock out pin. + // + McBSP_setTxClockSource(base, MCBSP_INTERNAL_TX_CLOCK_SOURCE); + + // + // Set internal clock (LSPCLK) as SRG clock source. + // + McBSP_setTxSRGClockSource(base, MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK); + + // + // Set SRG clock divider for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, + (uint16_t)ptrSPIMasterMode->clockSRGDivider); + + // + // Set the output master clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPIMasterMode->spiMode); + + // + // Set FSX as an output driven by SRG. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE); + + // + // FSX is triggered when data is written to DXR registers. + // + McBSP_setTxInternalFrameSyncSource(base, + MCBSP_TX_INTERNAL_FRAME_SYNC_DATA); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPIMasterMode->wordLength, 0U); + + // + // Set one bit data delay for transmission & reception to set correct + // setup time on FSX signal. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_1); + } +} + +//***************************************************************************** +// +// McBSP_configureSPISlaveMode +// +//***************************************************************************** +void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams *ptrSPISlaveMode) +{ + + // + // Configure clock stop mode. + // + if(((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_NO_DELAY) || + ((ptrSPISlaveMode->clockStopMode) == MCBSP_CLOCK_SPI_MODE_DELAY)) + { + // + // Set SPI mode. + // + McBSP_setClockStopMode(base, + (McBSP_ClockStopMode)ptrSPISlaveMode->clockStopMode); + // + // Set loop back mode. + // + if(ptrSPISlaveMode->loopbackModeFlag) + { + McBSP_enableLoopback(base); + } + else + { + McBSP_disableLoopback(base); + } + + // + // Configure module as Slave. MCLKX pin acts as input slave + // clock and is driven externally by SPI master. + // + McBSP_setTxClockSource(base, MCBSP_EXTERNAL_TX_CLOCK_SOURCE); + + // + // Set the input slave clock polarity. + // + McBSP_setTxClockPolarity(base, + (McBSP_TxClockPolarity)ptrSPISlaveMode->spiMode); + + // + // Set internal clock (LSPCLK) as SRG clock source. SRG is used to + // synchronize McBSP logic with externally generated master clock. + // + McBSP_setRxSRGClockSource(base, MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK); + + // + // Assign a clock divider value of 1 for generating CLKG. + // + McBSP_setSRGDataClockDivider(base, 1U); + + // + // Set FSX as an input which is driven by slave-enable signal + // from SPI master. + // + McBSP_setTxFrameSyncSource(base, MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE); + + // + // Set the polarity for FSX pin as active low. + // + McBSP_setTxFrameSyncPolarity(base, + MCBSP_TX_FRAME_SYNC_POLARITY_LOW); + + // + // Disable dual phase mode. + // + McBSP_disableTwoPhaseTx(base); + + // + // Set the data format for transmission & reception.. + // + McBSP_setTxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + McBSP_setRxDataSize(base, MCBSP_PHASE_ONE_FRAME, + (McBSP_DataBitsPerWord)ptrSPISlaveMode->wordLength, 0U); + + // + // Set zero bit data delay for transmission & reception. + // + McBSP_setTxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + McBSP_setRxDataDelayBits(base, MCBSP_DATA_DELAY_BIT_0); + } +} diff --git a/gpio_driverlib_cpu1/device/driverlib/mcbsp.h b/gpio_driverlib_cpu1/device/driverlib/mcbsp.h new file mode 100644 index 0000000..949987d --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/mcbsp.h @@ -0,0 +1,3340 @@ +//########################################################################### +// +// FILE: mcbsp.h +// +// TITLE: C28x McBSP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MCBSP_H +#define MCBSP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup mcbsp_api McBSP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_ints.h" +#include "inc/hw_types.h" +#include "inc/hw_mcbsp.h" +#include "inc/hw_memmap.h" +#include "debug.h" +#include "interrupt.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Define to specify mask for setting the word and frame length in +// McBSP_setTxDataSize() anf McBSP_setRxDataSize(). +// +//***************************************************************************** +#define MCBSP_XCR1_M (MCBSP_XCR1_XWDLEN1_M | \ + MCBSP_XCR1_XFRLEN1_M) +#define MCBSP_RCR1_M (MCBSP_RCR1_RWDLEN1_M | \ + MCBSP_RCR1_RFRLEN1_M) +#define MCBSP_XCR2_M (MCBSP_XCR2_XWDLEN2_M | \ + MCBSP_XCR2_XFRLEN2_M) +#define MCBSP_RCR2_M (MCBSP_RCR2_RWDLEN2_M | \ + MCBSP_RCR2_RFRLEN2_M) + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getRxErrorStatus() when +// there is an error in Rx. +// +//***************************************************************************** +#define MCBSP_RX_NO_ERROR 0x0U //!< No error. +#define MCBSP_RX_BUFFER_ERROR 0x4U //!< Buffer Full. +#define MCBSP_RX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_RX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Defines the values that can be returned by McBSP_getTxErrorStatus() when +// there is an error in Tx. +// +//***************************************************************************** +#define MCBSP_TX_NO_ERROR 0x0U //!< No error. +#define MCBSP_TX_BUFFER_ERROR 0x4U //!< Buffer overrun. +#define MCBSP_TX_FRAME_SYNC_ERROR 0x8U //!< Frame sync error. +#define MCBSP_TX_BUFFER_FRAME_SYNC_ERROR 0xCU //!< Buffer and frame sync error. + +//***************************************************************************** +// +// Values that can be returned by McBSP_configureTxMultichannel() and +// McBSP_configureRxMultichannel(). +// +//***************************************************************************** +#define MCBSP_ERROR_EXCEEDED_CHANNELS 0x1U //!< Exceeded number of channels. +#define MCBSP_ERROR_2_PARTITION_A 0x2U //!< Error in 2 partition A setup. +#define MCBSP_ERROR_2_PARTITION_B 0x4U //!< Error in 2 partition B setup. +#define MCBSP_ERROR_INVALID_MODE 0x8U //!< Invalid mode. + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxSignExtension() as the \e +//! mode parameters. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RIGHT_JUSTIFY_FILL_ZERO = 0x0000U, //!< Right justify and + //!< zero fill MSB. + MCBSP_RIGHT_JUSTIFY_FILL_SIGN = 0x2000U, //!< Right justified sign + //!< extended into MSBs. + MCBSP_LEFT_JUSTIFY_FILL_ZER0 = 0x4000U //!< Left justifies LBS + //!< filled with zero. +}McBSP_RxSignExtensionMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setClockStopMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_CLOCK_MCBSP_MODE = 0x0000U, //!< Disables clock stop mode. + MCBSP_CLOCK_SPI_MODE_NO_DELAY = 0x1000U, //!< Enables clock stop mode. + MCBSP_CLOCK_SPI_MODE_DELAY = 0x1800U //!< Enables clock stop mode + //!< with half cycle delay. +}McBSP_ClockStopMode; + +//***************************************************************************** +// +//! Values that can be passed to McBSP_setRxInterruptSource() as the +//! \e interruptSource parameter. +// +//***************************************************************************** +typedef enum +{ + MCBSP_RX_ISR_SOURCE_SERIAL_WORD = 0x0000U, //!> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Configures transmitter input clock source for sample generator. +//! +//! \param base is the base address of the McBSP module. +//! \param srgClockSource is clock source for the sample generator. +//! +//! This functions sets the clock source for the sample rate generator. +//! Valid values for \e clockSource are +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK for LSPCLK. +//! - \b MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN for external clock at MCLKR pin. +//! MCLKX pin will be an output driven by sample rate generator. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxSRGClockSource(uint32_t base, + const McBSP_SRGTxClockSource srgClockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKSM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_CLKSM) | + ((uint16_t)((uint16_t)srgClockSource & 0x1U) << 13U)); + // + // Set or clear SCLKME bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_SCLKME) | + (uint16_t)(((uint16_t)srgClockSource >> 1U) << 7U)); +} + +//***************************************************************************** +// +//! Sets the mode for transmitter internal frame sync signal. +//! +//! \param base is the base address of the McBSP module. +//! \param syncMode is the frame sync mode. +//! +//! This function sets the frame sync signal generation mode. The signal can be +//! generated based on clock divider as set in McBSP_setFrameSyncPulsePeriod() +//! function or when data is transferred from DXR registers to XSR registers. +//! Valid input for syncMode are: +//! +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_DATA - frame sync signal is +//! generated when data is transferred from +//! DXR registers to XSR registers. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SRG - frame sync signal is +//! generated based on the clock counter +//! value as defined in +//! McBSP_setFrameSyncPulsePeriod() +//! function. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxInternalFrameSyncSource(uint32_t base, + const McBSP_TxInternalFrameSyncSource syncMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSGM bit. + // + HWREGH(base + MCBSP_O_SRGR2) = + ((HWREGH(base + MCBSP_O_SRGR2) & ~MCBSP_SRGR2_FSGM) | (uint16_t)syncMode); +} + +//***************************************************************************** +// +//! Set Multichannel receiver partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel receiver. Valid values +//! for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or Clear RMCME bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to receiver in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! receiver partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Check the block value if it is 0,2,4,6 or 1,3,5,7. + // + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to RPABLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPABLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to RPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RPBBLK_M) | + (uint16_t)(((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active receiver block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active receiver block involved in McBSP +//! reception. +//! +//! \return Active block in McBSP reception. Returned values range from 0 to 7 +//! representing the respective active block number . +// +//***************************************************************************** +static inline uint16_t +McBSP_getRxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return RCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR1) & MCBSP_MCR1_RCBLK_M) >> + MCBSP_MCR1_RCBLK_S); +} + +//***************************************************************************** +// +//! Configure channel selection mode for receiver. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_RX_CHANNELS_ENABLED - enables all channels. +//! - \b MCBSP_RX_CHANNEL_SELECTION_ENABLED - lets the user enable desired +//! channels by using McBSP_enableRxChannel(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxChannelMode(uint32_t base, const McBSP_RxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear RMCM bit. + // + HWREGH(base + MCBSP_O_MCR1) = + ((HWREGH(base + MCBSP_O_MCR1) & ~MCBSP_MCR1_RMCM) | (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Set Multichannel transmitter partitions. +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the number of partitions. +//! +//! This function sets the partitions for Multichannel transmitter. Valid +//! values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or \b +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 and 8 partitions respectively. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxMultichannelPartition(uint32_t base, + const McBSP_MultichannelPartition partition) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear XMCME bit. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCME) | (uint16_t)partition); +} + +//***************************************************************************** +// +//! Sets block to transmitter in two partition configuration. +//! +//! \param base is the base address of the McBSP module. +//! \param block is the block to assign to the partition. +//! +//! This function assigns the block the user provides to the appropriate +//! transmitter partition. +//! If user sets the value of block to 0,2,4 or 6 the API will assign the +//! blocks to partition A. If values 1,3,5,or 7 are set to block, then +//! the API assigns the block to partition B. +//! +//! \note This function should be used with the two partition configuration +//! only and not with eight partition configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxTwoPartitionBlock(uint32_t base, const McBSP_PartitionBlock block) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + if(((uint16_t)block == 0U) || + ((uint16_t)block == 2U) || + ((uint16_t)block == 4U) || + ((uint16_t)block == 6U)) + { + // + // write to XPABLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPABLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 5U)); + } + else + { + // + // write to XPBBLK bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XPBBLK_M) | + ((uint16_t)((uint16_t)block >> 1U)<< 7U)); + } +} + +//***************************************************************************** +// +//! Returns the current active transmitter block number. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function returns the current active transmitter block involved in +//! McBSP transmission. +//! +//! \return Active block in McBSP transmission. Returned values range from +//! 0 to 7 representing the respective active block number. +// +//***************************************************************************** +static inline uint16_t +McBSP_getTxActiveBlock(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // return XCBLK bits. + // + return((HWREGH(base + MCBSP_O_MCR2) & MCBSP_MCR2_XCBLK_M) >> + MCBSP_MCR2_XCBLK_S); + +} + +//***************************************************************************** +// +//! Configure channel selection mode for transmitter. +//! +//! \param base is the base address of the McBSP module. +//! \param channelMode is the channel selection mode. +//! +//! This function configures the channel selection mode. The following are +//! valid values for channelMode: +//! +//! - \b MCBSP_ALL_TX_CHANNELS_ENABLED - enables and unmasks all channels +//! - \b MCBSP_TX_CHANNEL_SELECTION_ENABLED - lets the user enable and unmask +//! desired channels by using McBSP_enableTxChannel() +//! - \b MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION - All channels enables but +//! until enabled by McBSP_enableTxChannel() +//! - \b MCBSP_SYMMERTIC_RX_TX_SELECTION - Symmetric transmission and +//! reception. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxChannelMode(uint32_t base, const McBSP_TxChannelMode channelMode) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set values to the XMCM bits. + // + HWREGH(base + MCBSP_O_MCR2) = + ((HWREGH(base + MCBSP_O_MCR2) & ~MCBSP_MCR2_XMCM_M) | + (uint16_t)channelMode); +} + +//***************************************************************************** +// +//! Select the transmitter frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the transmitter frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSX. +//! - \b MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! internally. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncSource(uint32_t base, + const McBSP_TxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + //Set or Clear the FSXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Select receiver frame sync signal source. +//! +//! \param base is the base address of the McBSP module. +//! \param syncSource is the receiver frame sync source. +//! +//! This function sets external or internal sync signal source based on the +//! syncSource selection. Valid input for syncSource are: +//! +//! - \b MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! externally by pin FSR. +//! - \b MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE - frame sync signal is supplied +//! by SRG. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncSource(uint32_t base, + const McBSP_RxFrameSyncSource syncSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRM) | (uint16_t)syncSource); +} + +//***************************************************************************** +// +//! Configures the Transmit clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the transmission pin. +//! +//! This function configures the clock source for the transmitter. Valid input +//! for rxClockSource are: +//! - \b MCBSP_INTERNAL_TX_CLOCK_SOURCE - internal clock source. SRG is the +//! source. +//! - \b MCBSP_EXTERNAL_TX_CLOCK_SOURCE - external clock source. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockSource(uint32_t base, const McBSP_TxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKXM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXM ) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Configures the Receive clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockSource is clock source for the reception pin. +//! +//! This function configures the clock source for the receiver. Valid input +//! for base are: +//! - \b MCBSP_INTERNAL_RX_CLOCK_SOURCE - internal clock source. Sample Rate +//! Generator will be used. +//! - \b MCBSP_EXTERNAL_RX_CLOCK_SOURCE - external clock will drive the data. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockSource(uint32_t base, const McBSP_RxClockSource clockSource) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear CLKRM bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRM) | (uint16_t)clockSource); +} + +//***************************************************************************** +// +//! Sets transmitter frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSX pin. Use \b MCBSP_TX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_TX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxFrameSyncPolarity(uint32_t base, + const McBSP_TxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSXP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets receiver frame sync polarity. +//! +//! \param base is the base address of the McBSP module. +//! \param syncPolarity is the polarity of frame sync pulse. +//! +//! This function sets the polarity (rising or falling edge)of the frame sync +//! on FSR pin. Use \b MCBSP_RX_FRAME_SYNC_POLARITY_LOW for active low +//! frame sync pulse and \b MCBSP_RX_FRAME_SYNC_POLARITY_HIGH for active +//! high sync pulse. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxFrameSyncPolarity(uint32_t base, + const McBSP_RxFrameSyncPolarity syncPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set or clear FSRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_FSRP) | (uint16_t)syncPolarity); +} + +//***************************************************************************** +//! Sets transmitter clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the transmitter +//! clock on MCLKX pin. +//! Valid values for clockPolarity are: +//! - \b MCBSP_TX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_TX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setTxClockPolarity(uint32_t base, + const McBSP_TxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKXP bit first , then set or clear CLKXP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKXP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +//! Sets receiver clock polarity when using external clock source. +//! +//! \param base is the base address of the McBSP module. +//! \param clockPolarity is the polarity of external clock. +//! +//! This function sets the polarity (rising or falling edge) of the receiver +//! clock on MCLKR pin. If external clock is used, the polarity will affect +//! CLKG signal. +//! Valid values for clockPolarity are: +//! - \b MCBSP_RX_POLARITY_RISING_EDGE for rising edge. +//! - \b MCBSP_RX_POLARITY_FALLING_EDGE for falling edge. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_setRxClockPolarity(uint32_t base, + const McBSP_RxClockPolarity clockPolarity) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear CLKRP bit first , then set or clear CLKRP bit. + // + HWREGH(base + MCBSP_O_PCR) = + ((HWREGH(base + MCBSP_O_PCR) & ~MCBSP_PCR_CLKRP) | + (uint16_t)clockPolarity); +} + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data value in data receive register. +//! +//! \return received data. +// +//***************************************************************************** +static inline +uint16_t McBSP_read16bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DRR1 register. + // + return(HWREGH(base + MCBSP_O_DRR1)); +} + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers. +//! +//! \param base is the base address of the McBSP port. +//! +//! This function returns the data values in data receive registers. +//! +//! \return received data. +// +//***************************************************************************** +static inline uint32_t +McBSP_read32bitData(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Read DDR1 register and return DDR2:DDR1. + // + return((((uint32_t)HWREGH(base + MCBSP_O_DRR2) << 16U) | + HWREGH(base + MCBSP_O_DRR1))); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 8,12 or 16 bit data to data transmit register. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write16bitData(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data; +} + +//***************************************************************************** +// +//! Write 20, 24 or 32 bit data word to McBSP data transmit registers. +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function writes 20, 24 or 32 bit data to data transmit registers. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_write32bitData(uint32_t base, uint32_t data) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Write to DXR2 register first. + // + HWREGH(base + MCBSP_O_DXR2) = data >> 16U; + + // + // Write to DXR1 register. + // + HWREGH(base + MCBSP_O_DXR1) = data & 0xFFFFU; +} + +//***************************************************************************** +// +//! Return left justified for data for U Law or A Law companding. +//! +//! \param data is the 14 bit word. +//! \param compandingType specifies the type comapnding desired. +//! +//! This functions returns U law or A law adjusted word. +//! +//! \return U law or A law left justified word. +// +//***************************************************************************** +static inline uint16_t +McBSP_getLeftJustifyData(uint16_t data, + const McBSP_CompandingType compandingType) +{ + return(data << (uint16_t)compandingType); +} + + +//***************************************************************************** +// +//! Enable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_RINT; +} + +//***************************************************************************** +// +//! Disable Recieve Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Recieve Interrupt on RRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableRxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear RINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_RINT); +} + +//***************************************************************************** +// +//! Enable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function enables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_enableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Set XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= MCBSP_MFFINT_XINT; +} + +//***************************************************************************** +// +//! Disable Transmit Interrupt. +//! +//! \param base is the base address of the McBSP module. +//! +//! This function disables Transmit Interrupt on XRDY. +//! +//! \return None. +// +//***************************************************************************** +static inline void +McBSP_disableTxInterrupt(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(McBSP_isBaseValid(base)); + + // + // Clear XINT ENA bit. + // + HWREGH(base + MCBSP_O_MFFINT) |= ~(MCBSP_MFFINT_XINT); +} + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. +//! +//! \return None. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataNonBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 8,12 or 16 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 16 bit or less data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written to +//! the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit16BitDataBlocking(uint32_t base, uint16_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! the transmitter buffer is empty the data will be written to the data +//! registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataNonBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Write 20 , 24 or 32 bit data word to McBSP data transmit registers +//! +//! \param base is the base address of the McBSP port. +//! \param data is the data to be written. +//! +//! This function sends 20 , 24 or 32 bit data to the transmitter buffer. If +//! transmit buffer is not ready the function will wait until transmit buffer +//! is empty. If the transmitter buffer is empty the data will be written +//! to the data registers. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_transmit32BitDataBlocking(uint32_t base, uint32_t data); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataNonBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 8,12 or 16 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 8,12 or 16 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive16BitDataBlocking(uint32_t base, uint16_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataNonBlocking(uint32_t base, uint32_t *receiveData); + +//***************************************************************************** +// +//! Read 20, 24 or 32 bit data word from McBSP data receive registers +//! +//! \param base is the base address of the McBSP port. +//! \param receiveData is the pointer to the receive data. +//! +//! This function reads 20, 24 or 32 bit data from the receiver buffer. If +//! receiver buffer is not ready the function will wait until receiver buffer +//! has new data. +//! If the receiver buffer has new data, the data will be read. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_receive32BitDataBlocking(uint32_t base, uint32_t *receiveData); + + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Reception. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing the first or second frame phase +//! respectively. Valid value for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setRxDataSize(uint32_t base, const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Sets number of words per frame and bits per word for data Transmission. +//! +//! \param base is the base address of the McBSP module. +//! \param dataFrame is the data frame phase. +//! \param bitsPerWord is the number of bits per word. +//! \param wordsPerFrame is the number of words per frame per phase. +//! +//! This function sets the number of bits per word and the number of words per +//! frame for the given phase. +//! Valid inputs for phase are \b MCBSP_PHASE_ONE_FRAME or \b +//! MCBSP_PHASE_TWO_FRAME representing single or dual phase respectively. +//! Valid values for bitsPerWord are: +//! - \b MCBSP_BITS_PER_WORD_8 8 bit word. +//! - \b MCBSP_BITS_PER_WORD_12 12 bit word. +//! - \b MCBSP_BITS_PER_WORD_16 16 bit word. +//! - \b MCBSP_BITS_PER_WORD_20 20 bit word. +//! - \b MCBSP_BITS_PER_WORD_24 24 bit word. +//! - \b MCBSP_BITS_PER_WORD_32 32 bit word. +//! The maximum value for wordsPerFrame is 127 (128 - 1)representing 128 words. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_setTxDataSize(uint32_t base, + const McBSP_DataPhaseFrame dataFrame, + const McBSP_DataBitsPerWord bitsPerWord, + uint16_t wordsPerFrame); + +//***************************************************************************** +// +//! Disables a channel in an eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function disables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition receiver +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the receiver channel number to be enabled. +//! +//! This function enables the given receiver channel number for the partition +//! provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableRxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Disables a channel in an eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function disables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_disableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Enables a channel for eight partition transmitter +//! +//! \param base is the base address of the McBSP module. +//! \param partition is the partition of the channel. +//! \param channel is the transmitter channel number to be enabled. +//! +//! This function enables the given transmitter channel number for the +//! partition provided. +//! Valid values for partition are \b MCBSP_MULTICHANNEL_TWO_PARTITION or +//! \b MCBSP_MULTICHANNEL_EIGHT_PARTITION for 2 or 8 partitions respectively. +//! Valid values for channel range from 0 to 127. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_enableTxChannel(uint32_t base, + const McBSP_MultichannelPartition partition, + uint16_t channel); + +//***************************************************************************** +// +//! Configures transmitter clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the transmitter clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFSR - true to sync with signal on FSR pin, +//! false to ignore signal on FSR pin. +//! the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_TX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_TX_CLOCK_SOURCE +//! - \b clockTxSRGSource - MCBSP_SRG_TX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_TX_CLOCK_SOURCE_MCLKR_PIN +//! - \b clockMCLKXPolarity - Output polarity on MCLKX pin. +//! - MCBSP_TX_POLARITY_RISING_EDGE +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockMCLKRPolarity - Input polarity on MCLKR pin (if SRG is +//! sourced from MCLKR pin). +//! - MCBSP_RX_POLARITY_FALLING_EDGE +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures receiver clock +//! +//! \param base is the base address of the McBSP module. +//! \param ptrClockParams is a pointer to a structure containing \e clock +//! parameters McBSP_ClockParams. +//! This function sets up the receiver clock. The following are valid +//! values and ranges for the parameters of the McBSP_TxFsyncParams. +//! - \b clockSRGSyncFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin. +//! - \b clockSRGDivider - Maximum valid value is 255. +//! - \b clockSource - MCBSP_EXTERNAL_RX_CLOCK_SOURCE or +//! MCBSP_INTERNAL_RX_CLOCK_SOURCE +//! - \b clockRxSRGSource - MCBSP_SRG_RX_CLOCK_SOURCE_LSPCLK or +//! MCBSP_SRG_RX_CLOCK_SOURCE_MCLKX_PIN +//! - \b clockMCLKRPolarity- output polarity on MCLKR pin. +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! - MCBSP_RX_POLARITY_RISING_EDGE +//! - \b clockMCLKXPolarity- Input polarity on MCLKX pin (if SRG is sourced +//! from MCLKX pin). +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! - MCBSP_TX_POLARITY_FALLING_EDGE +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxClock(uint32_t base, + const McBSP_ClockParams * ptrClockParams); + +//***************************************************************************** +// +//! Configures transmitter frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSPTxFsyncParams. +//! This function sets up the transmitter frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, false to +//! ignore the pulse on FSR pin.This value has to +//! be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. false +//! to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceTx - MCBSP_TX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_TX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncIntSource - MCBSP_TX_INTERNAL_FRAME_SYNC_DATA or +//! MCBSP_TX_INTERNAL_FRAME_SYNC_SRG +//! - \b syncFSXPolarity - MCBSP_TX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_TX_FRAME_SYNC_POLARITY_HIGH. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxFrameSync(uint32_t base, + const McBSP_TxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures receiver frame sync. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrFsyncParams is a pointer to a structure containing \e frame sync +//! parameters McBSP_RxFsyncParams. +//! This function sets up the receiver frame sync. The following are valid +//! values and ranges for the parameters of the McBSPTxFsyncParams. +//! - \b syncSRGSyncFSRFlag - true to sync with signal on FSR pin, +//! false to ignore the pulse on FSR pin. +//! This value has to be similar to the value of +//! McBSP_ClockParams.clockSRGSyncFlag. +//! - \b syncErrorDetect - true to enable frame sync error detect. +//! false to disable. +//! - \b syncClockDivider - Maximum valid value is 4095. +//! - \b syncPulseDivider - Maximum valid value is 255. +//! - \b syncSourceRx - MCBSP_RX_INTERNAL_FRAME_SYNC_SOURCE or +//! MCBSP_RX_EXTERNAL_FRAME_SYNC_SOURCE +//! - \b syncFSRPolarity - MCBSP_RX_FRAME_SYNC_POLARITY_LOW or +//! MCBSP_RX_FRAME_SYNC_POLARITY_HIGH +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxFrameSync(uint32_t base, + const McBSP_RxFsyncParams * ptrFsyncParams); + +//***************************************************************************** +// +//! Configures transmitter data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing \e data format +//! parameters McBSPTxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSPTxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for no loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b pinDelayEnableFlag - true to enable DX pin delay. +//! false to disable DX pin delay. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b interruptMode - MCBSP_TX_ISR_SOURCE_TX_READY, +//! MCBSP_TX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_TX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_TX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureTxDataFormat(uint32_t base, + const McBSP_TxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures receiver data format. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrDataParams is a pointer to a structure containing data format +//! parameters McBSP_RxDataParams. +//! This function sets up the transmitter data format and properties. The +//! following are valid values and ranges for the parameters of the +//! McBSP_RxDataParams. +//! - \b loopbackModeFlag - true for digital loop-back mode. +//! false for non loop-back mode. +//! - \b twoPhaseModeFlag - true for two phase mode. +//! false for single phase mode. +//! - \b phase1FrameLength - maximum value of 127. +//! - \b phase2FrameLength - maximum value of 127. +//! - \b phase1WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b phase2WordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b compandingMode - MCBSP_COMPANDING_NONE, +//! MCBSP_COMPANDING_NONE_LSB_FIRST +//! MCBSP_COMPANDING_U_LAW_SET or +//! MCBSP_COMPANDING_A_LAW_SET. +//! - \b dataDelayBits - MCBSP_DATA_DELAY_BIT_0, +//! MCBSP_DATA_DELAY_BIT_1 or +//! MCBSP_DATA_DELAY_BIT_2 +//! - \b signExtMode - MCBSP_RIGHT_JUSTIFY_FILL_ZERO, +//! MCBSP_RIGHT_JUSTIFY_FILL_SIGN or +//! MCBSP_LEFT_JUSTIFY_FILL_ZER0 +//! - \b interruptMode - MCBSP_RX_ISR_SOURCE_SERIAL_WORD, +//! MCBSP_RX_ISR_SOURCE_END_OF_BLOCK, +//! MCBSP_RX_ISR_SOURCE_FRAME_SYNC or +//! MCBSP_RX_ISR_SOURCE_SYNC_ERROR +//! +//! \b Note - When using companding,phase1WordLength and phase2WordLength +//! must be 8 bits wide. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureRxDataFormat(uint32_t base, + const McBSP_RxDataParams * ptrDataParams); + +//***************************************************************************** +// +//! Configures transmitter multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_TxMultichannelParams. +//! +//! This function sets up the transmitter multichannel mode. The following are +//! valid values and ranges for the parameters of the +//! McBSP_TxMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_TX_CHANNELS_ENABLED, +//! MCBSP_TX_CHANNEL_SELECTION_ENABLED, +//! MCBSP_ENABLE_MASKED_TX_CHANNEL_SELECTION or +//! MCBSP_SYMMERTIC_RX_TX_SELECTION +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even and +//! odd channels. For example you can have channels [48 -63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63] and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureTxMultichannel(uint32_t base, + const McBSP_TxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures receiver multichannel. +//! +//! \param base is the base address of the McBSP module. +//! \param ptrMchnParams is a pointer to a structure containing multichannel +//! parameters McBSP_RxMultiChannelParams. +//! +//! This function sets up the receiver multichannel mode. The following are +//! valid values and ranges for the parameters of the McBSPMultichannelParams. +//! - \b channelCount - Maximum value of 128 for partition 8 +//! Maximum value of 32 for partition 2 +//! - \b ptrChannelsList - Pointer to an array of size channelCount that +//! has unique channels. +//! - \b multichannelMode - MCBSP_ALL_RX_CHANNELS_ENABLED, +//! MCBSP_RX_CHANNEL_SELECTION_ENABLED, +//! - \b partition - MCBSP_MULTICHANNEL_TWO_PARTITION or +//! MCBSP_MULTICHANNEL_EIGHT_PARTITION +//! \note - In 2 partition mode only channels that belong to a single even or +//! odd block number should be listed. It is valid to have an even +//! and odd channels. For example you can have channels [48 - 63] and +//! channels [96 - 111] enables as one belongs to an even block and +//! the other to an odd block or two partitions. But not channels +//! [48 - 63]and channels [112 - 127] since they both are even blocks +//! or similar partitions. +//! +//! \return returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - number of channels exceeds 128 +//! - \b MCBSP_ERROR_2_PARTITION_A - invalid channel combination for +//! partition A +//! - \b MCBSP_ERROR_2_PARTITION_B - invalid channel combination for +//! partition B +//! - \b MCBSP_ERROR_INVALID_MODE - invalid transmitter channel mode. +//! +//! \return Returns the following error codes. +//! - \b MCBSP_ERROR_EXCEEDED_CHANNELS - Exceeded number of channels. +//! - \b MCBSP_ERROR_2_PARTITION_A - Error in 2 partition A setup. +//! - \b MCBSP_ERROR_2_PARTITION_B - Error in 2 partition B setup. +//! - \b MCBSP_ERROR_INVALID_MODE - Invalid mode. +// +//***************************************************************************** +extern uint16_t +McBSP_configureRxMultichannel(uint32_t base, + const McBSP_RxMultichannelParams * ptrMchnParams); + +//***************************************************************************** +// +//! Configures McBSP in SPI master mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPIMasterMode is a pointer to a structure containing SPI +//! parameters McBSP_SPIMasterModeParams. +//! This function sets up the McBSP module in SPI master mode.The following are +//! valid values and ranges for the parameters of the +//! McBSP_SPIMasterModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity can take values: +//! - MCBSP_TX_POLARITY_RISING_EDGE or +//! MCBSP_TX_POLARITY_FALLING_EDGE +//! - \b clockSRGDivider - Maximum valid value is 255. +//! +//! \note Make sure the clock divider is such that, the McBSP clock is not +//! running faster than 1/2 the speed of the source clock. +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPIMasterMode(uint32_t base, + const McBSP_SPIMasterModeParams * ptrSPIMasterMode); + +//***************************************************************************** +// +//! Configures McBSP in SPI slave mode +//! +//! \param base is the base address of the McBSP module. +//! \param ptrSPISlaveMode is a pointer to a structure containing SPI +//! parameters McBSP_SPISlaveModeParams. +//! This function sets up the McBSP module in SPI slave mode.The following are +//! valid values and ranges for the parameters of the McBSP_SPISlaveModeParams. +//! - \b loopbackModeFlag - true for digital loop-back +//! false for no loop-back +//! - \b clockStopMode - MCBSP_CLOCK_SPI_MODE_NO_DELAY or +//! MCBSP_CLOCK_SPI_MODE_DELAY +//! - \b wordLength - MCBSP_BITS_PER_WORD_x , x = 8,12,16,20,24,32 +//! - \b spiMode It represents the clock polarity and can take +//! values: +//! - MCBSP_RX_POLARITY_FALLING_EDGE or +//! MCBSP_RX_POLARITY_RISING_EDGE +//! +//! \return None. +// +//***************************************************************************** +extern void +McBSP_configureSPISlaveMode(uint32_t base, + const McBSP_SPISlaveModeParams * ptrSPISlaveMode); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MCBSP_H diff --git a/gpio_driverlib_cpu1/device/driverlib/memcfg.c b/gpio_driverlib_cpu1/device/driverlib/memcfg.c new file mode 100644 index 0000000..c9a4dc7 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/memcfg.c @@ -0,0 +1,701 @@ +//########################################################################### +// +// FILE: memcfg.c +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "memcfg.h" + + +//***************************************************************************** +// +// MemCfg_lockConfig +// +//***************************************************************************** +void +MemCfg_lockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that blocks writes to the sections' configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Lock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_unlockConfig +// +//***************************************************************************** +void +MemCfg_unlockConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Clear the bit that blocks writes to the sections' configuration + // registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= ~(MEMCFG_SECT_NUM_MASK & + memSections); + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Unlock configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_DX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_LSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_LSX_ALL)); + HWREG(MEMCFG_BASE + MEMCFG_O_GSXLOCK) &= + ~((uint32_t)(MEMCFG_SECT_NUM_MASK & MEMCFG_SECT_GSX_ALL)); + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of memory sections. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_commitConfig +// +//***************************************************************************** +void +MemCfg_commitConfig(uint32_t memSections) +{ + // + // Check the arguments. + // + ASSERT(((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + (memSections == MEMCFG_SECT_ALL)); + + // + // Set the bit that permanently blocks writes to the sections' + // configuration registers. + // + EALLOW; + + switch(memSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + memSections; + break; + + + case MEMCFG_SECT_TYPE_MASK: + // + // Commit configuration for all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXCOMMIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + break; + + default: + // + // Do nothing. Invalid memSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setProtection +// +//***************************************************************************** +void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + uint32_t regOffset; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 8 bits in the corresponding ACCPROT register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 8U; + } + + // + // Calculate register offset. Also, make sure the shift value is no greater + // than 31. + // + regOffset = (shiftVal & ~(0x1FU)) >> 4U; + shiftVal &= 0x0001FU; + maskVal = (uint32_t)MEMCFG_XACCPROTX_M << shiftVal; + regVal = protectMode << shiftVal; + + // + // Write the access protection mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXACCPROT0 + regOffset) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXACCPROT0 + regOffset) |= regVal; + break; + + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setLSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel) +{ + uint32_t shiftVal; + uint32_t temp; + + // + // Check the arguments. + // + ASSERT((ramSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Calculate how far the controller select value needs to be shifted. Each + // section number is represented by a bit in the lower word of ramSection + // and 2 bits in the corresponding MSEL register. + // + shiftVal = 0U; + temp = MEMCFG_SECT_NUM_MASK & ramSection; + + while(temp != 1U) + { + temp = temp >> 1U; + shiftVal += 2U; + } + + // + // Write the controller select setting into the appropriate field + // + EALLOW; + + HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) = + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXMSEL) & + ~((uint32_t)MEMCFG_LSXMSEL_MSEL_LS0_M << shiftVal)) | + ((uint32_t)controllerSel << shiftVal); + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setGSRAMControllerSel +// +//***************************************************************************** +void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel) +{ + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS); + + // + // We only need the section number bits for this function. + // + sectionNum = ramSections & MEMCFG_SECT_NUM_MASK; + + // + // Write the controller select setting into the appropriate field. + // + EALLOW; + if(controllerSel == MEMCFG_GSRAMCONTROLLER_CPU1) + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) &= ~sectionNum; + } + else + { + HWREG(MEMCFG_BASE + MEMCFG_O_GSXMSEL) |= sectionNum; + } + EDIS; +} + +//***************************************************************************** +// +// MemCfg_setTestMode +// +//***************************************************************************** +void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode) +{ + uint32_t shiftVal = 0U; + uint32_t maskVal; + uint32_t regVal; + uint32_t sectionNum; + + // + // Check the arguments. + // + ASSERT(((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((memSection & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG)); + + // + // Calculate how far the protect mode value needs to be shifted. Each + // section number is represented by a bit in the lower word of memSection + // and 2 bits in the corresponding TEST register. + // + sectionNum = memSection & MEMCFG_SECT_NUM_MASK; + + while(sectionNum != 1U) + { + sectionNum = sectionNum >> 1U; + shiftVal += 2U; + } + + maskVal = (uint32_t)MEMCFG_XTEST_M << shiftVal; + regVal = (uint32_t)testMode << shiftVal; + + // + // Write the test mode into the appropriate field + // + EALLOW; + + switch(memSection & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_DXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXTEST) |= regVal; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) &= ~maskVal; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXTEST) |= regVal; + break; + + default: + // + // Do nothing. Invalid memSection. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_initSections +// +//***************************************************************************** +void +MemCfg_initSections(uint32_t ramSections) +{ + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Set the bit in the various initialization registers that starts + // initialization. + // + EALLOW; + + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_LS: + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_GS: + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MSG: + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + ramSections; + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Initialize all sections. + // + HWREG(MEMCFG_BASE + MEMCFG_O_DXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_DX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_LSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_LSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_GSXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_GSX_ALL; + HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINIT) |= MEMCFG_SECT_NUM_MASK & + MEMCFG_SECT_MSGX_ALL; + break; + + default: + // + // Do nothing. Invalid ramSections. Make sure you aren't OR-ing + // values for two different types of RAM. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +// MemCfg_getInitStatus +// +//***************************************************************************** +bool +MemCfg_getInitStatus(uint32_t ramSections) +{ + uint32_t status; + + // + // Check the arguments. + // + ASSERT(((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_D) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_GS) || + ((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_MSG) || + (ramSections == MEMCFG_SECT_ALL)); + + // + // Read registers containing the initialization complete status. + // + switch(ramSections & MEMCFG_SECT_TYPE_MASK) + { + case MEMCFG_SECT_TYPE_D: + status = HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE); + break; + + case MEMCFG_SECT_TYPE_LS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_GS: + status = HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MSG: + status = HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE); + break; + + case MEMCFG_SECT_TYPE_MASK: + // + // Return the overall status. + // + if((HWREG(MEMCFG_BASE + MEMCFG_O_DXINITDONE) == + (MEMCFG_SECT_DX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_LSXINITDONE) == + (MEMCFG_SECT_LSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_GSXINITDONE) == + (MEMCFG_SECT_GSX_ALL & MEMCFG_SECT_NUM_MASK)) && + (HWREG(MEMCFG_BASE + MEMCFG_O_MSGXINITDONE) == + (MEMCFG_SECT_MSGX_ALL & MEMCFG_SECT_NUM_MASK))) + { + status = MEMCFG_SECT_NUM_MASK; + } + else + { + status = 0U; + } + break; + + default: + // + // Invalid ramSections. Make sure you aren't OR-ing values for two + // different types of RAM. + // + status = 0U; + break; + } + + return((ramSections & status) == (ramSections & MEMCFG_SECT_NUM_MASK)); +} + +//***************************************************************************** +// +// MemCfg_getViolationAddress +// +//***************************************************************************** +uint32_t +MemCfg_getViolationAddress(uint32_t intFlag) +{ + uint32_t address; + uint32_t stsNumber; + + // + // Calculate the the address of the desired violation address register. + // + if((intFlag & MEMCFG_MVIOL_MASK) != 0U) + { + stsNumber = intFlag >> MEMCFG_MVIOL_SHIFT; + address = ACCESSPROTECTION_BASE + MEMCFG_O_MCPUFAVADDR; + } + else + { + stsNumber = intFlag; + address = ACCESSPROTECTION_BASE + MEMCFG_O_NMCPURDAVADDR; + } + + while(stsNumber > 1U) + { + stsNumber = stsNumber >> 1U; + address += (uint32_t)(MEMCFG_O_NMCPUWRAVADDR - MEMCFG_O_NMCPURDAVADDR); + } + + // + // Read and return the access violation address at the calculated location. + // + return(HWREG(address)); +} + +//***************************************************************************** +// +// MemCfg_getCorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag) +{ + // + // Check the arguments. + // + if(stsFlag != MEMCFG_CERR_CPUREAD) + { + // + // Currently, the only correctable error address that can be read + // from a register is one for a CPU read error (MEMCFG_CERR_CPUREAD). + // For the sake of keeping this function portable to possible future + // devices with other error types, it still takes a stsFlag parameter. + // + ASSERT((bool)false); + } + + // + // Read and return the error address. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CCPUREADDR)); +} + +//***************************************************************************** +// +// MemCfg_getUncorrErrorAddress +// +//***************************************************************************** +uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag) +{ + uint32_t address; + uint32_t temp; + + // + // Calculate the the address of the desired error address register. + // + address = MEMORYERROR_BASE + MEMCFG_O_UCCPUREADDR; + + temp = stsFlag; + + while(temp > 1U) + { + temp = temp >> 1U; + address += (uint32_t)(MEMCFG_O_UCDMAREADDR - MEMCFG_O_UCCPUREADDR); + } + + // + // Read and return the error address at the calculated location. + // + return(HWREG(address)); +} + + diff --git a/gpio_driverlib_cpu1/device/driverlib/memcfg.h b/gpio_driverlib_cpu1/device/driverlib/memcfg.h new file mode 100644 index 0000000..8a9b6fc --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/memcfg.h @@ -0,0 +1,1266 @@ +//########################################################################### +// +// FILE: memcfg.h +// +// TITLE: C28x RAM config driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef MEMCFG_H +#define MEMCFG_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup memcfg_api MemCfg +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memcfg.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. Not intended for use by +// application code. +// +//***************************************************************************** +// +// Masks to decode memory section defines. +// +#define MEMCFG_SECT_TYPE_MASK 0xFF000000U +#define MEMCFG_SECT_TYPE_D 0x00000000U +#define MEMCFG_SECT_TYPE_LS 0x01000000U +#define MEMCFG_SECT_TYPE_GS 0x02000000U +#define MEMCFG_SECT_TYPE_MSG 0x03000000U +#define MEMCFG_SECT_NUM_MASK 0x00FFFFFFU +#define MEMCFG_XACCPROTX_M ((uint32_t)MEMCFG_GSXACCPROT0_FETCHPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_CPUWRPROT_GS0 | \ + (uint32_t)MEMCFG_GSXACCPROT0_DMAWRPROT_GS0) +#define MEMCFG_XTEST_M MEMCFG_DXTEST_TEST_M0_M + +// +// Used for access violation functions. +// +#define MEMCFG_NMVIOL_MASK 0x0000FFFFU +#define MEMCFG_MVIOL_MASK 0x000F0000U +#define MEMCFG_MVIOL_SHIFT 16U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to MemCfg_lockConfig(), MemCfg_unlockConfig(), +// MemCfg_commitConfig(), MemCfg_setProtection(), MemCfg_initSections(), +// MemCfg_setCLAMemType(), MemCfg_setLSRAMControllerSel(), +// MemCfg_getInitStatus() as the memSection(s) or ramSection(s) parameter. +// +//***************************************************************************** +// +// DxRAM - Dedicated RAM config +// +#define MEMCFG_SECT_M0 0x00000001U //!< M0 RAM +#define MEMCFG_SECT_M1 0x00000002U //!< M1 RAM +#define MEMCFG_SECT_D0 0x00000004U //!< D0 RAM +#define MEMCFG_SECT_D1 0x00000008U //!< D1 RAM +#define MEMCFG_SECT_DX_ALL 0x0000000FU //!< All M and D RAM + +// +// LSxRAM - Local shared RAM config +// +#define MEMCFG_SECT_LS0 0x01000001U //!< LS0 RAM +#define MEMCFG_SECT_LS1 0x01000002U //!< LS1 RAM +#define MEMCFG_SECT_LS2 0x01000004U //!< LS2 RAM +#define MEMCFG_SECT_LS3 0x01000008U //!< LS3 RAM +#define MEMCFG_SECT_LS4 0x01000010U //!< LS4 RAM +#define MEMCFG_SECT_LS5 0x01000020U //!< LS5 RAM +#define MEMCFG_SECT_LSX_ALL 0x0100003FU //!< All LS RAM + +// +// GSxRAM - Global shared RAM config +// +#define MEMCFG_SECT_GS0 0x02000001U //!< GS0 RAM +#define MEMCFG_SECT_GS1 0x02000002U //!< GS1 RAM +#define MEMCFG_SECT_GS2 0x02000004U //!< GS2 RAM +#define MEMCFG_SECT_GS3 0x02000008U //!< GS3 RAM +#define MEMCFG_SECT_GS4 0x02000010U //!< GS4 RAM +#define MEMCFG_SECT_GS5 0x02000020U //!< GS5 RAM +#define MEMCFG_SECT_GS6 0x02000040U //!< GS6 RAM +#define MEMCFG_SECT_GS7 0x02000080U //!< GS7 RAM +#define MEMCFG_SECT_GS8 0x02000100U //!< GS8 RAM +#define MEMCFG_SECT_GS9 0x02000200U //!< GS9 RAM +#define MEMCFG_SECT_GS10 0x02000400U //!< GS10 RAM +#define MEMCFG_SECT_GS11 0x02000800U //!< GS11 RAM +#define MEMCFG_SECT_GS12 0x02001000U //!< GS12 RAM +#define MEMCFG_SECT_GS13 0x02002000U //!< GS13 RAM +#define MEMCFG_SECT_GS14 0x02004000U //!< GS14 RAM +#define MEMCFG_SECT_GS15 0x02008000U //!< GS15 RAM +#define MEMCFG_SECT_GSX_ALL 0x0200FFFFU //!< All GS RAM + +// +// MSGxRAM - Message RAM config +// +#define MEMCFG_SECT_MSGCPUTOCPU 0x03000001U //!< CPU-to-CPU message RAM +#define MEMCFG_SECT_MSGCPUTOCLA1 0x03000002U //!< CPU-to-CLA1 message RAM +#define MEMCFG_SECT_MSGCLA1TOCPU 0x03000004U //!< CLA1-to-CPU message RAM +#define MEMCFG_SECT_MSGX_ALL 0x03000007U //!< All message RAM + + +// +// All sections +// +#define MEMCFG_SECT_ALL 0xFFFFFFFFU //!< All configurable RAM + +//***************************************************************************** +// +// Values that can be passed to MemCfg_setProtection() as the protectMode +// parameter. +// +//***************************************************************************** +#define MEMCFG_PROT_ALLOWCPUFETCH 0x00000000U //!< CPU fetch allowed +#define MEMCFG_PROT_BLOCKCPUFETCH 0x00000001U //!< CPU fetch blocked + +#define MEMCFG_PROT_ALLOWCPUWRITE 0x00000000U //!< CPU write allowed +#define MEMCFG_PROT_BLOCKCPUWRITE 0x00000002U //!< CPU write blocked + +#define MEMCFG_PROT_ALLOWDMAWRITE 0x00000000U //!< DMA write allowed (GSxRAM) +#define MEMCFG_PROT_BLOCKDMAWRITE 0x00000004U //!< DMA write blocked (GSxRAM) + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_NMVIOL_CPUREAD 0x00000001U //!< Non-controller CPU read access +#define MEMCFG_NMVIOL_CPUWRITE 0x00000002U //!< Non-controller CPU write access +#define MEMCFG_NMVIOL_CPUFETCH 0x00000004U //!< Non-controller CPU fetch access +#define MEMCFG_NMVIOL_DMAWRITE 0x00000008U //!< Non-controller DMA write access +#define MEMCFG_NMVIOL_CLA1READ 0x00000010U //!< Non-controller CLA1 read access +#define MEMCFG_NMVIOL_CLA1WRITE 0x00000020U //!< Non-controller CLA1 write access +#define MEMCFG_NMVIOL_CLA1FETCH 0x00000040U //!< Non-controller CLA1 fetch access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_enableViolationInterrupt() +// MemCfg_disableViolationInterrupt(), MemCfg_forceViolationInterrupt(), +// MemCfg_clearViolationInterruptStatus(), and MemCfg_getViolationAddress() as +// the intFlags parameter. They also make up the return value of +// MemCfg_getViolationInterruptStatus(). +// +//***************************************************************************** +#define MEMCFG_MVIOL_CPUFETCH 0x00010000U //!< Controller CPU fetch access +#define MEMCFG_MVIOL_CPUWRITE 0x00020000U //!< Controller CPU write access +#define MEMCFG_MVIOL_DMAWRITE 0x00040000U //!< Controller DMA write access + +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceCorrErrorStatus(), +// MemCfg_clearCorrErrorStatus(), and MemCfg_getCorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getCorrErrorStatus(). +// +// Note that MEMCFG_CERR_CPUREAD is the only value below that has a +// corresponding interrupt and may be used with the error functions that take +// an intFlag(s) parameter. +// +//***************************************************************************** +#define MEMCFG_CERR_CPUREAD 0x0001U //!< Correctable CPU read error +#define MEMCFG_CERR_DMAREAD 0x0002U //!< Correctable DMA read error +#define MEMCFG_CERR_CLA1READ 0x0004U //!< Correctable CLA1 read error +//***************************************************************************** +// +// Values that can be passed to MemCfg_forceUncorrErrorStatus(), +// MemCfg_clearUncorrErrorStatus(), and MemCfg_getUncorrErrorAddress() as the +// stsFlag(s) parameter and returned by MemCfg_getUncorrErrorStatus(). +// +//***************************************************************************** +#define MEMCFG_UCERR_CPUREAD 0x0001U //!< Uncorrectable CPU read error +#define MEMCFG_UCERR_DMAREAD 0x0002U //!< Uncorrectable DMA read error +#define MEMCFG_UCERR_CLA1READ 0x0004U //!< Uncorrectable CLA1 read error + +#endif + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setCLAMemType() as the \e claMemType +//! parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_CLA_MEM_DATA, //!< Section is CLA data memory + MEMCFG_CLA_MEM_PROGRAM //!< Section is CLA program memory +} MemCfg_CLAMemoryType; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setLSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_LSRAMCONTROLLER_CPU_ONLY, //!< CPU is the owner of the section + MEMCFG_LSRAMCONTROLLER_CPU_CLA1 //!< CPU and CLA1 share this section +} MemCfg_LSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setGSRAMControllerSel() as the +//! \e controllerSel parameter. +// +//***************************************************************************** +typedef enum +{ + MEMCFG_GSRAMCONTROLLER_CPU1, //!< CPU1 is controller of the section + MEMCFG_GSRAMCONTROLLER_CPU2 //!< CPU2 is controller of the section +} MemCfg_GSRAMControllerSel; + +//***************************************************************************** +// +//! Values that can be passed to MemCfg_setTestMode() as the \e testMode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Functional mode. Test mode is disabled. + MEMCFG_TEST_FUNCTIONAL = 0, + //! Writes allowed to data only + MEMCFG_TEST_WRITE_DATA = 1, + //! Writes allowed to ECC only (for DxRAM/MxRAM) + MEMCFG_TEST_WRITE_ECC = 2, + //! Writes allowed to parity only (for LSxRAM, GSxRAM, and MSGxRAM) + MEMCFG_TEST_WRITE_PARITY = 2 +} MemCfg_TestMode; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** + +//***************************************************************************** +// +//! Sets the CLA memory type of the specified RAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param claMemType indicates data memory or program memory. +//! +//! This function sets the CLA memory type configuration of the RAM section. If +//! the \e claMemType parameter is \b MEMCFG_CLA_MEM_DATA, the RAM section will +//! be configured as CLA data memory. If \b MEMCFG_CLA_MEM_PROGRAM, the RAM +//! section will be configured as CLA program memory. +//! +//! The \e ramSections parameter is an OR of the following indicators: +//! \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx. +//! +//! \note This API only applies to LSx RAM and has no effect if the CLA isn't +//! controller of the memory section. +//! +//! \sa MemCfg_setLSRAControllerSel() +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCLAMemType(uint32_t ramSections, MemCfg_CLAMemoryType claMemType) +{ + // + // Check the arguments. + // + ASSERT((ramSections & MEMCFG_SECT_TYPE_MASK) == MEMCFG_SECT_TYPE_LS); + + // + // Write the CLA memory configuration to the appropriate register. Either + // set or clear the bit that determines the function of the RAM section as + // it relates to the CLA. + // + EALLOW; + + if(claMemType == MEMCFG_CLA_MEM_PROGRAM) + { + // + // Program memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) |= ramSections; + } + else + { + // + // Data memory + // + HWREG(MEMCFG_BASE + MEMCFG_O_LSXCLAPGM) &= ~ramSections; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! This function enables the indicated RAM access violation interrupt sources. +//! Only the sources that are enabled can be reflected to the processor +//! interrupt; disabled sources have no effect on the processor. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableViolationInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM access violation interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function disables the indicated RAM access violation interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only non-controller violations may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableViolationInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVINTEN) &= + ~(intFlags & MEMCFG_NMVIOL_MASK); + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVINTEN) &= + ~((intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM access violation status. +//! +//! This function returns the RAM access violation status. This function will +//! return flags for both controller and non-controller access violations +//! although only the non-controller flags have the ability to cause the +//! generation of an interrupt. +//! +//! \return Returns the current violation status, enumerated as a bit field of +//! the values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//***************************************************************************** +static inline uint32_t +MemCfg_getViolationInterruptStatus(void) +{ + uint32_t status; + + // + // Read and return RAM access status flags. + // + status = (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVFLG)) | + (HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVFLG) << + MEMCFG_MVIOL_SHIFT); + + return(status); +} + +//***************************************************************************** +// +//! Sets the RAM access violation status. +//! +//! \param intFlags is a bit mask of the access violation flags to be set. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! This function sets the RAM access violation status. This function will +//! set flags for both controller and non-controller access violations, and an +//! interrupt will be generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceViolationInterrupt(uint32_t intFlags) +{ + // + // Shift and mask the flags appropriately and write them to the + // corresponding SET register. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVSET) = + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVSET) = + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Clears RAM access violation flags. +//! +//! \param intFlags is a bit mask of the access violation flags to be cleared. +//! Can be a logical OR any of the following values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearViolationInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested access violation flags. + // + EALLOW; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_NMAVCLR) |= + intFlags & MEMCFG_NMVIOL_MASK; + + HWREG(ACCESSPROTECTION_BASE + MEMCFG_O_MAVCLR) |= + (intFlags & MEMCFG_MVIOL_MASK) >> MEMCFG_MVIOL_SHIFT; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the correctable error threshold value. +//! +//! \param threshold is the correctable error threshold. +//! +//! This value sets the error-count threshold at which a correctable error +//! interrupt is generated. That is when the error count register reaches the +//! value specified by the \e threshold parameter, an interrupt is +//! generated if it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_setCorrErrorThreshold(uint32_t threshold) +{ + // + // Write the threshold value to the appropriate register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRTHRES) = threshold; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the correctable error count. +//! +//! \return Returns the number of correctable error have occurred. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorCount(void) +{ + // + // Read and return the number of errors that have occurred. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCNT)); +} + +//***************************************************************************** +// +//! Enables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be enabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function enables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Enable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Disables individual RAM correctable error interrupt sources. +//! +//! \param intFlags is a bit mask of the interrupt sources to be disabled. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function disables the indicated RAM correctable error interrupt +//! sources. Only the sources that are enabled can be reflected to the +//! processor interrupt; disabled sources have no effect on the processor. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Disable the specified interrupts. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTEN) &= ~(intFlags); + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current RAM correctable error interrupt status. +//! +//! \return Returns the current error interrupt status. Will return a value of +//! \b MEMCFG_CERR_CPUREAD if an interrupt has been generated. If not, the +//! function will return 0. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorInterruptStatus(void) +{ + // + // Read and return correctable error interrupt flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTFLG)); +} + +//***************************************************************************** +// +//! Sets the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be set. Can take +//! the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function sets the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorInterrupt(uint32_t intFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTSET) = intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears the RAM correctable error interrupt status. +//! +//! \param intFlags is a bit mask of the interrupt sources to be cleared. Can +//! take the value \b MEMCFG_CERR_CPUREAD only. Other values are reserved. +//! +//! This function clears the correctable error interrupt flag. +//! +//! \note Note that only correctable errors may generate interrupts. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorInterruptStatus(uint32_t intFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CEINTCLR) |= intFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the current correctable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +// +//***************************************************************************** +static inline uint32_t +MemCfg_getCorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRFLG)); +} + +//***************************************************************************** +// +//! Gets the current uncorrectable RAM error status. +//! +//! \return Returns the current error status, enumerated as a bit field of +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +// +//***************************************************************************** +static inline uint32_t +MemCfg_getUncorrErrorStatus(void) +{ + // + // Read and return RAM error status flags. + // + return(HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRFLG)); +} + +//***************************************************************************** +// +//! Sets the specified correctable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function sets the specified correctable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceCorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Sets the specified uncorrectable RAM error status flag. +//! +//! \param stsFlags is a bit mask of the error sources. This parameter can be +//! any of the following values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function sets the specified uncorrectable RAM error status flag. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_forceUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Write the flags to the appropriate SET register. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRSET) = stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears correctable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_CERR_CPUREAD, \b MEMCFG_CERR_DMAREAD, or \b MEMCFG_CERR_CLA1READ +//! +//! This function clears the specified correctable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearCorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_CERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Clears uncorrectable RAM error flags. +//! +//! \param stsFlags is a bit mask of the status flags to be cleared. +//! This parameter can be any of the following : +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, \b MEMCFG_UCERR_CLA1READ, +//! or \b MEMCFG_UCERR_ECATMEMREAD. +//! +//! This function clears the specified uncorrectable RAM error flags. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_clearUncorrErrorStatus(uint32_t stsFlags) +{ + // + // Clear the requested flags. + // + EALLOW; + + HWREG(MEMORYERROR_BASE + MEMCFG_O_UCERRCLR) |= stsFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 1-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMWaitState(void) +{ + // + // Clear the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) &= + ~((uint32_t)MEMCFG_ROMWAITSTATE_WSDISABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM wait state. +//! +//! This function enables the ROM wait state. This mean CPU accesses to ROM are +//! 0-wait. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMWaitState(void) +{ + // + // Set the disable bit. + // + EALLOW; + + HWREG(ROMWAITSTATE_BASE + MEMCFG_O_ROMWAITSTATE) |= + MEMCFG_ROMWAITSTATE_WSDISABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Enables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_enableROMPrefetch(void) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) |= + MEMCFG_ROMPREFETCH_PFENABLE; + + EDIS; +} + +//***************************************************************************** +// +//! Disables ROM prefetch. +//! +//! This function enables the ROM prefetch for both secure ROM and boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +MemCfg_disableROMPrefetch(void) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(ROMPREFETCH_BASE + MEMCFG_O_ROMPREFETCH) &= + ~((uint32_t)MEMCFG_ROMPREFETCH_PFENABLE); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the writes to the configuration of specified memory sections. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function locks writes to the access protection and controller select +//! configuration of a memory section.That means calling MemCfg_setProtection() +//! or MemCfg_setLSRAMControllerSel() for a locked memory section will have no +//! effect until MemCfg_unlockConfig() is called. +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_lockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Unlocks the writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function unlocks writes to the access protection and controller select +//! configuration of a memory section that has been locked using +//! MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_unlockConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Permanently locks writes to the configuration of a memory section. +//! +//! \param memSections is the logical OR of the sections to be configured. +//! +//! This function permanently locks writes to the access protection and +//! controller select configuration of a memory section. That means calling +//! MemCfg_setProtection() or MemCfg_setLSRAMControllerSel() for a locked memory +//! section will have no effect. To lock the configuration in a nonpermanent +//! way, use MemCfg_lockConfig(). +//! +//! The \e memSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_D0 and \b MEMCFG_SECT_D1 or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx or \b MEMCFG_SECT_GSX_ALL +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_commitConfig(uint32_t memSections); + +//***************************************************************************** +// +//! Sets the access protection mode of a single memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param protectMode is the logical OR of the settings to be applied. +//! +//! This function sets the access protection mode of a specified memory section. +//! The mode is passed into the \e protectMode parameter as the logical OR of +//! the following values: +//! - \b MEMCFG_PROT_ALLOWCPUFETCH or \b MEMCFG_PROT_BLOCKCPUFETCH - CPU fetch +//! - \b MEMCFG_PROT_ALLOWCPUWRITE or \b MEMCFG_PROT_BLOCKCPUWRITE - CPU write +//! - \b MEMCFG_PROT_ALLOWDMAWRITE or \b MEMCFG_PROT_BLOCKDMAWRITE - DMA write +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_D0 or \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig() or if the memory +//! is configured as CLA program memory. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setProtection(uint32_t memSection, uint32_t protectMode); + +//***************************************************************************** +// +//! Sets the controller of the specified LSxRAM section. +//! +//! \param ramSection is the LSxRAM section to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the LSxRAM +//! section. +//! If the \e controllerSel parameter is \b MEMCFG_LSRAMCONTROLLER_CPU_ONLY, +//! the LSxRAM section passed into the \e ramSection parameter will be dedicated +//! to the CPU. If \b MEMCFG_LSRAMCONTROLLER_CPU_CLA1, the memory section will +//! be shared between the CPU and the CLA. +//! +//! The \e ramSection parameter should be a value from \b MEMCFG_SECT_LS0 +//! through \b MEMCFG_SECT_LSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to LSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setLSRAMControllerSel(uint32_t ramSection, + MemCfg_LSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the controller of the specified GSxRAM section. +//! +//! \param ramSections is the logical OR of the sections to be configured. +//! \param controllerSel is the sharing selection. +//! +//! This function sets the controller select configuration of the GSxRAM +//! section.If the \e controllerSel parameter is \b MEMCFG_GSRAMCONTROLLER_CPU1, +//! the GSRAM sections passed into the \e ramSections parameter will be +//! dedicated to CPU1. If \b MEMCFG_GSRAMCONTROLLER_CPU2, the memory section +//! will be dedicated to CPU2. +//! +//! The \e ramSections parameter should be a logical OR of values from +//! \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx. +//! +//! This function will have no effect if the associated registers have been +//! locked by MemCfg_lockConfig() or MemCfg_commitConfig(). +//! +//! \note This API only applies to GSxRAM. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setGSRAMControllerSel(uint32_t ramSections, + MemCfg_GSRAMControllerSel controllerSel); + +//***************************************************************************** +// +//! Sets the test mode of the specified memory section. +//! +//! \param memSection is the memory section to be configured. +//! \param testMode is the test mode selected. +//! +//! This function sets the test mode configuration of the RAM section. The +//! \e testMode parameter can take one of the following values: +//! - \b MEMCFG_TEST_FUNCTIONAL +//! - \b MEMCFG_TEST_WRITE_DATA +//! - \b MEMCFG_TEST_WRITE_ECC +//! - \b MEMCFG_TEST_WRITE_PARITY +//! +//! The \e memSection parameter is one of the following indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1 +//! - \b MEMCFG_SECT_D0, \b MEMCFG_SECT_D1 +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_setTestMode(uint32_t memSection, MemCfg_TestMode testMode); + +//***************************************************************************** +// +//! Starts the initialization the specified RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be initialized. +//! +//! This function starts the initialization of the specified RAM sections. Use +//! MemCfg_getInitStatus() to check if the initialization is done. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to configure all possible sections. +//! +//! \return None. +// +//***************************************************************************** +extern void +MemCfg_initSections(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the status of initialized RAM sections. +//! +//! \param ramSections is the logical OR of the sections to be checked. +//! +//! This function gets the initialization status of the RAM sections specified +//! by the \e ramSections parameter. +//! +//! The \e ramSections parameter is an OR of one of the following sets of +//! indicators: +//! - \b MEMCFG_SECT_M0, \b MEMCFG_SECT_M1, \b MEMCFG_SECT_D0, +//! \b MEMCFG_SECT_D1, or \b MEMCFG_SECT_DX_ALL +//! - \b MEMCFG_SECT_LS0 through \b MEMCFG_SECT_LSx, or \b MEMCFG_SECT_LSX_ALL +//! - \b MEMCFG_SECT_GS0 through \b MEMCFG_SECT_GSx, or \b MEMCFG_SECT_GSX_ALL +//! - \b MEMCFG_SECT_MSGCPUTOCPU, \b MEMCFG_SECT_MSGCPUTOCLA1, or +//! \b MEMCFG_SECT_MSGCLA1TOCPU +//! - \b OR use \b MEMCFG_SECT_ALL to get status of all possible sections. +//! +//! \note Use MemCfg_initSections() to start the initialization. +//! +//! \return Returns \b true if all the sections specified by \e ramSections +//! have been initialized and \b false if not. +// +//***************************************************************************** +extern bool +MemCfg_getInitStatus(uint32_t ramSections); + +//***************************************************************************** +// +//! Get the violation address associated with a intFlag. +//! +//! \param intFlag is the type of access violation as indicated by ONE of +//! these values: +//! - \b MEMCFG_NMVIOL_CPUREAD - Non-controller CPU read access +//! - \b MEMCFG_NMVIOL_CPUWRITE - Non-controller CPU write access +//! - \b MEMCFG_NMVIOL_CPUFETCH - Non-controller CPU fetch access +//! - \b MEMCFG_NMVIOL_DMAWRITE - Non-controller DMA write access +//! - \b MEMCFG_NMVIOL_CLA1READ - Non-controller CLA1 read access +//! - \b MEMCFG_NMVIOL_CLA1WRITE - Non-controller CLA1 write access +//! - \b MEMCFG_NMVIOL_CLA1FETCH - Non-controller CLA1 fetch access +//! - \b MEMCFG_MVIOL_CPUFETCH - Controller CPU fetch access +//! - \b MEMCFG_MVIOL_CPUWRITE - Controller CPU write access +//! - \b MEMCFG_MVIOL_DMAWRITE - Controller DMA write access +//! +//! \return Returns the violation address associated with the \e intFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getViolationAddress(uint32_t intFlag); + +//***************************************************************************** +// +//! Get the correctable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. Can currently take the value \b MEMCFG_CERR_CPUREAD only. +//! Other values are reserved. +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getCorrErrorAddress(uint32_t stsFlag); + +//***************************************************************************** +// +//! Get the uncorrectable error address associated with a stsFlag. +//! +//! \param stsFlag is the type of error to which the returned address will +//! correspond. It may be passed one of these values: +//! \b MEMCFG_UCERR_CPUREAD, \b MEMCFG_UCERR_DMAREAD, or +//! \b MEMCFG_UCERR_CLA1READ values +//! +//! \return Returns the error address associated with the stsFlag. +// +//***************************************************************************** +extern uint32_t +MemCfg_getUncorrErrorAddress(uint32_t stsFlag); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // MEMCFG_H diff --git a/gpio_driverlib_cpu1/device/driverlib/pin_map.h b/gpio_driverlib_cpu1/device/driverlib/pin_map.h new file mode 100644 index 0000000..95c6fa3 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/pin_map.h @@ -0,0 +1,894 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_H__ +#define __PIN_MAP_H__ + +//***************************************************************************** +// 0x00000003 = MUX register value +// 0x0000000C = GMUX register value +// 0x0000FF00 = Shift amount within mux registers +// 0xFFFF0000 = Offset of MUX register +//***************************************************************************** + + +#define GPIO_0_GPIO0 0x00060000U +#define GPIO_0_EPWM1A 0x00060001U +#define GPIO_0_SDAA 0x00060006U + +#define GPIO_1_GPIO1 0x00060200U +#define GPIO_1_EPWM1B 0x00060201U +#define GPIO_1_MFSRB 0x00060203U +#define GPIO_1_SCLA 0x00060206U + +#define GPIO_2_GPIO2 0x00060400U +#define GPIO_2_EPWM2A 0x00060401U +#define GPIO_2_OUTPUTXBAR1 0x00060405U +#define GPIO_2_SDAB 0x00060406U + +#define GPIO_3_GPIO3 0x00060600U +#define GPIO_3_EPWM2B 0x00060601U +#define GPIO_3_OUTPUTXBAR2 0x00060602U +#define GPIO_3_MCLKRB 0x00060603U +#define GPIO_3_SCLB 0x00060606U + +#define GPIO_4_GPIO4 0x00060800U +#define GPIO_4_EPWM3A 0x00060801U +#define GPIO_4_OUTPUTXBAR3 0x00060805U +#define GPIO_4_CANTXA 0x00060806U + +#define GPIO_5_GPIO5 0x00060A00U +#define GPIO_5_EPWM3B 0x00060A01U +#define GPIO_5_MFSRA 0x00060A02U +#define GPIO_5_OUTPUTXBAR3 0x00060A03U +#define GPIO_5_CANRXA 0x00060A06U + +#define GPIO_6_GPIO6 0x00060C00U +#define GPIO_6_EPWM4A 0x00060C01U +#define GPIO_6_OUTPUTXBAR4 0x00060C02U +#define GPIO_6_EPWMSYNCO 0x00060C03U +#define GPIO_6_EQEP3A 0x00060C05U +#define GPIO_6_CANTXB 0x00060C06U + +#define GPIO_7_GPIO7 0x00060E00U +#define GPIO_7_EPWM4B 0x00060E01U +#define GPIO_7_MCLKRA 0x00060E02U +#define GPIO_7_OUTPUTXBAR5 0x00060E03U +#define GPIO_7_EQEP3B 0x00060E05U +#define GPIO_7_CANRXB 0x00060E06U + +#define GPIO_8_GPIO8 0x00061000U +#define GPIO_8_EPWM5A 0x00061001U +#define GPIO_8_CANTXB 0x00061002U +#define GPIO_8_ADCSOCAO 0x00061003U +#define GPIO_8_EQEP3S 0x00061005U +#define GPIO_8_SCITXDA 0x00061006U + +#define GPIO_9_GPIO9 0x00061200U +#define GPIO_9_EPWM5B 0x00061201U +#define GPIO_9_SCITXDB 0x00061202U +#define GPIO_9_OUTPUTXBAR6 0x00061203U +#define GPIO_9_EQEP3I 0x00061205U +#define GPIO_9_SCIRXDA 0x00061206U + +#define GPIO_10_GPIO10 0x00061400U +#define GPIO_10_EPWM6A 0x00061401U +#define GPIO_10_CANRXB 0x00061402U +#define GPIO_10_ADCSOCBO 0x00061403U +#define GPIO_10_EQEP1A 0x00061405U +#define GPIO_10_SCITXDB 0x00061406U +#define GPIO_10_UPP_WAIT 0x0006140FU + +#define GPIO_11_GPIO11 0x00061600U +#define GPIO_11_EPWM6B 0x00061601U +#define GPIO_11_SCIRXDB 0x00061602U +#define GPIO_11_OUTPUTXBAR7 0x00061603U +#define GPIO_11_EQEP1B 0x00061605U +#define GPIO_11_UPP_STRT 0x0006160FU + +#define GPIO_12_GPIO12 0x00061800U +#define GPIO_12_EPWM7A 0x00061801U +#define GPIO_12_CANTXB 0x00061802U +#define GPIO_12_MDXB 0x00061803U +#define GPIO_12_EQEP1S 0x00061805U +#define GPIO_12_SCITXDC 0x00061806U +#define GPIO_12_UPP_ENA 0x0006180FU + +#define GPIO_13_GPIO13 0x00061A00U +#define GPIO_13_EPWM7B 0x00061A01U +#define GPIO_13_CANRXB 0x00061A02U +#define GPIO_13_MDRB 0x00061A03U +#define GPIO_13_EQEP1I 0x00061A05U +#define GPIO_13_SCIRXDC 0x00061A06U +#define GPIO_13_UPP_D7 0x00061A0FU + +#define GPIO_14_GPIO14 0x00061C00U +#define GPIO_14_EPWM8A 0x00061C01U +#define GPIO_14_SCITXDB 0x00061C02U +#define GPIO_14_MCLKXB 0x00061C03U +#define GPIO_14_OUTPUTXBAR3 0x00061C06U +#define GPIO_14_UPP_D6 0x00061C0FU + +#define GPIO_15_GPIO15 0x00061E00U +#define GPIO_15_EPWM8B 0x00061E01U +#define GPIO_15_SCIRXDB 0x00061E02U +#define GPIO_15_MFSXB 0x00061E03U +#define GPIO_15_OUTPUTXBAR4 0x00061E06U +#define GPIO_15_UPP_D5 0x00061E0FU + +#define GPIO_16_GPIO16 0x00080000U +#define GPIO_16_SPISIMOA 0x00080001U +#define GPIO_16_CANTXB 0x00080002U +#define GPIO_16_OUTPUTXBAR7 0x00080003U +#define GPIO_16_EPWM9A 0x00080005U +#define GPIO_16_SD1_D1 0x00080007U +#define GPIO_16_UPP_D4 0x0008000FU + +#define GPIO_17_GPIO17 0x00080200U +#define GPIO_17_SPISOMIA 0x00080201U +#define GPIO_17_CANRXB 0x00080202U +#define GPIO_17_OUTPUTXBAR8 0x00080203U +#define GPIO_17_EPWM9B 0x00080205U +#define GPIO_17_SD1_C1 0x00080207U +#define GPIO_17_UPP_D3 0x0008020FU + +#define GPIO_18_GPIO18 0x00080400U +#define GPIO_18_SPICLKA 0x00080401U +#define GPIO_18_SCITXDB 0x00080402U +#define GPIO_18_CANRXA 0x00080403U +#define GPIO_18_EPWM10A 0x00080405U +#define GPIO_18_SD1_D2 0x00080407U +#define GPIO_18_UPP_D2 0x0008040FU + +#define GPIO_19_GPIO19 0x00080600U +#define GPIO_19_SPISTEA 0x00080601U +#define GPIO_19_SCIRXDB 0x00080602U +#define GPIO_19_CANTXA 0x00080603U +#define GPIO_19_EPWM10B 0x00080605U +#define GPIO_19_SD1_C2 0x00080607U +#define GPIO_19_UPP_D1 0x0008060FU + +#define GPIO_20_GPIO20 0x00080800U +#define GPIO_20_EQEP1A 0x00080801U +#define GPIO_20_MDXA 0x00080802U +#define GPIO_20_CANTXB 0x00080803U +#define GPIO_20_EPWM11A 0x00080805U +#define GPIO_20_SD1_D3 0x00080807U +#define GPIO_20_UPP_D0 0x0008080FU + +#define GPIO_21_GPIO21 0x00080A00U +#define GPIO_21_EQEP1B 0x00080A01U +#define GPIO_21_MDRA 0x00080A02U +#define GPIO_21_CANRXB 0x00080A03U +#define GPIO_21_EPWM11B 0x00080A05U +#define GPIO_21_SD1_C3 0x00080A07U +#define GPIO_21_UPP_CLK 0x00080A0FU + +#define GPIO_22_GPIO22 0x00080C00U +#define GPIO_22_EQEP1S 0x00080C01U +#define GPIO_22_MCLKXA 0x00080C02U +#define GPIO_22_SCITXDB 0x00080C03U +#define GPIO_22_EPWM12A 0x00080C05U +#define GPIO_22_SPICLKB 0x00080C06U +#define GPIO_22_SD1_D4 0x00080C07U + +#define GPIO_23_GPIO23 0x00080E00U +#define GPIO_23_EQEP1I 0x00080E01U +#define GPIO_23_MFSXA 0x00080E02U +#define GPIO_23_SCIRXDB 0x00080E03U +#define GPIO_23_EPWM12B 0x00080E05U +#define GPIO_23_SPISTEB 0x00080E06U +#define GPIO_23_SD1_C4 0x00080E07U + +#define GPIO_24_GPIO24 0x00081000U +#define GPIO_24_OUTPUTXBAR1 0x00081001U +#define GPIO_24_EQEP2A 0x00081002U +#define GPIO_24_MDXB 0x00081003U +#define GPIO_24_SPISIMOB 0x00081006U +#define GPIO_24_SD2_D1 0x00081007U + +#define GPIO_25_GPIO25 0x00081200U +#define GPIO_25_OUTPUTXBAR2 0x00081201U +#define GPIO_25_EQEP2B 0x00081202U +#define GPIO_25_MDRB 0x00081203U +#define GPIO_25_SPISOMIB 0x00081206U +#define GPIO_25_SD2_C1 0x00081207U + +#define GPIO_26_GPIO26 0x00081400U +#define GPIO_26_OUTPUTXBAR3 0x00081401U +#define GPIO_26_EQEP2I 0x00081402U +#define GPIO_26_MCLKXB 0x00081403U +#define GPIO_26_SPICLKB 0x00081406U +#define GPIO_26_SD2_D2 0x00081407U + +#define GPIO_27_GPIO27 0x00081600U +#define GPIO_27_OUTPUTXBAR4 0x00081601U +#define GPIO_27_EQEP2S 0x00081602U +#define GPIO_27_MFSXB 0x00081603U +#define GPIO_27_SPISTEB 0x00081606U +#define GPIO_27_SD2_C2 0x00081607U + +#define GPIO_28_GPIO28 0x00081800U +#define GPIO_28_SCIRXDA 0x00081801U +#define GPIO_28_EM1CS4N 0x00081802U +#define GPIO_28_OUTPUTXBAR5 0x00081805U +#define GPIO_28_EQEP3A 0x00081806U +#define GPIO_28_SD2_D3 0x00081807U + +#define GPIO_29_GPIO29 0x00081A00U +#define GPIO_29_SCITXDA 0x00081A01U +#define GPIO_29_EM1SDCKE 0x00081A02U +#define GPIO_29_OUTPUTXBAR6 0x00081A05U +#define GPIO_29_EQEP3B 0x00081A06U +#define GPIO_29_SD2_C3 0x00081A07U + +#define GPIO_30_GPIO30 0x00081C00U +#define GPIO_30_CANRXA 0x00081C01U +#define GPIO_30_EM1CLK 0x00081C02U +#define GPIO_30_OUTPUTXBAR7 0x00081C05U +#define GPIO_30_EQEP3S 0x00081C06U +#define GPIO_30_SD2_D4 0x00081C07U + +#define GPIO_31_GPIO31 0x00081E00U +#define GPIO_31_CANTXA 0x00081E01U +#define GPIO_31_EM1WEN 0x00081E02U +#define GPIO_31_OUTPUTXBAR8 0x00081E05U +#define GPIO_31_EQEP3I 0x00081E06U +#define GPIO_31_SD2_C4 0x00081E07U + +#define GPIO_32_GPIO32 0x00460000U +#define GPIO_32_SDAA 0x00460001U +#define GPIO_32_EM1CS0N 0x00460002U + +#define GPIO_33_GPIO33 0x00460200U +#define GPIO_33_SCLA 0x00460201U +#define GPIO_33_EM1RNW 0x00460202U + +#define GPIO_34_GPIO34 0x00460400U +#define GPIO_34_OUTPUTXBAR1 0x00460401U +#define GPIO_34_EM1CS2N 0x00460402U +#define GPIO_34_SDAB 0x00460406U +#define GPIO_34_OFSD_2_N 0x0046040FU + +#define GPIO_35_GPIO35 0x00460600U +#define GPIO_35_SCIRXDA 0x00460601U +#define GPIO_35_EM1CS3N 0x00460602U +#define GPIO_35_SCLB 0x00460606U +#define GPIO_35_IID 0x0046060FU + +#define GPIO_36_GPIO36 0x00460800U +#define GPIO_36_SCITXDA 0x00460801U +#define GPIO_36_EM1WAIT 0x00460802U +#define GPIO_36_CANRXA 0x00460806U +#define GPIO_36_ISESSEND 0x0046080FU + +#define GPIO_37_GPIO37 0x00460A00U +#define GPIO_37_OUTPUTXBAR2 0x00460A01U +#define GPIO_37_EM1OEN 0x00460A02U +#define GPIO_37_CANTXA 0x00460A06U +#define GPIO_37_IAVALID 0x00460A0FU + +#define GPIO_38_GPIO38 0x00460C00U +#define GPIO_38_EM1A0 0x00460C02U +#define GPIO_38_SCITXDC 0x00460C05U +#define GPIO_38_CANTXB 0x00460C06U + +#define GPIO_39_GPIO39 0x00460E00U +#define GPIO_39_EM1A1 0x00460E02U +#define GPIO_39_SCIRXDC 0x00460E05U +#define GPIO_39_CANRXB 0x00460E06U + +#define GPIO_40_GPIO40 0x00461000U +#define GPIO_40_EM1A2 0x00461002U +#define GPIO_40_SDAB 0x00461006U + +#define GPIO_41_GPIO41 0x00461200U +#define GPIO_41_EM1A3 0x00461202U +#define GPIO_41_EMU1 0x00461203U +#define GPIO_41_SCLB 0x00461206U + +#define GPIO_42_GPIO42 0x00461400U +#define GPIO_42_SDAA 0x00461406U +#define GPIO_42_SCITXDA 0x0046140FU + +#define GPIO_43_GPIO43 0x00461600U +#define GPIO_43_SCLA 0x00461606U +#define GPIO_43_SCIRXDA 0x0046160FU + +#define GPIO_44_GPIO44 0x00461800U +#define GPIO_44_EM1A4 0x00461802U +#define GPIO_44_IXRCV 0x0046180FU + +#define GPIO_45_GPIO45 0x00461A00U +#define GPIO_45_EM1A5 0x00461A02U +#define GPIO_45_IDM 0x00461A0FU + +#define GPIO_46_GPIO46 0x00461C00U +#define GPIO_46_EM1A6 0x00461C02U +#define GPIO_46_SCIRXDD 0x00461C06U +#define GPIO_46_IDP 0x00461C0FU + +#define GPIO_47_GPIO47 0x00461E00U +#define GPIO_47_EM1A7 0x00461E02U +#define GPIO_47_SCITXDD 0x00461E06U +#define GPIO_47_OFSD_1_N 0x00461E0FU + +#define GPIO_48_GPIO48 0x00480000U +#define GPIO_48_OUTPUTXBAR3 0x00480001U +#define GPIO_48_EM1A8 0x00480002U +#define GPIO_48_SCITXDA 0x00480006U +#define GPIO_48_SD1_D1 0x00480007U + +#define GPIO_49_GPIO49 0x00480200U +#define GPIO_49_OUTPUTXBAR4 0x00480201U +#define GPIO_49_EM1A9 0x00480202U +#define GPIO_49_SCIRXDA 0x00480206U +#define GPIO_49_SD1_C1 0x00480207U + +#define GPIO_50_GPIO50 0x00480400U +#define GPIO_50_EQEP1A 0x00480401U +#define GPIO_50_EM1A10 0x00480402U +#define GPIO_50_SPISIMOC 0x00480406U +#define GPIO_50_SD1_D2 0x00480407U + +#define GPIO_51_GPIO51 0x00480600U +#define GPIO_51_EQEP1B 0x00480601U +#define GPIO_51_EM1A11 0x00480602U +#define GPIO_51_SPISOMIC 0x00480606U +#define GPIO_51_SD1_C2 0x00480607U + +#define GPIO_52_GPIO52 0x00480800U +#define GPIO_52_EQEP1S 0x00480801U +#define GPIO_52_EM1A12 0x00480802U +#define GPIO_52_SPICLKC 0x00480806U +#define GPIO_52_SD1_D3 0x00480807U + +#define GPIO_53_GPIO53 0x00480A00U +#define GPIO_53_EQEP1I 0x00480A01U +#define GPIO_53_EM1D31 0x00480A02U +#define GPIO_53_EM2D15 0x00480A03U +#define GPIO_53_SPISTEC 0x00480A06U +#define GPIO_53_SD1_C3 0x00480A07U + +#define GPIO_54_GPIO54 0x00480C00U +#define GPIO_54_SPISIMOA 0x00480C01U +#define GPIO_54_EM1D30 0x00480C02U +#define GPIO_54_EM2D14 0x00480C03U +#define GPIO_54_EQEP2A 0x00480C05U +#define GPIO_54_SCITXDB 0x00480C06U +#define GPIO_54_SD1_D4 0x00480C07U + +#define GPIO_55_GPIO55 0x00480E00U +#define GPIO_55_SPISOMIA 0x00480E01U +#define GPIO_55_EM1D29 0x00480E02U +#define GPIO_55_EM2D13 0x00480E03U +#define GPIO_55_EQEP2B 0x00480E05U +#define GPIO_55_SCIRXDB 0x00480E06U +#define GPIO_55_SD1_C4 0x00480E07U + +#define GPIO_56_GPIO56 0x00481000U +#define GPIO_56_SPICLKA 0x00481001U +#define GPIO_56_EM1D28 0x00481002U +#define GPIO_56_EM2D12 0x00481003U +#define GPIO_56_EQEP2S 0x00481005U +#define GPIO_56_SCITXDC 0x00481006U +#define GPIO_56_SD2_D1 0x00481007U + +#define GPIO_57_GPIO57 0x00481200U +#define GPIO_57_SPISTEA 0x00481201U +#define GPIO_57_EM1D27 0x00481202U +#define GPIO_57_EM2D11 0x00481203U +#define GPIO_57_EQEP2I 0x00481205U +#define GPIO_57_SCIRXDC 0x00481206U +#define GPIO_57_SD2_C1 0x00481207U + +#define GPIO_58_GPIO58 0x00481400U +#define GPIO_58_MCLKRA 0x00481401U +#define GPIO_58_EM1D26 0x00481402U +#define GPIO_58_EM2D10 0x00481403U +#define GPIO_58_OUTPUTXBAR1 0x00481405U +#define GPIO_58_SPICLKB 0x00481406U +#define GPIO_58_SD2_D2 0x00481407U +#define GPIO_58_SPISIMOA 0x0048140FU + +#define GPIO_59_GPIO59 0x00481600U +#define GPIO_59_MFSRA 0x00481601U +#define GPIO_59_EM1D25 0x00481602U +#define GPIO_59_EM2D9 0x00481603U +#define GPIO_59_OUTPUTXBAR2 0x00481605U +#define GPIO_59_SPISTEB 0x00481606U +#define GPIO_59_SD2_C2 0x00481607U +#define GPIO_59_SPISOMIA 0x0048160FU + +#define GPIO_60_GPIO60 0x00481800U +#define GPIO_60_MCLKRB 0x00481801U +#define GPIO_60_EM1D24 0x00481802U +#define GPIO_60_EM2D8 0x00481803U +#define GPIO_60_OUTPUTXBAR3 0x00481805U +#define GPIO_60_SPISIMOB 0x00481806U +#define GPIO_60_SD2_D3 0x00481807U +#define GPIO_60_SPICLKA 0x0048180FU + +#define GPIO_61_GPIO61 0x00481A00U +#define GPIO_61_MFSRB 0x00481A01U +#define GPIO_61_EM1D23 0x00481A02U +#define GPIO_61_EM2D7 0x00481A03U +#define GPIO_61_OUTPUTXBAR4 0x00481A05U +#define GPIO_61_SPISOMIB 0x00481A06U +#define GPIO_61_SD2_C3 0x00481A07U +#define GPIO_61_SPISTEA 0x00481A0FU + +#define GPIO_62_GPIO62 0x00481C00U +#define GPIO_62_SCIRXDC 0x00481C01U +#define GPIO_62_EM1D22 0x00481C02U +#define GPIO_62_EM2D6 0x00481C03U +#define GPIO_62_EQEP3A 0x00481C05U +#define GPIO_62_CANRXA 0x00481C06U +#define GPIO_62_SD2_D4 0x00481C07U + +#define GPIO_63_GPIO63 0x00481E00U +#define GPIO_63_SCITXDC 0x00481E01U +#define GPIO_63_EM1D21 0x00481E02U +#define GPIO_63_EM2D5 0x00481E03U +#define GPIO_63_EQEP3B 0x00481E05U +#define GPIO_63_CANTXA 0x00481E06U +#define GPIO_63_SD2_C4 0x00481E07U +#define GPIO_63_SPISIMOB 0x00481E0FU + +#define GPIO_64_GPIO64 0x00860000U +#define GPIO_64_EM1D20 0x00860002U +#define GPIO_64_EM2D4 0x00860003U +#define GPIO_64_EQEP3S 0x00860005U +#define GPIO_64_SCIRXDA 0x00860006U +#define GPIO_64_SPISOMIB 0x0086000FU + +#define GPIO_65_GPIO65 0x00860200U +#define GPIO_65_EM1D19 0x00860202U +#define GPIO_65_EM2D3 0x00860203U +#define GPIO_65_EQEP3I 0x00860205U +#define GPIO_65_SCITXDA 0x00860206U +#define GPIO_65_SPICLKB 0x0086020FU + +#define GPIO_66_GPIO66 0x00860400U +#define GPIO_66_EM1D18 0x00860402U +#define GPIO_66_EM2D2 0x00860403U +#define GPIO_66_SDAB 0x00860406U +#define GPIO_66_SPISTEB 0x0086040FU + +#define GPIO_67_GPIO67 0x00860600U +#define GPIO_67_EM1D17 0x00860602U +#define GPIO_67_EM2D1 0x00860603U + +#define GPIO_68_GPIO68 0x00860800U +#define GPIO_68_EM1D16 0x00860802U +#define GPIO_68_EM2D0 0x00860803U + +#define GPIO_69_GPIO69 0x00860A00U +#define GPIO_69_EM1D15 0x00860A02U +#define GPIO_69_EMU0 0x00860A03U +#define GPIO_69_SCLB 0x00860A06U +#define GPIO_69_SPISIMOC 0x00860A0FU + +#define GPIO_70_GPIO70 0x00860C00U +#define GPIO_70_EM1D14 0x00860C02U +#define GPIO_70_EMU0 0x00860C03U +#define GPIO_70_CANRXA 0x00860C05U +#define GPIO_70_SCITXDB 0x00860C06U +#define GPIO_70_SPISOMIC 0x00860C0FU + +#define GPIO_71_GPIO71 0x00860E00U +#define GPIO_71_EM1D13 0x00860E02U +#define GPIO_71_EMU1 0x00860E03U +#define GPIO_71_CANTXA 0x00860E05U +#define GPIO_71_SCIRXDB 0x00860E06U +#define GPIO_71_SPICLKC 0x00860E0FU + +#define GPIO_72_GPIO72 0x00861000U +#define GPIO_72_EM1D12 0x00861002U +#define GPIO_72_CANTXB 0x00861005U +#define GPIO_72_SCITXDC 0x00861006U +#define GPIO_72_SPISTEC 0x0086100FU + +#define GPIO_73_GPIO73 0x00861200U +#define GPIO_73_EM1D11 0x00861202U +#define GPIO_73_XCLKOUT 0x00861203U +#define GPIO_73_CANRXB 0x00861205U +#define GPIO_73_SCIRXDC 0x00861206U + +#define GPIO_74_GPIO74 0x00861400U +#define GPIO_74_EM1D10 0x00861402U + +#define GPIO_75_GPIO75 0x00861600U +#define GPIO_75_EM1D9 0x00861602U + +#define GPIO_76_GPIO76 0x00861800U +#define GPIO_76_EM1D8 0x00861802U +#define GPIO_76_SCITXDD 0x00861806U + +#define GPIO_77_GPIO77 0x00861A00U +#define GPIO_77_EM1D7 0x00861A02U +#define GPIO_77_SCIRXDD 0x00861A06U + +#define GPIO_78_GPIO78 0x00861C00U +#define GPIO_78_EM1D6 0x00861C02U +#define GPIO_78_EQEP2A 0x00861C06U + +#define GPIO_79_GPIO79 0x00861E00U +#define GPIO_79_EM1D5 0x00861E02U +#define GPIO_79_EQEP2B 0x00861E06U + +#define GPIO_80_GPIO80 0x00880000U +#define GPIO_80_EM1D4 0x00880002U +#define GPIO_80_EQEP2S 0x00880006U + +#define GPIO_81_GPIO81 0x00880200U +#define GPIO_81_EM1D3 0x00880202U +#define GPIO_81_EQEP2I 0x00880206U + +#define GPIO_82_GPIO82 0x00880400U +#define GPIO_82_EM1D2 0x00880402U + +#define GPIO_83_GPIO83 0x00880600U +#define GPIO_83_EM1D1 0x00880602U + +#define GPIO_84_GPIO84 0x00880800U +#define GPIO_84_SCITXDA 0x00880805U +#define GPIO_84_MDXB 0x00880806U +#define GPIO_84_MDXA 0x0088080FU + +#define GPIO_85_GPIO85 0x00880A00U +#define GPIO_85_EM1D0 0x00880A02U +#define GPIO_85_SCIRXDA 0x00880A05U +#define GPIO_85_MDRB 0x00880A06U +#define GPIO_85_MDRA 0x00880A0FU + +#define GPIO_86_GPIO86 0x00880C00U +#define GPIO_86_EM1A13 0x00880C02U +#define GPIO_86_EM1CAS 0x00880C03U +#define GPIO_86_SCITXDB 0x00880C05U +#define GPIO_86_MCLKXB 0x00880C06U +#define GPIO_86_MCLKXA 0x00880C0FU + +#define GPIO_87_GPIO87 0x00880E00U +#define GPIO_87_EM1A14 0x00880E02U +#define GPIO_87_EM1RAS 0x00880E03U +#define GPIO_87_SCIRXDB 0x00880E05U +#define GPIO_87_MFSXB 0x00880E06U +#define GPIO_87_MFSXA 0x00880E0FU + +#define GPIO_88_GPIO88 0x00881000U +#define GPIO_88_EM1A15 0x00881002U +#define GPIO_88_EM1DQM0 0x00881003U + +#define GPIO_89_GPIO89 0x00881200U +#define GPIO_89_EM1A16 0x00881202U +#define GPIO_89_EM1DQM1 0x00881203U +#define GPIO_89_SCITXDC 0x00881206U + +#define GPIO_90_GPIO90 0x00881400U +#define GPIO_90_EM1A17 0x00881402U +#define GPIO_90_EM1DQM2 0x00881403U +#define GPIO_90_SCIRXDC 0x00881406U + +#define GPIO_91_GPIO91 0x00881600U +#define GPIO_91_EM1A18 0x00881602U +#define GPIO_91_EM1DQM3 0x00881603U +#define GPIO_91_SDAA 0x00881606U + +#define GPIO_92_GPIO92 0x00881800U +#define GPIO_92_EM1A19 0x00881802U +#define GPIO_92_EM1BA1 0x00881803U +#define GPIO_92_SCLA 0x00881806U + +#define GPIO_93_GPIO93 0x00881A00U +#define GPIO_93_EM1A20 0x00881A02U +#define GPIO_93_EM1BA0 0x00881A03U +#define GPIO_93_SCITXDD 0x00881A06U + +#define GPIO_94_GPIO94 0x00881C00U +#define GPIO_94_EM1A21 0x00881C02U +#define GPIO_94_SCIRXDD 0x00881C06U + +#define GPIO_95_GPIO95 0x00881E00U + +#define GPIO_96_GPIO96 0x00C60000U +#define GPIO_96_EM2DQM1 0x00C60003U +#define GPIO_96_EQEP1A 0x00C60005U + +#define GPIO_97_GPIO97 0x00C60200U +#define GPIO_97_EM2DQM0 0x00C60203U +#define GPIO_97_EQEP1B 0x00C60205U + +#define GPIO_98_GPIO98 0x00C60400U +#define GPIO_98_EM2A0 0x00C60403U +#define GPIO_98_EQEP1S 0x00C60405U + +#define GPIO_99_GPIO99 0x00C60600U +#define GPIO_99_EM2A1 0x00C60603U +#define GPIO_99_EQEP1I 0x00C60605U + +#define GPIO_100_GPIO100 0x00C60800U +#define GPIO_100_EM2A2 0x00C60803U +#define GPIO_100_EQEP2A 0x00C60805U +#define GPIO_100_SPISIMOC 0x00C60806U + +#define GPIO_101_GPIO101 0x00C60A00U +#define GPIO_101_EM2A3 0x00C60A03U +#define GPIO_101_EQEP2B 0x00C60A05U +#define GPIO_101_SPISOMIC 0x00C60A06U + +#define GPIO_102_GPIO102 0x00C60C00U +#define GPIO_102_EM2A4 0x00C60C03U +#define GPIO_102_EQEP2S 0x00C60C05U +#define GPIO_102_SPICLKC 0x00C60C06U + +#define GPIO_103_GPIO103 0x00C60E00U +#define GPIO_103_EM2A5 0x00C60E03U +#define GPIO_103_EQEP2I 0x00C60E05U +#define GPIO_103_SPISTEC 0x00C60E06U + +#define GPIO_104_GPIO104 0x00C61000U +#define GPIO_104_SDAA 0x00C61001U +#define GPIO_104_EM2A6 0x00C61003U +#define GPIO_104_EQEP3A 0x00C61005U +#define GPIO_104_SCITXDD 0x00C61006U + +#define GPIO_105_GPIO105 0x00C61200U +#define GPIO_105_SCLA 0x00C61201U +#define GPIO_105_EM2A7 0x00C61203U +#define GPIO_105_EQEP3B 0x00C61205U +#define GPIO_105_SCIRXDD 0x00C61206U + +#define GPIO_106_GPIO106 0x00C61400U +#define GPIO_106_EM2A8 0x00C61403U +#define GPIO_106_EQEP3S 0x00C61405U +#define GPIO_106_SCITXDC 0x00C61406U + +#define GPIO_107_GPIO107 0x00C61600U +#define GPIO_107_EM2A9 0x00C61603U +#define GPIO_107_EQEP3I 0x00C61605U +#define GPIO_107_SCIRXDC 0x00C61606U + +#define GPIO_108_GPIO108 0x00C61800U +#define GPIO_108_EM2A10 0x00C61803U + +#define GPIO_109_GPIO109 0x00C61A00U +#define GPIO_109_EM2A11 0x00C61A03U + +#define GPIO_110_GPIO110 0x00C61C00U +#define GPIO_110_EM2WAIT 0x00C61C03U + +#define GPIO_111_GPIO111 0x00C61E00U +#define GPIO_111_EM2BA0 0x00C61E03U + +#define GPIO_112_GPIO112 0x00C80000U +#define GPIO_112_EM2BA1 0x00C80003U + +#define GPIO_113_GPIO113 0x00C80200U +#define GPIO_113_EM2CAS 0x00C80203U + +#define GPIO_114_GPIO114 0x00C80400U +#define GPIO_114_EM2RAS 0x00C80403U + +#define GPIO_115_GPIO115 0x00C80600U +#define GPIO_115_EM2CS0N 0x00C80603U + +#define GPIO_116_GPIO116 0x00C80800U +#define GPIO_116_EM2CS2N 0x00C80803U + +#define GPIO_117_GPIO117 0x00C80A00U +#define GPIO_117_EM2SDCKE 0x00C80A03U + +#define GPIO_118_GPIO118 0x00C80C00U +#define GPIO_118_EM2CLK 0x00C80C03U + +#define GPIO_119_GPIO119 0x00C80E00U +#define GPIO_119_EM2RNW 0x00C80E03U + +#define GPIO_120_GPIO120 0x00C81000U +#define GPIO_120_EM2WEN 0x00C81003U +#define GPIO_120_USB0PFLT 0x00C8100FU + +#define GPIO_121_GPIO121 0x00C81200U +#define GPIO_121_EM2OEN 0x00C81203U +#define GPIO_121_USB0EPEN 0x00C8120FU + +#define GPIO_122_GPIO122 0x00C81400U +#define GPIO_122_SPISIMOC 0x00C81406U +#define GPIO_122_SD1_D1 0x00C81407U +#define GPIO_122_ODISCHRGVBUS 0x00C8140FU + +#define GPIO_123_GPIO123 0x00C81600U +#define GPIO_123_SPISOMIC 0x00C81606U +#define GPIO_123_SD1_C1 0x00C81607U +#define GPIO_123_OCHRGVBUS 0x00C8160FU + +#define GPIO_124_GPIO124 0x00C81800U +#define GPIO_124_SPICLKC 0x00C81806U +#define GPIO_124_SD1_D2 0x00C81807U +#define GPIO_124_ODMPULLDN 0x00C8180FU + +#define GPIO_125_GPIO125 0x00C81A00U +#define GPIO_125_SPISTEC 0x00C81A06U +#define GPIO_125_SD1_C2 0x00C81A07U +#define GPIO_125_ODPPULLDN 0x00C81A0FU + +#define GPIO_126_GPIO126 0x00C81C00U +#define GPIO_126_SD1_D3 0x00C81C07U +#define GPIO_126_OLSD_2_N 0x00C81C0FU + +#define GPIO_127_GPIO127 0x00C81E00U +#define GPIO_127_SD1_C3 0x00C81E07U +#define GPIO_127_OLSD_1_N 0x00C81E0FU + +#define GPIO_128_GPIO128 0x01060000U +#define GPIO_128_SD1_D4 0x01060007U +#define GPIO_128_OIDPULLUP 0x0106000FU + +#define GPIO_129_GPIO129 0x01060200U +#define GPIO_129_SD1_C4 0x01060207U +#define GPIO_129_OSPEED 0x0106020FU + +#define GPIO_130_GPIO130 0x01060400U +#define GPIO_130_SD2_D1 0x01060407U +#define GPIO_130_OSUSPEND 0x0106040FU + +#define GPIO_131_GPIO131 0x01060600U +#define GPIO_131_SD2_C1 0x01060607U +#define GPIO_131_OOE 0x0106060FU + +#define GPIO_132_GPIO132 0x01060800U +#define GPIO_132_SD2_D2 0x01060807U +#define GPIO_132_ODMSE1 0x0106080FU + +#define GPIO_133_GPIO133 0x01060A00U +#define GPIO_133_SD2_C2 0x01060A07U +#define GPIO_133_ODPDAT 0x01060A0FU + +#define GPIO_134_GPIO134 0x01060C00U +#define GPIO_134_SD2_D3 0x01060C07U +#define GPIO_134_IVBUSVALID 0x01060C0FU + +#define GPIO_135_GPIO135 0x01060E00U +#define GPIO_135_SCITXDA 0x01060E06U +#define GPIO_135_SD2_C3 0x01060E07U + +#define GPIO_136_GPIO136 0x01061000U +#define GPIO_136_SCIRXDA 0x01061006U +#define GPIO_136_SD2_D4 0x01061007U + +#define GPIO_137_GPIO137 0x01061200U +#define GPIO_137_SCITXDB 0x01061206U +#define GPIO_137_SD2_C4 0x01061207U + +#define GPIO_138_GPIO138 0x01061400U +#define GPIO_138_SCIRXDB 0x01061406U + +#define GPIO_139_GPIO139 0x01061600U +#define GPIO_139_SCIRXDC 0x01061606U + +#define GPIO_140_GPIO140 0x01061800U +#define GPIO_140_SCITXDC 0x01061806U + +#define GPIO_141_GPIO141 0x01061A00U +#define GPIO_141_SCIRXDD 0x01061A06U + +#define GPIO_142_GPIO142 0x01061C00U +#define GPIO_142_SCITXDD 0x01061C06U + +#define GPIO_143_GPIO143 0x01061E00U + +#define GPIO_144_GPIO144 0x01080000U + +#define GPIO_145_GPIO145 0x01080200U +#define GPIO_145_EPWM1A 0x01080201U + +#define GPIO_146_GPIO146 0x01080400U +#define GPIO_146_EPWM1B 0x01080401U + +#define GPIO_147_GPIO147 0x01080600U +#define GPIO_147_EPWM2A 0x01080601U + +#define GPIO_148_GPIO148 0x01080800U +#define GPIO_148_EPWM2B 0x01080801U + +#define GPIO_149_GPIO149 0x01080A00U +#define GPIO_149_EPWM3A 0x01080A01U + +#define GPIO_150_GPIO150 0x01080C00U +#define GPIO_150_EPWM3B 0x01080C01U + +#define GPIO_151_GPIO151 0x01080E00U +#define GPIO_151_EPWM4A 0x01080E01U + +#define GPIO_152_GPIO152 0x01081000U +#define GPIO_152_EPWM4B 0x01081001U + +#define GPIO_153_GPIO153 0x01081200U +#define GPIO_153_EPWM5A 0x01081201U + +#define GPIO_154_GPIO154 0x01081400U +#define GPIO_154_EPWM5B 0x01081401U + +#define GPIO_155_GPIO155 0x01081600U +#define GPIO_155_EPWM6A 0x01081601U + +#define GPIO_156_GPIO156 0x01081800U +#define GPIO_156_EPWM6B 0x01081801U + +#define GPIO_157_GPIO157 0x01081A00U +#define GPIO_157_EPWM7A 0x01081A01U + +#define GPIO_158_GPIO158 0x01081C00U +#define GPIO_158_EPWM7B 0x01081C01U + +#define GPIO_159_GPIO159 0x01081E00U +#define GPIO_159_EPWM8A 0x01081E01U + +#define GPIO_160_GPIO160 0x01460000U +#define GPIO_160_EPWM8B 0x01460001U + +#define GPIO_161_GPIO161 0x01460200U +#define GPIO_161_EPWM9A 0x01460201U + +#define GPIO_162_GPIO162 0x01460400U +#define GPIO_162_EPWM9B 0x01460401U + +#define GPIO_163_GPIO163 0x01460600U +#define GPIO_163_EPWM10A 0x01460601U + +#define GPIO_164_GPIO164 0x01460800U +#define GPIO_164_EPWM10B 0x01460801U + +#define GPIO_165_GPIO165 0x01460A00U +#define GPIO_165_EPWM11A 0x01460A01U + +#define GPIO_166_GPIO166 0x01460C00U +#define GPIO_166_EPWM11B 0x01460C01U + +#define GPIO_167_GPIO167 0x01460E00U +#define GPIO_167_EPWM12A 0x01460E01U + +#define GPIO_168_GPIO168 0x01461000U +#define GPIO_168_EPWM12B 0x01461001U + +#endif // PIN_MAP_H diff --git a/gpio_driverlib_cpu1/device/driverlib/pin_map_legacy.h b/gpio_driverlib_cpu1/device/driverlib/pin_map_legacy.h new file mode 100644 index 0000000..c503ad4 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/pin_map_legacy.h @@ -0,0 +1,95 @@ +//########################################################################### +// +// FILE: pin_map.h +// +// TITLE: Legacy definitions of pin mux info for gpio.c. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef __PIN_MAP_LEGACY_H__ +#define __PIN_MAP_LEGACY_H__ + + +#include "pin_map.h" + +//***************************************************************************** +// Legacy pinmuxing MACROS - Retained for portability across devices ONLY +// Not recommended for new users +//***************************************************************************** +#define GPIO_16_SD_D1 GPIO_16_SD1_D1 + +#define GPIO_17_SD_C1 GPIO_17_SD1_C1 + +#define GPIO_18_SD_D2 GPIO_18_SD1_D2 + +#define GPIO_19_SD_C2 GPIO_19_SD1_C2 + +#define GPIO_20_SD_D3 GPIO_20_SD1_D3 + +#define GPIO_21_SD_C3 GPIO_21_SD1_C3 + +#define GPIO_22_SD_D4 GPIO_22_SD1_D4 + +#define GPIO_23_SD_C4 GPIO_23_SD1_C4 + +#define GPIO_24_SD_D5 GPIO_24_SD2_D1 + +#define GPIO_25_SD_C5 GPIO_25_SD2_C1 + +#define GPIO_26_SD_D6 GPIO_26_SD2_D2 + +#define GPIO_27_SD_C6 GPIO_27_SD2_C2 + +#define GPIO_28_SD_D7 GPIO_28_SD2_D3 + +#define GPIO_29_SD_C7 GPIO_29_SD2_C3 + +#define GPIO_30_SD_D8 GPIO_30_SD2_D4 + +#define GPIO_31_SD_C8 GPIO_31_SD2_C4 + +#define GPIO_36_EM1WAIT1 GPIO_36_EM1WAIT + +#define GPIO_110_EM2WAIT1 GPIO_110_EM2WAIT + +#define GPIO_115_EM2CS0 GPIO_115_EM2CS0N + +#define GPIO_116_EM2CS2 GPIO_116_EM2CS2N + +#define GPIO_132_ODMSE0 GPIO_132_ODMSE1 + +#endif // __PIN_MAP_LEGACY_H__ diff --git a/gpio_driverlib_cpu1/device/driverlib/sci.c b/gpio_driverlib_cpu1/device/driverlib/sci.c new file mode 100644 index 0000000..dfd8e30 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sci.c @@ -0,0 +1,421 @@ +//########################################################################### +// +// FILE: sci.c +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sci.h" + +//***************************************************************************** +// +// SCI_setConfig +// +//***************************************************************************** +void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, uint32_t config) +{ + uint32_t divider; + + // + // Check the arguments. + // Is the required baud rate greater than the maximum rate supported? + // + ASSERT(SCI_isBaseValid(base)); + ASSERT(baud != 0U); + ASSERT((baud * 16U) <= lspclkHz); + + // + // Stop the SCI. + // + SCI_disableModule(base); + + // + // Compute the baud rate divider. + // + divider = ((lspclkHz / (baud * 8U)) - 1U); + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; + + // + // Set parity, data length, and number of stop bits. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK)) | config); + + // + // Start the SCI. + // + SCI_enableModule(base); +} + +//***************************************************************************** +// +// SCI_writeCharArray +// +//***************************************************************************** +void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } + else + { + // + // FIFO is not enabled. + // For loop to write (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = array[i]; + } + } +} + +//***************************************************************************** +// +// SCI_readCharArray +// +//***************************************************************************** +void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + uint16_t i; + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // FIFO is enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } + else + { + // + // FIFO is not enabled. + // For loop to read (Blocking) 'length' number of characters + // + for(i = 0U; i < length; i++) + { + // + // Wait until a character is available in the receive buffer. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + array[i] = (uint16_t) + (HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M); + } + } +} + +//***************************************************************************** +// +// SCI_enableInterrupt +// +//***************************************************************************** +void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) |= SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_disableInterrupt +// +//***************************************************************************** +void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the specified interrupts. + // + if((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) + { + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXERRINTENA; + } + if((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_RXBKINTENA; + } + if((intFlags & SCI_INT_TXRDY) == SCI_INT_TXRDY) + { + HWREGH(base + SCI_O_CTL2) &= ~SCI_CTL2_TXINTENA; + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFFIENA; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SCI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SCI_getInterruptStatus(uint32_t base) +{ + uint32_t interruptStatus = 0; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the interrupt status. + // + if((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == SCI_CTL2_TXRDY) + { + interruptStatus |= SCI_INT_TXRDY; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXERROR) == SCI_RXST_RXERROR) + { + interruptStatus |= SCI_INT_RXERR; + } + if(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == SCI_RXST_RXRDY) || + ((HWREGH(base + SCI_O_RXST) & SCI_RXST_BRKDT) == SCI_RXST_BRKDT)) + { + interruptStatus |= SCI_INT_RXRDY_BRKDT; + } + if((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFINT) == SCI_FFTX_TXFFINT) + { + interruptStatus |= SCI_INT_TXFF; + } + if((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFINT) == SCI_FFRX_RXFFINT) + { + interruptStatus |= SCI_INT_RXFF; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_FE) == SCI_RXST_FE) + { + interruptStatus |= SCI_INT_FE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_OE) == SCI_RXST_OE) + { + interruptStatus |= SCI_INT_OE; + } + if((HWREGH(base + SCI_O_RXST) & SCI_RXST_PE) == SCI_RXST_PE) + { + interruptStatus |= SCI_INT_PE; + } + + return(interruptStatus); +} + +//***************************************************************************** +// +// SCI_clearInterruptStatus +// +//***************************************************************************** +void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the requested interrupt sources. + // + if(((intFlags & SCI_INT_RXERR) == SCI_INT_RXERR) || + ((intFlags & SCI_INT_RXRDY_BRKDT) == SCI_INT_RXRDY_BRKDT) || + ((intFlags & SCI_INT_FE) == SCI_INT_FE) || + ((intFlags & SCI_INT_OE) == SCI_INT_OE) || + ((intFlags & SCI_INT_PE) == SCI_INT_PE)) + { + SCI_performSoftwareReset(base); + } + if((intFlags & SCI_INT_TXFF) == SCI_INT_TXFF) + { + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFFINTCLR; + } + if((intFlags & SCI_INT_RXFF) == SCI_INT_RXFF) + { + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFINTCLR; + } +} + +//***************************************************************************** +// +// SCI_setBaud +// +//***************************************************************************** +void SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud) +{ + uint32_t divider; + + // + // Compute the baud rate divider {ROUND TO NEAREST INTEGER} + // + divider = ((float)((float)lspclkHz / ((float)baud * 8.0F)) - 1.0F) + 0.5F; + + // + // Set the baud rate. + // + HWREGH(base + SCI_O_HBAUD) = (divider & 0xFF00U) >> 8U; + HWREGH(base + SCI_O_LBAUD) = divider & 0x00FFU; +} + +//***************************************************************************** +// +// SCI_setWakeFlag +// +//***************************************************************************** +void SCI_setWakeFlag(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the TX wake flag bit to indicate + // that the next frame is an address frame. + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_TXWAKE; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/sci.h b/gpio_driverlib_cpu1/device/driverlib/sci.h new file mode 100644 index 0000000..454ee12 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sci.h @@ -0,0 +1,1646 @@ +//########################################################################### +// +// FILE: sci.h +// +// TITLE: C28x SCI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SCI_H +#define SCI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sci_api SCI +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_sci.h" +#include "inc/hw_types.h" +#include "debug.h" + +//***************************************************************************** +// +// Values that can be passed to SCI_enableInterrupt, SCI_disableInterrupt, and +// SCI_clearInterruptStatus as the intFlags parameter, and returned from +// SCI_getInterruptStatus. +// +//***************************************************************************** +#define SCI_INT_RXERR 0x01U //!< RXERR interrupt +#define SCI_INT_RXRDY_BRKDT 0x02U //!< RXRDY interrupt +#define SCI_INT_TXRDY 0x04U //!< TXRDY interrupt +#define SCI_INT_TXFF 0x08U //!< TX FIFO level interrupt +#define SCI_INT_RXFF 0x10U //!< RX FIFO level interrupt +#define SCI_INT_FE 0x20U //!< Frame Error +#define SCI_INT_OE 0x40U //!< Overrun Error +#define SCI_INT_PE 0x80U //!< Parity Error + +//***************************************************************************** +// +// Values that can be passed to SCI_setConfig as the config parameter +// and returned by SCI_getConfig in the config parameter. +// Additionally, the SCI_CONFIG_PAR_* enum subset can be passed to +// SCI_setParityMode as the parity parameter, and are returned by +// SCI_getParityMode. +// +//***************************************************************************** +#define SCI_CONFIG_WLEN_MASK 0x0007U //!< Mask for extracting word length +#define SCI_CONFIG_WLEN_8 0x0007U //!< 8 bit data +#define SCI_CONFIG_WLEN_7 0x0006U //!< 7 bit data +#define SCI_CONFIG_WLEN_6 0x0005U //!< 6 bit data +#define SCI_CONFIG_WLEN_5 0x0004U //!< 5 bit data +#define SCI_CONFIG_WLEN_4 0x0003U //!< 4 bit data +#define SCI_CONFIG_WLEN_3 0x0002U //!< 3 bit data +#define SCI_CONFIG_WLEN_2 0x0001U //!< 2 bit data +#define SCI_CONFIG_WLEN_1 0x0000U //!< 1 bit data +#define SCI_CONFIG_STOP_MASK 0x0080U //!< Mask for extracting stop bits +#define SCI_CONFIG_STOP_ONE 0x0000U //!< One stop bit +#define SCI_CONFIG_STOP_TWO 0x0080U //!< Two stop bits +#define SCI_CONFIG_PAR_MASK 0x0060U //!< Parity Mask + +//***************************************************************************** +// +//! Values that can be used with SCI_setParityMode() and SCI_getParityMode() to +//! describe the parity of the SCI communication. +// +//***************************************************************************** +typedef enum +{ + SCI_CONFIG_PAR_NONE = 0x0000U, //!< No parity + SCI_CONFIG_PAR_EVEN = 0x0060U, //!< Even parity + SCI_CONFIG_PAR_ODD = 0x0020U //!< Odd parity +} SCI_ParityType; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the txLevel +//! parameter and returned by SCI_getFIFOInteruptLevel() and +//! SCI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_TX0 = 0x0000U, //!< Transmit interrupt empty + SCI_FIFO_TX1 = 0x0001U, //!< Transmit interrupt 1/16 full + SCI_FIFO_TX2 = 0x0002U, //!< Transmit interrupt 2/16 full + SCI_FIFO_TX3 = 0x0003U, //!< Transmit interrupt 3/16 full + SCI_FIFO_TX4 = 0x0004U, //!< Transmit interrupt 4/16 full + SCI_FIFO_TX5 = 0x0005U, //!< Transmit interrupt 5/16 full + SCI_FIFO_TX6 = 0x0006U, //!< Transmit interrupt 6/16 full + SCI_FIFO_TX7 = 0x0007U, //!< Transmit interrupt 7/16 full + SCI_FIFO_TX8 = 0x0008U, //!< Transmit interrupt 8/16 full + SCI_FIFO_TX9 = 0x0009U, //!< Transmit interrupt 9/16 full + SCI_FIFO_TX10 = 0x000AU, //!< Transmit interrupt 10/16 full + SCI_FIFO_TX11 = 0x000BU, //!< Transmit interrupt 11/16 full + SCI_FIFO_TX12 = 0x000CU, //!< Transmit interrupt 12/16 full + SCI_FIFO_TX13 = 0x000DU, //!< Transmit interrupt 13/16 full + SCI_FIFO_TX14 = 0x000EU, //!< Transmit interrupt 14/16 full + SCI_FIFO_TX15 = 0x000FU, //!< Transmit interrupt 15/16 full + SCI_FIFO_TX16 = 0x0010U //!< Transmit interrupt full +} SCI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SCI_setFIFOInterruptLevel() as the rxLevel +//! parameter and returned by SCI_getFIFOInterruptLevel() and +//! SCI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SCI_FIFO_RX0 = 0x0000U, //!< Receive interrupt empty + SCI_FIFO_RX1 = 0x0001U, //!< Receive interrupt 1/16 full + SCI_FIFO_RX2 = 0x0002U, //!< Receive interrupt 2/16 full + SCI_FIFO_RX3 = 0x0003U, //!< Receive interrupt 3/16 full + SCI_FIFO_RX4 = 0x0004U, //!< Receive interrupt 4/16 full + SCI_FIFO_RX5 = 0x0005U, //!< Receive interrupt 5/16 full + SCI_FIFO_RX6 = 0x0006U, //!< Receive interrupt 6/16 full + SCI_FIFO_RX7 = 0x0007U, //!< Receive interrupt 7/16 full + SCI_FIFO_RX8 = 0x0008U, //!< Receive interrupt 8/16 full + SCI_FIFO_RX9 = 0x0009U, //!< Receive interrupt 9/16 full + SCI_FIFO_RX10 = 0x000AU, //!< Receive interrupt 10/16 full + SCI_FIFO_RX11 = 0x000BU, //!< Receive interrupt 11/16 full + SCI_FIFO_RX12 = 0x000CU, //!< Receive interrupt 12/16 full + SCI_FIFO_RX13 = 0x000DU, //!< Receive interrupt 13/16 full + SCI_FIFO_RX14 = 0x000EU, //!< Receive interrupt 14/16 full + SCI_FIFO_RX15 = 0x000FU, //!< Receive interrupt 15/16 full + SCI_FIFO_RX16 = 0x0010U //!< Receive interrupt full +} SCI_RxFIFOLevel; + +//***************************************************************************** +// +// Values returned from SCI_getRxStatus(). These correspond to the different +// bits and flags of the SCIRXST register. +// +//***************************************************************************** +#define SCI_RXSTATUS_WAKE 0x0002U //!< Receiver wake up detect +#define SCI_RXSTATUS_PARITY 0x0004U //!< Parity error +#define SCI_RXSTATUS_OVERRUN 0x0008U //!< Overrun error +#define SCI_RXSTATUS_FRAMING 0x0010U //!< Framing error +#define SCI_RXSTATUS_BREAK 0x0020U //!< Break detect +#define SCI_RXSTATUS_READY 0x0040U //!< Receiver ready +#define SCI_RXSTATUS_ERROR 0x0080U //!< Receiver error + +//***************************************************************************** +// +// API Function prototypes +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks a SCI base address. +//! +//! \param base is the base address of the SCI port. +//! +//! This function determines if a SCI port base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SCI_isBaseValid(uint32_t base) +{ + return( + (base == SCIA_BASE) || + (base == SCIB_BASE) || + (base == SCIC_BASE) || + (base == SCID_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Sets the type of parity. +//! +//! \param base is the base address of the SCI port. +//! \param parity specifies the type of parity to use. +//! +//! Sets the type of parity to use for transmitting and expect when receiving. +//! The \e parity parameter must be one of the following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setParityMode(uint32_t base, SCI_ParityType parity) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the parity mode. + // + HWREGH(base + SCI_O_CCR) = ((HWREGH(base + SCI_O_CCR) & + ~(SCI_CONFIG_PAR_MASK)) | (uint16_t)parity); +} + +//***************************************************************************** +// +//! Gets the type of parity currently being used. +//! +//! \param base is the base address of the SCI port. +//! +//! This function gets the type of parity used for transmitting data and +//! expected when receiving data. +//! +//! \return Returns the current parity settings, specified as one of the +//! following: +//! \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, \b SCI_CONFIG_PAR_ODD. +// +//***************************************************************************** +static inline SCI_ParityType +SCI_getParityMode(uint32_t base) +{ + uint16_t parity; + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current parity setting. + // + parity = (HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK)); + + return((SCI_ParityType)parity); +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to address-bit mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to address-bit mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setAddrMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Sets the multiprocessor protocol to idle-line mode. +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the multi-processor protocol to idle-line protocol. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setIdleMultiProcessorMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the address-bit mode protocol + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_ADDRIDLE_MODE; +} + +//***************************************************************************** +// +//! Locks Autobaud. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs an autobaud lock for the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_lockAutobaud(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Prime the baud register + // + HWREGH(base + SCI_O_HBAUD) = 0x0U; + HWREGH(base + SCI_O_LBAUD) = 0x1U; + + // + // Prepare for autobaud detection. + // Set the CDC bit to enable autobaud detection and clear the ABD bit. + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_CDC; + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + + // + // Wait until we correctly read an 'A' or 'a' and lock + // + while((HWREGH(base + SCI_O_FFCT) & SCI_FFCT_ABD) != SCI_FFCT_ABD) + { + } + + // + // After autobaud lock, clear the ABD and CDC bits + // + HWREGH(base + SCI_O_FFCT) |= SCI_FFCT_ABDCLR; + HWREGH(base + SCI_O_FFCT) &= ~SCI_FFCT_CDC; +} + +//***************************************************************************** +// +//! Sets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as one of +//! the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, . . . or +//! \b SCI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as one of +//! the following +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_setFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel txLevel, + SCI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SCI_O_FFTX) = (HWREGH(base + SCI_O_FFTX) & + (~SCI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SCI_O_FFRX) = (HWREGH(base + SCI_O_FFRX) & + (~SCI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO interrupt level at which interrupts are generated. +//! +//! \param base is the base address of the SCI port. +//! \param txLevel is a pointer to storage for the transmit FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, ... or \b SCI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO interrupt +//! level, returned as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, ... or \b SCI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getFIFOInterruptLevel(uint32_t base, SCI_TxFIFOLevel *txLevel, + SCI_RxFIFOLevel *rxLevel) +{ + + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SCI_TxFIFOLevel)(HWREGH(base + SCI_O_FFTX) & + SCI_FFTX_TXFFIL_M); + *rxLevel = (SCI_RxFIFOLevel)(HWREGH(base + SCI_O_FFRX) & + SCI_FFRX_RXFFIL_M); +} + +//***************************************************************************** +// +//! Gets the current configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is a pointer to storage for the baud rate. +//! \param config is a pointer to storage for the data format. +//! +//! The baud rate and data format for the SCI is determined, given an +//! explicitly provided peripheral clock (hence the ExpClk suffix). The +//! returned baud rate is the actual baud rate; it may not be the exact baud +//! rate requested or an ``official'' baud rate. The data format returned in +//! \e config is enumerated the same as the \e config parameter of +//! SCI_setConfig(). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_getConfig(uint32_t base, uint32_t lspclkHz, uint32_t *baud, + uint32_t *config) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Compute the baud rate. + // + *baud = lspclkHz / + ((1U + (((uint32_t)HWREGH(base + SCI_O_HBAUD) << 8U) | + HWREGH(base + SCI_O_LBAUD))) * 8U); + + // + // Get the parity, data length, and number of stop bits. + // + *config = (uint32_t)HWREGH(base + SCI_O_CCR) & (SCI_CONFIG_PAR_MASK | + SCI_CONFIG_STOP_MASK | + SCI_CONFIG_WLEN_MASK); +} + +//***************************************************************************** +// +//! Enables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA, and +//! RXENA bits which enables transmit and receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX, TX, and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_RXENA | + SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting and receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Clears the SCIEN, TXE, and RXE bits. The user should ensure that all the +//! data has been sent before disable the module during transmission. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~(SCI_FFTX_SCIFFENA); + + // + // Disable the SCI. + // + HWREGH(base + SCI_O_CTL1) &= ~(SCI_CTL1_TXENA | SCI_CTL1_RXENA); +} + +//***************************************************************************** +// +//! Enables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the TXENA bit +//! which enables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable TX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_TXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables transmitting. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the TXENA bit +//! which disables transmit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableTxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable TX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_TXENA; +} + +//***************************************************************************** +// +//! Enables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Enables SCI by taking SCI out of the software reset. Sets the RXENA bit +//! which enables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable RX and the SCI. + // + HWREGH(base + SCI_O_CTL1) |= (SCI_CTL1_RXENA | SCI_CTL1_SWRESET); +} + +//***************************************************************************** +// +//! Disables receiving. +//! +//! \param base is the base address of the SCI port. +//! +//! Disables SCI by taking SCI out of the software reset. Clears the RXENA bit +//! which disables receive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableRxModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable RX. + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_RXENA; +} + +//***************************************************************************** +// +//! Enables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the sleep mode in SCI by setting the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set sleep bit + // + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Disables Sleep Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the sleep mode in SCI by clearing the SLEEP bit in SCICTL1 register +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableSleepMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear sleep bit + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SLEEP; +} + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions enables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIFFENA | SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions disables the transmit and receive FIFOs in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIFFENA; +} + +//***************************************************************************** +// +//! Determines if the FIFO enhancement is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not the FIFO enhancement +//! is enabled. +//! +//! \return Returns \b true if the FIFO enhancement is enabled or \b false +//! if the FIFO enhancement is disabled. +// +//***************************************************************************** +static inline bool +SCI_isFIFOEnabled(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return true if the FIFO is enabled and false if it is disabled. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_SCIFFENA) == + SCI_FFTX_SCIFFENA) ? true : false); +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the receive FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFRX) &= ~SCI_FFRX_RXFIFORESET; + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets the transmit FIFO of the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the specified FIFO. + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_TXFIFORESET; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_TXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the SCI Transmit and Receive Channels +//! +//! \param base is the base address of the SCI port. +//! +//! This functions resets transmit and receive channels in the SCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_resetChannels(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Reset the Tx and Rx Channels + // + HWREGH(base + SCI_O_FFTX) &= ~SCI_FFTX_SCIRST; + HWREGH(base + SCI_O_FFTX) |= SCI_FFTX_SCIRST; +} + +//***************************************************************************** +// +//! Determines if there are any characters in the receive buffer when the +//! FIFO enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is data +//! available in the receive buffer. +//! +//! \return Returns \b true if there is data in the receive buffer or \b false +//! if there is no data in the receive buffer. +// +//***************************************************************************** +static inline bool +SCI_isDataAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of characters with FIFO disabled. + // + return(((HWREGH(base + SCI_O_RXST) & SCI_RXST_RXRDY) == + SCI_RXST_RXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Determines if there is any space in the transmit buffer when the FIFO +//! enhancement is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns a flag indicating whether or not there is space +//! available in the transmit buffer when not using the FIFO enhancement. +//! +//! \return Returns \b true if there is space available in the transmit buffer +//! or \b false if there is no space available in the transmit buffer. +// +//***************************************************************************** +static inline bool +SCI_isSpaceAvailableNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the availability of space. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXRDY) == + SCI_CTL2_TXRDY) ? true : false); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SCI_FIFO_TX0, \b SCI_FIFO_TX1, \b SCI_FIFO_TX2, \b SCI_FIFO_TX3 +//! \b SCI_FIFO_TX4, ..., or \b SCI_FIFO_TX16 +// +//***************************************************************************** +static inline SCI_TxFIFOLevel +SCI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_TxFIFOLevel)((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) >> + SCI_FFTX_TXFFST_S)); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SCI_FIFO_RX0, \b SCI_FIFO_RX1, \b SCI_FIFO_RX2, \b SCI_FIFO_RX3 +//! \b SCI_FIFO_RX4, ..., or \b SCI_FIFO_RX16 +// +//***************************************************************************** +static inline SCI_RxFIFOLevel +SCI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SCI_RxFIFOLevel)((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFST_M) >> + SCI_FFRX_RXFFST_S)); +} + +//***************************************************************************** +// +//! Determines whether the SCI transmitter is busy or not. +//! +//! \param base is the base address of the SCI port. +//! +//! Allows the caller to determine whether all transmitted bytes have cleared +//! the transmitter hardware when the FIFO is not enabled. When the FIFO is +//! enabled, this function allows the caller to determine whether there is any +//! data in the FIFO. +//! +//! Without the FIFO enabled, if \b false is returned, the transmit buffer and +//! shift registers are empty and the transmitter is not busy. With the FIFO +//! enabled, if \b false is returned, the FIFO is empty. This does not +//! necessarily mean that the transmitter is not busy. The empty FIFO does not +//! reflect the status of the transmitter shift register. The FIFO may be empty +//! while the transmitter is still transmitting data. +//! +//! \return Returns \b true if the SCI is transmitting or \b false if +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SCI_isTransmitterBusy(uint32_t base) +{ + // + // Check the argument. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Check if FIFO enhancement is enabled. + // + if(SCI_isFIFOEnabled(base)) + { + // + // With FIFO enhancement, determine if the SCI is busy. + // + return(((HWREGH(base + SCI_O_FFTX) & SCI_FFTX_TXFFST_M) != + 0U) ? true : false); + } + else + { + // + // Without FIFO enhancement, determine if the SCI is busy. + // Check if the transmit buffer and shift register empty. + // + return(((HWREGH(base + SCI_O_CTL2) & SCI_CTL2_TXEMPTY) == + SCI_CTL2_TXEMPTY) ? false : true); + } +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit FIFO, this function waits +//! until there is space available before returning. \e data is a uint16_t but +//! only 8 bits are written to the SCI port. SCI only transmits 8 bit +//! characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit FIFO. + // + while(SCI_getTxFIFOStatus(base) == SCI_FIFO_TX16) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits to send a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Sends the character \e data to the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! before returning. \e data is a uint16_t but only 8 bits are written to the +//! SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until space is available in the transmit buffer. + // + while(!SCI_isSpaceAvailableNonFIFO(base)) + { + } + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Sends a character to the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param data is the character to be transmitted. +//! +//! Writes the character \e data to the transmit buffer for the specified port. +//! This function does not block and only writes to the transmit buffer. +//! The user should use SCI_isSpaceAvailableNonFIFO() or SCI_getTxFIFOStatus() +//! to determine if the transmit buffer or FIFO have space available. +//! \e data is a uint16_t but only 8 bits are written to the SCI port. SCI +//! only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_writeCharNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Send a char. + // + HWREGH(base + SCI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets current receiver status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function returns the current receiver status flags. The returned +//! error flags are equivalent to the error bits returned via the previous +//! reading or receiving of a character with the exception that the overrun +//! error is set immediately the overrun occurs rather than when a character +//! is next read. +//! +//! \return Returns a bitwise OR combination of the receiver status flags, +//! \b SCI_RXSTATUS_WAKE, \b SCI_RXSTATUS_PARITY, \b SCI_RXSTATUS_OVERRUN, +//! \b SCI_RXSTATUS_FRAMING, \b SCI_RXSTATUS_BREAK, \b SCI_RXSTATUS_READY, +//! and \b SCI_RXSTATUS_ERROR. +// +//***************************************************************************** +static inline uint16_t +SCI_getRxStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current value of the receive status register. + // + return(HWREGH(base + SCI_O_RXST)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive FIFO for the specified port. If there +//! are no characters available, this function waits until a character is +//! received before returning. Returns immediately in case of Error. +//! +//! \return Returns the character read from the specified port as \e uint16_t +//! or 0x0 in case of Error. The application must use +//! SCI_getRxStatus() API to check if some error occurred before +//! consuming the data +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(SCI_getRxFIFOStatus(base) == SCI_FIFO_RX0) + { + // + //If there is any error return + // + if((SCI_getRxStatus(base) & SCI_RXSTATUS_ERROR) != 0U) + { + return(0U); + } + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Waits for a character from the specified port when the FIFO enhancement +//! is not enabled. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. If there +//! is no characters available, this function waits until a character is +//! received before returning. +//! +//! \return Returns the character read from the specified port as \e uint16_t. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Wait until a character is available in the receive FIFO. + // + while(!SCI_isDataAvailableNonFIFO(base)) + { + } + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Receives a character from the specified port. +//! +//! \param base is the base address of the SCI port. +//! +//! Gets a character from the receive buffer for the specified port. This +//! function does not block and only reads the receive buffer. The user should +//! use SCI_isDataAvailableNonFIFO() or SCI_getRxFIFOStatus() to determine if +//! the receive buffer or FIFO have data available. +//! +//! \return Returns \e uin16_t which is read from the receive buffer. +// +//***************************************************************************** +static inline uint16_t +SCI_readCharNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the character from the receive buffer. + // + return((uint16_t)(HWREGH(base + SCI_O_RXBUF) & SCI_RXBUF_SAR_M)); +} + +//***************************************************************************** +// +//! Performs a software reset of the SCI and Clears all reported receiver +//! status flags. +//! +//! \param base is the base address of the SCI port. +//! +//! This function performs a software reset of the SCI port. It affects the +//! operating flags of the SCI, but it neither affects the configuration bits +//! nor restores the reset values. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_performSoftwareReset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // To clear all errors a sw reset of the module is required + // + HWREGH(base + SCI_O_CTL1) &= ~SCI_CTL1_SWRESET; + HWREGH(base + SCI_O_CTL1) |= SCI_CTL1_SWRESET; +} + +//***************************************************************************** +// +//! Enables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Enables the loop back test mode where the Tx pin is internally connected +//! to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Set the loop back mode. + // + HWREGH(base + SCI_O_CCR) |= SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Disables Loop Back Test Mode +//! +//! \param base is the base address of the SCI port. +//! +//! Disables the loop back test mode where the Tx pin is no longer internally +//! connected to the Rx pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the loop back mode. + // + HWREGH(base + SCI_O_CCR) &= ~SCI_CCR_LOOPBKENA; +} + +//***************************************************************************** +// +//! Get the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions gets the receive FIFO overflow flag status. +//! +//! \return Returns \b true if overflow has occurred, else returned \b false if +//! an overflow hasn't occurred. +// +//***************************************************************************** +static inline bool +SCI_getOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Return the current FIFO overflow status + // + return((HWREGH(base + SCI_O_FFRX) & SCI_FFRX_RXFFOVF) == SCI_FFRX_RXFFOVF); +} + +//***************************************************************************** +// +//! Clear the receive FIFO Overflow flag status +//! +//! \param base is the base address of the SCI port. +//! +//! This functions clears the receive FIFO overflow flag status. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SCI_clearOverflowStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SCI_isBaseValid(base)); + + // + // Clear the current FIFO overflow status + // + HWREGH(base + SCI_O_FFRX) |= SCI_FFRX_RXFFOVRCLR; +} + +//***************************************************************************** +// +//! Sets the configuration of a SCI. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! \param config is the data format for the port (number of data bits, +//! number of stop bits, and parity). +//! +//! This function configures the SCI for operation in the specified data +//! format. The baud rate is provided in the \e baud parameter and the data +//! format in the \e config parameter. +//! +//! The \e config parameter is the bitwise OR of three values: the number of +//! data bits, the number of stop bits, and the parity. \b SCI_CONFIG_WLEN_8, +//! \b SCI_CONFIG_WLEN_7, \b SCI_CONFIG_WLEN_6, \b SCI_CONFIG_WLEN_5, +//! \b SCI_CONFIG_WLEN_4, \b SCI_CONFIG_WLEN_3, \b SCI_CONFIG_WLEN_2, and +//! \b SCI_CONFIG_WLEN_1. Select from eight to one data bits per byte +//! (respectively). +//! \b SCI_CONFIG_STOP_ONE and \b SCI_CONFIG_STOP_TWO select one or two stop +//! bits (respectively). \b SCI_CONFIG_PAR_NONE, \b SCI_CONFIG_PAR_EVEN, +//! \b SCI_CONFIG_PAR_ODD, select the parity mode (no parity bit, even parity +//! bit, odd parity bit respectively). +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock(), or it can be explicitly +//! hard coded if it is constant and known (to save the code/execution overhead +//! of a call to SysCtl_getLowSpeedClock()). +//! +//! A baud rate divider (BRR) is used in this function to calculate the +//! baud rate. The value of BRR is calculated in float and type casted as int +//! to be fed in the \b SCIHBAUD and \b SCILBAUD registers. This conversion +//! brings an error in the calculated baud rate and the requested. Error will +//! be significant when operating at higher baud rates. The error is due to +//! lower BRR integer value granularity at higher baud rates. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setConfig(uint32_t base, uint32_t lspclkHz, uint32_t baud, + uint32_t config); + +//***************************************************************************** +// +//! Waits to send an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be transmitted. +//! It is pointer to the array of characters to be transmitted. +//! \param length is the length of the array, or number of characters in the +//! array to be transmitted. +//! +//! Sends the number of characters specified by \e length, starting at the +//! address \e array, out of the transmit buffer for the specified port. +//! If there is no space available in the transmit buffer, or the transmit +//! FIFO if it is enabled, this function waits until there is space available +//! and \e length number of characters are transmitted before returning. +//! \e array is a pointer to uint16_ts but only the least significant 8 bits +//! are written to the SCI port. SCI only transmits 8 bit characters. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_writeCharArray(uint32_t base, const uint16_t * const array, + uint16_t length); + +//***************************************************************************** +// +//! Waits to receive an array of characters from the specified port. +//! +//! \param base is the base address of the SCI port. +//! \param array is the address of the array of characters to be received. +//! It is a pointer to the array of characters to be received. +//! \param length is the length of the array, or number of characters in the +//! array to be received. +//! +//! Receives an array of characters from the receive buffer for the specified +//! port, and stores them as an array of characters starting at address +//! \e array. This function waits until the \e length number of characters are +//! received before returning. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_readCharArray(uint32_t base, uint16_t * const array, uint16_t length); + +//***************************************************************************** +// +//! Enables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be enabled. +//! +//! Enables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter is the bitwise OR of any of the following: +//! +//! - \b SCI_INT_RXERR - RXERR Interrupt +//! - \b SCI_INT_RXRDY_BRKDT - RXRDY/BRKDT Interrupt +//! - \b SCI_INT_TXRDY - TXRDY Interrupt +//! - \b SCI_INT_TXFF - TX FIFO Level Interrupt +//! - \b SCI_INT_RXFF - RX FIFO Level Interrupt +//! - \b SCI_INT_FE - Frame Error +//! - \b SCI_INT_OE - Overrun Error +//! - \b SCI_INT_PE - Parity Error +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is the bit mask of the interrupt sources to be disabled. +//! +//! Disables the indicated SCI interrupt sources. Only the sources that are +//! enabled can be reflected to the processor interrupt; disabled sources have +//! no effect on the processor. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base is the base address of the SCI port. +//! +//! \return Returns the current interrupt status, enumerated as a bit field of +//! values described in SCI_enableInterrupt(). +// +//***************************************************************************** +extern uint32_t +SCI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SCI interrupt sources. +//! +//! \param base is the base address of the SCI port. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! The specified SCI interrupt sources are cleared, so that they no longer +//! assert. This function must be called in the interrupt handler to keep the +//! interrupt from being recognized again immediately upon exit. +//! +//! The \e intFlags parameter has the same definition as the \e intFlags +//! parameter to SCI_enableInterrupt(). +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Sets SCI Baud rate. +//! +//! \param base is the base address of the SCI port. +//! \param lspclkHz is the rate of the clock supplied to the SCI module. This +//! is the LSPCLK. +//! \param baud is the desired baud rate. +//! +//! This function configures the SCI for operation in the specified baud rate +//! The baud rate is provided in the \e baud parameter. +//! +//! The peripheral clock is the low speed peripheral clock. This will be +//! the value returned by SysCtl_getLowSpeedClock() +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setBaud(uint32_t base, uint32_t lspclkHz, uint32_t baud); + +//***************************************************************************** +// +//! Sets the SCI TXWAKE flag +//! +//! \param base is the base address of the SCI port. +//! +//! This function sets the TXWAKE flag bit to indicate that the next frame +//! is an address frame. +//! TXWAKE bit controls selection of data-transmit feature based on +//! which mode is selected from idle-line and address-bit. +//! +//! \return None. +// +//***************************************************************************** +extern void +SCI_setWakeFlag(uint32_t base); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SCI_H diff --git a/gpio_driverlib_cpu1/device/driverlib/sdfm.c b/gpio_driverlib_cpu1/device/driverlib/sdfm.c new file mode 100644 index 0000000..41bc605 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sdfm.c @@ -0,0 +1,188 @@ +//########################################################################### +// +// FILE: sdfm.c +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "sdfm.h" + +//***************************************************************************** +// +// Defines for filter configurations. Not intended for use by application code. +// +//***************************************************************************** +// +// Get filter oversampling ratio +// +#define SDFM_GET_OSR(C) ((C) >> 8U) + +// +// Maximum acceptable comparator filter oversampling ratio +// +#define SDFM_MAX_COMP_FILTER_OSR 31U + +// +// Maximum acceptable data filter oversampling ratio +// +#define SDFM_MAX_DATA_FILTER_OSR 255U + +// +// Get the filter type +// +#define SDFM_GET_FILTER_TYPE(C) ((C) & 0x30U) + +// +// Get the filter number +// +#define SDFM_GET_FILTER_NUMBER(C) ((C) & 0x3U) + + +// +// Get data shift value +// +#define SDFM_GET_SHIFT_VALUE(C) (((C) >> 2U) & 0x1FU) + +//***************************************************************************** +// +// SDFM_configComparator +// +//***************************************************************************** +void SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_COMP_FILTER_OSR) + { + ratio = SDFM_MAX_COMP_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setComparatorFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setCompFilterOverSamplingRatio(base, filter, ratio); + + // + // Set the comparator high threshold value + // + SDFM_setCompFilterHighThreshold(base, filter, + SDFM_GET_HIGH_THRESHOLD(config2)); + + // + // Set the comparator low threshold value + // + SDFM_setCompFilterLowThreshold(base, filter, + SDFM_GET_LOW_THRESHOLD(config2)); + +} + +//***************************************************************************** +// +// SDFM_configDataFilter +// +//***************************************************************************** +void SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2) +{ + SDFM_FilterNumber filter; + uint16_t ratio; + SDFM_FilterType filterType; + + filter = (SDFM_FilterNumber)(SDFM_GET_FILTER_NUMBER(config1)); + ratio = SDFM_GET_OSR(config1); + filterType = (SDFM_FilterType)SDFM_GET_FILTER_TYPE(config1); + + // + // Limit the oversampling ratio + // + if(ratio > SDFM_MAX_DATA_FILTER_OSR) + { + ratio = SDFM_MAX_DATA_FILTER_OSR; + } + + // + // Set the comparator filter type + // + SDFM_setFilterType(base, filter, filterType); + + // + // Set the comparator filter over sampling ratio + // + SDFM_setFilterOverSamplingRatio(base, filter, ratio); + + // + // If filter switch on + // + if((config2 & SDFM_FILTER_ENABLE) == SDFM_FILTER_ENABLE) + { + SDFM_enableFilter(base, filter); + } + else + { + SDFM_disableFilter(base, filter); + } + + // + // Set output data format + // + SDFM_setOutputDataFormat(base, filter, + (SDFM_OutputDataFormat)(config2 & 0x1U)); + + // + // Set the shift value if data is in 16-bit 2's complement format + // + if((config2 & 0x1U) == (uint16_t)(SDFM_DATA_FORMAT_16_BIT)) + { + SDFM_setDataShiftValue(base, filter, SDFM_GET_SHIFT_VALUE(config2)); + } +} + + diff --git a/gpio_driverlib_cpu1/device/driverlib/sdfm.h b/gpio_driverlib_cpu1/device/driverlib/sdfm.h new file mode 100644 index 0000000..afbdfb7 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sdfm.h @@ -0,0 +1,1178 @@ +//########################################################################### +// +// FILE: sdfm.h +// +// TITLE: C28x SDFM Driver +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef SDFM_H +#define SDFM_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** + +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sdfm_api SDFM +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_types.h" +#include "inc/hw_sdfm.h" +#include "inc/hw_memmap.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//! Macro to get the low threshold +//! +#define SDFM_GET_LOW_THRESHOLD(C) ((uint16_t)(C)) + +//! Macro to get the high threshold +//! +#define SDFM_GET_HIGH_THRESHOLD(C) ((uint16_t)((uint32_t)(C) >> 16U)) + + +//! Macro to convert comparator over sampling ratio to acceptable bit location +//! +#define SDFM_SET_OSR(X) (((X) - 1U) << 8U) +//! Macro to convert the data shift bit values to acceptable bit location +//! +#define SDFM_SHIFT_VALUE(X) ((X) << 2U) + +//! Macro to combine high threshold and low threshold values +//! +#define SDFM_THRESHOLD(H, L) ((((uint32_t)(H)) << 16U) | (L)) + +//! Macro to set the FIFO level to acceptable bit location +//! +#define SDFM_SET_FIFO_LEVEL(X) ((X) << 7U) + +//! Macro to set and enable the zero cross threshold value. +//! +#define SDFM_SET_ZERO_CROSS_THRESH_VALUE(X) (0x8000 | (X)) + +//! Macros to enable or disable filter. +//! +#define SDFM_FILTER_DISABLE 0x0U +#define SDFM_FILTER_ENABLE 0x2U + +//***************************************************************************** +// +//! Values that can be returned from SDFM_getThresholdStatus() +// +//***************************************************************************** +typedef enum +{ + SDFM_OUTPUT_WITHIN_THRESHOLD = 0, //!< SDFM output is within threshold + SDFM_OUTPUT_ABOVE_THRESHOLD = 1, //!< SDFM output is above threshold + SDFM_OUTPUT_BELOW_THRESHOLD = 2 //!< SDFM output is below threshold +} SDFM_OutputThresholdStatus; + +//***************************************************************************** +// +//! Values that can be passed to all functions as the \e filterNumber +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SDFM_FILTER_1 = 0, //!< Digital filter 1 + SDFM_FILTER_2 = 1, //!< Digital filter 2 + SDFM_FILTER_3 = 2, //!< Digital filter 3 + SDFM_FILTER_4 = 3 //!< Digital filter 4 +} SDFM_FilterNumber; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setFilterType(), +//! SDFM_setComparatorFilterType() as the \e filterType parameter. +// +//***************************************************************************** +typedef enum +{ + //! Digital filter with SincFast structure. + SDFM_FILTER_SINC_FAST = 0x00, + //! Digital filter with Sinc1 structure + SDFM_FILTER_SINC_1 = 0x10, + //! Digital filter with Sinc3 structure. + SDFM_FILTER_SINC_2 = 0x20, + //! Digital filter with Sinc4 structure. + SDFM_FILTER_SINC_3 = 0x30 +} SDFM_FilterType; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setupModulatorClock(),as the +//! \e clockMode parameter. +// +//***************************************************************************** +typedef enum +{ + //! Modulator clock is identical to the data rate + SDFM_MODULATOR_CLK_EQUAL_DATA_RATE = 0, + //! Modulator clock is half the data rate + SDFM_MODULATOR_CLK_HALF_DATA_RATE = 1, + //! Modulator clock is off. Data is Manchester coded. + SDFM_MODULATOR_CLK_OFF = 2, + //! Modulator clock is double the data rate. + SDFM_MODULATOR_CLK_DOUBLE_DATA_RATE = 3 +} SDFM_ModulatorClockMode; + +//***************************************************************************** +// +//! Values that can be passed to SDFM_setOutputDataFormat(),as the +//! \e dataFormat parameter. +// +//***************************************************************************** +typedef enum +{ + //! Filter output is in 16 bits 2's complement format. + SDFM_DATA_FORMAT_16_BIT = 0, + //! Filter output is in 32 bits 2's complement format. + SDFM_DATA_FORMAT_32_BIT = 1 +} SDFM_OutputDataFormat; + +//***************************************************************************** +// +// Values that can be passed to SDFM_enableInterrupt and SDFM_disableInterrupt +// as intFlags parameter +// +//***************************************************************************** +//! Interrupt is generated if Modulator fails. +//! +#define SDFM_MODULATOR_FAILURE_INTERRUPT 0x200U +//! Interrupt on Comparator low-level threshold. +//! +#define SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT 0x40U +//! Interrupt on Comparator high-level threshold. +//! +#define SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT 0x20U +//! Interrupt on Acknowledge flag +//! +#define SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT 0x1U + +//***************************************************************************** +// +// Values that can be passed to SDFM_clearInterruptFlag flags parameter +// +//***************************************************************************** +//! Main interrupt flag +//! +#define SDFM_MAIN_INTERRUPT_FLAG 0x80000000U +//! Filter 1 high -level threshold flag +//! +#define SDFM_FILTER_1_HIGH_THRESHOLD_FLAG 0x1U +//! Filter 1 low -level threshold flag +//! +#define SDFM_FILTER_1_LOW_THRESHOLD_FLAG 0x2U +//! Filter 2 high -level threshold flag +//! +#define SDFM_FILTER_2_HIGH_THRESHOLD_FLAG 0x4U +//! Filter 2 low -level threshold flag +//! +#define SDFM_FILTER_2_LOW_THRESHOLD_FLAG 0x8U +//! Filter 3 high -level threshold flag +//! +#define SDFM_FILTER_3_HIGH_THRESHOLD_FLAG 0x10U +//! Filter 3 low -level threshold flag +//! +#define SDFM_FILTER_3_LOW_THRESHOLD_FLAG 0x20U +//! Filter 4 high -level threshold flag +//! +#define SDFM_FILTER_4_HIGH_THRESHOLD_FLAG 0x40U +//! Filter 4 low -level threshold flag +//! +#define SDFM_FILTER_4_LOW_THRESHOLD_FLAG 0x80U +//! Filter 1 modulator failed flag +//! +#define SDFM_FILTER_1_MOD_FAILED_FLAG 0x100U +//! Filter 2 modulator failed flag +//! +#define SDFM_FILTER_2_MOD_FAILED_FLAG 0x200U +//! Filter 3 modulator failed flag +//! +#define SDFM_FILTER_3_MOD_FAILED_FLAG 0x400U +//! Filter 4 modulator failed flag +//! +#define SDFM_FILTER_4_MOD_FAILED_FLAG 0x800U +//! Filter 1 new data flag +//! +#define SDFM_FILTER_1_NEW_DATA_FLAG 0x1000U +//! Filter 2 new data flag +//! +#define SDFM_FILTER_2_NEW_DATA_FLAG 0x2000U +//! Filter 3 new data flag +//! +#define SDFM_FILTER_3_NEW_DATA_FLAG 0x4000U +//! Filter 4 new data flag +//! +#define SDFM_FILTER_4_NEW_DATA_FLAG 0x8000U + +//***************************************************************************** +// +//! \internal +//! Checks SDFM base address. +//! +//! \param base specifies the SDFM module base address. +//! +//! This function determines if SDFM module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SDFM_isBaseValid(uint32_t base) +{ + return( + (base == SDFM1_BASE) || + (base == SDFM2_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables data filter to be reset by an external source (PWM +//! compare output). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable external reset +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables data filter from being reset by an external source +//! (PWM compare output). +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableExternalReset(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the SDSYNCEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_SDSYNCEN; + EDIS; +} + +//***************************************************************************** +// +//! Enable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function enables the filter specified by the \e filterNumber variable. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) |= + SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Disable filter +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function disables the filter specified by the \e filterNumber +//! variable. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_disableFilter(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear the FEN bit + // + EALLOW; + HWREGH(base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U)) &= + ~SDFM_SDDFPARM1_FEN; + EDIS; +} + +//***************************************************************************** +// +//! Set filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the filter type or structure. +//! +//! This function sets the filter type or structure to be used as specified by +//! filterType for the selected filter number as specified by filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SST bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_SST_M)) | + ((uint16_t)filterType << 6U); + EDIS; +} + +//***************************************************************************** +// +//! Set data filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the data filter over sampling ratio. +//! +//! This function sets the filter oversampling ratio for the filter specified +//! by the filterNumber variable.Valid values for the variable +//! overSamplingRatio are 0 to 255 inclusive. The actual oversampling ratio +//! will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setFilterOverSamplingRatio(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 256U); + + address = base + SDFM_O_SDDFPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DOSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDFPARM1_DOSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Set modulator clock mode. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param clockMode is the modulator clock mode. +//! +//! This function sets the modulator clock mode specified by clockMode +//! for the filter specified by filterNumber. +//! +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setupModulatorClock(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_ModulatorClockMode clockMode) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCTLPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to MOD bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCTLPARM1_MOD_M)) | + (uint16_t)clockMode; + + EDIS; +} + +//***************************************************************************** +// +//! Set the output data format +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param dataFormat is the output data format. +//! +//! This function sets the output data format for the filter specified by +//! filterNumber. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setOutputDataFormat(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_OutputDataFormat dataFormat) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to DR bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_DR)) | + ((uint16_t)dataFormat << 10U); + EDIS; +} + +//***************************************************************************** +// +//! Set data shift value. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param shiftValue is the data shift value. +//! +//! This function sets the shift value for the 16 bit 2's complement data +//! format. The valid maximum value for shiftValue is 31. +//! +//! \b Note: Use this function with 16 bit 2's complement data format only. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setDataShiftValue(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t shiftValue) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(shiftValue < 32U); + + address = base + SDFM_O_SDDPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to SH bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDDPARM1_SH_M)) | + (shiftValue << SDFM_SDDPARM1_SH_S); + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output high-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param highThreshold is the high-level threshold. +//! +//! This function sets the unsigned high-level threshold value for the +//! Comparator filter output. If the output value of the filter exceeds +//! highThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterHighThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t highThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(highThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPH1 + ((uint32_t)filterNumber * 16U); + + // + // Write to HLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPH1_HLT_M) | highThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Set Filter output low-level threshold. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param lowThreshold is the low-level threshold. +//! +//! This function sets the unsigned low-level threshold value for the +//! Comparator filter output. If the output value of the filter gets below +//! lowThreshold and interrupt generation is enabled, an interrupt will be +//! issued. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_setCompFilterLowThreshold(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t lowThreshold) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(lowThreshold < 0x7FFFU); + + address = base + SDFM_O_SDCMPL1 + ((uint32_t)filterNumber * 16U); + + // + // Write to LLT bit + // + EALLOW; + HWREGH(address) = (HWREGH(address) & ~SDFM_SDCMPL1_LLT_M) | lowThreshold; + EDIS; +} + +//***************************************************************************** +// +//! Enable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function enables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter specified +//! by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_enableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, Modulator failure + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) |= + (intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) |= SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Disable SDFM interrupts. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param intFlags is the interrupt source. +//! +//! This function disables the low threshold , high threshold or modulator +//! failure interrupt as determined by intFlags for the filter +//! specified by filterNumber. +//! Valid values for intFlags are: +//! SDFM_MODULATOR_FAILURE_INTERRUPT , SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT, +//! SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT,SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SDFM_disableInterrupt(uint32_t base, SDFM_FilterNumber filterNumber, + uint16_t intFlags) +{ + uint16_t offset; + + ASSERT(SDFM_isBaseValid(base)); + + offset = (uint16_t)filterNumber * 16U; + + EALLOW; + + // + // Low, high threshold, modulator failure interrupts + // + if((intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)) != 0U) + { + // + // Set IEL or IEH or MFIE bit of SDFM_O_SDCPARMx + // + HWREGH(base + SDFM_O_SDCPARM1 + offset) &= + ~(intFlags & (SDFM_MODULATOR_FAILURE_INTERRUPT | + SDFM_LOW_LEVEL_THRESHOLD_INTERRUPT | + SDFM_HIGH_LEVEL_THRESHOLD_INTERRUPT)); + } + + // + // Data filter acknowledge interrupt + // + if((intFlags & SDFM_DATA_FILTER_ACKNOWLEDGE_INTERRUPT) != 0U) + { + HWREGH(base + SDFM_O_SDDFPARM1 + offset) &= ~SDFM_SDDFPARM1_AE; + } + EDIS; +} + +//***************************************************************************** +// +//! Set the comparator filter type. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param filterType is the comparator filter type or structure. +//! +//! This function sets the Comparator filter type or structure to be used as +//! specified by filterType for the selected filter number as specified by +//! filterNumber. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setComparatorFilterType(uint32_t base, SDFM_FilterNumber filterNumber, + SDFM_FilterType filterType) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to CS1_CS0 bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_CS1_CS0_M)) | + ((uint16_t)filterType << 3U); + EDIS; +} + +//***************************************************************************** +// +//! Set Comparator filter over sampling ratio. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! \param overSamplingRatio is the comparator filter over sampling ration. +//! +//! This function sets the comparator filter oversampling ratio for the filter +//! specified by the filterNumber.Valid values for the variable +//! overSamplingRatio are 0 to 31 inclusive. +//! The actual oversampling ratio will be this value plus one. +//! +//! \return None. +//***************************************************************************** +static inline void +SDFM_setCompFilterOverSamplingRatio(uint32_t base, + SDFM_FilterNumber filterNumber, + uint16_t overSamplingRatio) +{ + uint32_t address; + + ASSERT(SDFM_isBaseValid(base)); + ASSERT(overSamplingRatio < 32U); + + address = base + SDFM_O_SDCPARM1 + ((uint32_t)filterNumber * 16U); + + // + // Write to COSR bits + // + EALLOW; + HWREGH(address) = (HWREGH(address) & (~SDFM_SDCPARM1_COSR_M)) | + overSamplingRatio; + EDIS; +} + +//***************************************************************************** +// +//! Get the filter data output. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the latest data filter output. Depending on the +//! filter data output format selected, the valid value will be the lower 16 +//! bits or the whole 32 bits of the returned value. +//! +//! \return Returns the latest data filter output. +//***************************************************************************** +static inline uint32_t +SDFM_getFilterData(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDDATA bits + // + return(HWREG(base + SDFM_O_SDDATA1 + ((uint32_t)filterNumber * 16U))); +} + +//***************************************************************************** +// +//! Get the Comparator threshold status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Comparator output threshold status for the given +//! filterNumber. +//! +//! \return Returns the following status flags. +//! - \b SDFM_OUTPUT_WITHIN_THRESHOLD if the output is within the +//! specified threshold. +//! - \b SDFM_OUTPUT_ABOVE_THRESHOLD if the output is above the high +//! threshold +//! - \b SDFM_OUTPUT_BELOW_THRESHOLD if the output is below the low +//! threshold. +//! +//***************************************************************************** +static inline SDFM_OutputThresholdStatus +SDFM_getThresholdStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG high/low threshold bits + // + return((SDFM_OutputThresholdStatus)((HWREG(base + SDFM_O_SDIFLG) >> + (2U * (uint16_t)filterNumber)) & 0x3U)); +} + +//***************************************************************************** +// +//! Get the Modulator status. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns the Modulator status. +//! +//! \return Returns true if the Modulator is operating normally +//! Returns false if the Modulator has failed +//! +//***************************************************************************** +static inline bool +SDFM_getModulatorStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MF1, MF2, MF3 OR MF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 8U)) & + 0x1U) != 0x1U); +} + +//***************************************************************************** +// +//! Check if new Filter data is available. +//! +//! \param base is the base address of the SDFM module +//! \param filterNumber is the filter number. +//! +//! This function returns new filter data status. +//! +//! \return Returns \b true if new filter data is available +//! Returns \b false if no new filter data is available +//! +//***************************************************************************** +static inline bool +SDFM_getNewFilterDataStatus(uint32_t base, SDFM_FilterNumber filterNumber) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG AF1, AF2, AF3 OR AF4 bits + // + return(((HWREG(base + SDFM_O_SDIFLG) >> ((uint16_t)filterNumber + 12U)) & + 0x1U) == 0x1U); +} + +//***************************************************************************** +// +//! Get pending interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function returns any pending interrupt status. +//! +//! \return Returns \b true if there is a pending interrupt. +//! Returns \b false if no interrupt is pending. +//! +//***************************************************************************** +static inline bool +SDFM_getIsrStatus(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Read SDIFLG MIF + // + return((HWREG(base + SDFM_O_SDIFLG) >> 31U) == 0x1U); +} + +//***************************************************************************** +// +//! Clear pending flags. +//! +//! \param base is the base address of the SDFM module +//! \param flag is the SDFM status +//! +//! This function clears the specified pending interrupt flag. +//! Valid values are +//! SDFM_MAIN_INTERRUPT_FLAG,SDFM_FILTER_1_NEW_DATA_FLAG, +//! SDFM_FILTER_2_NEW_DATA_FLAG,SDFM_FILTER_3_NEW_DATA_FLAG, +//! SDFM_FILTER_4_NEW_DATA_FLAG,SDFM_FILTER_1_MOD_FAILED_FLAG, +//! SDFM_FILTER_2_MOD_FAILED_FLAG,SDFM_FILTER_3_MOD_FAILED_FLAG, +//! SDFM_FILTER_4_MOD_FAILED_FLAG,SDFM_FILTER_1_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_1_LOW_THRESHOLD_FLAG,SDFM_FILTER_2_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_2_LOW_THRESHOLD_FLAG,SDFM_FILTER_3_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_3_LOW_THRESHOLD_FLAG,SDFM_FILTER_4_HIGH_THRESHOLD_FLAG, +//! SDFM_FILTER_4_LOW_THRESHOLD_FLAG or any combination of the above +//! flags. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_clearInterruptFlag(uint32_t base, uint32_t flag) +{ + ASSERT(SDFM_isBaseValid(base)); + ASSERT((flag & 0x8000FFFFU) == flag); + + // + // Write to SDIFLGCLR register + // + HWREG(base + SDFM_O_SDIFLGCLR) |= flag; +} + +//***************************************************************************** +// +//! Enable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) |= SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main interrupt. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables the main SDFM interrupt. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainInterrupt(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDCTL MIE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDCTL) &= ~SDFM_SDCTL_MIE; + EDIS; +} + +//***************************************************************************** +// +//! Enable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function enables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_enableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Set SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) |= SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +//! Disable main filter. +//! +//! \param base is the base address of the SDFM module +//! +//! This function disables main filter. +//! +//! \return None +//! +//***************************************************************************** +static inline void +SDFM_disableMainFilter(uint32_t base) +{ + ASSERT(SDFM_isBaseValid(base)); + + // + // Clear SDMFILEN MFE bit + // + EALLOW; + HWREGH(base + SDFM_O_SDMFILEN) &= ~SDFM_SDMFILEN_MFE; + EDIS; +} + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Configures SDFM comparator for filter config & threshold values +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio. +//! \param config2 is high-level and low-level threshold values. +//! +//! This function configures the comparator filter for filter config and +//! threshold values based on provided inputs. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] filter number +//! - config1.[7:4] filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio ,which ranges [1,32] inclusive, in the appropriate bit location. +//! For example the value +//! (SDFM_FILTER_1 | SDFM_FILTER_SINC_2 | SDFM_SET_OSR(16)) +//! will select Filter 1, SINC 2 type with an oversampling ratio of 16. +//! +//! The config2 parameter is the logical OR of the filter high and low +//! threshold values. +//! The bit definitions for config2 are as follow: +//! - config2.[15:0] low threshold +//! - config2.[31:16] high threshold +//! The upper 16 bits define the high threshold and the lower +//! 16 bits define the low threshold. +//! SDFM_THRESHOLD(H,L) can be used to combine the high and low thresholds. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configComparator(uint32_t base, uint16_t config1, uint32_t config2); + +//***************************************************************************** +// +//! Configure SDFM data filter +//! +//! \param base is the base address of the SDFM module +//! \param config1 is the filter number, filter type and over sampling ratio +//! configuration. +//! \param config2 is filter switch, data representation and data shift values +//! configuration. +//! +//! This function configures the data filter based on configurations +//! config1 and config2. +//! +//! The config1 parameter is the logical OR of the filter number, filter type +//! and oversampling ratio. +//! The bit definitions for config1 are as follow: +//! - config1.[3:0] Filter number +//! - config1.[7:4] Filter type +//! - config1.[15:8] Over sampling Ratio +//! Valid values for filter number and filter type are defined in +//! SDFM_FilterNumber and SDFM_FilterType enumerations respectively. +//! SDFM_SET_OSR(X) macro can be used to set the value of the oversampling +//! ratio , which ranges [1,256] inclusive , in the appropriate bit location +//! for config1. For example the value +//! (SDFM_FILTER_2 | SDFM_FILTER_SINC_3 | SDFM_SET_OSR(64)) +//! will select Filter 2 , SINC 3 type with an oversampling ratio of 64. +//! +//! The config2 parameter is the logical OR of data representation, filter +//! switch, and data shift values +//! The bit definitions for config2 are as follow: +//! - config2.[0] Data representation +//! - config2.[1] Filter switch +//! - config2.[15:2] Shift values +//! Valid values for data representation are given in SDFM_OutputDataFormat +//! enumeration. SDFM_FILTER_DISABLE or SDFM_FILTER_ENABLE will define the +//! filter switch values.SDFM_SHIFT_VALUE(X) macro can be used to set the value +//! of the data shift value,which ranges [0,31] inclusive, in the appropriate +//! bit location for config2. +//! The shift value is valid only in SDFM_DATA_FORMAT_16_BIT data +//! representation format. +//! +//! \return None. +//! +//***************************************************************************** +extern void +SDFM_configDataFilter(uint32_t base, uint16_t config1, uint16_t config2); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif +#endif // SDFM_H diff --git a/gpio_driverlib_cpu1/device/driverlib/spi.c b/gpio_driverlib_cpu1/device/driverlib/spi.c new file mode 100644 index 0000000..b077369 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/spi.c @@ -0,0 +1,661 @@ +//########################################################################### +// +// FILE: spi.c +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "spi.h" + +//***************************************************************************** +// +// SPI_setConfig +// +//***************************************************************************** +void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth) +{ + uint16_t regValue; + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + ASSERT((dataWidth >= 1U) && (dataWidth <= 16U)); + ASSERT((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPISWRESET) == 0U); + + // + // Set polarity and data width. + // + regValue = (((uint16_t)protocol << 6U) & SPI_CCR_CLKPOLARITY) | + (dataWidth - 1U); + + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & + ~(SPI_CCR_CLKPOLARITY | SPI_CCR_SPICHAR_M)) | + regValue; + + // + // Set the mode and phase. + // + regValue = (uint16_t)mode | (((uint16_t)protocol << 2U) & + SPI_CTL_CLK_PHASE); + + HWREGH(base + SPI_O_CTL) = (HWREGH(base + SPI_O_CTL) & + ~(SPI_CTL_TALK | SPI_CTL_CONTROLLER_PERIPHERAL | + SPI_CTL_CLK_PHASE)) | regValue; + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_setBaudRate +// +//***************************************************************************** +void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate) +{ + uint32_t baud; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(bitRate <= (lspclkHz / 4U)); + ASSERT((lspclkHz / bitRate) <= 128U); + + // + // Set the clock. + // + baud = (lspclkHz / bitRate) - 1U; + HWREGH(base + SPI_O_BRR) = (uint16_t)baud; +} + +//***************************************************************************** +// +// SPI_enableInterrupt +// +//***************************************************************************** +void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_SPIINTENA; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) |= SPI_CTL_OVERRUNINTENA; + } + + // + // Enable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFIENA; + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFIENA; + } +} + +//***************************************************************************** +// +// SPI_disableInterrupt +// +//***************************************************************************** +void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the specified non-FIFO interrupts. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_SPIINTENA); + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_CTL) &= ~(SPI_CTL_OVERRUNINTENA); + } + + // + // Disable the specified FIFO-mode interrupts. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_TXFFIENA); + } + + if((intFlags & (SPI_INT_RXFF | SPI_INT_RXFF_OVERFLOW)) != 0U) + { + HWREGH(base + SPI_O_FFRX) &= ~(SPI_FFRX_RXFFIENA); + } +} + +//***************************************************************************** +// +// SPI_getInterruptStatus +// +//***************************************************************************** +uint32_t +SPI_getInterruptStatus(uint32_t base) +{ + uint32_t temp = 0; + + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + if((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) != 0U) + { + temp |= SPI_INT_RX_DATA_TX_EMPTY; + } + + if((HWREGH(base + SPI_O_STS) & SPI_STS_OVERRUN_FLAG) != 0U) + { + temp |= SPI_INT_RX_OVERRUN; + } + + if((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFINT) != 0U) + { + temp |= SPI_INT_TXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFINT) != 0U) + { + temp |= SPI_INT_RXFF; + } + + if((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFOVF) != 0U) + { + temp |= SPI_INT_RXFF_OVERFLOW; + } + + return(temp); +} + +//***************************************************************************** +// +// SPI_clearInterruptStatus +// +//***************************************************************************** +void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the specified non-FIFO interrupt sources. + // + if((intFlags & SPI_INT_RX_DATA_TX_EMPTY) != 0U) + { + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; + } + + if((intFlags & SPI_INT_RX_OVERRUN) != 0U) + { + HWREGH(base + SPI_O_STS) |= SPI_STS_OVERRUN_FLAG; + } + + // + // Clear the specified FIFO-mode interrupt sources. + // + if((intFlags & SPI_INT_TXFF) != 0U) + { + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFINTCLR; + } + + if((intFlags & SPI_INT_RXFF_OVERFLOW) != 0U) + { + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFFOVFCLR; + } +} +//***************************************************************************** +// +// SPI_pollingNonFIFOTransaction +// +//***************************************************************************** +uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, uint16_t data) +{ + uint16_t rxData; + + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + ASSERT(data < ((uint32_t)1U << charLength)); + + // + // Write to SPI Transmit buffer + // + SPI_writeDataBlockingNonFIFO(base, data << (16U - charLength)); + + // + // Read SPI Receive buffer + // + rxData = SPI_readDataBlockingNonFIFO(base); + + return(rxData); +} +//***************************************************************************** +// +// SPI_pollingFIFOTransaction +// +//***************************************************************************** + +void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay) +{ + ASSERT(((HWREGH(base + SPI_O_CCR) & SPI_CCR_SPICHAR_M) + 1U) == charLength); + + // + // Reset the TX / RX FIFO buffers to default state + // + SPI_disableFIFO(base); // Disable FIFO register + SPI_enableFIFO(base); // Enable FIFO register + + // + // Configure the FIFO Transmit Delay + // + SPI_setTxFifoTransmitDelay(base, txDelay); + + // + // Determine the number of 16-level words from number of words to be + // transmitted / received + // + uint16_t numOfSixteenWords = numOfWords / (uint16_t)SPI_FIFO_TXFULL; + + // + // Determine the number of remaining words from number of words to be + // transmitted / received + // + uint16_t remainingWords = numOfWords % (uint16_t)SPI_FIFO_TXFULL; + + uint16_t count = 0; + uint16_t i = 0; + uint16_t txBuffer_pos = 0; + uint16_t rxBuffer_pos = 0; + + // + // Number of transactions is based on numOfSixteenWords + // Each transaction will transmit and receive 16 words. + // + while(count < numOfSixteenWords) + { + // + // Fill-up the SPI Transmit FIFO buffers + // + for(i = 1; i <= (uint16_t)SPI_FIFO_TXFULL; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer is full + // + while(SPI_getRxFIFOStatus(base) < SPI_FIFO_RXFULL) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 1U; i <= (uint16_t)SPI_FIFO_RXFULL; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + count++; + } + + // + // Number of transactions is based on remainingWords + // + for(i = 0U; i < remainingWords; i++) + { + SPI_writeDataBlockingFIFO(base, pTxBuffer[txBuffer_pos] << + (16U - charLength)); + txBuffer_pos++; + } + + // + // Wait till SPI Receive FIFO buffer remaining words + // + while((uint16_t)SPI_getRxFIFOStatus(base) < remainingWords) + { + } + + // + // Read the SPI Receive FIFO buffers + // + for(i = 0; i < remainingWords; i++) + { + if(pRxBuffer == NULL) + { + SPI_readDataBlockingFIFO(base); + } + else + { + pRxBuffer[rxBuffer_pos] = SPI_readDataBlockingFIFO(base); + rxBuffer_pos++; + } + } + + // + // Disable SPI FIFO + // + SPI_disableFIFO(base); +} + +//***************************************************************************** +// +// SPI_transmit24Bits +// +//***************************************************************************** +void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t rxBuffer[3]; + uint16_t txBuffer[3]; + + ASSERT(data < ((uint32_t)1U << 24U)); + + // + // Empty Receive buffer + // + for(i = 0U; i < 3U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[23:16] + txBuffer[1] = (uint16_t)(data) >> 8U; // data[15:8] + txBuffer[2] = (uint16_t)(data) & 0x00FFU; // data[7:0] + + // + // Three 8-bits make a 24-bit + // Character length = 8 + // number of bytes = 3 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); +} +//***************************************************************************** +// +// SPI_receive16Bits +// +//***************************************************************************** + +uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + uint16_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 2U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 2U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = (rxBuffer[1] << 8) | rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = (rxBuffer[0] << 8) | rxBuffer[1]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_receive24Bits +// +//***************************************************************************** + +uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[3]; + uint16_t rxBuffer[3]; + uint32_t rxData = 0; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 3U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Two 8-bits make a 16-bit + // Character length = 8 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 3U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[2] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 16) | + ((uint32_t)rxBuffer[1] << 8) | + (uint32_t)rxBuffer[2]; + } + + return(rxData); +} +//***************************************************************************** +// +// SPI_transmit32Bits +// +//***************************************************************************** + +void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[2]; + uint16_t rxBuffer[2]; + + // + // Empty Receive buffer + // + for(i = 0U; i < 2U; i++) + { + rxBuffer[i] = 0U; + } + + // + // Fill Transmit buffer with appropriate data + // + txBuffer[0] = (uint16_t)(data >> 16U); // data[31:16] + txBuffer[1] = (uint16_t)(data); // data[15:0] + + // + // Two 16-bits make a 32-bit + // Character length = 16 + // number of bytes = 2 + // + SPI_pollingFIFOTransaction(base, 16U, txBuffer, rxBuffer, 2U, txDelay); +} +//***************************************************************************** +// +// SPI_receive32Bits +// +//***************************************************************************** + +uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay) +{ + uint16_t i; + uint16_t txBuffer[4]; + uint16_t rxBuffer[4]; + uint32_t rxData = 0U; + + ASSERT(dummyData <= 0xFFU); + + // + // Empty Transmit buffer + // + for(i = 0U; i < 4U; i++) + { + txBuffer[i] = dummyData; + rxBuffer[i] = 0U; + } + + // + // Send dummy words to receive data from peripheral + // Four 8-bits make a 32-bit + // Character length = 8 + // number of bytes = 4 + // + SPI_pollingFIFOTransaction(base, 8U, txBuffer, rxBuffer, 4U, txDelay); + + if(endianness == SPI_DATA_LITTLE_ENDIAN) + { + // + // LITTLE_ENDIAN + // + rxData = ((uint32_t)rxBuffer[3] << 24U) | + ((uint32_t)rxBuffer[2] << 16U) | + ((uint32_t)rxBuffer[1] << 8U) | + (uint32_t)rxBuffer[0]; + } + else + { + // + // BIG_ENDIAN + // + rxData = ((uint32_t)rxBuffer[0] << 24U) | + ((uint32_t)rxBuffer[1] << 16U) | + ((uint32_t)rxBuffer[2] << 8U) | + (uint32_t)rxBuffer[3]; + } + + return(rxData); +} diff --git a/gpio_driverlib_cpu1/device/driverlib/spi.h b/gpio_driverlib_cpu1/device/driverlib/spi.h new file mode 100644 index 0000000..b9e0d38 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/spi.h @@ -0,0 +1,1743 @@ +//########################################################################### +// +// FILE: spi.h +// +// TITLE: C28x SPI driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SPI_H +#define SPI_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup spi_api SPI +//! \brief This module is used for SPI configurations. +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_spi.h" +#include "debug.h" +#include "hw_reg_inclusive_terminology.h" + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// Values that can be passed to SPI_enableInterrupt(), SPI_disableInterrupt(), +// and SPI_clearInterruptStatus() as the intFlags parameter, and returned by +// SPI_getInterruptStatus(). +// +//***************************************************************************** +#define SPI_INT_RX_OVERRUN 0x0001U //!< Receive overrun interrupt +#define SPI_INT_RX_DATA_TX_EMPTY 0x0002U //!< Data received, transmit empty +#define SPI_INT_RXFF 0x0004U //!< RX FIFO level interrupt +#define SPI_INT_TXFF 0x0008U //!< TX FIFO level interrupt +#define SPI_INT_RXFF_OVERFLOW 0x0010U //!< RX FIFO overflow +#endif + + +//***************************************************************************** +// +//! This macro definition is used to transmit a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitByte(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 8U, txData) + +//***************************************************************************** +// +//! This macro definition is used to transmit a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! +//! This macro definition is to transmit a 16-bit word of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmit16Bits(base, txData) \ + SPI_pollingNonFIFOTransaction(base, 16U, txData) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of bytes to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' bytes of data. +//! This macro definition uses SPI_pollingFIFOTransaction function. +//! +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNBytes(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' 16-bit words of data +//! +//! \param base specifies the SPI module base address. +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit 'N' 16-bit words of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitN16BitWord(base, txBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, txBuffer, NULL, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition can be used to transmit 'N' with previously +//! configured SPI character length +//! +//! \param base specifies the SPI module base address +//! \param charLength specifies the SPI character length +//! \param txBuffer is the transmit buffer to be transmitted over SPI +//! \param numOfWords is the number of 16-bit word to be transmitted +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This macro definition can be used to transmit 'N' with configurable +//! SPI character length. +//! +//! This macro uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_transmitNWordsWithCharLength(base, charLength, txBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, txBuffer, NULL, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro definition is used to receive a byte of data +//! +//! \param base specifies the SPI module base address. +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! +//! This macro definition is to receive a byte of data. +//! This macro uses SPI_pollingNonFIFOTransaction function +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received byte. +// +//***************************************************************************** +#define SPI_receiveByte(base, dummyData) \ + SPI_pollingNonFIFOTransaction(base, 8U, dummyData) + +//***************************************************************************** +// +//! This macro is used to receive 'N' bytes of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of bytes to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' bytes of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNBytes(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 8U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' 16-bits words of data +//! +//! \param base specifies the SPI module base address. +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of 16-bit words to be received +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' 16-bit words of data +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveN16BitWord(base, rxBuffer, numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, 16U, NULL, rxBuffer, numOfWords, txDelay) + +//***************************************************************************** +// +//! This macro is used to receive 'N' words with previously configured character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param rxBuffer specifies receive buffer which will store the received bytes +//! \param numOfWords specifies the number of words with specified character +//! length +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive 'N' words with specified character length +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to required value BEFORE calling +//! the function, and passed as the charLength parameter. +//! +//! \return None. +// +//***************************************************************************** +#define SPI_receiveNWordsWithcharLength(base, charLength, rxBuffer, \ + numOfWords, txDelay) \ + SPI_pollingFIFOTransaction(base, charLength, NULL, rxBuffer, \ + numOfWords, txDelay) + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e protocol parameter. +// +//***************************************************************************** +typedef enum +{ + //! Mode 0. Polarity 0, phase 0. Rising edge without delay. + SPI_PROT_POL0PHA0 = 0x0000U, + //! Mode 1. Polarity 0, phase 1. Rising edge with delay. + SPI_PROT_POL0PHA1 = 0x0002U, + //! Mode 2. Polarity 1, phase 0. Falling edge without delay. + SPI_PROT_POL1PHA0 = 0x0001U, + //! Mode 3. Polarity 1, phase 1. Falling edge with delay. + SPI_PROT_POL1PHA1 = 0x0003U +} SPI_TransferProtocol; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setConfig() as the \e mode parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_MODE_PERIPHERAL = 0x0002U, //!< SPI peripheral + SPI_MODE_CONTROLLER = 0x0006U, //!< SPI controller + SPI_MODE_PERIPHERAL_OD = 0x0000U, //!< SPI peripheral w/ output disabled + SPI_MODE_CONTROLLER_OD = 0x0004U //!< SPI controller w/ output disabled +} SPI_Mode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e txLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e txLevel +//! parameter, and returned by SPI_getTxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_TXEMPTY = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX0 = 0x0000U, //!< Transmit FIFO empty + SPI_FIFO_TX1 = 0x0001U, //!< Transmit FIFO 1/16 full + SPI_FIFO_TX2 = 0x0002U, //!< Transmit FIFO 2/16 full + SPI_FIFO_TX3 = 0x0003U, //!< Transmit FIFO 3/16 full + SPI_FIFO_TX4 = 0x0004U, //!< Transmit FIFO 4/16 full + SPI_FIFO_TX5 = 0x0005U, //!< Transmit FIFO 5/16 full + SPI_FIFO_TX6 = 0x0006U, //!< Transmit FIFO 6/16 full + SPI_FIFO_TX7 = 0x0007U, //!< Transmit FIFO 7/16 full + SPI_FIFO_TX8 = 0x0008U, //!< Transmit FIFO 8/16 full + SPI_FIFO_TX9 = 0x0009U, //!< Transmit FIFO 9/16 full + SPI_FIFO_TX10 = 0x000AU, //!< Transmit FIFO 10/16 full + SPI_FIFO_TX11 = 0x000BU, //!< Transmit FIFO 11/16 full + SPI_FIFO_TX12 = 0x000CU, //!< Transmit FIFO 12/16 full + SPI_FIFO_TX13 = 0x000DU, //!< Transmit FIFO 13/16 full + SPI_FIFO_TX14 = 0x000EU, //!< Transmit FIFO 14/16 full + SPI_FIFO_TX15 = 0x000FU, //!< Transmit FIFO 15/16 full + SPI_FIFO_TX16 = 0x0010U, //!< Transmit FIFO full + SPI_FIFO_TXFULL = 0x0010U //!< Transmit FIFO full +} SPI_TxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setFIFOInterruptLevel() as the \e rxLevel +//! parameter, returned by SPI_getFIFOInterruptLevel() in the \e rxLevel +//! parameter, and returned by SPI_getRxFIFOStatus(). +// +//***************************************************************************** +typedef enum +{ + SPI_FIFO_RXEMPTY = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX0 = 0x0000U, //!< Receive FIFO empty + SPI_FIFO_RX1 = 0x0001U, //!< Receive FIFO 1/16 full + SPI_FIFO_RX2 = 0x0002U, //!< Receive FIFO 2/16 full + SPI_FIFO_RX3 = 0x0003U, //!< Receive FIFO 3/16 full + SPI_FIFO_RX4 = 0x0004U, //!< Receive FIFO 4/16 full + SPI_FIFO_RX5 = 0x0005U, //!< Receive FIFO 5/16 full + SPI_FIFO_RX6 = 0x0006U, //!< Receive FIFO 6/16 full + SPI_FIFO_RX7 = 0x0007U, //!< Receive FIFO 7/16 full + SPI_FIFO_RX8 = 0x0008U, //!< Receive FIFO 8/16 full + SPI_FIFO_RX9 = 0x0009U, //!< Receive FIFO 9/16 full + SPI_FIFO_RX10 = 0x000AU, //!< Receive FIFO 10/16 full + SPI_FIFO_RX11 = 0x000BU, //!< Receive FIFO 11/16 full + SPI_FIFO_RX12 = 0x000CU, //!< Receive FIFO 12/16 full + SPI_FIFO_RX13 = 0x000DU, //!< Receive FIFO 13/16 full + SPI_FIFO_RX14 = 0x000EU, //!< Receive FIFO 14/16 full + SPI_FIFO_RX15 = 0x000FU, //!< Receive FIFO 15/16 full + SPI_FIFO_RX16 = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXFULL = 0x0010U, //!< Receive FIFO full + SPI_FIFO_RXDEFAULT = 0x001FU //!< To prevent interrupt at reset +} SPI_RxFIFOLevel; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setEmulationMode() as the \e mode +//! parameter. +// +//***************************************************************************** +typedef enum +{ + //! Transmission stops after midway in the bit stream + SPI_EMULATION_STOP_MIDWAY = 0x0000U, + //! Continue SPI operation regardless + SPI_EMULATION_FREE_RUN = 0x0010U, + //! Transmission will stop after a started transmission completes + SPI_EMULATION_STOP_AFTER_TRANSMIT = 0x0020U +} SPI_EmulationMode; + +//***************************************************************************** +// +//! Values that can be passed to SPI_setPTESignalPolarity() as the \e polarity +//! parameter. +// +//***************************************************************************** +typedef enum +{ + SPI_PTE_ACTIVE_LOW = 0x0000U, //!< SPIPTE is active low (normal) + SPI_PTE_ACTIVE_HIGH = SPI_PRI_PTEINV //!< SPIPTE is active high (inverted) +} SPI_PTEPolarity; + +//***************************************************************************** +// +//! Values that can be passed to SPI_receive16Bits(), SPI_receive24Bits(), +//! SPI_receive32Bits() +// +//***************************************************************************** +typedef enum +{ + SPI_DATA_LITTLE_ENDIAN = 0U, //!< LITTLE ENDIAN + SPI_DATA_BIG_ENDIAN = 1U, //!< BIG ENDIAN +} SPI_endianess; + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! \internal +//! Checks an SPI base address. +//! +//! \param base specifies the SPI module base address. +//! +//! This function determines if a SPI module base address is valid. +//! +//! \return Returns \b true if the base address is valid and \b false +//! otherwise. +// +//***************************************************************************** +#ifdef DEBUG +static inline bool +SPI_isBaseValid(uint32_t base) +{ + return( + (base == SPIA_BASE) || + (base == SPIB_BASE) || + (base == SPIC_BASE) + ); +} +#endif + +//***************************************************************************** +// +//! Enables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function enables operation of the serial peripheral interface. The +//! serial peripheral interface must be configured before it is enabled. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPISWRESET; +} + +//***************************************************************************** +// +//! Disables the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! +//! This function disables operation of the serial peripheral interface. Call +//! this function before doing any configuration. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableModule(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + HWREGH(base + SPI_O_CCR) &= ~(SPI_CCR_SPISWRESET); +} + +//***************************************************************************** +// +//! Sets the character length of SPI transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the character length of SPI transaction +//! +//! This function configures the character length of SPI transaction. +//! SPI character length can be from anywhere between 1-bit word to 16 bit word +//! of character length +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setcharLength(uint32_t base, uint16_t charLength) +{ + // + // Check the arguments. + // + ASSERT((charLength >= 1U) && (charLength <= 16U)); + + bool originalStatus = ((HWREGH(base + SPI_O_CCR) & (SPI_CCR_SPISWRESET)) + == SPI_CCR_SPISWRESET ); + + SPI_disableModule(base); + HWREGH(base + SPI_O_CCR) = (HWREGH(base + SPI_O_CCR) & ~SPI_CCR_SPICHAR_M) | + (charLength - 1U); + // + // Restore original status + // + if(originalStatus){ + SPI_enableModule(base); + } +} + + +//***************************************************************************** +// +//! Enables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions enables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Enable the FIFO. + // + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Disables the transmit and receive FIFOs. +//! +//! \param base is the base address of the SPI port. +//! +//! This functions disables the transmit and receive FIFOs in the SPI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Disable the FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~(SPI_FFTX_SPIFFENA | SPI_FFTX_TXFIFO); + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Resets the transmit FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the transmit FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetTxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_TXFIFO; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_TXFIFO; +} + +//***************************************************************************** +// +//! Resets the receive FIFO. +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the receive FIFO, setting the FIFO pointer back to +//! zero. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_resetRxFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Reset the RX FIFO. + // + HWREGH(base + SPI_O_FFRX) &= ~SPI_FFRX_RXFIFORESET; + HWREGH(base + SPI_O_FFRX) |= SPI_FFRX_RXFIFORESET; +} + +//***************************************************************************** +// +//! Sets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is the transmit FIFO interrupt level, specified as +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, . . . or +//! \b SPI_FIFO_TX16. +//! \param rxLevel is the receive FIFO interrupt level, specified as +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, . . . or +//! \b SPI_FIFO_RX16. +//! +//! This function sets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel txLevel, + SPI_RxFIFOLevel rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the FIFO interrupt levels. + // + HWREGH(base + SPI_O_FFTX) = (HWREGH(base + SPI_O_FFTX) & + (~SPI_FFTX_TXFFIL_M)) | (uint16_t)txLevel; + HWREGH(base + SPI_O_FFRX) = (HWREGH(base + SPI_O_FFRX) & + (~SPI_FFRX_RXFFIL_M)) | (uint16_t)rxLevel; +} + +//***************************************************************************** +// +//! Gets the FIFO level at which interrupts are generated. +//! +//! \param base is the base address of the SPI port. +//! \param txLevel is a pointer to storage for the transmit FIFO level, +//! returned as one of \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, +//! \b SPI_FIFO_TX2, . . . or \b SPI_FIFO_TX16. +//! \param rxLevel is a pointer to storage for the receive FIFO level, +//! returned as one of \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, +//! \b SPI_FIFO_RX2, . . . or \b SPI_FIFO_RX16. +//! +//! This function gets the FIFO level at which transmit and receive interrupts +//! are generated. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_getFIFOInterruptLevel(uint32_t base, SPI_TxFIFOLevel *txLevel, + SPI_RxFIFOLevel *rxLevel) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Extract the transmit and receive FIFO levels. + // + *txLevel = (SPI_TxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFTX) & + SPI_FFTX_TXFFIL_M)); + *rxLevel = (SPI_RxFIFOLevel)((uint16_t)(HWREGH(base + SPI_O_FFRX) & + SPI_FFRX_RXFFIL_M)); +} + +//***************************************************************************** +// +//! Get the transmit FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the transmit FIFO. +//! +//! \return Returns the current number of words in the transmit FIFO specified +//! as one of the following: +//! \b SPI_FIFO_TX0, \b SPI_FIFO_TX1, \b SPI_FIFO_TX2, \b SPI_FIFO_TX3, +//! ..., or \b SPI_FIFO_TX16 +// +//***************************************************************************** +static inline SPI_TxFIFOLevel +SPI_getTxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_TxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) >> + SPI_FFTX_TXFFST_S))); +} + +//***************************************************************************** +// +//! Get the receive FIFO status +//! +//! \param base is the base address of the SPI port. +//! +//! This function gets the current number of words in the receive FIFO. +//! +//! \return Returns the current number of words in the receive FIFO specified +//! as one of the following: +//! \b SPI_FIFO_RX0, \b SPI_FIFO_RX1, \b SPI_FIFO_RX2, \b SPI_FIFO_RX3, +//! ..., or \b SPI_FIFO_RX16 +// +//***************************************************************************** +static inline SPI_RxFIFOLevel +SPI_getRxFIFOStatus(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Get the current FIFO status + // + return((SPI_RxFIFOLevel)((uint16_t)((HWREGH(base + SPI_O_FFRX) & SPI_FFRX_RXFFST_M) >> + SPI_FFRX_RXFFST_S))); +} + +//***************************************************************************** +// +//! Determines whether the SPI transmitter is busy or not. +//! +//! \param base is the base address of the SPI port. +//! +//! This function allows the caller to determine whether all transmitted bytes +//! have cleared the transmitter hardware. If \b false is returned, then the +//! transmit FIFO is empty and all bits of the last transmitted word have left +//! the hardware shift register. This function is only valid when operating in +//! FIFO mode. +//! +//! \return Returns \b true if the SPI is transmitting or \b false if all +//! transmissions are complete. +// +//***************************************************************************** +static inline bool +SPI_isBusy(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Determine if the SPI is busy. + // + return((HWREGH(base + SPI_O_FFTX) & SPI_FFTX_TXFFST_M) != 0U); +} + +//***************************************************************************** +// +//! Puts a data element into the SPI transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataNonBlocking(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Gets a data element from the SPI receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function gets received data from the receive buffer of the specified +//! SPI module and returns it. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataNonBlocking(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for space in the FIFO and then puts data into the transmit buffer. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once space is available in the transmit FIFO. This +//! function should only be used when the FIFO is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until space is available in the receive FIFO. + // + while(SPI_getTxFIFOStatus(base) == SPI_FIFO_TXFULL) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data in the FIFO and then reads it from the receive buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits until there is data in the receive FIFO and then reads +//! received data from the receive buffer. This function should only be used +//! when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data is available in the receive FIFO. + // + while(SPI_getRxFIFOStatus(base) == SPI_FIFO_RXEMPTY) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Waits for the transmit buffer to empty and then writes data to it. +//! +//! \param base specifies the SPI module base address. +//! \param data is the left-justified data to be transmitted over SPI. +//! +//! This function places the supplied data into the transmit buffer of the +//! specified SPI module once it is empty. This function should not be used +//! when FIFO mode is enabled. +//! +//! \note The data being sent must be left-justified in \e data. The lower +//! 16 - N bits will be discarded where N is the data width selected in +//! SPI_setConfig(). For example, if configured for a 6-bit data width, the +//! lower 10 bits of data will be discarded. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_writeDataBlockingNonFIFO(uint32_t base, uint16_t data) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until the transmit buffer is not full. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_BUFFULL_FLAG) != 0U) + { + } + + // + // Write data to the transmit buffer. + // + HWREGH(base + SPI_O_TXBUF) = data; +} + +//***************************************************************************** +// +//! Waits for data to be received and then reads it from the buffer. +//! +//! \param base specifies the SPI module base address. +//! +//! This function waits for data to be received and then reads it from the +//! receive buffer of the specified SPI module. This function should not be +//! used when FIFO mode is enabled. +//! +//! \note Only the lower N bits of the value written to \e data contain valid +//! data, where N is the data width as configured by SPI_setConfig(). For +//! example, if the interface is configured for 8-bit data width, only the +//! lower 8 bits of the value written to \e data contain valid data. +//! +//! \return Returns the word of data read from the SPI receive buffer. +// +//***************************************************************************** +static inline uint16_t +SPI_readDataBlockingNonFIFO(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Wait until data has been received. + // + while((HWREGH(base + SPI_O_STS) & SPI_STS_INT_FLAG) == 0U) + { + } + + // + // Check for data to read. + // + return(HWREGH(base + SPI_O_RXBUF)); +} + +//***************************************************************************** +// +//! Enables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables 3-wire mode. When in controller mode, this allows +//! SPIPICO to become SPICOCI and SPIPOCI to become free for non-SPI use. +//! When in peripheral mode, SPIPOCI because the SPIPIPO pin and SPIPICO is +//! free for non-SPI use. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the tri-wire bit to enable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) |= SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Disables SPI 3-wire mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables 3-wire mode. SPI will operate in normal 4-wire mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableTriWire(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the tri-wire bit to disable 3-wire mode. + // + HWREGH(base + SPI_O_PRI) &= ~SPI_PRI_TRIWIRE; +} + +//***************************************************************************** +// +//! Enables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables loopback mode. This mode is only valid during +//! controller mode and is helpful during device testing as it internally +//! connects PICO and POCI. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Disables SPI loopback mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables loopback mode. Loopback mode is disabled by default +//! after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableLoopback(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables loopback mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_SPILBK; +} + +//***************************************************************************** +// +//! Set the peripheral select (SPIPTE) signal polarity. +//! +//! \param base is the base address of the SPI port. +//! \param polarity is the SPIPTE signal polarity. +//! +//! This function sets the polarity of the peripheral select (SPIPTE) signal. +//! The two modes to choose from for the \e polarity parameter are +//! \b SPI_PTE_ACTIVE_LOW for active-low polarity (typical) and +//! \b SPI_PTE_ACTIVE_HIGH for active-high polarity (considered inverted). +//! +//! \note This has no effect on the PTE signal when in controller mode. It is +//! only applicable to peripheral mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setPTESignalPolarity(uint32_t base, SPI_PTEPolarity polarity) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the polarity of the SPIPTE signal to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & ~SPI_PRI_PTEINV) | + (uint16_t)polarity; +} + +//***************************************************************************** +// +//! Enables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function enables high speed mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_enableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) |= SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Disables SPI high speed mode. +//! +//! \param base is the base address of the SPI port. +//! +//! This function disables high speed mode. High speed mode is disabled by +//! default after reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_disableHighSpeedMode(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Clear the bit that enables high speed mode. + // + HWREGH(base + SPI_O_CCR) &= ~SPI_CCR_HS_MODE; +} + +//***************************************************************************** +// +//! Sets SPI emulation mode. +//! +//! \param base is the base address of the SPI port. +//! \param mode is the emulation mode. +//! +//! This function sets the behavior of the SPI operation when an emulation +//! suspend occurs. The \e mode parameter can be one of the following: +//! +//! - \b SPI_EMULATION_STOP_MIDWAY - Transmission stops midway through the bit +//! stream. The rest of the bits will be transmitting after the suspend is +//! deasserted. +//! - \b SPI_EMULATION_STOP_AFTER_TRANSMIT - If the suspend occurs before the +//! first SPICLK pulse, the transmission will not start. If it occurs later, +//! the transmission will be completed. +//! - \b SPI_EMULATION_FREE_RUN - SPI operation continues regardless of a +//! the suspend. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SPI_setEmulationMode(uint32_t base, SPI_EmulationMode mode) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write the desired emulation mode to the register. + // + HWREGH(base + SPI_O_PRI) = (HWREGH(base + SPI_O_PRI) & + ~(SPI_PRI_FREE | SPI_PRI_SOFT)) | + (uint16_t)mode; +} + +//***************************************************************************** +// +//! Configures the FIFO Transmit Delay +//! +//! \param base is the base address of the SPI port. +//! \param delay Tx FIFO delay to be configured in cycles (0..0xFF) +//! +//! This function sets the delay between every transfer from FIFO +//! transmit buffer to transmit shift register. The delay is defined in +//! number SPI serial clock cycles. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_setTxFifoTransmitDelay(uint32_t base, uint16_t delay) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + ASSERT(delay <= 0xFFU); + + // + // Configure the FIFO Transmit Delay Bits + // + HWREGH(base + SPI_O_FFCT) = delay; +} + +//***************************************************************************** +// +//! Returns the Emulation Buffer Received Data +//! +//! \param base is the base address of the SPI port. +//! +//! This function returns the Emulation Buffer Received Data +//! +//! \return Rx emulation buffer data +// +//***************************************************************************** +static inline uint16_t +SPI_readRxEmulationBuffer(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Return Emulation Buffer Received Data + // + return(HWREGH(base + SPI_O_RXEMU)); +} + +//***************************************************************************** +// +//! Enable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function sets the TALK bit enabling the data trasnmission. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_enableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) |= SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Disable Trasnmit +//! +//! \param base is the base address of the SPI port. +//! +//! This function clears the TALK bit disabling the data trasnmission. The +//! output pin will be put in high-impedance state. +//! This bit is enabled by SPI_setConfig if the parameter \r mode is selected as +//! SPI_MODE_PERIPHERAL or SPI_MODE_CONTROLLER. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_disableTalk(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Set the TALK bit + // + HWREGH(base + SPI_O_CTL) &= ~SPI_CTL_TALK; +} + +//***************************************************************************** +// +//! Reset SPI transmit and receive channels +//! +//! \param base is the base address of the SPI port. +//! +//! This function resets the SPI transmit and receive channels. +//! +//! \return None +// +//***************************************************************************** +static inline void +SPI_reset(uint32_t base) +{ + // + // Check the arguments. + // + ASSERT(SPI_isBaseValid(base)); + + // + // Write to SPRST bit the TX FIFO. + // + HWREGH(base + SPI_O_FFTX) &= ~SPI_FFTX_SPIRST; + HWREGH(base + SPI_O_FFTX) |= SPI_FFTX_SPIRST; +} + +//***************************************************************************** +// +//! Configures the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param protocol specifies the data transfer protocol. +//! \param mode specifies the mode of operation. +//! \param bitRate specifies the clock rate in Hz. +//! \param dataWidth specifies number of bits transferred per frame. +//! +//! This function configures the serial peripheral interface. It sets the SPI +//! protocol, mode of operation, bit rate, and data width. +//! +//! The \e protocol parameter defines the data frame format. The \e protocol +//! parameter can be one of the following values: \b SPI_PROT_POL0PHA0, +//! \b SPI_PROT_POL0PHA1, \b SPI_PROT_POL1PHA0, or +//! \b SPI_PROT_POL1PHA1. These frame formats encode the following polarity +//! and phase configurations: +//! +//! 

    +//! Polarity Phase       Mode
+//!   0       0   SPI_PROT_POL0PHA0
+//!   0       1   SPI_PROT_POL0PHA1
+//!   1       0   SPI_PROT_POL1PHA0
+//!   1       1   SPI_PROT_POL1PHA1
+//!
    +//! +//! The \e mode parameter defines the operating mode of the SPI module. The +//! SPI module can operate as a controller or peripheral; the SPI can also be be +//! configured to disable output on its serial output line. The \e mode +//! parameter can be one of the following values: \b SPI_MODE_CONTROLLER, +//! \b SPI_MODE_PERIPHERAL, \b SPI_MODE_CONTROLLER_OD or +//! \b SPI_MODE_PERIPHERAL_OD ("OD" indicates "output disabled"). +//! +//! The \e bitRate parameter defines the bit rate for the SPI. This bit rate +//! must satisfy the following clock ratio criteria: +//! +//! - \e bitRate can be no greater than lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The \e dataWidth parameter defines the width of the data transfers and +//! can be a value between 1 and 16, inclusive. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI operation should be disabled via SPI_disableModule() before any +//! changes to its configuration. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setConfig(uint32_t base, uint32_t lspclkHz, SPI_TransferProtocol protocol, + SPI_Mode mode, uint32_t bitRate, uint16_t dataWidth); + +//***************************************************************************** +// +//! Configures the baud rate of the serial peripheral interface. +//! +//! \param base specifies the SPI module base address. +//! \param lspclkHz is the rate of the clock supplied to the SPI module +//! (LSPCLK) in Hz. +//! \param bitRate specifies the clock rate in Hz. +//! +//! This function configures the SPI baud rate. The \e bitRate parameter +//! defines the bit rate for the SPI. This bit rate must satisfy the following +//! clock ratio criteria: +//! +//! - \e bitRate can be no greater than \e lspclkHz divided by 4. +//! - \e lspclkHz / \e bitRate cannot be greater than 128. +//! +//! The peripheral clock is the low speed peripheral clock. This value is +//! returned by SysCtl_getLowSpeedClock(), or it can be explicitly hard coded +//! if it is constant and known (to save the code/execution overhead of a call +//! to SysCtl_getLowSpeedClock()). +//! +//! \note SPI_setConfig() also sets the baud rate. Use SPI_setBaudRate() +//! if you wish to configure it separately from protocol and mode. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_setBaudRate(uint32_t base, uint32_t lspclkHz, uint32_t bitRate); + +//***************************************************************************** +// +//! Enables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be enabled. +//! +//! This function enables the indicated SPI interrupt sources. Only the sources +//! that are enabled can be reflected to the processor interrupt; disabled +//! sources have no effect on the processor. The \e intFlags parameter can be +//! any of the following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF (also enables \b SPI_INT_RXFF_OVERFLOW) - RX FIFO level +//! interrupt (and RX FIFO overflow) +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_enableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Disables individual SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be disabled. +//! +//! This function disables the indicated SPI interrupt sources. The +//! \e intFlags parameter can be any of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF (also disables \b SPI_INT_RXFF_OVERFLOW) +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_disableInterrupt(uint32_t base, uint32_t intFlags); + +//***************************************************************************** +// +//! Gets the current interrupt status. +//! +//! \param base specifies the SPI module base address. +//! +//! This function returns the interrupt status for the SPI module. +//! +//! \return The current interrupt status, enumerated as a bit field of the +//! following values: +//! - \b SPI_INT_RX_OVERRUN - Receive overrun interrupt +//! - \b SPI_INT_RX_DATA_TX_EMPTY - Data received, transmit empty +//! - \b SPI_INT_RXFF - RX FIFO level interrupt +//! - \b SPI_INT_RXFF_OVERFLOW - RX FIFO overflow +//! - \b SPI_INT_TXFF - TX FIFO level interrupt +// +//***************************************************************************** +extern uint32_t +SPI_getInterruptStatus(uint32_t base); + +//***************************************************************************** +// +//! Clears SPI interrupt sources. +//! +//! \param base specifies the SPI module base address. +//! \param intFlags is a bit mask of the interrupt sources to be cleared. +//! +//! This function clears the specified SPI interrupt sources so that they no +//! longer assert. This function must be called in the interrupt handler to +//! keep the interrupts from being triggered again immediately upon exit. The +//! \e intFlags parameter can consist of a bit field of the following values: +//! - \b SPI_INT_RX_OVERRUN +//! - \b SPI_INT_RX_DATA_TX_EMPTY +//! - \b SPI_INT_RXFF +//! - \b SPI_INT_RXFF_OVERFLOW +//! - \b SPI_INT_TXFF +//! +//! \note \b SPI_INT_RX_DATA_TX_EMPTY is cleared by a read of the receive +//! receive buffer, so it usually doesn't need to be cleared using this +//! function. +//! +//! \note Also note that \b SPI_INT_RX_OVERRUN, \b SPI_INT_RX_DATA_TX_EMPTY, +//! \b SPI_INT_RXFF_OVERFLOW, and \b SPI_INT_RXFF are associated with +//! \b SPIRXINT; \b SPI_INT_TXFF is associated with \b SPITXINT. +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_clearInterruptStatus(uint32_t base, uint32_t intFlags); + + +//***************************************************************************** +// +//! This function can be used to transmit a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 24-bit word of data. +//! 24-bit word data is divided into three bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit24Bits(uint32_t base, uint32_t data, uint16_t txDelay); + +//***************************************************************************** +// +//! This function can be used to transmit a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param txData is the data to be transmitted over SPI +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function can be used to transmit a 32-bit word of data. +//! 32-bit word data is divided into four bytes of data. +//! +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 16 bits BEFORE calling the +//! function +//! +//! \return None. +// +//***************************************************************************** +extern void +SPI_transmit32Bits(uint32_t base, uint32_t data, uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to receive a 16-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 16-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 16-bit word. +// +//***************************************************************************** +extern uint16_t +SPI_receive16Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 24-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 24-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 24-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive24Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + +//***************************************************************************** +// +//! This function is used to receive a 32-bit word of data +//! +//! \param base specifies the SPI module base address. +//! \param endianness specifies the endianess of received data +//! \param dummyData is the data which is transmitted to initiate +//! SPI transaction to receive SPI data +//! \param txDelay specifies the number of serial clock cycles delay time after +//! completion of perious word +//! +//! This function is used to receive a 32-bit word of data. +//! This function uses SPI_pollingFIFOTransaction function. +//! SPI character length must be configured to 8 bits BEFORE calling the +//! function +//! +//! \return the received 32-bit word. +// +//***************************************************************************** +extern uint32_t +SPI_receive32Bits(uint32_t base, SPI_endianess endianness, uint16_t dummyData, + uint16_t txDelay); + + + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param data specified the data to be transmitted +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return . +// +//***************************************************************************** +extern uint16_t +SPI_pollingNonFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t data); + +//***************************************************************************** +// +//! This function is used to initiate SPI transaction of specified character +//! length and 'N' words of transaction +//! +//! \param base specifies the SPI module base address. +//! \param charLength specifies the SPI character length of SPI transaction +//! \param pTxBuffer specifies the pointer to transmit buffer +//! \param pRxBuffer specifies the pointer to receive buffer +//! \param numOfWords specified the number of data to be transmitted / received +//! +//! The SPI must be configured to the provided charLength BEFORE the function +//! is called. This function does not set/change the SPI char length. +//! +//! \return none +// +//***************************************************************************** +extern void +SPI_pollingFIFOTransaction(uint32_t base, uint16_t charLength, + uint16_t *pTxBuffer, uint16_t *pRxBuffer, + uint16_t numOfWords, uint16_t txDelay); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SPI_H diff --git a/gpio_driverlib_cpu1/device/driverlib/sysctl.c b/gpio_driverlib_cpu1/device/driverlib/sysctl.c new file mode 100644 index 0000000..f4708f2 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sysctl.c @@ -0,0 +1,1469 @@ +//########################################################################### +// +// FILE: sysctl.c +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "cputimer.h" +#include "sysctl.h" + +// +// Define to isolate inline assembly +// +#define SYSCTL_DELAY __asm(" .if __TI_EABI__\n" \ + " .asg SysCtl_delay , _SysCtl_delay\n" \ + " .endif\n" \ + " .def _SysCtl_delay\n" \ + " .sect \".TI.ramfunc\"\n" \ + " .global _SysCtl_delay\n" \ + "_SysCtl_delay:\n" \ + " SUB ACC,#1\n" \ + " BF _SysCtl_delay, GEQ\n" \ + " LRETR\n") +#define SYSCTL_CLRC_DBGM __asm(" CLRC DBGM") + +// +// Define Timer1 and Timer2 seed values +// +#define TMR1SYSCLKCTR 0xF0000000U +#define TMR2INPCLKCTR 0x800U + +#define XTAL_CPUTIMER_PERIOD 1023U + +//***************************************************************************** +// +// SysCtl_delay() +// +//***************************************************************************** +SYSCTL_DELAY; + + +static void +SysCtl_pollCpuTimer(void) +{ + // + // Delay for 1 ms while the XTAL powers up + // + // 2000 loops, 5 cycles per loop + 9 cycles overhead = 10009 cycles + // + SysCtl_delay(2000); + + // + // Wait for cpu timer 2 to overflow + // + while(CPUTimer_getTimerOverflowStatus(CPUTIMER2_BASE) == false); + { + // + // If your application is stuck in this loop, please check if the + // input clock source is valid. + // + } + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); +} + +//***************************************************************************** +// +// SysCtl_getClock() +// +//***************************************************************************** +uint32_t +SysCtl_getClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + // + // Don't proceed if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning the INTOSC1 rate. You need + // to handle the MCD and clear the failure. + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (uint32_t)SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + if((oscSource == (SYSCTL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) || + (oscSource == (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S))) + { + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) & + (SYSCTL_SYSPLLCTL1_PLLEN | SYSCTL_SYSPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_FMULT_M) >> + SYSCTL_SYSPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier and fixed divide by 2 + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) & + SYSCTL_SYSPLLMULT_IMULT_M) >> + SYSCTL_SYSPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + if((HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)); + } + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getAuxClock() +// +//***************************************************************************** +uint32_t SysCtl_getAuxClock(uint32_t clockInHz) +{ + uint32_t temp; + uint32_t oscSource; + uint32_t clockOut; + + oscSource = HWREG(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + (uint32_t)SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M; + + // + // If one of the internal oscillators is being used, start from the + // known default frequency. Otherwise, use clockInHz parameter. + // + if(oscSource == (SYSCTL_AUXPLL_OSCSRC_OSC2 >> SYSCTL_OSCSRC_S)) + { + // + // 10MHz Internal Clock + // + clockOut = SYSCTL_DEFAULT_OSC_FREQ; + } + else + { + clockOut = clockInHz; + } + + // + // If the PLL is enabled calculate its effect on the clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) & + (SYSCTL_AUXPLLCTL1_PLLEN | SYSCTL_AUXPLLCTL1_PLLCLKEN)) == 3U) + { + // + // Calculate portion from fractional multiplier + // + temp = (clockInHz * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M) >> + SYSCTL_AUXPLLMULT_FMULT_S)) / 4U; + + // + // Calculate integer multiplier + // + clockOut = clockOut * ((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_IMULT_M) >> + SYSCTL_AUXPLLMULT_IMULT_S); + + // + // Add in fractional portion + // + clockOut += temp; + } + + clockOut /= (1U << (HWREG(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)); + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_setClock() +// +//***************************************************************************** +bool +SysCtl_setClock(uint32_t config) +{ + uint16_t divSel; + uint16_t iMult = 0U, fMult = 0U, pllMult = 0U, div; + bool status, sysclkInvalidFreq = true; + uint16_t i, tempSCSR, tempWDCR, tempWDWCR, intStatus; + uint16_t t1TCR, t1TPR, t1TPRH, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t1PRD, t2PRD, ctr1; + float32_t sysclkToInClkError, mult; + + // + // Check the arguments. + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Don't proceed to the PLL initialization if an MCD failure is detected. + // + if(SysCtl_isMCDClockFailureDetected()) + { + // + // OSCCLKSRC2 failure detected. Returning false. You'll need to clear + // the MCD error. + // + status = false; + } + else + { + // + // Configure oscillator source + // + SysCtl_selectOscSource(config & SYSCTL_OSCSRC_M); + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure PLL if enabled + // + EALLOW; + if((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) + { + if((HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) & + SYSCTL_SYSDBGCTL_BIT_0) != 0U) + { + // + // The user can optionally insert handler code here. This will + // only be executed if a watchdog reset occurred after a failed + // system PLL initialization. See your device user's guide for + // more information. + // + // If the application has a watchdog reset handler, this bit + // should be checked to determine if the watchdog reset + // occurred because of the PLL. + // + // No action here will continue with retrying the PLL as + // normal. + // + } + + // + // Set dividers to /1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = 0U; + + // + // Get the PLL multiplier settings from config + // + iMult |= (uint16_t)(config & SYSCTL_IMULT_M); + fMult |= (uint16_t)((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S); + pllMult |= (iMult << SYSCTL_SYSPLLMULT_IMULT_S) | + (fMult << SYSCTL_SYSPLLMULT_FMULT_S); + + // + // Lock the PLL five times. This helps ensure a successful start. + // Five is the minimum recommended number. The user can increase + // this number according to allotted system initialization time. + // + for(i = 0U; i < 5U; i++) + { + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + asm(" RPT #60 || NOP"); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) = pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + } + } + + // + // Configure Dividers. Set divider to produce slower output frequency + // to limit current increase. + // + divSel = (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + + if(divSel != (126U / 2U)) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | (divSel + 1U); + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(uint16_t)SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + } + + // + // *CAUTION* + // It is recommended to use the following watchdog code to monitor the + // PLLstartup sequence. If your application has already cleared the + // watchdog SCRS[WDOVERRIDE] bit this cannot be done. It is recommended + // not to clear this bit until after the PLL has been initiated. + // + + // + // Backup User Watchdog + // + tempSCSR = HWREGH(WD_BASE + SYSCTL_O_SCSR); + tempWDCR = HWREGH(WD_BASE + SYSCTL_O_WDCR); + tempWDWCR = HWREGH(WD_BASE + SYSCTL_O_WDWCR); + + // + // Disable windowed functionality, reset counter + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = 0x0U; + SysCtl_serviceWatchdog(); + + // + // Disable global interrupts + // + intStatus = __disable_interrupts(); + + // + // Configure for watchdog reset and to run at max frequency + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = 0x0U; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + + // + // This bit is reset only by power-on-reset (POR) and will not be + // cleared by a WD reset + // + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) |= SYSCTL_SYSDBGCTL_BIT_0; + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_SYSPLLCTL1) |= SYSCTL_SYSPLLCTL1_PLLCLKEN; + + EDIS; + + // + // Delay to ensure system is clocking from PLL prior to clearing + // status bit + // + SysCtl_delay(3U); + + // + // Slip Bit Monitor and SYSCLK Frequency Check using timers + // Re-lock routine for SLIP condition or if SYSCLK and CLKSRC timer + // counts are off by +/- 10%. At a minimum, SYSCLK check is performed. + // Re-lock attempt is carried out if SLIPS bit is set. + // This while loop is monitored by watchdog. + // In the event that the PLL does not successfully lock, the loop will + // be aborted by watchdog reset. + // + while(((config & SYSCTL_PLL_ENABLE) == SYSCTL_PLL_ENABLE) && + (sysclkInvalidFreq == true)) + { + EALLOW; + + // + // Perform PLL re-lock only if SLIPS bit is set, otherwise monitor + // SYSCLK frequency with timers + // + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_SLIPS) == 1U) + { + // + // Bypass PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~SYSCTL_SYSPLLCTL1_PLLEN; + + SysCtl_delay(12U); + + // + // Write multiplier, which automatically turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLMULT) |= pllMult; + + // + // Wait for the SYSPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLSTS) & + SYSCTL_SYSPLLSTS_LOCKS) == 0U) + { + ; + } + + // + // Enable PLLSYSCLK is fed from system PLL clock + // + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) |= + SYSCTL_SYSPLLCTL1_PLLCLKEN; + + // + // Delay to ensure system is clocking from PLL prior to + // clearing status bit + // + SysCtl_delay(12U); + } + + // + // Backup timer1 and timer2 settings + // + t1TCR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR); + t1PRD = HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD); + t1TPR = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR); + t1TPRH = HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH); + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Set up timers 1 and 2 + // Configure timer1 to count SYSCLK cycles + // + + // + // Stop timer 1 + // Seed timer1 counter + // Set sysclock divider + // Reload timer with value in PRD + // Clear interrupt flag + // Enable interrupt + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR1SYSCLKCTR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + + // + // Configure timer2 to count Input clock cycles + // + switch (config & SYSCTL_OSCSRC_M) + { + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INT_OSC1 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 1U; + break; + + case SYSCTL_OSCSRC_OSC2: + // + // Clk Src = INT_OSC2 + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 2U; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Clk Src = XTAL + // + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M) | 3U; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + + // + // Clear interrupt flag + // Enable interrupt + // Stop timer 2 + // Seed timer2 counter + // Set sysclock divider + // Reload timer with value in PRD + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIE; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = (uint32_t)TMR2INPCLKCTR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Stop/Start timer counters + // + + // + // Stop timer 1 + // Stop timer 2 + // Reload timer1 with value in PRD + // Reload timer2 with value in PRD + // Clear timer2 interrupt flag + // Start timer2 + // Start timer1 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Wait for Timers - Stop if either timer overflows + // + while(((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U) && + ((HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) == 0U)) + { + ; + } + + // + // Stop timer 1 and 2 + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + // + // Calculate elapsed counts on timer1 + // + ctr1 = (uint32_t)TMR1SYSCLKCTR - HWREG(CPUTIMER1_BASE + + CPUTIMER_O_TIM); + + // + // Restore timer settings + // + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TCR) = t1TCR; + HWREG(CPUTIMER1_BASE + CPUTIMER_O_PRD) = t1PRD; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPR) = t1TPR; + HWREGH(CPUTIMER1_BASE + CPUTIMER_O_TPRH) = t1TPRH; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Calculate Clock Error: + // Error = (mult/div) - (timer1 count/timer2 count) + // + mult = (float32_t)iMult + ((float32_t)fMult / 4.0F); + + if((HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & 0x3FU) == 0U) + { + div = 1U; + } + else + { + div = (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + 0x3FU) << 1; + } + + sysclkToInClkError = (mult / (float32_t)div) - + ((float32_t)ctr1 / (float32_t)TMR2INPCLKCTR); + + // + // sysclkInvalidFreq will be set to true if sysclkToInClkError is + // off by 10% + // + sysclkInvalidFreq = ((sysclkToInClkError > 0.10F) || + (sysclkToInClkError < -0.10F)); + + EDIS; + } + + // + // Clear bit + // + EALLOW; + HWREGH(DEVCFG_BASE + SYSCTL_O_SYSDBGCTL) &= ~SYSCTL_SYSDBGCTL_BIT_0; + EDIS; + + // + // Restore user watchdog, first resetting counter + // + SysCtl_serviceWatchdog(); + + // + // Set the KEY bits and make sure not to set the WDOVERRIDE bit + // + EALLOW; + HWREGH(WD_BASE + SYSCTL_O_WDCR) = tempWDCR | SYSCTL_WD_CHKBITS; + HWREGH(WD_BASE + SYSCTL_O_WDWCR) = tempWDWCR; + HWREGH(WD_BASE + SYSCTL_O_SCSR) = tempSCSR & ~SYSCTL_SCSR_WDOVERRIDE; + EDIS; + + // + // Restore state of ST1[INTM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x1U) == 0U) + { + EINT; + } + + // + // Restore state of ST1[DBGM]. This was set by the + // __disable_interrupts() intrinsic previously. + // + if((intStatus & 0x2U) == 0U) + { + SYSCTL_CLRC_DBGM; + } + + // + // ~200 PLLSYSCLK delay to allow voltage regulator to stabilize prior + // to increasing entire system clock frequency. + // + SysCtl_delay(40U); + + // + // Set the divider to user value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M) | divSel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + status = true; + } + + return(status); +} +//***************************************************************************** +// +// SysCtl_setAuxClock() +// +//***************************************************************************** +void SysCtl_setAuxClock(uint32_t config) +{ + uint16_t pllMult = 0U; + uint16_t counter = 0U, started = 0U, attempts = 0U; + uint16_t mult; + uint16_t i, t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Check the arguments + // + ASSERT((config & SYSCTL_OSCSRC_M) != SYSCTL_OSCSRC_M); // 3 is not valid + + // + // Bypass PLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + EDIS; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Configure oscillator source + // + SysCtl_selectOscSourceAuxPLL(config & SYSCTL_OSCSRC_M); + + // + // Get the PLL multiplier settings from config + // + pllMult |= (uint16_t)((config & SYSCTL_IMULT_M) << + SYSCTL_AUXPLLMULT_IMULT_S); + pllMult |= (uint16_t)(((config & SYSCTL_FMULT_M) >> SYSCTL_FMULT_S) << + SYSCTL_AUXPLLMULT_FMULT_S); + + // + // Get the PLL multipliers currently programmed + // + mult = (uint16_t)((HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_M) >> + (uint32_t)SYSCTL_AUXPLLMULT_IMULT_S); + mult |= (uint16_t)(HWREG(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) & + SYSCTL_AUXPLLMULT_FMULT_M); + + // + // Lock PLL only if the multipliers need update + // + if(mult != pllMult) + { + + // + // Configure PLL if enabled + // + if((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE) + { + // + // Backup Timer 2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Configure Timer 2 for AUXPLL as source in known configuration + // - Clock source to AUXPLL + // - Clock divider to divide by 1 + // - Small period to detect overflow + // - Interrupt disabled + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = 6U; + + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = 10U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = 0U; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TIE; + + // + // Set AUX Divide by 8 to ensure that AUXPLLCLK <= SYSCLK / 2 + // while using Timer 2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = 0x3U; + SYSCTL_REGWRITE_DELAY; + EDIS; + + // + // Lock the PLL up to five times. + //CPU Timer 2 will monitor a successful + // lock and break out of the loop earlier if detected. + // + while((counter < 5U) && (started == 0U)) + { + EALLOW; + + // + // Turn off AUXPLL and delay for it to power down. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= + ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically + // turns on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + SYSCTL_REGWRITE_DELAY; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLEN; + EDIS; + + // + // Wait for the AUXPLL lock counter + // + + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= + SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + + // + // CPU Timer 2 will now be setup to be clocked from AUXPLLCLK. + // This is used to test that the PLL has successfully started. + // + // Reload and start the timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) &= ~CPUTIMER_TCR_TSS; + + // + // Check to see timer is counting properly + // + for(i = 0U; i < 1000U; i++) + { + // + // Check overflow flag + // + if((HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) & + CPUTIMER_TCR_TIF) != 0U) + { + // + // Clear overflow flag + // + HWREGH(CPUTIMER2_BASE + + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TIF; + + // + // Set flag to indicate PLL started and break out of + // for-loop + // + started = 1U; + break; + } + } + + // + // Stop timer + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TSS; + counter++; + EDIS; + } + + if(started == 0U) + { + // + // AUX PLL may not have started. Reset multiplier to 0 (bypass + // PLL). + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) = 0U; + EDIS; + + // + // The user should put some handler code here based on how + // this condition should be handled in their application. + // + ESTOP0; + } + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + + // + // Reload period value + // + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + EDIS; + } + } + else + { + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + SysCtl_delay(3U); + EDIS; + } + + // + // Slip Bit Monitor + // Re-lock routine for SLIP condition + // + while(((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_SLIPS) != 0U) && (attempts < 10U) && + ((config & SYSCTL_AUXPLL_ENABLE) == SYSCTL_AUXPLL_ENABLE)) + { + EALLOW; + + // + // Bypass AUXPLL + // + HWREGH(CLKCFG_BASE + + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLCLKEN; + + // + // Delay of at least 120 OSCCLK cycles required post PLL bypass + // + SysCtl_delay(23U); + + // + // Turn off AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) &= ~SYSCTL_AUXPLLCTL1_PLLEN; + SysCtl_delay(3U); + + // + // Set integer and fractional multiplier, which automatically turns + // on the PLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLMULT) |= pllMult; + + // + // Enable AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLEN; + + // + // Wait for the AUXPLL lock counter + // + while((HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLSTS) & + SYSCTL_AUXPLLSTS_LOCKS) != 1U) + { + // + // Consider to servicing the watchdog using + // SysCtl_serviceWatchdog() + // + } + + // + // Enable AUXPLLCLK to be fed from AUXPLL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) |= SYSCTL_AUXPLLCTL1_PLLCLKEN; + + SysCtl_delay(3U); + + attempts++; + + EDIS; + } + + // + // Set divider to desired value + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (uint16_t)(config & SYSCTL_SYSDIV_M) >> SYSCTL_SYSDIV_S; + SYSCTL_REGWRITE_DELAY; + EDIS; + +} + + +//***************************************************************************** +// +// SysCtl_selectXTAL() +// +//***************************************************************************** +void +SysCtl_selectXTAL(void) +{ + uint16_t t2TCR, t2TPR, t2TPRH, t2CLKCTL; + uint32_t t2PRD; + + // + // Backup CPU timer2 settings + // + t2CLKCTL = HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL); + t2TCR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR); + t2PRD = HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD); + t2TPR = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR); + t2TPRH = HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH); + + // + // Backup AUX clock settings + // + uint16_t clksrcctl2 = HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2); + uint16_t auxpllctl1 = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1); + uint16_t auxclkdivsel = HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL); + + // + // Set AUX clock source to XTAL, bypass mode. + // AUXCLK is used as the CPUTimer Clock source. SYSCLK frequency must be + // atleast twice the frequency of AUXCLK. SYSCLK = INTOSC2(10MHz) + // Set the AUX divider to 8. The above condition will be met for XTAL + // frequencies up to 40MHz + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = 0x0U; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = SYSCTL_AUXPLLCLK_DIV_8; + SYSCTL_REGWRITE_DELAY; + + + // + // Disable cpu timer 2 interrupt + // + CPUTimer_disableInterrupt(CPUTIMER2_BASE); + + // + // Stop cpu timer 2 if running + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Initialize cpu timer 2 period + // + CPUTimer_setPeriod(CPUTIMER2_BASE, XTAL_CPUTIMER_PERIOD); + + // + // Set cpu timer 2 clock source to XTAL + // + CPUTimer_selectClockSource(CPUTIMER2_BASE, CPUTIMER_CLOCK_SOURCE_AUX, + CPUTIMER_CLOCK_PRESCALER_1); + + // + // Clear cpu timer 2 overflow flag + // + CPUTimer_clearOverflowFlag(CPUTIMER2_BASE); + + // + // Start cpu timer 2 + // + CPUTimer_startTimer(CPUTIMER2_BASE); + + EALLOW; + // + // Turn on XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_XTALOFF; + EDIS; + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + + // + // If a missing clock failure was detected, try waiting for the cpu timer 2 + // to overflow again. + // + while(SysCtl_isMCDClockFailureDetected()) + { + // + // Clear the MCD failure + // + SysCtl_resetMCD(); + + // + // Wait for the X1 clock to overflow cpu timer 2 + // + SysCtl_pollCpuTimer(); + + // + // Select XTAL as the oscillator source + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + ((HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + (~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M)) | + (SYSCTL_OSCSRC_XTAL >> SYSCTL_OSCSRC_S)); + EDIS; + } + + // + // Stop cpu timer 2 + // + CPUTimer_stopTimer(CPUTIMER2_BASE); + + // + // Restore Timer 2 configuration + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = t2CLKCTL; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) = t2TCR; + HWREG(CPUTIMER2_BASE + CPUTIMER_O_PRD) = t2PRD; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPR) = t2TPR; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TPRH) = t2TPRH; + HWREGH(CPUTIMER2_BASE + CPUTIMER_O_TCR) |= CPUTIMER_TCR_TRB; + + // + // Restore AUX clock settings + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = clksrcctl2; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXPLLCTL1) = auxpllctl1; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = auxclkdivsel; + SYSCTL_REGWRITE_DELAY; + EDIS; + + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSource() +// +//***************************************************************************** +void +SysCtl_selectOscSource(uint32_t oscSource) +{ + ASSERT((oscSource == SYSCTL_OSCSRC_OSC1) || + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL)); + + // + // Select the specified source. + // + EALLOW; + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M; + + SYSCTL_CLKSRCCTL_DELAY; + + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Select XTAL in crystal mode and wait for it to power up + // + SysCtl_selectXTAL(); + break; + + case SYSCTL_OSCSRC_OSC1: + // + // Clk Src = INTOSC1 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) & + ~SYSCTL_CLKSRCCTL1_OSCCLKSRCSEL_M) | + (SYSCTL_OSCSRC_OSC1 >> SYSCTL_OSCSRC_S); + + SYSCTL_CLKSRCCTL_DELAY; + + // + //Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_selectOscSourceAuxPLL() +// +//***************************************************************************** +void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource) +{ + bool status = false; + + EALLOW; + + switch(oscSource) + { + case SYSCTL_AUXPLL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_INTOSC2OFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) &= + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M); + break; + + case SYSCTL_AUXPLL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~(SYSCTL_CLKSRCCTL1_XTALOFF); + SYSCTL_CLKSRCCTL_DELAY; + + // + // Clk Src = XTAL + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (1U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + break; + + case SYSCTL_AUXPLL_OSCSRC_AUXCLKIN: + // + // Clk Src = AUXCLKIN + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL2) & + ~(SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_M)) | + (2U << SYSCTL_CLKSRCCTL2_AUXOSCCLKSRCSEL_S); + SYSCTL_CLKSRCCTL_DELAY; + break; + + default: + // + // Do nothing. Not a valid clock source value. + // + break; + } + EDIS; +} + +//***************************************************************************** +// +// SysCtl_getLowSpeedClock() +// +//***************************************************************************** +uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz) +{ + uint32_t clockOut; + + // + // Get the main system clock + // + clockOut = SysCtl_getClock(clockInHz); + + // + // Apply the divider to the main clock + // + if((HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M) != 0U) + { + clockOut /= (2U * (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + SYSCTL_LOSPCP_LSPCLKDIV_M)); + } + + return(clockOut); +} + +//***************************************************************************** +// +// SysCtl_getDeviceParametric() +// +//***************************************************************************** +uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric) +{ + uint32_t value; + + // + // Get requested parametric value + // + switch(parametric) + { + case SYSCTL_DEVICE_QUAL: + // + // Qualification Status + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_QUAL_M) >> SYSCTL_PARTIDL_QUAL_S); + break; + + case SYSCTL_DEVICE_PINCOUNT: + // + // Pin Count + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PIN_COUNT_M) >> + SYSCTL_PARTIDL_PIN_COUNT_S); + break; + + case SYSCTL_DEVICE_INSTASPIN: + // + // InstaSPIN Feature Set + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_INSTASPIN_M) >> + SYSCTL_PARTIDL_INSTASPIN_S); + break; + + case SYSCTL_DEVICE_FLASH: + // + // Flash Size (KB) + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_FLASH_SIZE_M) >> + SYSCTL_PARTIDL_FLASH_SIZE_S); + break; + + case SYSCTL_DEVICE_PARTID: + // + // PARTID Format Revision + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDL) & + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_M) >> + SYSCTL_PARTIDL_PARTID_FORMAT_REVISION_S); + break; + + case SYSCTL_DEVICE_FAMILY: + // + // Device Family + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_FAMILY_M) >> SYSCTL_PARTIDH_FAMILY_S); + break; + + case SYSCTL_DEVICE_PARTNO: + // + // Part Number + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_PARTNO_M) >> SYSCTL_PARTIDH_PARTNO_S); + break; + + case SYSCTL_DEVICE_CLASSID: + // + // Class ID + // + value = ((HWREG(DEVCFG_BASE + SYSCTL_O_PARTIDH) & + SYSCTL_PARTIDH_DEVICE_CLASS_ID_M) >> + SYSCTL_PARTIDH_DEVICE_CLASS_ID_S); + break; + + default: + // + // Not a valid value for PARTID register + // + value = 0U; + break; + } + + return((uint16_t)value); +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/sysctl.h b/gpio_driverlib_cpu1/device/driverlib/sysctl.h new file mode 100644 index 0000000..8b263eb --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/sysctl.h @@ -0,0 +1,3531 @@ +//########################################################################### +// +// FILE: sysctl.h +// +// TITLE: C28x system control driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef SYSCTL_H +#define SYSCTL_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup sysctl_api SysCtl +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_memmap.h" +#include "inc/hw_nmi.h" +#include "inc/hw_sysctl.h" +#include "inc/hw_otp.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" +#include "interrupt.h" + + +// +// Macro used for adding delay between 2 consecutive writes to CLKSRCCTL1 +// register. +// Delay = 300 NOPs +// +#define SYSCTL_CLKSRCCTL_DELAY asm(" RPT #250 || NOP \n RPT #50 || NOP") + +// +// Macro used for adding delay between 2 consecutive writes to memory mapped +// register in System control +// Total delay = 3 * (DEVICE_SYSCLK_FREQ / INTOSC1 Freq) + 9 +// +#define SYSCTL_REGWRITE_DELAY asm(" RPT #69 || NOP") + +//***************************************************************************** +// +// Defines for system control functions. Not intended for use by application +// code. +// +//***************************************************************************** + +// +// Shifted pattern for WDCR register's WDCHK field. +// +#define SYSCTL_WD_CHKBITS 0x0028U + +// +// Keys for WDKEY field. The first enables resets and the second resets. +// +#define SYSCTL_WD_ENRSTKEY 0x0055U +#define SYSCTL_WD_RSTKEY 0x00AAU + +// +// Values to help decode peripheral parameter +// +#define SYSCTL_PERIPH_REG_M 0x001FU +#define SYSCTL_PERIPH_REG_S 0x0000U +#define SYSCTL_PERIPH_BIT_M 0x1F00U +#define SYSCTL_PERIPH_BIT_S 0x0008U + +// +//Keys for the System control registers write protection +// +#define SYSCTL_REG_KEY 0xA5A50000U +#define SYSCTL_PLL_KEY 0XCAFE0000U + +// +//Values to help access shifting of bits +// +#define SYSCTL_TYPE_LOCK_S 0xFU + + +// +// LPM defines for LPMCR.LPM +// +#define SYSCTL_LPM_IDLE 0x0000U +#define SYSCTL_LPM_STANDBY 0x0001U +#define SYSCTL_LPM_HALT 0x0002U +#define SYSCTL_LPM_HIB 0x0003U + +// +// Bit shift for DAC to configure the CPUSEL register +// +#define SYSCTL_CPUSEL_DAC_S 0x10U + +// +// Default internal oscillator frequency, 10 MHz +// +#define SYSCTL_DEFAULT_OSC_FREQ 10000000U + +// +// Mask for SYNCSELECT.SYNCIN +// +#define SYSCTL_SYNCSELECT_SYNCIN_M SYSCTL_SYNCSELECT_EPWM4SYNCIN_M + +// +// Boot ROM Booting and Reset Status +// +#if defined(CPU2) +#define SYSCTL_BOOT_ROM_STATUS 0x0002U +#else +#define SYSCTL_BOOT_ROM_STATUS 0x002CU +#endif +#define SYSCTL_BOOT_ROM_POR 0x8000U +#define SYSCTL_BOOT_ROM_XRS 0x4000U + +#define SYSCTL_DEVICECAL_CONTEXT_SAVE asm(" PUSH ACC \n\ + PUSH DP \n\ + PUSH XAR0 \n\ + PUSH XAR2 \n\ + PUSH XAR3 \n\ + PUSH XAR4 \n\ + PUSH XAR5 \n\ + ") + +#define SYSCTL_DEVICECAL_CONTEXT_RESTORE asm(" POP XAR5 \n\ + POP XAR4 \n\ + POP XAR3 \n\ + POP XAR2 \n\ + POP XAR0 \n\ + POP DP \n\ + POP ACC \n\ + ") + +// +// Device_cal function which is available in OTP memory +// This function is called in SysCtl_resetPeripheral after resetting +// analog peripherals +// +#define Device_cal ((void (*)(void))((uintptr_t)0x070282)) + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setClock() API as +// the config parameter. +// +//***************************************************************************** +// +// System clock divider (SYSDIV) +// + + + +#define SYSCTL_SYSDIV_M 0x00001F80UL // Mask for SYSDIV value in config +#define SYSCTL_SYSDIV_S 7U // Shift for SYSDIV value in config + +//! Macro to format system clock divider value. x must be 1 or even values up +//! to 126. +#define SYSCTL_SYSDIV(x) ((((x) / 2U) << SYSCTL_SYSDIV_S) & SYSCTL_SYSDIV_M) + +// +// Integer multiplier (IMULT) +// +#define SYSCTL_IMULT_M 0x0000007FUL // Mask for IMULT value in config +#define SYSCTL_IMULT_S 0U // Shift for IMULT value in config +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_IMULT(x) (((x) << SYSCTL_IMULT_S) & SYSCTL_IMULT_M) + +#ifndef DOXYGEN_PDF_IGNORE +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_FMULT_M 0x00006000UL // Mask for FMULT value in config +#define SYSCTL_FMULT_S 13U // Shift for FMULT value in config +#define SYSCTL_FMULT_NONE 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_0 0x00000000UL //!< No fractional multiplier +#define SYSCTL_FMULT_1_4 0x00002000UL //!< Fractional multiplier of 0.25 +#define SYSCTL_FMULT_1_2 0x00004000UL //!< Fractional multiplier of 0.50 +#define SYSCTL_FMULT_3_4 0x00006000UL //!< Fractional multiplier of 0.75 + +// +// Oscillator source +// +// Also used with the SysCtl_selectOscSource(), SysCtl_turnOnOsc(), +// and SysCtl_turnOffOsc() functions as the oscSource parameter. +// +#define SYSCTL_OSCSRC_M 0x00030000UL // Mask for OSCSRC value in config +#define SYSCTL_OSCSRC_S 16U // Shift for OSCSRC value in config +//! Internal oscillator INTOSC2 +#define SYSCTL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) in crystal mode +#define SYSCTL_OSCSRC_XTAL 0x00010000U +//! Internal oscillator INTOSC1 +#define SYSCTL_OSCSRC_OSC1 0x00020000UL + +// +// Enable/disable PLL +// +#define SYSCTL_PLL_ENABLE 0x80000000U //!< Enable PLL +#define SYSCTL_PLL_DISABLE 0x00000000U //!< Disable PLL + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_setAuxClock() API +// as the config parameter. +// +//***************************************************************************** +// +// Auxiliary clock divider (AUXCLKDIV) +// +#define SYSCTL_AUXPLL_DIV_1 0x00000000UL //!< Auxiliary PLL divide by 1 +#define SYSCTL_AUXPLL_DIV_2 0x00000080UL //!< Auxiliary PLL divide by 2 +#define SYSCTL_AUXPLL_DIV_4 0x00000100UL //!< Auxiliary PLL divide by 4 +#define SYSCTL_AUXPLL_DIV_8 0x00000180UL //!< Auxiliary PLL divide by 8 + +// +// Integer multiplier (IMULT) +// +//! Macro to format integer multiplier value. x is a number from 1 to 127. +//! +#define SYSCTL_AUXPLL_IMULT(x) SYSCTL_IMULT((x)) + +// +// Fractional multiplier (FMULT) +// +#define SYSCTL_AUXPLL_FMULT_NONE 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_0 0x00000000U //!< No fractional multiplier +#define SYSCTL_AUXPLL_FMULT_1_4 0x00002000UL //!< Fractional multiplier - 0.25 +#define SYSCTL_AUXPLL_FMULT_1_2 0x00004000UL //!< Fractional multiplier - 0.50 +#define SYSCTL_AUXPLL_FMULT_3_4 0x00006000UL //!< Fractional multiplier - 0.75 + +// +// Oscillator source +// +//! Internal oscillator INTOSC2 as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_OSC2 0x00000000UL +//! External oscillator (XTAL) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_XTAL 0x00010000UL +//! AUXCLKIN (from GPIO) as auxiliary clock input +#define SYSCTL_AUXPLL_OSCSRC_AUXCLKIN 0x00020000U + +// +// Enable/disable PLL +// +#define SYSCTL_AUXPLL_ENABLE 0x80000000U //!< Enable AUXPLL +#define SYSCTL_AUXPLL_DISABLE 0x00000000U //!< Disable AUXPLL + +//***************************************************************************** +// +// Values that can be passed to SysCtl_selectSecController() as the +// periFrame1Config and periFrame2Config parameters. +// +//***************************************************************************** +//! Configure CLA as the secondary controller +#define SYSCTL_SEC_CONTROLLER_CLA 0x0U +//! Configure DMA a secondary controller +#define SYSCTL_SEC_CONTROLLER_DMA 0x1U + +//***************************************************************************** +// +// Values that can be passed to SysCtl_clearNMIStatus(), +// SysCtl_forceNMIFlags(), SysCtl_isNMIFlagSet(), and +// SysCtl_isNMIShadowFlagSet() as the nmiFlags parameter and returned by +// SysCtl_getNMIFlagStatus() and SysCtl_getNMIShadowFlagStatus(). +// +//***************************************************************************** +#define SYSCTL_NMI_NMIINT 0x1U //!< NMI Interrupt Flag +#define SYSCTL_NMI_CLOCKFAIL 0x2U //!< Clock Fail Interrupt Flag +#define SYSCTL_NMI_RAMUNCERR 0x4U //!< RAM Uncorrectable Error NMI Flag +#define SYSCTL_NMI_FLUNCERR 0x8U //!< Flash Uncorrectable Error NMI Flag +#define SYSCTL_NMI_CPU1HWBISTERR 0x10U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_CPU2HWBISTERR 0x20U //!< HW BIST Error NMI Flag +#define SYSCTL_NMI_PIEVECTERR 0x40U //!< PIE Vector Fetch Error Flag +#define SYSCTL_NMI_CLBNMI 0x100U //!< Configurable Logic Block NMI Flag +#define SYSCTL_NMI_CPU2WDRSN 0x200U //!< CPU2 WDRSn Reset Indication Flag +#define SYSCTL_NMI_CPU2NMIWDRSN 0x400U //!< CPU2 NMIWDRSn Reset Indication Flag + +//***************************************************************************** +// +// The following are values that can be passed to the SysCtl_clearResetCause() +// API as rstCauses or returned by the SysCtl_getResetCause() API. +// +//***************************************************************************** +#define SYSCTL_CAUSE_POR 0x00000001U //!< Power-on reset +#define SYSCTL_CAUSE_XRS 0x00000002U //!< External reset pin +#define SYSCTL_CAUSE_WDRS 0x00000004U //!< Watchdog reset +#define SYSCTL_CAUSE_NMIWDRS 0x00000008U //!< NMI watchdog reset +#define SYSCTL_CAUSE_SCCRESET 0x00000100U //!< SCCRESETn by DCSM +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_enablePeripheral() +//! and SysCtl_disablePeripheral() as the \e peripheral parameter. +//! The EPWM Clock enable bit is also used to enable clocking for CLB. +//! The EPWM and CLB clock enable bits are mapped to same value, +// +//***************************************************************************** +#define SYSCTL_PERIPH_CLK_CLB1 SYSCTL_PERIPH_CLK_EPWM1 //!< CLB1 clock +#define SYSCTL_PERIPH_CLK_CLB2 SYSCTL_PERIPH_CLK_EPWM2 //!< CLB2 clock +#define SYSCTL_PERIPH_CLK_CLB3 SYSCTL_PERIPH_CLK_EPWM3 //!< CLB3 clock +#define SYSCTL_PERIPH_CLK_CLB4 SYSCTL_PERIPH_CLK_EPWM4 //!< CLB4 clock +//***************************************************************************** +// +// The following values define the adcsocSrc parameter for +// SysCtl_enableExtADCSOCSource() and SysCtl_disableExtADCSOCSource(). +// +//***************************************************************************** +#define SYSCTL_ADCSOC_SRC_PWM1SOCA 0x1U //! EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM4SYNCOUT, //!< EPWM4SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM7SYNCOUT, //!< EPWM7SYNCOUT --> EXTSYNCOUT + SYSCTL_SYNC_OUT_SRC_EPWM10SYNCOUT //!< EPWM10SYNCOUT --> EXTSYNCOUT + +} SysCtl_SyncOutputSource; + +//***************************************************************************** +// +//! The following values define the \e parametric parameter for +//! SysCtl_getDeviceParametric(). +// +//***************************************************************************** +typedef enum +{ + SYSCTL_DEVICE_QUAL, //!< Device Qualification Status + SYSCTL_DEVICE_PINCOUNT, //!< Device Pin Count + SYSCTL_DEVICE_INSTASPIN, //!< Device InstaSPIN Feature Set + SYSCTL_DEVICE_FLASH, //!< Device Flash size (KB) + SYSCTL_DEVICE_PARTID, //!< Device Part ID Format Revision + SYSCTL_DEVICE_FAMILY, //!< Device Family + SYSCTL_DEVICE_PARTNO, //!< Device Part Number + SYSCTL_DEVICE_CLASSID //!< Device Class ID +} SysCtl_DeviceParametric; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setXClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_XCLKOUT_DIV_1 = 0, //!< XCLKOUT = XCLKOUT / 1 + SYSCTL_XCLKOUT_DIV_2 = 1, //!< XCLKOUT = XCLKOUT / 2 + SYSCTL_XCLKOUT_DIV_4 = 2, //!< XCLKOUT = XCLKOUT / 4 + SYSCTL_XCLKOUT_DIV_8 = 3 //!< XCLKOUT = XCLKOUT / 8 + +}SysCtl_XClkDivider; + + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setAuxPLLClk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_AUXPLLCLK_DIV_1, //!< AUXPLL clock = AUXPLL clock / 1 + SYSCTL_AUXPLLCLK_DIV_2, //!< AUXPLL clock = AUXPLL clock / 2 + SYSCTL_AUXPLLCLK_DIV_4, //!< AUXPLL clock = AUXPLL clock / 4 + SYSCTL_AUXPLLCLK_DIV_8, //!< AUXPLL clock = AUXPLL clock / 8 + SYSCTL_AUXPLLCLK_DIV_3, //!< AUXPLL clock = AUXPLL clock / 3 + SYSCTL_AUXPLLCLK_DIV_5, //!< AUXPLL clock = AUXPLL clock / 5 + SYSCTL_AUXPLLCLK_DIV_6, //!< AUXPLL clock = AUXPLL clock / 6 + SYSCTL_AUXPLLCLK_DIV_7 //!< AUXPLL clock = AUXPLL clock / 7 + +}SysCtl_AuxPLLClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to +//! SysCtl_setCputimer2Clk() as \e divider parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKPRESCALE_1, //!< Cputimer2 clock = Cputimer2 clock / 1 + SYSCTL_TMR2CLKPRESCALE_2, //!< Cputimer2 clock = Cputimer2 clock / 2 + SYSCTL_TMR2CLKPRESCALE_4, //!< Cputimer2 clock = Cputimer2 clock / 4 + SYSCTL_TMR2CLKPRESCALE_8, //!< Cputimer2 clock = Cputimer2 clock / 8 + SYSCTL_TMR2CLKPRESCALE_16 //!< Cputimer2 clock = Cputimer2 clock / 16 + +}SysCtl_Cputimer2ClkDivider; + +//***************************************************************************** +// +//! The following are values that can be passed to SysCtl_setCputimer2Clk() +//! as \e source parameter. +// +//***************************************************************************** +typedef enum +{ + SYSCTL_TMR2CLKSRCSEL_SYSCLK = 0U, //!< System Clock + SYSCTL_TMR2CLKSRCSEL_INTOSC1 = 1U, //!< Internal Oscillator 1 + SYSCTL_TMR2CLKSRCSEL_INTOSC2 = 2U, //!< Internal Oscillator 2 + SYSCTL_TMR2CLKSRCSEL_XTAL = 3U, //!< Crystal oscillator + SYSCTL_TMR2CLKSRCSEL_AUXPLLCLK = 6U //!< Aux PLL CLock + +}SysCtl_Cputimer2ClkSource; + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Wrapper function for Device_cal function +//! +//! \param None +//! +//! This is a wrapper function for the Device_cal function available in the OTP +//! memory. +//! The function saves and restores the core registers which are being +//! used by the Device_cal function +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_deviceCal(void) +{ + // + // Save the core registers used by Device_cal function in the stack + // + SYSCTL_DEVICECAL_CONTEXT_SAVE; + + // + // Call the Device_cal function + // + Device_cal(); + + // + // Restore the core registers + // + SYSCTL_DEVICECAL_CONTEXT_RESTORE; +} + +//***************************************************************************** +// +//! Resets a peripheral +//! +//! \param peripheral is the peripheral to reset. +//! +//! This function uses the SOFTPRESx registers to reset a specified peripheral. +//! Module registers will be returned to their reset states. +//! +//! \note This includes registers containing trim values.The peripheral +//! software reset needed by CPU2 can be communicated to CPU1 via +//! IPC for all shared peripherals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetPeripheral(SysCtl_PeripheralSOFTPRES peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Sets the appropriate reset bit and then clears it. + // + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) |= (1UL << bitIndex); + HWREG(DEVCFG_BASE + SYSCTL_O_SOFTPRES0 + regIndex) &= ~(1UL << bitIndex); + + // + // Call Device_cal function + // + if((((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0xDU) || // ADCx + (((uint16_t)peripheral & SYSCTL_PERIPH_REG_M) == 0x10U) // DACx + ) + { + SysCtl_deviceCal(); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables a peripheral. +//! +//! \param peripheral is the peripheral to enable. +//! +//! Peripherals are enabled with this function. At power-up, all peripherals +//! are disabled; they must be enabled in order to operate or respond to +//! register reads/writes. +//! +//! \note Note that there should be atleast 5 cycles delay between enabling the +//! peripheral clock and accessing the peripheral registers. The delay should be +//! added by the user if the peripheral is accessed immediately after this +//! function call. +//! Use asm(" RPT #5 || NOP"); to add 5 cycle delay post this function call. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn on the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) |= (1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Disables a peripheral. +//! +//! \param peripheral is the peripheral to disable. +//! +//! Peripherals are disabled with this function. Once disabled, they will not +//! operate or respond to register reads/writes. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disablePeripheral(SysCtl_PeripheralPCLOCKCR peripheral) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Decode the peripheral variable. + // + regIndex = (uint16_t)2U * ((uint16_t)peripheral & + (uint16_t)SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Turn off the module clock. + // + HWREG(CPUSYS_BASE + SYSCTL_O_PCLKCR0 + regIndex) &= ~(1UL << bitIndex); + EDIS; +} + +//***************************************************************************** +// +//! Resets the device. +//! +//! This function performs a watchdog reset of the device. +//! +//! \return This function does not return. +// +//***************************************************************************** +static inline void +SysCtl_resetDevice(void) +{ + // + // Write an incorrect check value to the watchdog control register + // This will cause a device reset + // + EALLOW; + + // + // Enable the watchdog + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + // + // Write a bad check value + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = 0U; + SYSCTL_REGWRITE_DELAY; + + EDIS; + + // + // The device should have reset, so this should never be reached. Just in + // case, loop forever. + // + while((bool)1) + { + } +} + +//***************************************************************************** +// +//! Gets the reason for a reset. +//! +//! This function will return the reason(s) for a reset. Since the reset +//! reasons are sticky until either cleared by software or an external reset, +//! multiple reset reasons may be returned if multiple resets have occurred. +//! The reset reason will be a logical OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! \note If you re-purpose the reserved boot ROM RAM, the POR and XRS reset +//! statuses won't be accurate. +//! +//! \return Returns the reason(s) for a reset. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getResetCause(void) +{ + uint32_t resetCauses; + + // + // Read CPU reset register + // + resetCauses = HWREG(CPUSYS_BASE + SYSCTL_O_RESC) & + ((uint32_t)SYSCTL_RESC_POR | (uint32_t)SYSCTL_RESC_XRSN | + (uint32_t)SYSCTL_RESC_WDRSN | + (uint32_t)SYSCTL_RESC_NMIWDRSN | + (uint32_t)SYSCTL_RESC_SCCRESETN + ); + + // + // Set POR and XRS Causes from boot ROM Status + // + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_POR) == + (uint32_t)SYSCTL_BOOT_ROM_POR) + { + resetCauses |= SYSCTL_RESC_POR; + } + if((HWREG(SYSCTL_BOOT_ROM_STATUS) & (uint32_t)SYSCTL_BOOT_ROM_XRS) == + (uint32_t)SYSCTL_BOOT_ROM_XRS) + { + resetCauses |= SYSCTL_RESC_XRSN; + } + + // + // Return the reset reasons. + // + return(resetCauses); +} + +//***************************************************************************** +// +//! Clears reset reasons. +//! +//! \param rstCauses are the reset causes to be cleared; must be a logical +//! OR of +//! - \b SYSCTL_CAUSE_POR - Power-on reset +//! - \b SYSCTL_CAUSE_XRS - External reset pin +//! - \b SYSCTL_CAUSE_WDRS - Watchdog reset +//! - \b SYSCTL_CAUSE_NMIWDRS - NMI watchdog reset +//! - \b SYSCTL_CAUSE_SCCRESET - SCCRESETn reset from DCSM +//! +//! This function clears the specified sticky reset reasons. Once cleared, +//! another reset for the same reason can be detected, and a reset for a +//! different reason can be distinguished (instead of having two reset causes +//! set). If the reset reason is used by an application, all reset causes +//! should be cleared after they are retrieved with SysCtl_getResetCause(). +//! +//! \note Some reset causes are cleared by the boot ROM. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearResetCause(uint32_t rstCauses) +{ + // + // Clear the given reset reasons. + // + HWREG(CPUSYS_BASE + SYSCTL_O_RESC) = rstCauses; +} + +//***************************************************************************** +// +//! Sets the low speed peripheral clock rate prescaler. +//! +//! \param prescaler is the LSPCLK rate relative to SYSCLK +//! +//! This function configures the clock rate of the low speed peripherals. The +//! \e prescaler parameter is the value by which the SYSCLK rate is divided to +//! get the LSPCLK rate. For example, a \e prescaler of +//! \b SYSCTL_LSPCLK_PRESCALE_4 will result in a LSPCLK rate that is a quarter +//! of the SYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setLowSpeedClock(SysCtl_LSPCLKPrescaler prescaler) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) = + (HWREG(CLKCFG_BASE + SYSCTL_O_LOSPCP) & + ~(uint32_t)SYSCTL_LOSPCP_LSPCLKDIV_M) | (uint32_t)prescaler; + EDIS; +} + +//***************************************************************************** +// +//! Sets the ePWM clock divider. +//! +//! \param divider is the value by which PLLSYSCLK is divided +//! +//! This function configures the clock rate of the EPWMCLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EPWMCLK rate. For example, \b SYSCTL_EPWMCLK_DIV_2 will select an +//! EPWMCLK rate that is half the PLLSYSCLK rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEPWMClockDivider(SysCtl_EPWMCLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) & + ~SYSCTL_PERCLKDIVSEL_EPWMCLKDIV_M) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF1 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF1CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF1CLK rate. For example, \b SYSCTL_EMIF1CLK_DIV_2 will select an +//! EMIF1CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF1ClockDivider(SysCtl_EMIF1CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF1CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF1CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Sets the EMIF2 clock divider. +//! +//! \param divider is the value by which PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) is divided +//! +//! This function configures the clock rate of the EMIF2CLK. The +//! \e divider parameter is the value by which the SYSCLK rate is divided to +//! get the EMIF2CLK rate. For example, \b SYSCTL_EMIF2CLK_DIV_2 will select an +//! EMIF2CLK rate that is half the PLLSYSCLK (or CPU1.SYSCLK on a dual +//! core device) rate. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setEMIF2ClockDivider(SysCtl_EMIF2CLKDivider divider) +{ + // + // Write the divider selection to the appropriate register. + // + EALLOW; + if(divider == SYSCTL_EMIF2CLK_DIV_2) + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) |= + SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + else + { + HWREGH(CLKCFG_BASE + SYSCTL_O_PERCLKDIVSEL) &= + ~SYSCTL_PERCLKDIVSEL_EMIF2CLKDIV; + SYSCTL_REGWRITE_DELAY; + } + EDIS; +} + +//***************************************************************************** +// +//! Selects a clock source to mux to an external GPIO pin (XCLKOUT). +//! +//! \param source is the internal clock source to be configured. +//! +//! This function configures the specified clock source to be muxed to an +//! external clock out (XCLKOUT) GPIO pin. The \e source parameter may take a +//! value of one of the following values: +//! - \b SYSCTL_CLOCKOUT_PLLSYS +//! - \b SYSCTL_CLOCKOUT_PLLRAW +//! - \b SYSCTL_CLOCKOUT_SYSCLK +//! - \b SYSCTL_CLOCKOUT_INTOSC1 +//! - \b SYSCTL_CLOCKOUT_INTOSC2 +//! - \b SYSCTL_CLOCKOUT_XTALOSC +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectClockOutSource(SysCtl_ClockOut source) +{ + EALLOW; + + // + // Clear clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) &= + ~SYSCTL_CLKSRCCTL3_XCLKOUTSEL_M; + SYSCTL_CLKSRCCTL_DELAY; + + // + // Set clock out source + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL3) |= (uint16_t)source; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the external oscillator counter value. +//! +//! This function returns the X1 clock counter value. When the return value +//! reaches 0x3FF, it freezes. Before switching from INTOSC2 to an external +//! oscillator (XTAL), an application should call this function to make sure +//! the counter is saturated. +//! +//! \return Returns the value of the 10-bit X1 clock counter. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getExternalOscCounterValue(void) +{ + return(HWREGH(CLKCFG_BASE + SYSCTL_O_X1CNT) & SYSCTL_X1CNT_X1CNT_M); +} + +//***************************************************************************** +// +//! Turns on the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns on the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOnOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn on INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn on XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= + ~SYSCTL_CLKSRCCTL1_XTALOFF; + + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Turns off the specified oscillator sources. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function turns off the oscillator specified by the \e oscSource +//! parameter which may take a value of \b SYSCTL_OSCSRC_XTAL +//! or \b SYSCTL_OSCSRC_OSC2. +//! +//! \note \b SYSCTL_OSCSRC_OSC1 is not a valid value for \e oscSource. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_turnOffOsc(uint32_t oscSource) +{ + ASSERT( + (oscSource == SYSCTL_OSCSRC_OSC2) || + (oscSource == SYSCTL_OSCSRC_XTAL) + ); + + EALLOW; + + switch(oscSource) + { + case SYSCTL_OSCSRC_OSC2: + // + // Turn off INTOSC2 + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_INTOSC2OFF; + SYSCTL_CLKSRCCTL_DELAY; + break; + + case SYSCTL_OSCSRC_XTAL: + // + // Turn off XTALOSC + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= + SYSCTL_CLKSRCCTL1_XTALOFF; + break; + + default: + // + // Do nothing. Not a valid oscSource value. + // + break; + } + + EDIS; +} + +//***************************************************************************** +// +//! Enters IDLE mode. +//! +//! This function puts the device into IDLE mode. The CPU clock is gated while +//! all peripheral clocks are left running. Any enabled interrupt will wake the +//! CPU up from IDLE mode. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterIdleMode(void) +{ + EALLOW; + + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters STANDBY mode. +//! +//! This function puts the device into STANDBY mode. This will gate both the +//! CPU clock and any peripheral clocks derived from SYSCLK. The watchdog is +//! left active, and an NMI or an optional watchdog interrupt will wake the +//! CPU subsystem from STANDBY mode. +//! +//! GPIOs may be configured to wake the CPU subsystem. See +//! SysCtl_enableLPMWakeupPin(). +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterStandbyMode(void) +{ + EALLOW; + + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +} + +//***************************************************************************** +// +//! Enters HALT mode. +//! +//! This function puts the device into HALT mode. This will gate almost all +//! systems and clocks and allows for the power-down of oscillators and analog +//! blocks. The watchdog may be left clocked to produce a reset. See +//! SysCtl_enableWatchdogInHalt() to enable this. GPIOs should be +//! configured to wake the CPU subsystem. See SysCtl_enableLPMWakeupPin(). +//! +//! Enter HALT mode (dual CPU). Puts CPU2 in IDLE mode first. +//! +//! The CPU will receive an interrupt (WAKEINT) on wakeup. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHaltMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into IDLE mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_IDLE; + + EDIS; + asm(" IDLE"); + +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into HALT mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HALT; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +// +//! Enters Hibernate mode. +//! +//! This function puts the device into Hibernate mode. Hibernate (HIB) is a +//! global low-power mode that gates the supply voltages to most of the system. +//! This mode affects both CPU subsystems. HIB is essentially a controlled +//! power-down with remote wakeup capability, and can be used to save power +//! during long periods of inactivity. +//! +//! To wake the device from HIB mode: +//! 1. Assert the dedicated GPIOHIBWAKE pin (GPIO41) low to enable the +//! power-up of the device clock sources. +//! 2. Assert GPIOHIBWAKE pin high again. This triggers the power-up of the +//! rest of the device. +//! +//! To enter Hibernate mode in dual CPU put CPU2 in STANDBY mode first. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enterHibernateMode(void) +{ +#if defined(CPU2) + EALLOW; + // + // Configure the device to go into STANDBY mode when IDLE is executed. + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_STANDBY; + + EDIS; + asm(" IDLE"); +#elif defined(CPU1) + EALLOW; + + // + // Configure the device to go into Hibernate mode when IDLE is executed + // + HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREG(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint32_t)SYSCTL_LPMCR_LPM_M) | SYSCTL_LPM_HIB; + + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSPLLCTL1) &= + ~(SYSCTL_SYSPLLCTL1_PLLCLKEN | SYSCTL_SYSPLLCTL1_PLLEN); + SYSCTL_REGWRITE_DELAY; + + EDIS; + +#ifndef _DUAL_HEADERS + IDLE; +#else + IDLE_ASM; +#endif +#endif +} + +//***************************************************************************** +//! Enables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function connects a pin to the LPM circuit, allowing an event on the +//! pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are capable of +//! being connected to the LPM circuit. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) |= pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) |= pinMask; + } + + EDIS; +} + +//***************************************************************************** +//! Disables a pin to wake up the device from the following mode(s): +//! - STANDBY +//! - HALT +//! +//! \param pin is the identifying number of the pin. +//! +//! This function disconnects a pin to the LPM circuit, disallowing an event on +//! the pin to wake up the device when when it is in following mode(s): +//! - STANDBY +//! - HALT +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. Only GPIOs 0 through 63 are valid. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableLPMWakeupPin(uint32_t pin) +{ + uint32_t pinMask; + + // + // Check the arguments. + // + ASSERT(pin <= 63U); + + pinMask = 1UL << (pin % 32U); + + EALLOW; + + if(pin < 32U) + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL0) &= ~pinMask; + } + else + { + HWREG(CPUSYS_BASE + SYSCTL_O_GPIOLPMSEL1) &= ~pinMask; + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the number of cycles to qualify an input on waking from STANDBY mode. +//! +//! \param cycles is the number of OSCCLK cycles. +//! +//! This function sets the number of OSCCLK clock cycles used to qualify the +//! selected inputs when waking from STANDBY mode. The \e cycles parameter +//! should be passed a cycle count between 2 and 65 cycles inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setStandbyQualificationPeriod(uint16_t cycles) +{ + // + // Check the arguments. + // + ASSERT((cycles >= 2U) && (cycles <= 65U)); + + EALLOW; + + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) & + ~(uint16_t)SYSCTL_LPMCR_QUALSTDBY_M) | + ((cycles - 2U) << SYSCTL_LPMCR_QUALSTDBY_S); + + EDIS; +} + +//***************************************************************************** +// +//! Enable the device to wake from STANDBY mode upon a watchdog interrupt. +//! +//! \note In order to use this option, you must configure the watchdog to +//! generate an interrupt using SysCtl_setWatchdogMode(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Set the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) |= SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the device from waking from STANDBY mode upon a watchdog interrupt. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogStandbyWakeup(void) +{ + EALLOW; + + // + // Clear the bit enables the watchdog to wake up the device from STANDBY. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_LPMCR) &= ~SYSCTL_LPMCR_WDINTE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the watchdog to run while in HALT mode. +//! +//! This function configures the watchdog to continue to run while in HALT +//! mode. Additionally, INTOSC1 and INTOSC2 are not powered down when the +//! system enters HALT mode. By default the watchdog is gated when the system +//! enters HALT. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogInHalt(void) +{ + EALLOW; + + // + // Set the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) |= SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Disable the watchdog from running while in HALT mode. +//! +//! This function gates the watchdog when the system enters HALT mode. INTOSC1 +//! and INTOSC2 will be powered down. This is the default behavior of the +//! device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdogInHalt(void) +{ + EALLOW; + + // + // Clear the watchdog HALT mode ignore bit. + // + HWREGH(CLKCFG_BASE + SYSCTL_O_CLKSRCCTL1) &= ~SYSCTL_CLKSRCCTL1_WDHALTI; + SYSCTL_CLKSRCCTL_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the watchdog generates a reset or an interrupt signal. +//! +//! \param mode is a flag to select the watchdog mode. +//! +//! This function configures the action taken when the watchdog counter reaches +//! its maximum value. When the \e mode parameter is +//! \b SYSCTL_WD_MODE_INTERRUPT, the watchdog is enabled to generate a watchdog +//! interrupt signal and disables the generation of a reset signal. This will +//! allow the watchdog module to wake up the device from IDLE +//! or STANDBY if desired (see SysCtl_enableWatchdogStandbyWakeup()). +//! +//! When the \e mode parameter is \b SYSCTL_WD_MODE_RESET, the watchdog will +//! be put into reset mode and generation of a watchdog interrupt signal will +//! be disabled. This is how the watchdog is configured by default. +//! +//! \note Check the status of the watchdog interrupt using +//! SysCtl_isWatchdogInterruptActive() before calling this function. If the +//! interrupt is still active, switching from interrupt mode to reset mode will +//! immediately reset the device. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogMode(SysCtl_WDMode mode) +{ + EALLOW; + + // + // Either set or clear the WDENINT bit to that will determine whether the + // watchdog will generate a reset signal or an interrupt signal. Take care + // not to write a 1 to WDOVERRIDE. + // + if(mode == SYSCTL_WD_MODE_INTERRUPT) + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) = + (HWREGH(WD_BASE + SYSCTL_O_SCSR) & ~SYSCTL_SCSR_WDOVERRIDE) | + SYSCTL_SCSR_WDENINT; + } + else + { + HWREGH(WD_BASE + SYSCTL_O_SCSR) &= ~(SYSCTL_SCSR_WDENINT | + SYSCTL_SCSR_WDOVERRIDE); + } + + EDIS; +} + +//***************************************************************************** +// +//! Gets the status of the watchdog interrupt signal. +//! +//! This function returns the status of the watchdog interrupt signal. If the +//! interrupt is active, this function will return \b true. If \b false, the +//! interrupt is NOT active. +//! +//! \note Make sure to call this function to ensure that the interrupt is not +//! active before making any changes to the configuration of the watchdog to +//! prevent any unexpected behavior. For instance, switching from interrupt +//! mode to reset mode while the interrupt is active will immediately reset the +//! device. +//! +//! \return \b true if the interrupt is active and \b false if it is not. +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogInterruptActive(void) +{ + // + // If the status bit is cleared, the WDINTn signal is active. + // + return((HWREGH(WD_BASE + SYSCTL_O_SCSR) & SYSCTL_SCSR_WDINTS) == 0U); +} + +//***************************************************************************** +// +//! Disables the watchdog. +//! +//! This function disables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableWatchdog(void) +{ + EALLOW; + + // + // Set the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) |= SYSCTL_WD_CHKBITS | SYSCTL_WDCR_WDDIS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Enables the watchdog. +//! +//! This function enables the watchdog timer. Note that the watchdog timer is +//! enabled on reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdog(void) +{ + EALLOW; + + // + // Clear the disable bit. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~SYSCTL_WDCR_WDDIS) | SYSCTL_WD_CHKBITS; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Checks if the watchdog is enabled or not +//! +//! This function returns the watchdog status whether it is enabled or disabled +//! +//! \return \b true if the watchdog is enabled & \b false if the watchdog is +//! disabled +// +//***************************************************************************** +static inline bool +SysCtl_isWatchdogEnabled(void) +{ + + // + // Get the watchdog enable status + // + return ((HWREGH(WD_BASE + SYSCTL_O_WDCR) & SYSCTL_WDCR_WDDIS) == 0U); +} + +//***************************************************************************** +// +//! Services the watchdog. +//! +//! This function resets the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_serviceWatchdog(void) +{ + EALLOW; + + // + // Enable the counter to be reset and then reset it. + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the first key to enter the watchdog reset. +//! +//! This function writes the first key to enter the watchdog reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableWatchdogReset(void) +{ + EALLOW; + + // + // Enable the counter to be reset + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_ENRSTKEY; + + EDIS; +} + +//***************************************************************************** +// +//! Writes the second key to reset the watchdog. +//! +//! This function writes the second key to reset the watchdog. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetWatchdog(void) +{ + EALLOW; + + // + // Reset the watchdog counter + // + HWREGH(WD_BASE + SYSCTL_O_WDKEY) = SYSCTL_WD_RSTKEY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up watchdog clock (WDCLK) prescaler. +//! +//! \param prescaler is the value that configures the watchdog clock relative +//! to the value from the pre-divider. +//! +//! This function sets up the watchdog clock (WDCLK) prescaler. The +//! \e prescaler parameter divides INTOSC1 down to WDCLK. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogPrescaler(SysCtl_WDPrescaler prescaler) +{ + uint16_t regVal; + + regVal = (uint16_t)prescaler | (uint16_t)SYSCTL_WD_CHKBITS; + + EALLOW; + + // + // Write the prescaler to the appropriate register. + // + HWREGH(WD_BASE + SYSCTL_O_WDCR) = (HWREGH(WD_BASE + SYSCTL_O_WDCR) & + ~(SYSCTL_WDCR_WDPS_M)) | regVal; + SYSCTL_REGWRITE_DELAY; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the watchdog counter value. +//! +//! \return Returns the current value of the 8-bit watchdog counter. If this +//! count value overflows, a watchdog output pulse is generated. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getWatchdogCounterValue(void) +{ + // + // Read and return the value of the watchdog counter. + // + return(HWREGH(WD_BASE + SYSCTL_O_WDCNTR)); +} + +//***************************************************************************** +// +//! Gets the watchdog reset status. +//! +//! This function returns the watchdog reset status. If this function returns +//! \b true, that indicates that a watchdog reset generated the last reset +//! condition. Otherwise, it was an external device or power-up reset +//! condition. +//! +//! \return Returns \b true if the watchdog generated the last reset condition. +// +//***************************************************************************** +static inline bool +SysCtl_getWatchdogResetStatus(void) +{ + // + // Read and return the status of the watchdog reset status flag. + // + return((HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) & SYSCTL_RESC_WDRSN) != 0U); +} + +//***************************************************************************** +// +//! Clears the watchdog reset status. +//! +//! This function clears the watchdog reset status. To check if it was set +//! first, see SysCtl_getWatchdogResetStatus(). +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogResetStatus(void) +{ + EALLOW; + + // + // Read and return the status of the watchdog reset status flag. + // + HWREGH(CPUSYS_BASE + SYSCTL_O_RESC) = SYSCTL_RESC_WDRSN; + + EDIS; +} + +//***************************************************************************** +// +//! Set the minimum threshold value for windowed watchdog +//! +//! \param value is the value to set the window threshold +//! +//! This function sets the minimum threshold value used to define the lower +//! limit of the windowed watchdog functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setWatchdogWindowValue(uint16_t value) +{ + EALLOW; + + // + // Clear the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) &= ~SYSCTL_WDWCR_MIN_M; + + // + // Set the windowed value + // + HWREGH(WD_BASE + SYSCTL_O_WDWCR) |= (value & SYSCTL_WDWCR_MIN_M); + + EDIS; +} + +//***************************************************************************** +// +//! Clears the watchdog override. +//! +//! This function clears the watchdog override and locks the watchdog timer +//! module to remain in its prior state which could be either enable /disable. +//! The watchdog timer will remain in this state until the next system reset. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearWatchdogOverride(void) +{ + EALLOW; + + HWREGH(WD_BASE + SYSCTL_O_SCSR) |= SYSCTL_SCSR_WDOVERRIDE; + + EDIS; +} + +//***************************************************************************** +// +//! Enable the NMI Global interrupt bit +//! +//! \b Note: This bit should be set after the device security related +//! initialization is complete. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableNMIGlobalInterrupt(void) +{ + EALLOW; + + HWREGH(NMI_BASE + NMI_O_CFG) |= NMI_CFG_NMIE; + + EDIS; +} + +//***************************************************************************** +// +//! Read NMI interrupts. +//! +//! Read the current state of NMI interrupt. +//! +//! \return \b true if NMI interrupt is triggered, \b false if not. +// +//***************************************************************************** +static inline bool +SysCtl_getNMIStatus(void) +{ + // + // Read and return the current value of the NMI flag register, masking out + // all but the NMI bit. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & NMI_FLG_NMIINT) != 0U); +} + +//***************************************************************************** +// +//! Read NMI Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMIFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIFlagStatus(void) +{ + // + // Read and return the current value of the NMI flag register. + // + return(HWREGH(NMI_BASE + NMI_O_FLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI interrupts are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_FLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Function to clear individual NMI interrupts. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Clear NMI interrupt flags that correspond with the passed in bit mask. +//! +//! \b Note: The NMI Interrupt flag is always cleared by default and +//! therefore doesn't have to be included in the bit mask. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearNMIStatus(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Clear the individual flags as well as NMI Interrupt flag + // + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Clear all the NMI Flags that are currently set. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_clearAllNMIFlags(void) +{ + uint16_t nmiFlags; + + // + // Read the flag status register and then write to the clear register, + // clearing all the flags that were returned plus the NMI flag. + // + EALLOW; + + nmiFlags = SysCtl_getNMIFlagStatus(); + HWREGH(NMI_BASE + NMI_O_FLGCLR) = nmiFlags; + HWREGH(NMI_BASE + NMI_O_FLGCLR) = NMI_FLG_NMIINT; + + EDIS; +} + +//***************************************************************************** +// +//! Function to force individual NMI interrupt fail flags +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_forceNMIFlags(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + EALLOW; + + // + // Set the Flags for the individual interrupts in the NMI flag + // force register + // + HWREGH(NMI_BASE + NMI_O_FLGFRC) |= nmiFlags; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog counter value. +//! +//! \b Note: The counter is clocked at the SYSCLKOUT rate. +//! +//! \return Returns the NMI watchdog counter register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogCounter(void) +{ + // + // Read and return the NMI watchdog counter register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDCNT)); +} + +//***************************************************************************** +// +//! Sets the NMI watchdog period value. +//! +//! \param wdPeriod is the 16-bit value at which a reset is generated. +//! +//! This function writes to the NMI watchdog period register that holds the +//! value to which the NMI watchdog counter is compared. When the two registers +//! match, a reset is generated. By default, the period is 0xFFFF. +//! +//! \note If a value smaller than the current counter value is passed into the +//! \e wdPeriod parameter, a NMIRSn will be forced. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setNMIWatchdogPeriod(uint16_t wdPeriod) +{ + EALLOW; + + // + // Write to the period register. + // + HWREGH(NMI_BASE + NMI_O_WDPRD) = wdPeriod; + + EDIS; +} + +//***************************************************************************** +// +//! Gets the NMI watchdog period value. +//! +//! \return Returns the NMI watchdog period register's current value. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getNMIWatchdogPeriod(void) +{ + // + // Read and return the NMI watchdog period register's value. + // + return(HWREGH(NMI_BASE + NMI_O_WDPRD)); +} + +//***************************************************************************** +// +//! Read NMI Shadow Flags. +//! +//! Read the current state of individual NMI interrupts +//! +//! \return Value of NMISHDFLG register. These defines are provided to decode +//! the value: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +// +//***************************************************************************** +static inline uint32_t +SysCtl_getNMIShadowFlagStatus(void) +{ + // + // Read and return the current value of the NMI shadow flag register. + // + return(HWREGH(NMI_BASE + NMI_O_SHDFLG)); +} + +//***************************************************************************** +// +//! Check if the individual NMI shadow flags are set. +//! +//! \param nmiFlags Bit mask of the NMI interrupts that user wants to clear. +//! The bit format of this parameter is same as of the NMIFLG register. These +//! defines are provided: +//! - \b SYSCTL_NMI_NMIINT - NMI Interrupt Flag +//! - \b SYSCTL_NMI_CLOCKFAIL - Clock Fail Interrupt Flag +//! - \b SYSCTL_NMI_RAMUNCERR - RAM Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_FLUNCERR - Flash Uncorrectable Error NMI Flag +//! - \b SYSCTL_NMI_CPU1HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_CPU2HWBISTERR - HW BIST Error NMI Flag +//! - \b SYSCTL_NMI_PIEVECTERR - PIE Vector Fetch Error Flag +//! - \b SYSCTL_NMI_CLBNMI - Configurable Logic Block NMI Flag +//! - \b SYSCTL_NMI_CPU2WDRSN - CPU2 WDRSn Reset Indication Flag +//! - \b SYSCTL_NMI_CPU2NMIWDRSN - CPU2 NMIWDRSn Reset Indication Flag +//! +//! Check if interrupt flags corresponding to the passed in bit mask are +//! asserted. +//! +//! \return \b true if any of the NMI asked for in the parameter bit mask +//! is set. \b false if none of the NMI requested in the parameter bit mask are +//! set. +// +//***************************************************************************** +static inline bool +SysCtl_isNMIShadowFlagSet(uint16_t nmiFlags) +{ + // + // Check the arguments. + // Make sure if reserved bits are not set in nmiFlags. + // + ASSERT((nmiFlags & ~( + SYSCTL_NMI_NMIINT | + SYSCTL_NMI_CLOCKFAIL | + SYSCTL_NMI_RAMUNCERR | + SYSCTL_NMI_FLUNCERR | + SYSCTL_NMI_CPU1HWBISTERR | + SYSCTL_NMI_CPU2HWBISTERR | + SYSCTL_NMI_PIEVECTERR | + SYSCTL_NMI_CLBNMI | + SYSCTL_NMI_CPU2WDRSN | + SYSCTL_NMI_CPU2NMIWDRSN + )) == 0U); + + // + // Read the flag register and return true if any of them are set. + // + return((HWREGH(NMI_BASE + NMI_O_SHDFLG) & nmiFlags) != 0U); +} + +//***************************************************************************** +// +//! Enable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_MCLKOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disable the missing clock detection (MCD) Logic +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Get the missing clock detection Failure Status +//! +//! \note A failure means the oscillator clock is missing +//! +//! \return Returns \b true if a failure is detected or \b false if a +//! failure isn't detected +// +//***************************************************************************** +static inline bool +SysCtl_isMCDClockFailureDetected(void) +{ + // + // Check the status bit to determine failure + // + return((HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) & SYSCTL_MCDCR_MCLKSTS) != 0U); +} + +//***************************************************************************** +// +//! Reset the missing clock detection logic after clock failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_resetMCD(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_MCLKCLR; + + EDIS; +} + +//***************************************************************************** +// +//! Re-connect missing clock detection clock source to stop simulating clock +//! failure +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_connectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) &= ~(SYSCTL_MCDCR_OSCOFF); + + EDIS; +} + +//***************************************************************************** +// +//! Disconnect missing clock detection clock source to simulate clock failure. +//! This is for testing the MCD functionality. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disconnectMCDClockSource(void) +{ + EALLOW; + + HWREGH(CLKCFG_BASE + SYSCTL_O_MCDCR) |= SYSCTL_MCDCR_OSCOFF; + + EDIS; +} + +//***************************************************************************** +// +//! Configures the sync input source for the ePWM and eCAP signals. +//! +//! \param syncInput is the sync input being configured +//! \param syncSrc is sync input source selection. +//! +//! This function configures the sync input source for the ePWM and eCAP +//! modules. The \e syncInput parameter is the sync input being configured. It +//! should be passed a value of \b SYSCTL_SYNC_IN_XXXX, where XXXX is the ePWM +//! or eCAP instance the sync signal is entering. +//! +//! The \e syncSrc parameter is the sync signal selected as the source of the +//! sync input. It should be passed a value of \b SYSCTL_SYNC_IN_SRC_XXXX, +//! XXXX is a sync signal coming from an ePWM, eCAP or external sync output. +//! where For example, a \e syncInput value of \b SYSCTL_SYNC_IN_ECAP1 and a +//! \e syncSrc value of \b SYSCTL_SYNC_IN_SRC_EPWM1SYNCOUT will make the +//! EPWM1SYNCOUT signal drive eCAP1's SYNCIN signal. +//! +//! Note that some \e syncSrc values are only valid for certain values of +//! \e syncInput. See device technical reference manual for details on +//! time-base counter synchronization. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncInputConfig(SysCtl_SyncInput syncInput, + SysCtl_SyncInputSource syncSrc) +{ + uint32_t clearMask; + + // + // Write the input sync source selection to the appropriate register. + // + EALLOW; + clearMask = (uint32_t)SYSCTL_SYNCSELECT_SYNCIN_M << (uint32_t)syncInput; + + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & ~clearMask) | + ((uint32_t)syncSrc << (uint32_t)syncInput); + + EDIS; +} +//***************************************************************************** +// +//! Configures the sync output source. +//! +//! \param syncSrc is sync output source selection. +//! +//! This function configures the sync output source from the ePWM modules. The +//! \e syncSrc parameter is a value \b SYSCTL_SYNC_OUT_SRC_XXXX, where XXXX is +//! a sync signal coming from an ePWM such as SYSCTL_SYNC_OUT_SRC_EPWM1SYNCOUT +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setSyncOutputConfig(SysCtl_SyncOutputSource syncSrc) +{ + // + // Write the sync output source selection to the appropriate register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) = + (HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSELECT) & + ~((uint32_t)SYSCTL_SYNCSELECT_SYNCOUT_M)) | + ((uint32_t)syncSrc << SYSCTL_SYNCSELECT_SYNCOUT_S); + EDIS; + +} +//***************************************************************************** +// +//! Enables ePWM SOC signals to drive an external (off-chip) ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be enabled +//! +//! This function configures which ePWM SOC signals are enabled as a source for +//! either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical OR +//! of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_enableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Set the bits that correspond to signal to be enabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) |= adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Disables ePWM SOC signals from driving an external ADCSOC signal. +//! +//! \param adcsocSrc is a bit field of the selected signals to be disabled +//! +//! This function configures which ePWM SOC signals are disabled as a source +//! for either ADCSOCAO or ADCSOCBO. The \e adcsocSrc parameter takes a logical +//! OR of \b SYSCTL_ADCSOC_SRC_PWMxSOCA/B values that correspond to different +//! signals. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_disableExtADCSOCSource(uint32_t adcsocSrc) +{ + // + // Clear the bits that correspond to signal to be disabled. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_ADCSOCOUTSELECT) &= ~adcsocSrc; + EDIS; +} + +//***************************************************************************** +// +//! Locks the SOC Select of the Trig X-BAR. +//! +//! This function locks the external ADC SOC select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockExtADCSOCSelect(void) +{ + // + // Lock the ADCSOCOUTSELECT bit of the SYNCSOCLOCK register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = + SYSCTL_SYNCSOCLOCK_ADCSOCOUTSELECT; + EDIS; +} + +//***************************************************************************** +// +//! Configures whether the dual ported bridge is connected with DMA or +//! CLA as the secondary controller. +//! +//! \param periFrame1Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 1. +//! \param periFrame2Config indicates whether CLA or DMA is configured as +//! secondary controller on peripheral frame 2. +//! +//! One of the following values can be passed as parameter. +//! \b SYSCTL_SEC_CONTROLLER_CLA +//! \b SYSCTL_SEC_CONTROLLER_DMA +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectSecController(uint16_t periFrame1Config, uint16_t periFrame2Config) +{ + EALLOW; + + HWREG(CPUSYS_BASE + SYSCTL_O_SECMSEL) = + (((periFrame1Config << SYSCTL_SECMSEL_PF1SEL_S) & + SYSCTL_SECMSEL_PF1SEL_M) | + ((periFrame2Config << SYSCTL_SECMSEL_PF2SEL_S) & + SYSCTL_SECMSEL_PF2SEL_M)); + + EDIS; +} + +//***************************************************************************** +// +//! Locks the Sync Select of the Trig X-BAR. +//! +//! This function locks Sync Input and Output Select of the Trig X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockSyncSelect(void) +{ + // + // Lock the SYNCSELECT register. + // + EALLOW; + HWREG(SYNCSOC_BASE + SYSCTL_O_SYNCSOCLOCK) = SYSCTL_SYNCSOCLOCK_SYNCSELECT; + EDIS; +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeriphInstance +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheralInstance(SysCtl_CPUSelPeriphInstance peripheral, + SysCtl_CPUSel cpuInst) +{ + uint16_t regIndex; + uint16_t bitIndex; + + // + // Identify the register index and bit position + // + regIndex = 2U * ((uint16_t)peripheral & SYSCTL_PERIPH_REG_M); + bitIndex = ((uint16_t)peripheral & SYSCTL_PERIPH_BIT_M) >> + SYSCTL_PERIPH_BIT_S; + + EALLOW; + + // + // Configure the CPU owner for the specified peripheral instance + // + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) = + (HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + regIndex) & ~(1UL << bitIndex)) | + ((uint32_t)cpuInst << bitIndex); + + EDIS; + +} +//***************************************************************************** +// +//! Configures whether a peripheral is connected to CPU1 or CPU2. +//! +//! \param peripheral is the peripheral for which CPU needs to be configured. +//! \param peripheralInst is the instance for which CPU needs to be configured. +//! \param cpuInst is the CPU to which the peripheral instance need to be +//! connected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! The \e peripheralInst parameter is the instance number for example +//! 1 for EPWM1, 2 for EPWM2 so on.For instances which are named with alphabets +//! (instead of numbers) the following convention needs to be followed. +//! 1 for A (SPI_A), 2 for B (SPI_B), 3 for C (SPI_C) so on... +//! +//! The \e cpuInst parameter can have one the following values: +//! - \b SYSCTL_CPUSEL_CPU1 - to connect to CPU1 +//! - \b SYSCTL_CPUSEL_CPU2 - to connect to CPU2 +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \note This function is retained for compatibility puposes. Recommended to +//! to use the function \e SysCtl_selectCPUForPeripheralInstance() +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_selectCPUForPeripheral(SysCtl_CPUSelPeripheral peripheral, + uint16_t peripheralInst, SysCtl_CPUSel cpuInst) +{ + uint32_t tempValue; + uint16_t shift; + + if(SYSCTL_CPUSEL14_DAC == peripheral) + { + shift = peripheralInst + SYSCTL_CPUSEL_DAC_S - 1U; + } + else + { + shift = peripheralInst - 1U; + } + + tempValue = + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) & + (~(1UL << shift)); + + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_CPUSEL0 + ((uint32_t)peripheral * 2U)) = + tempValue | ((uint32_t)cpuInst << shift); + EDIS; +} +//***************************************************************************** +// +//! Get the Device Silicon Revision ID +//! +//! This function returns the silicon revision ID for the device. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the silicon revision ID value. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceRevision(void) +{ + // + // Returns the device silicon revision ID + // + return(HWREG(DEVCFG_BASE + SYSCTL_O_REVID)); +} + +//***************************************************************************** +// +//! Locks the CPU select registers for the peripherals +//! +//! \param peripheral is the peripheral for which CPU needs to be selected. +//! +//! The \e peripheral parameter can have one enumerated value from +//! SysCtl_CPUSelPeripheral +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_lockCPUSelectRegs(SysCtl_CPUSelPeripheral peripheral) +{ + EALLOW; + HWREG(DEVCFG_BASE + SYSCTL_O_DEVCFGLOCK1) |= (1UL << (uint32_t)peripheral); + EDIS; +} + + +//***************************************************************************** +// +//! Gets the error status of the Efuse +//! +//! The function provides both the Efuse Autoload & the Efuse Self Test +//! Error Status. +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Fuse Error status. +// +//***************************************************************************** +static inline uint16_t +SysCtl_getEfuseError(void) +{ + return(HWREGH(DEVCFG_BASE + SYSCTL_O_FUSEERR)); +} + +//***************************************************************************** +// +//! Sets up XCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the XCLK divider. There is only one +//! divider that scales INTOSC1 to XCLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_XClkDivider +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setXClk(SysCtl_XClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_XCLKOUTDIVSEL) & + ~(SYSCTL_XCLKOUTDIVSEL_XCLKOUTDIV_M)) | + (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up PLLSYSCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the PLLSYSCLK divider. There is only one +//! divider that scales PLLSYSCLK to generate the system clock. +//! +//! The \e divider parameter can have one value from the set below: +//! 0x0 = /1 +//! 0x1 = /2 +//! 0x2 = /4 (default on reset) +//! 0x3 = /6 +//! 0x4 = /8 +//! ...... +//! 0x3F =/126 +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setPLLSysClk(uint16_t divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_SYSCLKDIVSEL) & + ~(SYSCTL_SYSCLKDIVSEL_PLLSYSCLKDIV_M)) | divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up AUXPLLCLK divider. +//! +//! \param divider is the value that configures the divider. +//! +//! This function sets up the AUXPLLCLK divider. There is only one +//! divider that scales AUXPLLCLK to generate the system clock. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_AuxPLLClkDivider +//! +//! \return None. +//! +//! \note Please make sure to check if the PLL is locked and valid using the +//! SysCtl_isPLLValid() before setting the divider. +// +//***************************************************************************** +static inline void +SysCtl_setAuxPLLClk(SysCtl_AuxPLLClkDivider divider) +{ + // + // Clears the divider then configures it. + // + EALLOW; + HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) = + (HWREGH(CLKCFG_BASE + SYSCTL_O_AUXCLKDIVSEL) & + ~(SYSCTL_AUXCLKDIVSEL_AUXPLLDIV_M)) | (uint16_t)divider; + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Sets up CPU Timer 2 CLK source & divider. +//! +//! \param divider is the value that configures the divider. +//! \param source is the source for the clock divider +//! +//! This function sets up the CPU Timer 2 CLK divider based on the source that +//! is selected. There is only one divider that scales the "source" to +//! CPU Timer 2 CLK. +//! +//! The \e divider parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkDivider +//! The \e source parameter can have one enumerated value from +//! SysCtl_Cputimer2ClkSource +//! +//! \return None. +// +//***************************************************************************** +static inline void +SysCtl_setCputimer2Clk(SysCtl_Cputimer2ClkDivider divider, + SysCtl_Cputimer2ClkSource source) +{ + // + // Clears the divider & the source, then configures it. + // + EALLOW; + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) = + (HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) & + ~(SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_M | + SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_M)); + SYSCTL_REGWRITE_DELAY; + + HWREGH(CPUSYS_BASE + SYSCTL_O_TMR2CLKCTL) |= + ((uint16_t)divider << SYSCTL_TMR2CLKCTL_TMR2CLKPRESCALE_S) | + ((uint16_t)source << SYSCTL_TMR2CLKCTL_TMR2CLKSRCSEL_S); + SYSCTL_REGWRITE_DELAY; + EDIS; +} + +//***************************************************************************** +// +//! Gets the PIE Vector Fetch Error Handler Routine Address. +//! +//! The function indicates the address of the PIE Vector Fetch Error +//! handler routine. +//! +//! \return Error Handler Address. +//! +//! \note Its the responsibility of user to initialize this register. If this +//! register is not initialized, a default error handler at address +//! 0x3fffbe will get executed. +// +//***************************************************************************** +static inline uint32_t +SysCtl_getPIEVErrAddr(void) +{ + return(HWREG(CPUSYS_BASE + SYSCTL_O_PIEVERRADDR)); +} + +//***************************************************************************** +// +//! Check if the Internal PHY is present or not for the USB module +//! +//! Provides the USB module Internal PHY presence +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return \b true if Internal USB PHY Module is present \b false if +//! Internal USB PHY Module is not present +// +//***************************************************************************** +static inline bool +SysCtl_isPresentUSBPHY(void) +{ + return((HWREG(DEVCFG_BASE + SYSCTL_O_PERCNF1) & + SYSCTL_PERCNF1_USB_A_PHY) != 0U); +} + +//***************************************************************************** +// +//! Get the device UID_UNIQUE value +//! +//! This function returns the device UID_UNIQUE value +//! +//! \return Returns the device UID_UNIQUE value +// +//***************************************************************************** +static inline uint32_t +SysCtl_getDeviceUID(void) +{ + // + // Returns the device UID_UNIQUE value + // + return(HWREG(UID_BASE + OTP_O_UID_UNIQUE)); +} + +//***************************************************************************** +// +//! Delays for a fixed number of cycles. +//! +//! \param count is the number of delay loop iterations to perform. +//! +//! This function generates a constant length delay using assembly code. The +//! loop takes 5 cycles per iteration plus 9 cycles of overhead. +//! +//! \note If count is equal to zero, the loop will underflow and run for a +//! very long time. +//! +//! \note Refer to the macro DEVICE_DELAY_US(x) in device.h which can be used to +//! insert a delay in microseconds. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_delay(uint32_t count); + +//***************************************************************************** +// +//! Calculates the system clock frequency (SYSCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the system clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the PLL +//! and clock divider configuration registers. +//! +//! \return Returns the system clock frequency. If a missing clock is detected, +//! the function will return the INTOSC1 frequency. This needs to be +//! corrected and cleared (see SysCtl_resetMCD()) before trying to call this +//! function again. +// +//***************************************************************************** +extern uint32_t +SysCtl_getClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Calculates the system auxiliary clock frequency (AUXPLLCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source +//! (AUXOSCCLK). +//! +//! This function determines the frequency of the auxiliary clock based on the +//! frequency of the oscillator clock source (from \e clockInHz) and the AUXPLL +//! and clock divider configuration registers. +//! +//! \return Returns the auxiliary clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getAuxClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Configures the clocking of the device. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clocking of the device. The input crystal +//! frequency, oscillator to be used, use of the PLL, and the system clock +//! divider are all configured with this function. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with the macro \b SYSCTL_SYSDIV(x) +//! where x is either 1 or an even value up to 126. +//! +//! - The use of the PLL is chosen with either \b SYSCTL_PLL_ENABLE or +//! \b SYSCTL_PLL_DISABLE. +//! +//! - The integer multiplier is chosen \b SYSCTL_IMULT(x) where x is a value +//! from 1 to 127. +//! +//! - The fractional multiplier is chosen with either \b SYSCTL_FMULT_0, +//! \b SYSCTL_FMULT_1_4, \b SYSCTL_FMULT_1_2, or \b SYSCTL_FMULT_3_4. +//! +//! - The oscillator source chosen with \b SYSCTL_OSCSRC_OSC2, +//! \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! This function uses the watchdog as a monitor for the PLL. The user +//! watchdog settings will be modified and restored upon completion. Make sure +//! that the WDOVERRIDE bit isn't set before calling this function. Re-lock +//! attempt is carried out if either SLIP condition occurs or SYSCLK to input +//! clock ratio is off by 10%. +//! +//! This function uses the following resources to support PLL initialization: +//! - Watchdog +//! - CPU Timer 1 +//! - CPU Timer 2 +//! +//! +//! \note See your device errata for more details about locking the PLL. +//! +//! \return Returns \b false if a missing clock error is detected. This needs +//! to be cleared (see SysCtl_resetMCD()) before trying to call this function +//! again. Otherwise, returns \b true. +// +//***************************************************************************** +extern bool +SysCtl_setClock(uint32_t config); + +//***************************************************************************** +// +//! Configures the external oscillator for the clocking of the device. +//! +//! This function configures the external oscillator (XTAL) to be used for the +//! clocking of the device in crystal mode. It follows the procedure to turn on +//! the oscillator, wait for it to power up, and select it as the source of the +//! system clock. +//! +//! Please note that this function blocks while it waits for the XTAL to power +//! up. If the XTAL does not manage to power up properly, the function will +//! loop for a long time. It is recommended that you modify this function to +//! add an appropriate timeout and error-handling procedure. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectXTAL(void); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the clocking of the device. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! device. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSource(uint32_t oscSource); + +//***************************************************************************** +// +//! Selects the oscillator to be used for the AUXPLL. +//! +//! \param oscSource is the oscillator source to be configured. +//! +//! This function configures the oscillator to be used in the clocking of the +//! AUXPLL. The \e oscSource parameter may take a value of +//! \b SYSCTL_OSCSRC_OSC2, \b SYSCTL_OSCSRC_XTAL, or \b SYSCTL_OSCSRC_OSC1. +//! +//! \sa SysCtl_turnOnOsc() +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_selectOscSourceAuxPLL(uint32_t oscSource); + +//***************************************************************************** +// +//! Calculates the low-speed peripheral clock frequency (LSPCLK). +//! +//! \param clockInHz is the frequency of the oscillator clock source (OSCCLK). +//! +//! This function determines the frequency of the low-speed peripheral clock +//! based on the frequency of the oscillator clock source (from \e clockInHz) +//! and the PLL and clock divider configuration registers. +//! +//! \return Returns the low-speed peripheral clock frequency. +// +//***************************************************************************** +extern uint32_t +SysCtl_getLowSpeedClock(uint32_t clockInHz); + +//***************************************************************************** +// +//! Get the device part parametric value +//! +//! \param parametric is the requested device parametric value +//! +//! This function gets the device part parametric value. +//! +//! The \e parametric parameter can have one the following enumerated values: +//! - \b SYSCTL_DEVICE_QUAL - Device Qualification Status +//! - \b SYSCTL_DEVICE_PINCOUNT - Device Pin Count +//! - \b SYSCTL_DEVICE_INSTASPIN - Device InstaSPIN Feature Set +//! - \b SYSCTL_DEVICE_FLASH - Device Flash size (KB) +//! - \b SYSCTL_DEVICE_PARTID - Device Part ID Format Revision +//! - \b SYSCTL_DEVICE_FAMILY - Device Family +//! - \b SYSCTL_DEVICE_PARTNO - Device Part Number +//! - \b SYSCTL_DEVICE_CLASSID - Device Class ID +//! +//! \note This API is applicable only for the CPU1 subsystem. +//! +//! \return Returns the specified parametric value. +// +//***************************************************************************** +extern uint16_t +SysCtl_getDeviceParametric(SysCtl_DeviceParametric parametric); + +//***************************************************************************** +// +//! Configures the auxiliary PLL for clocking USB. +//! +//! \param config is the required configuration of the device clocking. +//! +//! This function configures the clock source for auxiliary PLL, the integer +//! multiplier, fractional multiplier and divider. +//! +//! The \e config parameter is the OR of several different values, many of +//! which are grouped into sets where only one can be chosen. +//! +//! - The system clock divider is chosen with one of the following macros: +//! \b SYSCTL_AUXPLL_DIV_1, +//! \b SYSCTL_AUXPLL_DIV_2, +//! \b SYSCTL_AUXPLL_DIV_4, +//! \b SYSCTL_AUXPLL_DIV_8 +//! +//! - The use of the PLL is chosen with either \b SYSCTL_AUXPLL_ENABLE or +//! \b SYSCTL_AUXPLL_DISABLE. +//! +//! - The integer multiplier is chosen with \b SYSCTL_AUXPLL_IMULT(x) where x +//! is a value from 1 to 127. +//! +//! - The oscillator source chosen with one of +//! \b SYSCTL_AUXPLL_OSCSRC_OSC2, +//! \b SYSCTL_AUXPLL_OSCSRC_XTAL, +//! \b SYSCTL_AUXPLL_OSCSRC_AUXCLKIN, +//! +//! \note This function uses CPU Timer 2 to monitor a successful lock of the +//! AUXPLL. For this function to properly detect the PLL startup +//! SYSCLK >= 2*AUXPLLCLK after the AUXPLL is selected as the clocking source. +//! User configuration of CPU Timer 2 will be backed up and restored. +//! \note See your device errata for more details about locking the PLL. +//! +//! \return None. +// +//***************************************************************************** +extern void +SysCtl_setAuxClock(uint32_t config); + + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//**************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // SYSCTL_H diff --git a/gpio_driverlib_cpu1/device/driverlib/upp.c b/gpio_driverlib_cpu1/device/driverlib/upp.c new file mode 100644 index 0000000..a3fb8da --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/upp.c @@ -0,0 +1,298 @@ +//########################################################################### +// +// FILE: upp.c +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include +#include +#include "upp.h" + +//***************************************************************************** +// +// UPP_setDMAReadThreshold +// +//***************************************************************************** +void +UPP_setDMAReadThreshold(uint32_t base, UPP_DMAChannel channel, + UPP_ThresholdSize size) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Set DMA read threshold for channel I. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEI_M) | + (uint16_t)size; + } + else + { + // + // Set DMA read threshold for channel Q. + // + HWREGH(base + UPP_O_THCFG) = (HWREGH(base + UPP_O_THCFG) & + ~(uint16_t)UPP_THCFG_RDSIZEQ_M) | + ((uint16_t)size << UPP_THCFG_RDSIZEQ_S); + } +} + +//***************************************************************************** +// +// UPP_setDMADescriptor +// +//***************************************************************************** +void +UPP_setDMADescriptor(uint32_t base, UPP_DMAChannel channel, + const UPP_DMADescriptor * const desc) +{ + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Sets DMA descriptors for channel I. + // + HWREG(base + UPP_O_CHIDESC0) = desc->addr; + HWREG(base + UPP_O_CHIDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHIDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHIDESC2) = desc->lineOffset; + } + else + { + // + // Sets DMA descriptors for channel Q. + // + HWREG(base + UPP_O_CHQDESC0) = desc->addr; + HWREG(base + UPP_O_CHQDESC1) = ((uint32_t)desc->byteCount | + (((uint32_t)desc->lineCount) << + UPP_CHQDESC1_LCNT_S)); + HWREGH(base + UPP_O_CHQDESC2) = desc->lineOffset; + } +} + +//***************************************************************************** +// +// UPP_getDMAChannelStatus +// +//***************************************************************************** +void +UPP_getDMAChannelStatus(uint32_t base, UPP_DMAChannel channel, + UPP_DMAChannelStatus * const status) +{ + uint32_t cntStatus; + + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the current status for channel I. + // + cntStatus = HWREG(base + UPP_O_CHIST1); + status->curAddr = HWREG(base + UPP_O_CHIST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHIDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHIDESC1_LCNT_S); + } + else + { + // + // Return the current status for channel Q. + // + cntStatus = HWREG(base + UPP_O_CHQST1); + status->curAddr = HWREG(base + UPP_O_CHQST0); + status->curByteCount = (uint16_t)(cntStatus & UPP_CHQDESC1_BCNT_M); + status->curLineCount = (uint16_t)(cntStatus >> UPP_CHQDESC1_LCNT_S); + } +} + +//***************************************************************************** +// +// UPP_isDescriptorPending +// +//***************************************************************************** +bool +UPP_isDescriptorPending(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the pend status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_PEND) == UPP_CHIST2_PEND); + } + else + { + // + // Return the pend status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_PEND) == UPP_CHQST2_PEND); + } + return(status); +} + +//***************************************************************************** +// +// UPP_isDescriptorActive +// +//***************************************************************************** +bool +UPP_isDescriptorActive(uint32_t base, UPP_DMAChannel channel) +{ + bool status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Returns active status for channel I descriptor. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_ACT) == UPP_CHIST2_ACT); + } + else + { + // + // Returns active status for channel Q descriptor. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_ACT) == UPP_CHQST2_ACT); + } + return(status); +} + +//***************************************************************************** +// +// UPP_getDMAFIFOWatermark +// +//***************************************************************************** +uint16_t +UPP_getDMAFIFOWatermark(uint32_t base, UPP_DMAChannel channel) +{ + uint16_t status; + // + // Check the arguments. + // + ASSERT(UPP_isBaseValid(base)); + if(channel == UPP_DMA_CHANNEL_I) + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHIST2) & + (uint16_t)UPP_CHIST2_WM_M) >> UPP_CHIST2_WM_S); + } + else + { + // + // Return the watermark for FIFO block count for DMA Channel I. + // + status = ((HWREGH(base + UPP_O_CHQST2) & + (uint16_t)UPP_CHQST2_WM_M) >> UPP_CHQST2_WM_S); + } + return(status); +} + +//***************************************************************************** +// +// UPP_readRxMsgRAM +// +//***************************************************************************** +void +UPP_readRxMsgRAM(uint32_t rxBase, uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isRxBaseValid(rxBase)); + ASSERT((length + offset) < UPP_RX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Read one 16-bit word. + // + array[i] = HWREGH(rxBase + offset + i); + } +} + +//***************************************************************************** +// +// UPP_writeTxMsgRAM +// +//***************************************************************************** +void +UPP_writeTxMsgRAM(uint32_t txBase, const uint16_t array[], uint16_t length, + uint16_t offset) +{ + uint16_t i; + // + // Check the arguments. + // + ASSERT(UPP_isTxBaseValid(txBase)); + ASSERT((length + offset) < UPP_TX_MSGRAM_MAX_SIZE); + + for(i = 0U; i < length; i++) + { + // + // Write one 16-bit word. + // + HWREGH(txBase + offset + i) = array[i]; + } +} diff --git a/gpio_driverlib_cpu1/device/driverlib/upp.h b/gpio_driverlib_cpu1/device/driverlib/upp.h new file mode 100644 index 0000000..128d077 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/upp.h @@ -0,0 +1,1574 @@ +//########################################################################### +// +// FILE: upp.h +// +// TITLE: C28x uPP driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef UPP_H +#define UPP_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup upp_api UPP +//! @{ +// +//***************************************************************************** + +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_upp.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Defines for the API. +// +//***************************************************************************** +//***************************************************************************** +// +// Defines that can be passed as addr field of UPP_DMADescriptor to +// UPP_setDMADescriptor(). Since the addresses for Tx & Rx MSG RAMs are +// different for CPU & DMA views, these defines can be used as DMA descriptor +// addresses. +// +//***************************************************************************** +#define UPP_DMA_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_DMA_RX_MSGRAM_STARTADDR 0x00007000U + +//***************************************************************************** +// +// Defines that can be used in user program as start address for CPU/CLA write +// to TX MSG RAM for transmitting data & for CPU/CLA read from RX MSG RAM for +// receiving data. Since the addresses for Tx & Rx MSG RAMs are different for +// CPU & DMA views, these defines can be used for CPU read/writes. +// +//***************************************************************************** +#define UPP_CPU_TX_MSGRAM_STARTADDR UPP_TX_MSG_RAM_BASE +#define UPP_CPU_RX_MSGRAM_STARTADDR UPP_RX_MSG_RAM_BASE + +//***************************************************************************** +// +// Defines to specify the size of the uPP Tx and Rx MSG RAMs. +// +//***************************************************************************** +#define UPP_TX_MSGRAM_MAX_SIZE 0x200U +#define UPP_RX_MSGRAM_MAX_SIZE 0x200U + +//***************************************************************************** +// +// Define to specify 32 cycle delay between software reset issue & release in +// UPP_performSoftReset(). +// +//***************************************************************************** +#ifndef UPP_32_CYCLE_NOP +#define UPP_32_CYCLE_NOP __asm(" RPT #31 || NOP") +#endif + +//***************************************************************************** +// +// Define to specify mask for setting emulation mode in UPP_setEmulationMode(). +// +//***************************************************************************** +#define UPP_SOFT_FREE_M ((uint16_t)UPP_PERCTL_SOFT | \ + (uint16_t)UPP_PERCTL_FREE) + +//***************************************************************************** +// +// Defines to specify masks for enabling/disabling uPP Tx/Rx control signals in +// UPP_setTxControlSignalMode() & UPP_setRxControlSignalMode() respectively. +// +//***************************************************************************** +#define UPP_TX_SIGNAL_MODE_M UPP_IFCFG_WAITA +#define UPP_RX_SIGNAL_MODE_M ((uint16_t)UPP_IFCFG_STARTA | \ + (uint16_t)UPP_IFCFG_ENAA) + +//***************************************************************************** +// +// Define to specify mask for configuring polarities for uPP control signals +// in UPP_setControlSignalPolarity(). +// +//***************************************************************************** +#define UPP_SIGNAL_POLARITY_M ((uint16_t)UPP_IFCFG_WAITPOLA | \ + (uint16_t)UPP_IFCFG_ENAPOLA | \ + (uint16_t)UPP_IFCFG_STARTPOLA) + +//***************************************************************************** +// +// Define to specify masks for returning interrupt status in +// UPP_getInterruptStatus() & UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_M ((uint16_t)UPP_ENINTST_DPEI | (uint16_t)UPP_ENINTST_UOEI | \ + (uint16_t)UPP_ENINTST_EOWI | (uint16_t)UPP_ENINTST_EOLI | \ + (uint16_t)UPP_ENINTST_DPEQ | (uint16_t)UPP_ENINTST_UOEQ | \ + (uint16_t)UPP_ENINTST_EOWQ | (uint16_t)UPP_ENINTST_EOLQ) + +//***************************************************************************** +// +// Values that can be passed to UPP_enableInterrupt(), +// UPP_disableInterrupt() and UPP_clearInterruptStatus() as the +// intFlags parameter and returned by UPP_getInterruptStatus() & +// UPP_getRawInterruptStatus(). +// +//***************************************************************************** +#define UPP_INT_CHI_DMA_PROG_ERR 0x0001U //! +#include +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "inc/hw_usb.h" +#include "debug.h" +#include "sysctl.h" +#include "usb.h" + +//***************************************************************************** +// +// Amount to shift the RX interrupt sources by in the flags used in the +// interrupt calls. +// +//***************************************************************************** +#define USB_INTEP_RX_SHIFT 16U + +//***************************************************************************** +// +// Amount to shift the RX endpoint status sources by in the flags used in the +// calls. +// +//***************************************************************************** +#define USB_RX_EPSTATUS_SHIFT 16U + +//***************************************************************************** +// +// Converts from an endpoint specifier to the offset of the endpoint's +// control/status registers. +// +//***************************************************************************** +#define EP_OFFSET(Endpoint) (Endpoint - 0x10U) + +//***************************************************************************** +// +// Sets one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// \param ui8Value is the value to write to the register. +// +// This function is used to access the indexed registers for each endpoint. +// The only registers that are indexed are the FIFO configuration registers, +// which are not used after configuration. +// +// \return None. +// +//***************************************************************************** +static void +_USBIndexWrite(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Value, uint32_t ui32Size) +{ + uint32_t ui32Index; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0U) || (ui32Endpoint == 1U) || (ui32Endpoint == 2U) || + (ui32Endpoint == 3U)); + ASSERT((ui32Size == 1U) || (ui32Size == 2U)); + + // + // Save the old index in case it was in use. + // + ui32Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1) + { + // + // Set the value. + // + HWREGB(ui32Base + ui32IndexedReg) = ui32Value; + } + else + { + // + // Set the value. + // + HWREGH(ui32Base + ui32IndexedReg) = ui32Value; + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Index; +} + +//***************************************************************************** +// +// Reads one of the indexed registers. +// +// \param ui32Base specifies the USB module base address. +// \param ui32Endpoint is the endpoint index to target for this write. +// \param ui32IndexedReg is the indexed register to write to. +// +// This function is used internally to access the indexed registers for each +// endpoint. The only registers that are indexed are the FIFO configuration +// registers, which are not used after configuration. +// +// \return The value in the register requested. +// +//***************************************************************************** +static uint32_t +_USBIndexRead(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32IndexedReg, uint32_t ui32Size) +{ + uint8_t ui8Index; + uint8_t ui8Value; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == 0) || (ui32Endpoint == 1) || (ui32Endpoint == 2) || + (ui32Endpoint == 3)); + ASSERT((ui32Size == 1) || (ui32Size == 2)); + + // + // Save the old index in case it was in use. + // + ui8Index = HWREGB(ui32Base + USB_O_EPIDX); + + // + // Set the index. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui32Endpoint; + + // + // Determine the size of the register value. + // + if(ui32Size == 1U) + { + // + // Get the value. + // + ui8Value = HWREGB(ui32Base + ui32IndexedReg); + } + else + { + // + // Get the value. + // + ui8Value = HWREGH(ui32Base + ui32IndexedReg); + } + + // + // Restore the old index in case it was in use. + // + HWREGB(ui32Base + USB_O_EPIDX) = ui8Index; + + // + // Return the register's value. + // + return(ui8Value); +} + +//***************************************************************************** +// +//! Puts the USB bus in a suspended state. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! When used in host mode, this function puts the USB bus in the suspended +//! state. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostSuspend(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send the suspend signaling to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SUSPEND; +} + +//***************************************************************************** +// +//! Handles the USB bus reset condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies whether to start or stop signaling reset on the USB +//! bus. +//! +//! When this function is called with the \e bStart parameter set to \b true, +//! this function causes the start of a reset condition on the USB bus. +//! The caller must then delay at least 20ms before calling this function +//! again with the \e bStart parameter set to \b false. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostReset(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a reset signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESET; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESET; + } +} + +//***************************************************************************** +// +//! Handles the USB bus resume condition. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if the USB controller is entering or leaving the +//! resume signaling state. +//! +//! When in device mode, this function brings the USB controller out of the +//! suspend state. This call must first be made with the \e bStart parameter +//! set to \b true to start resume signaling. The device application must +//! then delay at least 10ms but not more than 15ms before calling this +//! function with the \e bStart parameter set to \b false. +//! +//! When in host mode, this function signals devices to leave the suspend +//! state. This call must first be made with the \e bStart parameter set to +//! \b true to start resume signaling. The host application must then delay +//! at least 20ms before calling this function with the \e bStart parameter set +//! to \b false. This action causes the controller to complete the resume +//! signaling on the USB bus. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostResume(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Send a resume signal to the bus. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_RESUME; + } + else + { + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_RESUME; + } +} + +//***************************************************************************** +// +//! Returns the current speed of the USB device connected. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current speed of the USB bus in host mode. +//! +//! \b Example: Get the USB connection speed. +//! +//! \verbatim +//! // +//! // Get the connection speed of the device connected to the USB controller. +//! // +//! USBHostSpeedGet(USBA_BASE); +//! \endverbatim +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns one of the following: \b USB_LOW_SPEED, \b USB_FULL_SPEED, +//! or \b USB_UNDEF_SPEED. +// +//***************************************************************************** +uint32_t +USBHostSpeedGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If the Full Speed device bit is set, then this is a full speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_FSDEV) + { + return(USB_FULL_SPEED); + } + + // + // If the Low Speed device bit is set, then this is a low speed device. + // + if(HWREGB(ui32Base + USB_O_DEVCTL) & USB_DEVCTL_LSDEV) + { + return(USB_LOW_SPEED); + } + + // + // The device speed is not known. + // + return(USB_UNDEF_SPEED); +} + +//***************************************************************************** +// +//! Disables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to disable. +//! +//! This function disables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to disable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_INTCTRL_ALL)) == 0); + + // + // If any general interrupts were disabled then write the general interrupt + // settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) &= ~(ui32Flags & USB_INTCTRL_STATUS); + } + + // + // Disable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = 0U; + } + + // + // Disable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = 0U; + } +} + +//***************************************************************************** +// +//! Enables control interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which control interrupts to enable. +//! +//! This function enables the control interrupts for the USB controller +//! specified by the \e ui32Base parameter. The \e ui32Flags parameter +//! specifies which control interrupts to enable. The flags passed in the +//! \e ui32Flags parameters must be the definitions that start with +//! \b USB_INTCTRL_* and not any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableControl(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & (~USB_INTCTRL_ALL)) == 0U); + + // + // If any general interrupts were enabled, then write the general + // interrupt settings out to the hardware. + // + if(ui32Flags & USB_INTCTRL_STATUS) + { + HWREGB(ui32Base + USB_O_IE) |= ui32Flags; + } + + // + // Enable the power fault interrupt. + // + if(ui32Flags & USB_INTCTRL_POWER_FAULT) + { + HWREG(ui32Base + USB_O_EPCIM) = USB_EPCIM_PF; + } + + // + // Enable the ID pin detect interrupt. + // + if(ui32Flags & USB_INTCTRL_MODE_DETECT) + { + HWREG(ui32Base + USB_O_IDVIM) = USB_IDVIM_ID; + } +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32IntStatusEP is a pointer to the variable which holds the +//! endpoint interrupt status from RXIS And TXIS. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +//! This is the value of USBIS. +// +//***************************************************************************** +uint32_t +USBIntStatus(uint32_t ui32Base, uint32_t *pui32IntStatusEP) +{ + uint32_t ui32Status = 0U; + *pui32IntStatusEP = 0U; + uint32_t usbis = 0U; + uint32_t rxis = 0U; + uint32_t txis = 0U; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Do-While to make sure that all status registers are cleared before + // continuing. This eliminates the race condition which can cause the USB + // interrupt to stay high and never get triggered again. + // + do + { + // + // Get the general interrupt status. + // + usbis = (uint32_t)HWREGB(ui32Base + USB_O_IS); + + // + // Get the transmit interrupt status. + // + txis = (uint32_t)HWREGH(ui32Base + USB_O_TXIS); + + // + // Get the receive interrupt status. + // + rxis = (uint32_t)HWREGH(ui32Base + USB_O_RXIS); + + // + // Get the general interrupt status, these bits go into the lower 8 bits + // of the returned value. + // + ui32Status |= usbis; + + // + // Get the transmit interrupt status. + // + *pui32IntStatusEP |= txis; + + // + // Get the receive interrupt status, these bits go into the second byte + // of the returned value. + // + *pui32IntStatusEP |= ((uint32_t)rxis << USB_INTEP_RX_SHIFT); + + } while((usbis != 0x0000U) || (txis != 0x0000U) || (rxis != 0x0000U)); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Returns the control interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads control interrupt status for a USB controller. This +//! call returns the current status for control interrupts only, the endpoint +//! interrupt status is retrieved by calling USBIntStatusEndpoint(). The bit +//! values returned are compared against the \b USB_INTCTRL_* values. +//! +//! The following are the meanings of all \b USB_INCTRL_ flags and the modes +//! for which they are valid. These values apply to any calls to +//! USBIntStatusControl(), USBIntEnableControl(), and USBIntDisableControl(). +//! Some of these flags are only valid in the following modes as indicated in +//! the parentheses: Host, Device, and OTG. +//! +//! - \b USB_INTCTRL_ALL - A full mask of all control interrupt sources. +//! - \b USB_INTCTRL_VBUS_ERR - A VBUS error has occurred (Host Only). +//! - \b USB_INTCTRL_SESSION - Session Start Detected on A-side of cable +//! (OTG Only). +//! - \b USB_INTCTRL_SESSION_END - Session End Detected (Device Only) +//! - \b USB_INTCTRL_DISCONNECT - Device Disconnect Detected (Host Only) +//! - \b USB_INTCTRL_CONNECT - Device Connect Detected (Host Only) +//! - \b USB_INTCTRL_SOF - Start of Frame Detected. +//! - \b USB_INTCTRL_BABBLE - USB controller detected a device signaling past +//! the end of a frame (Host Only) +//! - \b USB_INTCTRL_RESET - Reset signaling detected by device (Device Only) +//! - \b USB_INTCTRL_RESUME - Resume signaling detected. +//! - \b USB_INTCTRL_SUSPEND - Suspend signaling detected by device (Device +//! Only) +//! - \b USB_INTCTRL_MODE_DETECT - OTG cable mode detection has completed +//! (OTG Only) +//! - \b USB_INTCTRL_POWER_FAULT - Power Fault detected (Host Only) +//! +//! \note This call clears the source of all of the control status interrupts. +//! +//! \return Returns the status of the control interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusControl(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the general interrupt status, these bits go into the upper 8 bits + // of the returned value. + // + ui32Status = HWREGB(ui32Base + USB_O_IS); + + // + // Add the power fault status. + // + if(HWREG(ui32Base + USB_O_EPCISC) & USB_EPCISC_PF) + { + // + // Indicate a power fault was detected. + // + ui32Status |= USB_INTCTRL_POWER_FAULT; + + // + // Clear the power fault interrupt. + // + HWREGB(ui32Base + USB_O_EPCISC) |= USB_EPCISC_PF; + } + + if(HWREG(ui32Base + USB_O_IDVISC) & USB_IDVRIS_ID) + { + // + // Indicate an id detection. + // + ui32Status |= USB_INTCTRL_MODE_DETECT; + + // + // Clear the id detection interrupt. + // + HWREG(ui32Base + USB_O_IDVISC) |= USB_IDVRIS_ID; + } + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Disables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to disable. +//! +//! This function disables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to disable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // If any transmit interrupts were disabled, then write the transmit + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_TXIE) &= + ~(ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0)); + + // + // If any receive interrupts were disabled, then write the receive + // interrupt settings out to the hardware. + // + HWREGH(ui32Base + USB_O_RXIE) &= + ~((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Enables endpoint interrupts on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies which endpoint interrupts to enable. +//! +//! This function enables endpoint interrupts for the USB controller specified +//! by the \e ui32Base parameter. The \e ui32Flags parameter specifies which +//! endpoint interrupts to enable. The flags passed in the \e ui32Flags +//! parameters must be the definitions that start with \b USB_INTEP_* and not +//! any other \b USB_INT flags. +//! +//! \return None. +// +//***************************************************************************** +void +USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable any transmit endpoint interrupts. + // + HWREGH(ui32Base + USB_O_TXIE) |= + ui32Flags & (USB_INTEP_HOST_OUT | USB_INTEP_DEV_IN | USB_INTEP_0); + + // + // Enable any receive endpoint interrupts. + // + HWREGH(ui32Base + USB_O_RXIE) |= + ((ui32Flags & (USB_INTEP_HOST_IN | USB_INTEP_DEV_OUT)) >> + USB_INTEP_RX_SHIFT); +} + +//***************************************************************************** +// +//! Returns the endpoint interrupt status on a given USB controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function reads endpoint interrupt status for a USB controller. This +//! call returns the current status for endpoint interrupts only, the control +//! interrupt status is retrieved by calling USBIntStatusControl(). The bit +//! values returned are compared against the \b USB_INTEP_* values. +//! These values are grouped into classes for \b USB_INTEP_HOST_* and +//! \b USB_INTEP_DEV_* values to handle both host and device modes with all +//! endpoints. +//! +//! \note This call clears the source of all of the endpoint interrupts. +//! +//! \return Returns the status of the endpoint interrupts for a USB controller. +// +//***************************************************************************** +uint32_t +USBIntStatusEndpoint(uint32_t ui32Base) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Get the transmit interrupt status. + // + ui32Status = HWREGH(ui32Base + USB_O_TXIS); + ui32Status |= ((uint32_t)HWREGH(ui32Base + USB_O_RXIS) << + USB_INTEP_RX_SHIFT); + + // + // Return the combined interrupt status. + // + return(ui32Status); +} + + +//***************************************************************************** +// +//! Returns the current status of an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the status of a given endpoint. If any of these +//! status bits must be cleared, then the USBDevEndpointStatusClear() or the +//! USBHostEndpointStatusClear() functions must be called. +//! +//! The following are the status flags for host mode: +//! +//! - \b USB_HOST_IN_PID_ERROR - PID error on the given endpoint. +//! - \b USB_HOST_IN_NOT_COMP - The device failed to respond to an IN request. +//! - \b USB_HOST_IN_STALL - A stall was received on an IN endpoint. +//! - \b USB_HOST_IN_DATA_ERROR - There was a CRC or bit-stuff error on an IN +//! endpoint in Isochronous mode. +//! - \b USB_HOST_IN_NAK_TO - NAKs received on this IN endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_IN_ERROR - Failed to communicate with a device using this IN +//! endpoint. +//! - \b USB_HOST_IN_FIFO_FULL - This IN endpoint's FIFO is full. +//! - \b USB_HOST_IN_PKTRDY - Data packet ready on this IN endpoint. +//! - \b USB_HOST_OUT_NAK_TO - NAKs received on this OUT endpoint for more than +//! the specified timeout period. +//! - \b USB_HOST_OUT_NOT_COMP - The device failed to respond to an OUT +//! request. +//! - \b USB_HOST_OUT_STALL - A stall was received on this OUT endpoint. +//! - \b USB_HOST_OUT_ERROR - Failed to communicate with a device using this +//! OUT endpoint. +//! - \b USB_HOST_OUT_FIFO_NE - This endpoint's OUT FIFO is not empty. +//! - \b USB_HOST_OUT_PKTPEND - The data transfer on this OUT endpoint has not +//! completed. +//! - \b USB_HOST_EP0_NAK_TO - NAKs received on endpoint zero for more than the +//! specified timeout period. +//! - \b USB_HOST_EP0_ERROR - The device failed to respond to a request on +//! endpoint zero. +//! - \b USB_HOST_EP0_IN_STALL - A stall was received on endpoint zero for an +//! IN transaction. +//! - \b USB_HOST_EP0_IN_PKTRDY - Data packet ready on endpoint zero for an IN +//! transaction. +//! +//! The following are the status flags for device mode: +//! +//! - \b USB_DEV_OUT_SENT_STALL - A stall was sent on this OUT endpoint. +//! - \b USB_DEV_OUT_DATA_ERROR - There was a CRC or bit-stuff error on an OUT +//! endpoint. +//! - \b USB_DEV_OUT_OVERRUN - An OUT packet was not loaded due to a full FIFO. +//! - \b USB_DEV_OUT_FIFO_FULL - The OUT endpoint's FIFO is full. +//! - \b USB_DEV_OUT_PKTRDY - There is a data packet ready in the OUT +//! endpoint's FIFO. +//! - \b USB_DEV_IN_NOT_COMP - A larger packet was split up, more data to come. +//! - \b USB_DEV_IN_SENT_STALL - A stall was sent on this IN endpoint. +//! - \b USB_DEV_IN_UNDERRUN - Data was requested on the IN endpoint and no +//! data was ready. +//! - \b USB_DEV_IN_FIFO_NE - The IN endpoint's FIFO is not empty. +//! - \b USB_DEV_IN_PKTPEND - The data transfer on this IN endpoint has not +//! completed. +//! - \b USB_DEV_EP0_SETUP_END - A control transaction ended before Data End +//! condition was sent. +//! - \b USB_DEV_EP0_SENT_STALL - A stall was sent on endpoint zero. +//! - \b USB_DEV_EP0_IN_PKTPEND - The data transfer on endpoint zero has not +//! completed. +//! - \b USB_DEV_EP0_OUT_PKTRDY - There is a data packet ready in endpoint +//! zero's OUT FIFO. +//! +//! \return The current status flags for the endpoint depending on mode. +// +//***************************************************************************** +uint32_t +USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Status; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the TX portion of the endpoint status. + // + ui32Status = HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1); + + // + // Get the RX portion of the endpoint status. + // + ui32Status |= + (((uint32_t)HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1)) + << USB_RX_EPSTATUS_SHIFT); + + // + // Return the endpoint status. + // + return(ui32Status); +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear the specified flags for the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~ui32Flags; + } + else + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~ui32Flags; + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Clears the status bits in this endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags are the status bits that are cleared. +//! +//! This function clears the status of any bits that are passed in the +//! \e ui32Flags parameter. The \e ui32Flags parameter can take the value +//! returned from the USBEndpointStatus() call. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // If this is endpoint 0, then the bits have different meaning and map + // into the TX memory location. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the Serviced RxPktRdy bit to clear the RxPktRdy. + // + if(ui32Flags & USB_DEV_EP0_OUT_PKTRDY) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_RXRDYC; + } + + // + // Set the serviced Setup End bit to clear the SetupEnd status. + // + if(ui32Flags & USB_DEV_EP0_SETUP_END) + { + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_SETENDC; + } + + // + // Clear the Sent Stall status flag. + // + if(ui32Flags & USB_DEV_EP0_SENT_STALL) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~(USB_DEV_EP0_SENT_STALL); + } + } + else + { + // + // Clear out any TX flags that were passed in. Only + // USB_DEV_TX_SENT_STALL and USB_DEV_TX_UNDERRUN must be cleared. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(ui32Flags & (USB_DEV_TX_SENT_STALL | USB_DEV_TX_UNDERRUN)); + + // + // Clear out valid RX flags that were passed in. Only + // USB_DEV_RX_SENT_STALL, USB_DEV_RX_DATA_ERROR, and USB_DEV_RX_OVERRUN + // must be cleared. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~((ui32Flags & (USB_DEV_RX_SENT_STALL | USB_DEV_RX_DATA_ERROR | + USB_DEV_RX_OVERRUN)) >> USB_RX_EPSTATUS_SHIFT); + } +} + +//***************************************************************************** +// +//! Sets the value data toggle on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param bDataToggle specifies whether to set the state to DATA0 or DATA1. +//! \param ui32Flags specifies whether to set the IN or OUT endpoint. +//! +//! This function is used to force the state of the data toggle in host mode. +//! If the value passed in the \e bDataToggle parameter is \b false, then the +//! data toggle is set to the DATA0 state, and if it is \b true it is set to +//! the DATA1 state. The \e ui32Flags parameter can be \b USB_EP_HOST_IN or +//! \b USB_EP_HOST_OUT to access the desired portion of this endpoint. The +//! \e ui32Flags parameter is ignored for endpoint zero. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags) +{ + uint32_t ui32DataToggle; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // The data toggle defaults to DATA0. + // + ui32DataToggle = 0; + + // + // See if the data toggle must be set to DATA1. + // + if(bDataToggle) + { + // + // Select the data toggle bit based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32DataToggle = USB_CSRH0_DT; + } + else if(ui32Flags == USB_EP_HOST_IN) + { + ui32DataToggle = USB_RXCSRH1_DT; + } + else + { + ui32DataToggle = USB_TXCSRH1_DT; + } + } + + // + // Set the data toggle based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the write enable and the bit value for endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRH0) = + ((HWREGB(ui32Base + USB_O_CSRH0) & + ~(USB_CSRH0_DTWE | USB_CSRH0_DT)) | + (ui32DataToggle | USB_CSRH0_DTWE)); + } + else if(ui32Flags == USB_EP_HOST_IN) + { + // + // Set the Write enable and the bit value for an IN endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_RXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_RXCSRH1_DTWE | USB_RXCSRH1_DT)) | + (ui32DataToggle | USB_RXCSRH1_DTWE)); + } + else + { + // + // Set the Write enable and the bit value for an OUT endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) = + ((HWREGB(ui32Base + USB_O_TXCSRH1 + EP_OFFSET(ui32Endpoint)) & + ~(USB_TXCSRH1_DTWE | USB_TXCSRH1_DT)) | + (ui32DataToggle | USB_TXCSRH1_DTWE)); + } +} + +//***************************************************************************** +// +//! Sets the data toggle on an endpoint to zero. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to reset the data toggle. +//! \param ui32Flags specifies whether to access the IN or OUT endpoint. +//! +//! This function causes the USB controller to clear the data toggle for an +//! endpoint. This call is not valid for endpoint zero and can be made with +//! host or device controllers. +//! +//! The \e ui32Flags parameter must be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDataToggleClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive data toggle must be cleared. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Stalls the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies the endpoint to stall. +//! \param ui32Flags specifies whether to stall the IN or OUT endpoint. +//! +//! This function causes the endpoint number passed in to go into a stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is issued on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is issued on the OUT portion +//! of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine how to stall this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Perform a stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) |= USB_CSRL0_STALL | USB_CSRL0_RXRDYC; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Perform a stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_STALL; + } + else + { + // + // Perform a stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_STALL; + } +} + +//***************************************************************************** +// +//! Clears the stall condition on the specified endpoint in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint to remove the stall condition. +//! \param ui32Flags specifies whether to remove the stall condition from the +//! IN or the OUT portion of this endpoint. +//! +//! This function causes the endpoint number passed in to exit the stall +//! condition. If the \e ui32Flags parameter is \b USB_EP_DEV_IN, then the +//! stall is cleared on the IN portion of this endpoint. If the \e ui32Flags +//! parameter is \b USB_EP_DEV_OUT, then the stall is cleared on the OUT +//! portion of this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + ASSERT((ui32Flags & ~(USB_EP_DEV_IN | USB_EP_DEV_OUT)) == 0U); + + // + // Determine how to clear the stall on this endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear the stall on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_STALLED; + } + else if(ui32Flags == USB_EP_DEV_IN) + { + // + // Clear the stall on an IN endpoint. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_CLRDT; + } + else + { + // + // Clear the stall on an OUT endpoint. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + + // + // Reset the data toggle. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Connects the USB controller to the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! be enabled. Call USBDevDisconnect() to remove the USB device from the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevConnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_SOFTCONN; +} + +//***************************************************************************** +// +//! Removes the USB controller from the bus in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function causes the soft connect feature of the USB controller to +//! remove the device from the USB bus. A call to USBDevConnect() is needed to +//! reconnect to the bus. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevDisconnect(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable connection to the USB bus. + // + HWREGB(ui32Base + USB_O_POWER) &= (~USB_POWER_SOFTCONN); +} + +//***************************************************************************** +// +//! Sets the address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Address is the address to use for a device. +//! +//! This function configures the device address on the USB bus. This address +//! was likely received via a SET ADDRESS command from the host controller. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the function address in the correct location. + // + HWREGB(ui32Base + USB_O_FADDR) = (uint8_t)ui32Address; +} + +//***************************************************************************** +// +//! Returns the current device address in device mode. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current device address. This address was set +//! by a call to USBDevAddrSet(). +//! +//! \note This function must only be called in device mode. +//! +//! \return The current device address. +// +//***************************************************************************** +uint32_t +USBDevAddrGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the function address. + // + return(HWREGB(ui32Base + USB_O_FADDR)); +} + +//***************************************************************************** +// +//! Sets the base configuration for a host endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPayload is the maximum payload for this endpoint. +//! \param ui32NAKPollInterval is the either the NAK timeout limit or the +//! polling interval, depending on the type of endpoint. +//! \param ui32TargetEndpoint is the endpoint that the host endpoint is +//! targeting. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for the transmit or receive +//! portion of an endpoint in host mode. The \e ui32Flags parameter determines +//! some of the configuration while the other parameters provide the rest. The +//! \e ui32Flags parameter determines whether this is an IN endpoint +//! (\b USB_EP_HOST_IN or \b USB_EP_DEV_IN) or an OUT endpoint +//! (\b USB_EP_HOST_OUT or \b USB_EP_DEV_OUT), whether this is a Full speed +//! endpoint (\b USB_EP_SPEED_FULL) or a Low speed endpoint +//! (\b USB_EP_SPEED_LOW). +//! +//! The \b USB_EP_MODE_ flags control the type of the endpoint. +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \e ui32NAKPollInterval parameter has different meanings based on the +//! \b USB_EP_MODE value and whether or not this call is being made for +//! endpoint zero or another endpoint. For endpoint zero or any Bulk +//! endpoints, this value always indicates the number of frames to allow a +//! device to NAK before considering it a timeout. If this endpoint is an +//! isochronous or interrupt endpoint, this value is the polling interval for +//! this endpoint. +//! +//! For interrupt endpoints, the polling interval is the number of frames +//! between interrupt IN requests to an endpoint and has a range of 1 to 255. +//! For isochronous endpoints this value represents a polling interval of +//! 2 ^ (\e ui32NAKPollInterval - 1) frames. When used as a NAK timeout, the +//! \e ui32NAKPollInterval value specifies 2 ^ (\e ui32NAKPollInterval - 1) +//! frames before issuing a time out. +//! +//! The \b USB_EP_DMA_MODE_ flags enable the type of DMA used to access the +//! endpoint's data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring the OUT portion of an endpoint, the \b USB_EP_AUTO_SET bit +//! is specified to cause the transmission of data on the USB bus to start +//! as soon as the number of bytes specified by \e ui32MaxPayload has been +//! written into the OUT FIFO for this endpoint. +//! +//! When configuring the IN portion of an endpoint, the \b USB_EP_AUTO_REQUEST +//! bit can be specified to trigger the request for more data once the FIFO has +//! been drained enough to fit \e ui32MaxPayload bytes. The +//! \b USB_EP_AUTO_CLEAR bit can be used to clear the data packet ready flag +//! automatically once the data has been read from the FIFO. If this option is +//! not used, this flag must be manually cleared via a call to +//! USBDevEndpointStatusClear() or USBHostEndpointStatusClear(). +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPayload, uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero is configured differently than the other endpoints, so see + // if this is endpoint zero. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Set the NAK timeout. + // + HWREGB(ui32Base + USB_O_NAKLMT) = ui32NAKPollInterval; + + // + // Set the transfer type information. + // + HWREGB(ui32Base + USB_O_TYPE0) = + ((ui32Flags & USB_EP_SPEED_FULL) ? USB_TYPE0_SPEED_FULL : + USB_TYPE0_SPEED_LOW); + } + else + { + // + // Start with the target endpoint. + // + ui32Register = ui32TargetEndpoint; + + // + // Set the speed for the device using this endpoint. + // + if(ui32Flags & USB_EP_SPEED_FULL) + { + ui32Register |= USB_TXTYPE1_SPEED_FULL; + } + else + { + ui32Register |= USB_TXTYPE1_SPEED_LOW; + } + + // + // Set the protocol for the device using this endpoint. + // + switch(ui32Flags & USB_EP_MODE_MASK) + { + // + // The bulk protocol is being used. + // + case USB_EP_MODE_BULK: + { + ui32Register |= USB_TXTYPE1_PROTO_BULK; + break; + } + + // + // The isochronous protocol is being used. + // + case USB_EP_MODE_ISOC: + { + ui32Register |= USB_TXTYPE1_PROTO_ISOC; + break; + } + + // + // The interrupt protocol is being used. + // + case USB_EP_MODE_INT: + { + ui32Register |= USB_TXTYPE1_PROTO_INT; + break; + } + + // + // The control protocol is being used. + // + case USB_EP_MODE_CTRL: + { + ui32Register |= USB_TXTYPE1_PROTO_CTRL; + break; + } + } + + // + // See if the transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPayload; + + // + // Set the transmit control value to zero. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been + // loaded into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Write out the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + } + else + { + // + // Set the transfer type information. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXTYPE1) = + ui32Register; + + // + // Set the NAK timeout or polling interval. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXINTERVAL1) = + ui32NAKPollInterval; + + // + // Set the Maximum Payload per transaction. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPayload; + + // + // Set the receive control value to zero. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register |= USB_RXCSRH1_AUTOCL; + } + + // + // Allow auto generation of DMA requests. + // + if(ui32Flags & USB_EP_AUTO_REQUEST) + { + ui32Register |= USB_RXCSRH1_AUTORQ; + } + + // + // Configure the DMA Mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Write out the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + } + } +} + +//***************************************************************************** +// +//! Sets the configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32MaxPacketSize is the maximum packet size for this endpoint. +//! \param ui32Flags are used to configure other endpoint settings. +//! +//! This function sets the basic configuration for an endpoint in device mode. +//! Endpoint zero does not have a dynamic configuration, so this function +//! must not be called for endpoint zero. The \e ui32Flags parameter +//! determines some of the configuration while the other parameters provide the +//! rest. +//! +//! The \b USB_EP_MODE_ flags define what the type is for the given endpoint. +//! +//! - \b USB_EP_MODE_CTRL is a control endpoint. +//! - \b USB_EP_MODE_ISOC is an isochronous endpoint. +//! - \b USB_EP_MODE_BULK is a bulk endpoint. +//! - \b USB_EP_MODE_INT is an interrupt endpoint. +//! +//! The \b USB_EP_DMA_MODE_ flags determine the type of DMA access to the +//! endpoint data FIFOs. The choice of the DMA mode depends on how the DMA +//! controller is configured and how it is being used. See the ``Using USB +//! with the uDMA Controller'' section for more information on DMA +//! configuration. +//! +//! When configuring an IN endpoint, the \b USB_EP_AUTO_SET bit can be +//! specified to cause the automatic transmission of data on the USB bus as +//! soon as \e ui32MaxPacketSize bytes of data are written into the FIFO for +//! this endpoint. This option is commonly used with DMA as no interaction is +//! required to start the transmission of data. +//! +//! When configuring an OUT endpoint, the \b USB_EP_AUTO_REQUEST bit is +//! specified to trigger the request for more data once the FIFO has been +//! drained enough to receive \e ui32MaxPacketSize more bytes of data. Also +//! for OUT endpoints, the \b USB_EP_AUTO_CLEAR bit can be used to clear the +//! data packet ready flag automatically once the data has been read from the +//! FIFO. If this option is not used, this flag must be manually cleared via a +//! call to USBDevEndpointStatusClear(). Both of these settings can be used to +//! remove the need for extra calls when using the controller in DMA mode. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, uint32_t ui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // Determine if a transmit or receive endpoint is being configured. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Set the maximum packet size. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXMAXP1) = + ui32MaxPacketSize; + + // + // The transmit control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if(ui32Flags & USB_EP_AUTO_SET) + { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_TXCSRH1_ISO; + } + + // + // Write the transmit control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRL1) = + USB_TXCSRL1_CLRDT; + } + else + { + // + // Set the MaxPacketSize. + // + HWREGH(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXMAXP1) = + ui32MaxPacketSize; + + // + // The receive control value is zero unless options are enabled. + // + ui32Register = 0; + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if(ui32Flags & USB_EP_AUTO_CLEAR) + { + ui32Register = USB_RXCSRH1_AUTOCL; + } + + // + // Configure the DMA mode. + // + if(ui32Flags & USB_EP_DMA_MODE_1) + { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } + else if(ui32Flags & USB_EP_DMA_MODE_0) + { + ui32Register |= USB_RXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if((ui32Flags & USB_EP_MODE_MASK) == USB_EP_MODE_ISOC) + { + ui32Register |= USB_RXCSRH1_ISO; + } + + // + // Write the receive control value. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + (uint8_t)ui32Register; + + // + // Reset the Data toggle to zero. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRL1) = + USB_RXCSRL1_CLRDT; + } +} + +//***************************************************************************** +// +//! Gets the current configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32MaxPacketSize is a pointer which is written with the maximum +//! packet size for this endpoint. +//! \param pui32Flags is a pointer which is written with the current endpoint +//! settings. On entry to the function, this pointer must contain either +//! \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT to indicate whether the IN or OUT +//! endpoint is to be queried. +//! +//! This function returns the basic configuration for an endpoint in device +//! mode. The values returned in \e *pui32MaxPacketSize and \e *pui32Flags are +//! equivalent to the \e ui32MaxPacketSize and \e ui32Flags previously passed +//! to USBDevEndpointConfigSet() for this endpoint. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, uint32_t *pui32Flags) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT(pui32MaxPacketSize && pui32Flags); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + if((pui32Flags != NULL) && (pui32MaxPacketSize != NULL)) + { + + // + // Determine if a transmit or receive endpoint is being queried. + // + if(*pui32Flags & USB_EP_DEV_IN) + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_IN; + + // + // Get the maximum packet size. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_TXMAXP1); + + // + // Get the current transmit control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_TXCSRH1); + + // + // Are we allowing auto setting of TxPktRdy when max packet size + // has been loaded into the FIFO? + // + if(ui32Register & USB_TXCSRH1_AUTOSET) + { + *pui32Flags |= USB_EP_AUTO_SET; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_TXCSRH1_DMAEN) + { + if(ui32Register & USB_TXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_TXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change. If they decode the returned mode, however, they + // may be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + else + { + // + // Clear the flags other than the direction bit. + // + *pui32Flags = USB_EP_DEV_OUT; + + // + // Get the MaxPacketSize. + // + *pui32MaxPacketSize = (uint32_t)HWREGH(ui32Base + + EP_OFFSET(ui32Endpoint) + + USB_O_RXMAXP1); + + // + // Get the current receive control register value. + // + ui32Register = (uint32_t)HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + + USB_O_RXCSRH1); + + // + // Are we allowing auto clearing of RxPktRdy when packet of size + // max packet has been unloaded from the FIFO? + // + if(ui32Register & USB_RXCSRH1_AUTOCL) + { + *pui32Flags |= USB_EP_AUTO_CLEAR; + } + + // + // Get the DMA mode. + // + if(ui32Register & USB_RXCSRH1_DMAEN) + { + if(ui32Register & USB_RXCSRH1_DMAMOD) + { + *pui32Flags |= USB_EP_DMA_MODE_1; + } + else + { + *pui32Flags |= USB_EP_DMA_MODE_0; + } + } + + // + // Are we in isochronous mode? + // + if(ui32Register & USB_RXCSRH1_ISO) + { + *pui32Flags |= USB_EP_MODE_ISOC; + } + else + { + // + // The hardware doesn't differentiate between bulk, interrupt + // and control mode for the endpoint so we just set something + // that isn't isochronous. This protocol ensures that anyone + // modifying the returned flags in preparation for a call to + // USBDevEndpointConfigSet do not see an unexpected mode + // change.If they decode the returned mode, however, they may + // be in for a surprise. + // + *pui32Flags |= USB_EP_MODE_BULK; + } + } + } +} + +//***************************************************************************** +// +//! Sets the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32FIFOAddress is the starting address for the FIFO. +//! \param ui32FIFOSize is the size of the FIFO specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to set in the FIFO +//! configuration. +//! +//! This function configures the starting FIFO RAM address and size of the FIFO +//! for a given endpoint. Endpoint zero does not have a dynamically +//! configurable FIFO, so this function must not be called for endpoint zero. +//! The \e ui32FIFOSize parameter must be one of the values in the +//! \b USB_FIFO_SZ_ values. +//! +//! The \e ui32FIFOAddress value must be a multiple of 8 bytes and directly +//! indicates the starting address in the USB controller's FIFO RAM. For +//! example, a value of 64 indicates that the FIFO starts 64 bytes into +//! the USB controller's FIFO memory. The \e ui32Flags value specifies whether +//! the endpoint's OUT or IN FIFO must be configured. If in host mode, use +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, use +//! \b USB_EP_DEV_OUT or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Set the transmit FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_TXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } + else + { + // + // Set the receive FIFO location and size for this endpoint. + // + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOSZ, + ui32FIFOSize, 1U); + _USBIndexWrite(ui32Base, ui32Endpoint >> 4U, USB_O_RXFIFOADD, + ui32FIFOAddress >> 3U, 2U); + } +} + +//***************************************************************************** +// +//! Returns the FIFO configuration for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui32FIFOAddress is the starting address for the FIFO. +//! \param pui32FIFOSize is the size of the FIFO as specified by one of the +//! USB_FIFO_SZ_ values. +//! \param ui32Flags specifies what information to retrieve from the FIFO +//! configuration. +//! +//! This function returns the starting address and size of the FIFO for a +//! given endpoint. Endpoint zero does not have a dynamically configurable +//! FIFO, so this function must not be called for endpoint zero. The +//! \e ui32Flags parameter specifies whether the endpoint's OUT or IN FIFO must +//! be read. If in host mode, the \e ui32Flags parameter must be +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN, and if in device mode, the +//! \e ui32Flags parameter must be either \b USB_EP_DEV_OUT or +//! \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, uint32_t *pui32FIFOSize, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive FIFO is being configured. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Get the transmit FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_TXFIFOSZ, 1U); + } + else + { + // + // Get the receive FIFO location and size for this endpoint. + // + *pui32FIFOAddress = (_USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOADD, + 2U)) << 3U; + *pui32FIFOSize = _USBIndexRead(ui32Base, ui32Endpoint >> 4U, + (uint32_t)USB_O_RXFIFOSZ, 1U); + } +} + +//***************************************************************************** +// +//! Configure the DMA settings for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Config specifies the configuration options for an endpoint. +//! +//! This function configures the DMA settings for a given endpoint without +//! changing other options that may already be configured. In order for the +//! DMA transfer to be enabled, the USBEndpointDMAEnable() function must be +//! called before starting the DMA transfer. The configuration +//! options are passed in the \e ui32Config parameter and can have the values +//! described below. +//! +//! One of the following values to specify direction: +//! - \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN - This setting is used with +//! DMA transfers from memory to the USB controller. +//! - \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT - This setting is used with +//! DMA transfers from the USB controller to memory. +//! +//! One of the following values: +//! - \b USB_EP_DMA_MODE_0(default) - This setting is typically used for +//! transfers that do not span multiple packets or when interrupts are +//! required for each packet. +//! - \b USB_EP_DMA_MODE_1 - This setting is typically used for +//! transfers that span multiple packets and do not require interrupts +//! between packets. +//! +//! Values only used with \b USB_EP_HOST_OUT or \b USB_EP_DEV_IN: +//! - \b USB_EP_AUTO_SET - This setting is used to allow transmit DMA transfers +//! to automatically be sent when a full packet is loaded into a FIFO. +//! This is needed with \b USB_EP_DMA_MODE_1 to ensure that packets go +//! out when the FIFO becomes full and the DMA has more data to send. +//! +//! Values only used with \b USB_EP_HOST_IN or \b USB_EP_DEV_OUT: +//! - \b USB_EP_AUTO_CLEAR - This setting is used to allow receive DMA +//! transfers to automatically be acknowledged as they are received. This is +//! needed with \b USB_EP_DMA_MODE_1 to ensure that packets continue to +//! be received and acknowledged when the FIFO is emptied by the DMA +//! transfer. +//! +//! Values only used with \b USB_EP_HOST_IN: +//! - \b USB_EP_AUTO_REQUEST - This setting is used to allow receive DMA +//! transfers to automatically request a new IN transaction when the +//! previous transfer has emptied the FIFO. This is typically used in +//! conjunction with \b USB_EP_AUTO_CLEAR so that receive DMA transfers +//! can continue without interrupting the main processor. +//! +//! \b Example: Set endpoint 1 receive endpoint to automatically acknowledge +//! request and automatically generate a new IN request in host mode. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for receiving multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_1, USB_EP_HOST_IN | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_CLEAR | +//! USB_EP_AUTO_REQUEST); +//! \endverbatim +//! +//! \b Example: Set endpoint 2 transmit endpoint to automatically send each +//! packet in host mode when spanning multiple packets. +//! +//! \verbatim +//! // +//! // Configure endpoint 1 for transmitting multiple packets using DMA. +//! // +//! USBEndpointDMAConfigSet(USBA_BASE, USB_EP_2, USB_EP_HOST_OUT | +//! USB_EP_DMA_MODE_1 | +//! USB_EP_AUTO_SET); +//! \endverbatim +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config) +{ + uint32_t ui32NewConfig; + + if(ui32Config & USB_EP_HOST_OUT) + { + // + // Clear mode and DMA enable. + // + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) & + ~(USB_TXCSRH1_DMAMOD | USB_TXCSRH1_AUTOSET)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_TXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_SET) + { + ui32NewConfig |= USB_TXCSRH1_AUTOSET; + } + + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) = + ui32NewConfig; + } + else + { + ui32NewConfig = + (HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) & + ~(USB_RXCSRH1_AUTORQ | USB_RXCSRH1_AUTOCL | USB_RXCSRH1_DMAMOD)); + + if(ui32Config & USB_EP_DMA_MODE_1) + { + ui32NewConfig |= USB_RXCSRH1_DMAMOD; + } + + if(ui32Config & USB_EP_AUTO_CLEAR) + { + ui32NewConfig |= USB_RXCSRH1_AUTOCL; + } + if(ui32Config & USB_EP_AUTO_REQUEST) + { + ui32NewConfig |= USB_RXCSRH1_AUTORQ; + } + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) = + ui32NewConfig; + } +} + +//***************************************************************************** +// +//! Enable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction and what mode to use when +//! enabling DMA. +//! +//! This function enables DMA on a given endpoint and configures the mode +//! according to the values in the \e ui32Flags parameter. The \e ui32Flags +//! parameter must have \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT set. Once this +//! function is called the only DMA or error interrupts are generated by the +//! USB controller. +//! +//! \note If this function is called when an endpoint is configured in DMA +//! mode 0 the USB controller does not generate an interrupt. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // See if the transmit DMA is being enabled. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Enable DMA on the transmit endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) |= + USB_TXCSRH1_DMAEN; + } + else + { + // + // Enable DMA on the receive endpoint. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) |= + USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Disable DMA on a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies which direction to disable. +//! +//! This function disables DMA on a given endpoint to allow non-DMA USB +//! transactions to generate interrupts normally. The \e ui32Flags parameter +//! must be \b USB_EP_DEV_IN or \b USB_EP_DEV_OUT; all other bits are ignored. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags) +{ + // + // If this was a request to disable DMA on the IN portion of the endpoint + // then handle it. + // + if(ui32Flags & USB_EP_DEV_IN) + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_TXCSRH1) &= + ~USB_TXCSRH1_DMAEN; + } + else + { + // + // Just disable DMA leave the mode setting. + // + HWREGB(ui32Base + EP_OFFSET(ui32Endpoint) + USB_O_RXCSRH1) &= + ~USB_RXCSRH1_DMAEN; + } +} + +//***************************************************************************** +// +//! Determine the number of bytes of data available in a given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function returns the number of bytes of data currently available in +//! the FIFO for the given receive (OUT) endpoint. It may be used prior to +//! calling USBEndpointDataGet() to determine the size of buffer required to +//! hold the newly-received packet. +//! +//! \return This call returns the number of bytes available in a given endpoint +//! FIFO. +// +//***************************************************************************** +uint32_t +USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Is there a packet ready in the FIFO? + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + return(0); + } + + // + // Return the byte count in the FIFO. + // + return(HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint)); +} + +//***************************************************************************** +// +//! Retrieves data from the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used to return the data from +//! the FIFO. +//! \param pui32Size is initially the size of the buffer passed into this call +//! via the \e pui8Data parameter. It is set to the amount of data returned in +//! the buffer. +//! +//! This function returns the data from the FIFO for the given endpoint. +//! The \e pui32Size parameter indicates the size of the buffer passed in +//! the \e pui32Data parameter. The data in the \e pui32Size parameter is +//! changed to match the amount of data returned in the \e pui8Data parameter. +//! If a zero-byte packet is received, this call does not return an error but +//! instead just returns a zero in the \e pui32Size parameter. The only error +//! case occurs when there is no data packet available. +//! +//! \return This call returns 0, or -1 if no packet was received. +// +//***************************************************************************** +int32_t +USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size) +{ + uint32_t ui32Register, ui32ByteCount, ui32FIFO; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the address of the receive status register to use, based on the + // endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Don't allow reading of data if the RxPktRdy bit is not set. + // + if((HWREGH(ui32Base + ui32Register) & USB_CSRL0_RXRDY) == 0) + { + // + // Can't read the data because none is available. + // + *pui32Size = 0; + + // + // Return a failure since there is no data to read. + // + return(-1); + } + + // + // Get the byte count in the FIFO. + // + ui32ByteCount = HWREGH(ui32Base + USB_O_COUNT0 + ui32Endpoint); + + // + // Determine how many bytes are copied. + // + ui32ByteCount = (ui32ByteCount < *pui32Size) ? ui32ByteCount : *pui32Size; + + // + // Return the number of bytes we are going to read. + // + *pui32Size = ui32ByteCount; + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Read the data out of the FIFO. + // + for(; ui32ByteCount > 0; ui32ByteCount--) + { + // + // Read a byte at a time from the FIFO. + // + *pui8Data++ = HWREGB(ui32FIFO); + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in device +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param bIsLastPacket indicates if this packet is the last one. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! The \e bIsLastPacket parameter is set to a \b true value if this is the +//! last in a series of data packets on endpoint zero. The \e bIsLastPacket +//! parameter is not used for endpoints other than endpoint zero. This call +//! can be used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in device mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Determine which endpoint is being acked. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Clear RxPktRdy, and optionally DataEnd, on endpoint zero. + // + HWREGB(ui32Base + USB_O_CSRL0) = + USB_CSRL0_RXRDYC | (bIsLastPacket ? USB_CSRL0_DATAEND : 0U); + } + else + { + // + // Clear RxPktRdy on all other endpoints. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Acknowledge that data was read from the given endpoint's FIFO in host +//! mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function acknowledges that the data was read from the endpoint's FIFO. +//! This call is used if processing is required between reading the data and +//! acknowledging that the data has been read. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Clear RxPktRdy. + // + if(ui32Endpoint == USB_EP_0) + { + HWREGB(ui32Base + USB_O_CSRL0) &= ~USB_CSRL0_RXRDY; + } + else + { + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) &= + ~(USB_RXCSRL1_RXRDY); + } +} + +//***************************************************************************** +// +//! Puts data into the given endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param pui8Data is a pointer to the data area used as the source for the +//! data to put into the FIFO. +//! \param ui32Size is the amount of data to put into the FIFO. +//! +//! This function puts the data from the \e pui8Data parameter into the FIFO +//! for this endpoint. If a packet is already pending for transmission, then +//! this call does not put any of the data into the FIFO and returns -1. Care +//! must be taken to not write more data than can fit into the FIFO +//! allocated by the call to USBFIFOConfigSet(). +//! +//! \return This call returns 0 on success, or -1 to indicate that the FIFO +//! is in use and cannot be written. +// +//***************************************************************************** +int32_t +USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size) +{ + uint32_t ui32FIFO; + uint8_t ui8TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + ui8TxPktRdy = USB_CSRL0_TXRDY; + } + else + { + ui8TxPktRdy = USB_TXCSRL1_TXRDY; + } + + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & ui8TxPktRdy) + { + return(-1); + } + + // + // Calculate the FIFO address. + // + ui32FIFO = ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2); + + // + // Write the data to the FIFO. + // + for(; ui32Size > 0U; ui32Size--) + { + HWREGB(ui32FIFO) = *pui8Data++; + } + + // + // Success. + // + return(0); +} + +//***************************************************************************** +// +//! Starts the transfer of data from an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32TransType is set to indicate what type of data is being sent. +//! +//! This function starts the transfer of data from the FIFO for a given +//! endpoint. This function is called if the \b USB_EP_AUTO_SET bit was +//! not enabled for the endpoint. Setting the \e ui32TransType parameter +//! allows the appropriate signaling on the USB bus for the type of transaction +//! being requested. The \e ui32TransType parameter must be one of the +//! following: +//! +//! - \b USB_TRANS_OUT for OUT transaction on any endpoint in host mode. +//! - \b USB_TRANS_IN for IN transaction on any endpoint in device mode. +//! - \b USB_TRANS_IN_LAST for the last IN transaction on endpoint zero in a +//! sequence of IN transactions. +//! - \b USB_TRANS_SETUP for setup transactions on endpoint zero. +//! - \b USB_TRANS_STATUS for status results on endpoint zero. +//! +//! \return This call returns 0 on success, or -1 if a transmission is already +//! in progress. +// +//***************************************************************************** +int32_t +USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType) +{ + uint32_t ui32TxPktRdy; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Get the bit position of TxPktRdy based on the endpoint. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0) & USB_CSRL0_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = ui32TransType & 0xFFU; + } + else + { + // + // Don't allow transmit of data if the TxPktRdy bit is already set. + // + if(HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) & USB_TXCSRL1_TXRDY) + { + return(-1); + } + + ui32TxPktRdy = (ui32TransType >> 8U) & 0xFFU; + } + + // + // Set TxPktRdy in order to send the data. + // + HWREGB(ui32Base + USB_O_CSRL0 + ui32Endpoint) = ui32TxPktRdy; + + // + // Success. + // + return(0U); +} + +//***************************************************************************** +// +//! Forces a flush of an endpoint's FIFO. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags specifies if the IN or OUT endpoint is accessed. +//! +//! This function forces the USB controller to flush out the data in the FIFO. +//! The function can be called with either host or device controllers and +//! requires the \e ui32Flags parameter be one of \b USB_EP_HOST_OUT, +//! \b USB_EP_HOST_IN, \b USB_EP_DEV_OUT, or \b USB_EP_DEV_IN. +//! +//! \return None. +// +//***************************************************************************** +void +USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero has a different register set for FIFO flushing. + // + if(ui32Endpoint == USB_EP_0) + { + // + // Nothing in the FIFO if neither of these bits are set. + // + if((HWREGB(ui32Base + USB_O_CSRL0) & + (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0U) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_CSRH0) = USB_CSRH0_FLUSH; + } + } + else + { + // + // Only reset the IN or OUT FIFO. + // + if(ui32Flags & (USB_EP_HOST_OUT | USB_EP_DEV_IN)) + { + // + // Make sure the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_TXCSRL1_TXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_TXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_TXCSRL1_FLUSH; + } + } + else + { + // + // Make sure that the FIFO is not empty. + // + if(HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) & + USB_RXCSRL1_RXRDY) + { + // + // Hit the Flush FIFO bit. + // + HWREGB(ui32Base + USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint)) |= + USB_RXCSRL1_FLUSH; + } + } + } +} + +//***************************************************************************** +// +//! Schedules a request for an IN transaction on an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function schedules a request for an IN transaction. When the USB +//! device being communicated with responds with the data, the data can be +//! retrieved by calling USBEndpointDataGet() or via a DMA transfer. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Set the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) = USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Clears a scheduled IN transaction for an endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! +//! This function clears a previously scheduled IN transaction if it is still +//! pending. This function is used to safely disable any scheduled IN +//! transactions if the endpoint specified by \e ui32Endpoint is reconfigured +//! for communications with other devices. +//! +//! \note This function must only be called in host mode and only for IN +//! endpoints. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + uint32_t ui32Register; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Endpoint zero uses a different offset than the other endpoints. + // + if(ui32Endpoint == USB_EP_0) + { + ui32Register = USB_O_CSRL0; + } + else + { + ui32Register = USB_O_RXCSRL1 + EP_OFFSET(ui32Endpoint); + } + + // + // Clear the request for an IN transaction. + // + HWREGB(ui32Base + ui32Register) &= ~USB_RXCSRL1_REQPKT; +} + +//***************************************************************************** +// +//! Issues a request for a status IN transaction on endpoint zero. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function is used to cause a request for a status IN transaction from +//! a device on endpoint zero. This function can only be used with endpoint +//! zero as that is the only control endpoint that supports this ability. This +//! function is used to complete the last phase of a control transaction to a +//! device and an interrupt is signaled when the status packet has been +//! received. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostRequestStatus(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the request for a status IN transaction. + // + HWREGB(ui32Base + USB_O_CSRL0) = USB_CSRL0_REQPKT | USB_CSRL0_STATUS; +} + +//***************************************************************************** +// +//! Sets the functional address for the device that is connected to an +//! endpoint in host mode. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the functional address for the controller to use for +//! this endpoint. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the functional address for a device that is using +//! this endpoint for communication. This \e ui32Addr parameter is the address +//! of the target device that this endpoint is communicating with. The +//! \e ui32Flags parameter indicates if the IN or OUT endpoint is set. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the transmit address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the receive address. + // + HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } +} + +//***************************************************************************** +// +//! Gets the current functional device address for an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current functional address that an endpoint is +//! using to communicate with a device. The \e ui32Flags parameter determines +//! if the IN or OUT endpoint's device address is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return Returns the current function address being used by an endpoint. +// +//***************************************************************************** +uint32_t +USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return this endpoint's transmit address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return this endpoint's receive address. + // + return(HWREGB(ui32Base + USB_O_TXFUNCADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the hub address for the device that is connected to an endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Addr is the hub address and port for the device using this +//! endpoint. The hub address must be defined in bits 0 through 6 with the +//! port number in bits 8 through 14. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function configures the hub address for a device that is using this +//! endpoint for communication. The \e ui32Flags parameter determines if the +//! device address for the IN or the OUT endpoint is configured by this call +//! and sets the speed of the downstream device. Valid values are one of +//! \b USB_EP_HOST_OUT or \b USB_EP_HOST_IN optionally ORed with +//! \b USB_EP_SPEED_LOW. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Addr, + uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is being set. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Set the hub transmit address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U)) = ui32Addr; + } + else + { + // + // Set the hub receive address and port number for this endpoint. + // + HWREGH(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U)) = + ui32Addr; + } + + // + // Set the speed of communication for endpoint 0. This configuration is + // done here because it changes on a transaction-by-transaction basis for + // EP0. For other endpoints, this is set in USBHostEndpointConfig(). + // + if(ui32Endpoint == USB_EP_0) + { + if(ui32Flags & USB_EP_SPEED_FULL) + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_FULL; + } + else + { + HWREGB(ui32Base + USB_O_TYPE0) = USB_TYPE0_SPEED_LOW; + } + } +} + +//***************************************************************************** +// +//! Gets the current device hub address for this endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint to access. +//! \param ui32Flags determines if this is an IN or an OUT endpoint. +//! +//! This function returns the current hub address that an endpoint is using +//! to communicate with a device. The \e ui32Flags parameter determines if the +//! device address for the IN or OUT endpoint is returned. +//! +//! \note This function must only be called in host mode. +//! +//! \return This function returns the current hub address being used by an +//! endpoint. +// +//***************************************************************************** +uint32_t +USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // See if the hub transmit or receive address is returned. + // + if(ui32Flags & USB_EP_HOST_OUT) + { + // + // Return the hub transmit address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + (ui32Endpoint >> 1U))); + } + else + { + // + // Return the hub receive address for this endpoint. + // + return(HWREGB(ui32Base + USB_O_TXHUBADDR0 + 4U + (ui32Endpoint >> 1U))); + } +} + +//***************************************************************************** +// +//! Sets the configuration for USB power fault. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Flags specifies the configuration of the power fault. +//! +//! This function controls how the USB controller uses its external power +//! control pins (USBnPFLT and USBnEPEN). The flags specify the power +//! fault level sensitivity, the power fault action, and the power enable level +//! and source. +//! +//! One of the following can be selected as the power fault level sensitivity: +//! +//! - \b USB_HOST_PWRFLT_LOW - An external power fault is indicated by the pin +//! being driven low. +//! - \b USB_HOST_PWRFLT_HIGH - An external power fault is indicated by the pin +//! being driven high. +//! +//! One of the following can be selected as the power fault action: +//! +//! - \b USB_HOST_PWRFLT_EP_NONE - No automatic action when power fault +//! detected. +//! - \b USB_HOST_PWRFLT_EP_TRI - Automatically tri-state the USBnEPEN pin on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_LOW - Automatically drive USBnEPEN pin low on a +//! power fault. +//! - \b USB_HOST_PWRFLT_EP_HIGH - Automatically drive USBnEPEN pin high on a +//! power fault. +//! +//! One of the following can be selected as the power enable level and source: +//! +//! - \b USB_HOST_PWREN_MAN_LOW - USBnEPEN is driven low by the USB controller +//! when USBHostPwrEnable() is called. +//! - \b USB_HOST_PWREN_MAN_HIGH - USBnEPEN is driven high by the USB +//! controller when USBHostPwrEnable() is +//! called. +//! - \b USB_HOST_PWREN_AUTOLOW - USBnEPEN is driven low by the USB controller +//! automatically if USBOTGSessionRequest() has +//! enabled a session. +//! - \b USB_HOST_PWREN_AUTOHIGH - USBnEPEN is driven high by the USB +//! controller automatically if +//! USBOTGSessionRequest() has enabled a +//! session. +//! +//! On devices that support the VBUS glitch filter, the +//! \b USB_HOST_PWREN_FILTER can be added to ignore small, short drops in VBUS +//! level caused by high power consumption. This feature is mainly used to +//! avoid causing VBUS errors caused by devices with high in-rush current. +//! +//! \note This function must only be called on microcontrollers that support +//! host mode or OTG operation. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Flags & ~(USB_HOST_PWREN_FILTER | USB_EPC_PFLTACT_M | + USB_EPC_PFLTAEN | USB_EPC_PFLTSEN_HIGH | + USB_EPC_EPEN_M)) == 0U); + + // + // If requested, enable VBUS droop detection on parts that support this + // feature. + // + HWREG(ui32Base + USB_O_VDC) = ui32Flags >> 16U; + + // + // Set the power fault configuration as specified. This configuration + // does not change whether fault detection is enabled or not. + // + HWREGH(ui32Base + USB_O_EPC) = + (ui32Flags | (HWREGH(ui32Base + USB_O_EPC) & + ~(USB_EPC_PFLTACT_M | USB_EPC_PFLTAEN | + USB_EPC_PFLTSEN_HIGH | USB_EPC_EPEN_M))); +} + +//***************************************************************************** +// +//! Enables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables power fault detection in the USB controller. If the +//! USBnPFLT pin is not in use, this function must not be used. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Disables power fault detection. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables power fault detection in the USB controller. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrFaultDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable power fault input. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_PFLTEN; +} + +//***************************************************************************** +// +//! Enables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function enables the USBnEPEN signal, which enables an external power +//! supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrEnable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Enable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) |= USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Disables the external power pin. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function disables the USBnEPEN signal, which disables an external +//! power supply in host mode operation. +//! +//! \note This function must only be called in host mode. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostPwrDisable(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the external power supply enable signal. + // + HWREGH(ui32Base + USB_O_EPC) &= ~USB_EPC_EPENDE; +} + +//***************************************************************************** +// +//! Get the current frame number. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the last frame number received. +//! +//! \return The last frame number received. +// +//***************************************************************************** +uint32_t +USBFrameNumberGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Return the most recent frame number. + // + return(HWREGH(ui32Base + USB_O_FRAME)); +} + +//***************************************************************************** +// +//! Starts or ends a session. +//! +//! \param ui32Base specifies the USB module base address. +//! \param bStart specifies if this call starts or ends a session. +//! +//! This function is used in OTG mode to start a session request or end a +//! session. If the \e bStart parameter is set to \b true, then this function +//! starts a session and if it is \b false it ends a session. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGSessionRequest(uint32_t ui32Base, bool bStart) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Start or end the session as directed. + // + if(bStart) + { + HWREGB(ui32Base + USB_O_DEVCTL) |= USB_DEVCTL_SESSION; + } + else + { + HWREGB(ui32Base + USB_O_DEVCTL) &= ~USB_DEVCTL_SESSION; + } +} + +//***************************************************************************** +// +//! Returns the absolute FIFO address for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! +//! This function returns the actual physical address of the FIFO. This +//! address is needed when the USB is going to be used with the uDMA +//! controller and the source or destination address must be set to the +//! physical FIFO address for a given endpoint. +//! +//! \return None. +// +//***************************************************************************** +uint32_t +USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + // + // Return the FIFO address for this endpoint. + // + return(ui32Base + USB_O_FIFO0 + (ui32Endpoint >> 2U)); +} + +//***************************************************************************** +// +//! Returns the current operating mode of the controller. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the current operating mode on USB controllers with +//! OTG or Dual mode functionality. +//! +//! For OTG controllers: +//! +//! The function returns one of the following values on OTG controllers: +//! \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE. +//! +//! \b USB_OTG_MODE_ASIDE_HOST indicates that the controller is in host mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_ASIDE_DEV indicates that the controller is in device mode +//! on the A-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_HOST indicates that the controller is in host mode +//! on the B-side of the cable. +//! +//! \b USB_OTG_MODE_BSIDE_DEV indicates that the controller is in device mode +//! on the B-side of the cable. If an OTG session request is started with no +//! cable in place, this mode is the default. +//! +//! \b USB_OTG_MODE_NONE indicates that the controller is not attempting to +//! determine its role in the system. +//! +//! For Dual Mode controllers: +//! +//! The function returns one of the following values: +//! \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +//! +//! \b USB_DUAL_MODE_HOST indicates that the controller is acting as a host. +//! +//! \b USB_DUAL_MODE_DEVICE indicates that the controller acting as a device. +//! +//! \b USB_DUAL_MODE_NONE indicates that the controller is not active as +//! either a host or device. +//! +//! \return Returns \b USB_OTG_MODE_ASIDE_HOST, \b USB_OTG_MODE_ASIDE_DEV, +//! \b USB_OTG_MODE_BSIDE_HOST, \b USB_OTG_MODE_BSIDE_DEV, +//! \b USB_OTG_MODE_NONE, \b USB_DUAL_MODE_HOST, \b USB_DUAL_MODE_DEVICE, or +//! \b USB_DUAL_MODE_NONE. +// +//***************************************************************************** +uint32_t +USBModeGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Checks the current mode in the USB_O_DEVCTL and returns the current + // mode. + // + // USB_OTG_MODE_ASIDE_HOST: USB_DEVCTL_HOST | USB_DEVCTL_SESSION + // USB_OTG_MODE_ASIDE_DEV: USB_DEVCTL_SESSION + // USB_OTG_MODE_BSIDE_HOST: USB_DEVCTL_DEV | USB_DEVCTL_SESSION | + // USB_DEVCTL_HOST + // USB_OTG_MODE_BSIDE_DEV: USB_DEVCTL_DEV | USB_DEVCTL_SESSION + // USB_OTG_MODE_NONE: USB_DEVCTL_DEV + // + return(HWREGB(ui32Base + USB_O_DEVCTL) & + (USB_DEVCTL_DEV | USB_DEVCTL_HOST | USB_DEVCTL_SESSION | + USB_DEVCTL_VBUS_M)); +} + +//***************************************************************************** +// +//! Sets the DMA channel to use for a given endpoint. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint specifies which endpoint's FIFO address to return. +//! \param ui32Channel specifies which DMA channel to use for which endpoint. +//! +//! This function is used to configure which DMA channel to use with a given +//! endpoint. Receive DMA channels can only be used with receive endpoints +//! and transmit DMA channels can only be used with transmit endpoints. As a +//! result, the 3 receive and 3 transmit DMA channels can be mapped to any +//! endpoint other than 0. The values that are passed into the +//! \e ui32Channel value are the UDMA_CHANNEL_USBEP* values defined in udma.h. +//! +//! \note This function only has an effect on microcontrollers that have the +//! ability to change the DMA channel for an endpoint. Calling this function +//! on other devices has no effect. +//! +//! \return None. +//! +//***************************************************************************** +void +USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel) +{ + uint32_t ui32Mask; + + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_1) || (ui32Endpoint == USB_EP_2) || + (ui32Endpoint == USB_EP_3) || (ui32Endpoint == USB_EP_4) || + (ui32Endpoint == USB_EP_5) || (ui32Endpoint == USB_EP_6) || + (ui32Endpoint == USB_EP_7) || (ui32Endpoint == USB_EP_8) || + (ui32Endpoint == USB_EP_9) || (ui32Endpoint == USB_EP_10) || + (ui32Endpoint == USB_EP_11) || (ui32Endpoint == USB_EP_12) || + (ui32Endpoint == USB_EP_13) || (ui32Endpoint == USB_EP_14) || + (ui32Endpoint == USB_EP_15)); + + // + // The input select mask must be shifted into the correct position + // based on the channel. + // + ui32Mask = (uint32_t)0xFU << (ui32Channel * 4U); + + // + // Clear out the current selection for the channel. + // + ui32Mask = HWREG(ui32Base + USB_O_DMASEL) & (~ui32Mask); + + // + // The input select is now shifted into the correct position based on the + // channel. + // + ui32Mask |= ((uint32_t)USBEPToIndex(ui32Endpoint)) << (ui32Channel * 4U); + + // + // Write the value out to the register. + // + HWREG(ui32Base + USB_O_DMASEL) = ui32Mask; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to host. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to host mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBHostMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Force mode in OTG parts that support forcing USB controller mode. + // This bit is not writable in USB controllers that do not support + // forcing the mode. Not setting the USB_GPCS_DEVMOD bit makes this a + // force of host mode. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to device mode. +//! +//! \note This function must only be called on microcontrollers that support +//! OTG operation and have the DEVMODOTG bit in the USBGPCS register. +//! +//! \return None. +// +//***************************************************************************** +void +USBDevMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the USB controller mode to device. + // + HWREGB(ui32Base + USB_O_GPCS) = USB_GPCS_DEVMODOTG | USB_GPCS_DEVMOD; +} + +//***************************************************************************** +// +//! Change the mode of the USB controller to OTG. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function changes the mode of the USB controller to OTG mode. This +//! function is only valid on microcontrollers that have the OTG capabilities. +//! +//! \return None. +// +//***************************************************************************** +void +USBOTGMode(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Disable the override of the USB controller mode when running on an OTG + // device. + // + HWREGB(ui32Base + USB_O_GPCS) = 0U; +} + +//***************************************************************************** +// +//! Powers off the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers off the USB PHY, reducing the current consuption +//! of the device. While in the powered-off state, the USB controller is +//! unable to operate. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOff(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Set the PWRDNPHY bit in the PHY, putting it into its low power mode. + // + HWREGB(ui32Base + USB_O_POWER) |= USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Powers on the USB PHY. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function powers on the USB PHY, enabling it return to normal +//! operation. By default, the PHY is powered on, so this function must +//! only be called if USBPHYPowerOff() has previously been called. +//! +//! \return None. +// +//***************************************************************************** +void +USBPHYPowerOn(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Clear the PWRDNPHY bit in the PHY, putting it into normal operating + // mode. + // + HWREGB(ui32Base + USB_O_POWER) &= ~USB_POWER_PWRDNPHY; +} + +//***************************************************************************** +// +//! Sets the number of packets to request when transferring multiple bulk +//! packets. +//! +//! \param ui32Base specifies the USB module base address. +//! \param ui32Endpoint is the endpoint index to target for this write. +//! \param ui32Count is the number of packets to request. +//! +//! This function sets the number of consecutive bulk packets to request +//! when transferring multiple bulk packets with DMA. +//! +//! \note This feature is not available on all Tiva devices. Please +//! check the data sheet to determine if the USB controller has a DMA +//! controller or if it must use the uDMA controller for DMA transfers. +//! +//! \return None. +// +//***************************************************************************** +void +USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + ASSERT((ui32Endpoint == USB_EP_0) || (ui32Endpoint == USB_EP_1) || + (ui32Endpoint == USB_EP_2) || (ui32Endpoint == USB_EP_3) || + (ui32Endpoint == USB_EP_4) || (ui32Endpoint == USB_EP_5) || + (ui32Endpoint == USB_EP_6) || (ui32Endpoint == USB_EP_7) || + (ui32Endpoint == USB_EP_8) || (ui32Endpoint == USB_EP_9) || + (ui32Endpoint == USB_EP_10) || (ui32Endpoint == USB_EP_11) || + (ui32Endpoint == USB_EP_12) || (ui32Endpoint == USB_EP_13) || + (ui32Endpoint == USB_EP_14) || (ui32Endpoint == USB_EP_15)); + + HWREG(ui32Base + USB_O_RQPKTCOUNT1 + + (0x4U * (USBEPToIndex(ui32Endpoint) - 1U))) = ui32Count; +} + +//***************************************************************************** +// +//! Returns the number of USB endpoint pairs on the device. +//! +//! \param ui32Base specifies the USB module base address. +//! +//! This function returns the number of endpoint pairs supported by the USB +//! controller corresponding to the passed base address. The value returned is +//! the number of IN or OUT endpoints available and does not include endpoint 0 +//! (the control endpoint). For example, if 15 is returned, there are 15 IN +//! and 15 OUT endpoints available in addition to endpoint 0. +//! +//! \return Returns the number of IN or OUT endpoints available. +// +//***************************************************************************** +uint32_t +USBNumEndpointsGet(uint32_t ui32Base) +{ + // + // Check the arguments. + // + ASSERT(ui32Base == USBA_BASE); + + // + // Read the number of endpoints from the hardware. The number of TX and + // RX endpoints are always the same. + // + return(15U); +} + diff --git a/gpio_driverlib_cpu1/device/driverlib/usb.h b/gpio_driverlib_cpu1/device/driverlib/usb.h new file mode 100644 index 0000000..ae3c7ad --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/usb.h @@ -0,0 +1,560 @@ +//########################################################################### +// +// FILE: usb.h +// +// TITLE: Prototypes for the USB Interface Driver. +// +//########################################################################### +// +// +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### +#ifndef USB_H +#define USB_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup usb_api USB +//! @{ +// +//***************************************************************************** + +//***************************************************************************** +// +// The following are defines for the g_usUSBFlags variable +// +//***************************************************************************** +#define USB_VBUS_VALID 0x0001U +#define USB_ID_HOST 0x0002U +#define USB_ID_DEVICE 0x0000U +#define USB_PFLT_ACTIVE 0x0004U + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FFUL // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FFUL // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080UL // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040UL // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040UL // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020UL // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010UL // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008UL // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004UL // Babble signaled +#define USB_INTCTRL_RESET 0x00000004UL // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002UL // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001UL // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200UL // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100UL // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFFUL // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000UL // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000UL // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000UL // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000UL // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000UL // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000UL // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000UL // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000UL // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000UL // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000UL // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000UL // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000UL // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000UL // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000UL // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000UL // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000UL // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000UL // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000UL // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000UL // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000UL // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000UL // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000UL // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000UL // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000UL // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000UL // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000UL // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000UL // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000UL // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000UL // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000UL // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000UL // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000UL // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFEUL // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000UL // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000UL // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000UL // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000UL // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800UL // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400UL // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200UL // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100UL // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080UL // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040UL // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020UL // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010UL // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008UL // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004UL // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002UL // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFEUL // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000UL // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000UL // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000UL // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000UL // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800UL // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400UL // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200UL // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100UL // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080UL // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040UL // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020UL // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010UL // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008UL // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004UL // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002UL // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000UL // Current speed is undefined +#define USB_FULL_SPEED 0x00000001UL // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000UL // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0xFFFF0000UL // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000UL // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000UL // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000UL // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000UL // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000UL // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000UL // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000UL // Data packet ready +#define USB_HOST_OUT_STATUS 0x0000FFFFUL // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080UL // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020UL // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004UL // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002UL // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001UL // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080UL // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040UL // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010UL // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004UL // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001UL // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000UL // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000UL // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000UL // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000UL // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000UL // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000UL // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080UL // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020UL // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004UL // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002UL // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001UL // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010UL // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004UL // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002UL // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001UL // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001UL // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002UL // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004UL // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008UL // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010UL // Enable DMA access using mode 1 +#define USB_EP_MODE_ISOC 0x00000000UL // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100UL // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200UL // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300UL // Control endpoint +#define USB_EP_MODE_MASK 0x00000300UL // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000UL // Low Speed +#define USB_EP_SPEED_FULL 0x00001000UL // Full Speed +#define USB_EP_HOST_IN 0x00000000UL // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000UL // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000UL // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000UL // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010UL +#define USB_HOST_PWRFLT_HIGH 0x00000030UL +#define USB_HOST_PWRFLT_EP_NONE 0x00000000UL +#define USB_HOST_PWRFLT_EP_TRI 0x00000140UL +#define USB_HOST_PWRFLT_EP_LOW 0x00000240UL +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340UL +#define USB_HOST_PWREN_MAN_LOW 0x00000000UL +#define USB_HOST_PWREN_MAN_HIGH 0x00000001UL +#define USB_HOST_PWREN_AUTOLOW 0x00000002UL +#define USB_HOST_PWREN_AUTOHIGH 0x00000003UL +#define USB_HOST_PWREN_FILTER 0x00010000UL + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64U + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000UL // Endpoint 0 +#define USB_EP_1 0x00000010UL // Endpoint 1 +#define USB_EP_2 0x00000020UL // Endpoint 2 +#define USB_EP_3 0x00000030UL // Endpoint 3 +#define USB_EP_4 0x00000040UL // Endpoint 4 +#define USB_EP_5 0x00000050UL // Endpoint 5 +#define USB_EP_6 0x00000060UL // Endpoint 6 +#define USB_EP_7 0x00000070UL // Endpoint 7 +#define USB_EP_8 0x00000080UL // Endpoint 8 +#define USB_EP_9 0x00000090UL // Endpoint 9 +#define USB_EP_10 0x000000A0UL // Endpoint 10 +#define USB_EP_11 0x000000B0UL // Endpoint 11 +#define USB_EP_12 0x000000C0UL // Endpoint 12 +#define USB_EP_13 0x000000D0UL // Endpoint 13 +#define USB_EP_14 0x000000E0UL // Endpoint 14 +#define USB_EP_15 0x000000F0UL // Endpoint 15 +#define NUM_USB_EP 16U // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) (((uint32_t)(x) << 4U) & 0xFFU) +#define USBEPToIndex(x) ((x) >> 4U) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000UL // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001UL // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002UL // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003UL // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004UL // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005UL // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006UL // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007UL // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008UL // 2048 byte FIFO +#define USB_FIFO_SZ_4096 0x00000009UL // 4096 byte FIFO +#define USB_FIFO_SZ_8_DB 0x00000010UL // 8 byte double buffered FIFO + // (occupying 16 bytes) +#define USB_FIFO_SZ_16_DB 0x00000011UL // 16 byte double buffered FIFO + // (occupying 32 bytes) +#define USB_FIFO_SZ_32_DB 0x00000012UL // 32 byte double buffered FIFO + // (occupying 64 bytes) +#define USB_FIFO_SZ_64_DB 0x00000013UL // 64 byte double buffered FIFO + // (occupying 128 bytes) +#define USB_FIFO_SZ_128_DB 0x00000014UL // 128 byte double buffered FIFO + // (occupying 256 bytes) +#define USB_FIFO_SZ_256_DB 0x00000015UL // 256 byte double buffered FIFO + // (occupying 512 bytes) +#define USB_FIFO_SZ_512_DB 0x00000016UL // 512 byte double buffered FIFO + // (occupying 1024 bytes) +#define USB_FIFO_SZ_1024_DB 0x00000017UL // 1024 byte double buffered FIFO + // (occupying 2048 bytes) +#define USB_FIFO_SZ_2048_DB 0x00000018UL // 2048 byte double buffered FIFO + // (occupying 4096 bytes) + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USB_FIFO_SIZE_DB_FLAG 0x00000010UL +#define USBFIFOSizeToBytes(x) ((uint32_t)8U << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102UL // Normal OUT transaction +#define USB_TRANS_IN 0x00000102UL // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010AUL // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110AUL // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142UL // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001UL // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081UL // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080UL // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001DUL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009UL // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011UL // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019UL // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009DUL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081UL // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080UL // OTG controller mode is not set. + + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +extern uint32_t USBDevAddrGet(uint32_t ui32Base); +extern void USBDevAddrSet(uint32_t ui32Base, uint32_t ui32Address); +extern void USBDevConnect(uint32_t ui32Base); +extern void USBDevDisconnect(uint32_t ui32Base); +extern void USBDevEndpointConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32Flags); +extern void USBDevEndpointConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32MaxPacketSize, + uint32_t *pui32Flags); +extern void USBDevEndpointDataAck(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bIsLastPacket); +extern void USBDevEndpointStall(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStallClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBDevEndpointStatusClear(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBEndpointDataAvail(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBEndpointDMAEnable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMADisable(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointDMAConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Config); +extern int32_t USBEndpointDataGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t *pui32Size); +extern int32_t USBEndpointDataPut(uint32_t ui32Base, uint32_t ui32Endpoint, + uint8_t *pui8Data, uint32_t ui32Size); +extern int32_t USBEndpointDataSend(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32TransType); +extern void USBEndpointDataToggleClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBEndpointPacketCountSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Count); +extern uint32_t USBEndpointStatus(uint32_t ui32Base, uint32_t ui32Endpoint); +extern uint32_t USBFIFOAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBFIFOConfigGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t *pui32FIFOAddress, + uint32_t *pui32FIFOSize, uint32_t ui32Flags); +extern void USBFIFOConfigSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32FIFOAddress, uint32_t ui32FIFOSize, + uint32_t ui32Flags); +extern void USBFIFOFlush(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBFrameNumberGet(uint32_t ui32Base); +extern uint32_t USBHostAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostEndpointConfig(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32MaxPacketSize, + uint32_t ui32NAKPollInterval, + uint32_t ui32TargetEndpoint, + uint32_t ui32Flags); +extern void USBHostEndpointDataAck(uint32_t ui32Base, + uint32_t ui32Endpoint); +extern void USBHostEndpointDataToggle(uint32_t ui32Base, uint32_t ui32Endpoint, + bool bDataToggle, uint32_t ui32Flags); +extern void USBHostEndpointStatusClear(uint32_t ui32Base, + uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern uint32_t USBHostHubAddrGet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Flags); +extern void USBHostHubAddrSet(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Addr, uint32_t ui32Flags); +extern void USBHostPwrDisable(uint32_t ui32Base); +extern void USBHostPwrEnable(uint32_t ui32Base); +extern void USBHostPwrConfig(uint32_t ui32Base, uint32_t ui32Flags); +extern void USBHostPwrFaultDisable(uint32_t ui32Base); +extern void USBHostPwrFaultEnable(uint32_t ui32Base); +extern void USBHostRequestIN(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestINClear(uint32_t ui32Base, uint32_t ui32Endpoint); +extern void USBHostRequestStatus(uint32_t ui32Base); +extern void USBHostReset(uint32_t ui32Base, bool bStart); +extern void USBHostResume(uint32_t ui32Base, bool bStart); +extern uint32_t USBHostSpeedGet(uint32_t ui32Base); +extern void USBHostSuspend(uint32_t ui32Base); +extern void USBIntDisableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableControl(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatus(uint32_t ui32Base, uint32_t *ui32IntStatusEP); +extern uint32_t USBIntStatusControl(uint32_t ui32Base); +extern void USBIntDisableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern void USBIntEnableEndpoint(uint32_t ui32Base, uint32_t ui32IntFlags); +extern uint32_t USBIntStatusEndpoint(uint32_t ui32Base); +extern void USBOTGSessionRequest(uint32_t ui32Base, bool bStart); +extern uint32_t USBModeGet(uint32_t ui32Base); +extern void USBEndpointDMAChannel(uint32_t ui32Base, uint32_t ui32Endpoint, + uint32_t ui32Channel); +extern void USBHostMode(uint32_t ui32Base); +extern void USBDevMode(uint32_t ui32Base); +extern void USBOTGMode(uint32_t ui32Base); +extern void USBPHYPowerOff(uint32_t ui32Base); +extern void USBPHYPowerOn(uint32_t ui32Base); +extern uint32_t USBNumEndpointsGet(uint32_t ui32Base); + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnable() and +// USBIntDisable() as the ulIntFlags parameter, and are returned from +// USBIntStatus(). +// +//***************************************************************************** +#define USB_INT_ALL 0xFF030E0FUL // All Interrupt sources +#define USB_INT_STATUS 0xFF000000UL // Status Interrupts +#define USB_INT_VBUS_ERR 0x80000000UL // VBUS Error +#define USB_INT_SESSION_START 0x40000000UL // Session Start Detected +#define USB_INT_SESSION_END 0x20000000UL // Session End Detected +#define USB_INT_DISCONNECT 0x20000000UL // Disconnect Detected +#define USB_INT_CONNECT 0x10000000UL // Device Connect Detected +#define USB_INT_SOF 0x08000000UL // Start of Frame Detected +#define USB_INT_BABBLE 0x04000000UL // Babble signaled +#define USB_INT_RESET 0x04000000UL // Reset signaled +#define USB_INT_RESUME 0x02000000UL // Resume detected +#define USB_INT_SUSPEND 0x01000000UL // Suspend detected +#define USB_INT_MODE_DETECT 0x00020000UL // Mode value valid +#define USB_INT_POWER_FAULT 0x00010000UL // Power Fault detected +#define USB_INT_HOST_IN 0x00000E00UL // Host IN Interrupts +#define USB_INT_DEV_OUT 0x00000E00UL // Device OUT Interrupts +#define USB_INT_HOST_IN_EP3 0x00000800UL // Endpoint 3 Host IN Interrupt +#define USB_INT_HOST_IN_EP2 0x00000400UL // Endpoint 2 Host IN Interrupt +#define USB_INT_HOST_IN_EP1 0x00000200UL // Endpoint 1 Host IN Interrupt +#define USB_INT_DEV_OUT_EP3 0x00000800UL // Endpoint 3 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP2 0x00000400UL // Endpoint 2 Device OUT Interrupt +#define USB_INT_DEV_OUT_EP1 0x00000200UL // Endpoint 1 Device OUT Interrupt +#define USB_INT_HOST_OUT 0x0000000EUL // Host OUT Interrupts +#define USB_INT_DEV_IN 0x0000000EUL // Device IN Interrupts +#define USB_INT_HOST_OUT_EP3 0x00000008UL // Endpoint 3 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP2 0x00000004UL // Endpoint 2 HOST_OUT Interrupt +#define USB_INT_HOST_OUT_EP1 0x00000002UL // Endpoint 1 HOST_OUT Interrupt +#define USB_INT_DEV_IN_EP3 0x00000008UL // Endpoint 3 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP2 0x00000004UL // Endpoint 2 DEV_IN Interrupt +#define USB_INT_DEV_IN_EP1 0x00000002UL // Endpoint 1 DEV_IN Interrupt +#define USB_INT_EP0 0x00000001UL // Endpoint 0 Interrupt + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // USB_H diff --git a/gpio_driverlib_cpu1/device/driverlib/version.c b/gpio_driverlib_cpu1/device/driverlib/version.c new file mode 100644 index 0000000..ced29c1 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/version.c @@ -0,0 +1,54 @@ +//########################################################################### +// +// FILE: version.c +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "version.h" + +//***************************************************************************** +// +// Version_getLibVersion +// +//***************************************************************************** +uint32_t +Version_getLibVersion(void) +{ + return(VERSION_NUMBER); +} diff --git a/gpio_driverlib_cpu1/device/driverlib/version.h b/gpio_driverlib_cpu1/device/driverlib/version.h new file mode 100644 index 0000000..8a3b431 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/version.h @@ -0,0 +1,101 @@ +//########################################################################### +// +// FILE: version.h +// +// TITLE: API to return the version number of the driverlib.lib in use. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef VERSION_H +#define VERSION_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup version_api Version +//! @{ +// +//***************************************************************************** +#include + +//! Version number to be returned by Version_getLibVersion() +//! +#define VERSION_NUMBER 26000000U + +//***************************************************************************** +// +//! Returns the driverlib version number +//! +//! This function can be used to check the version number of the driverlib.lib +//! that is in use. The version number will take the format yy.mm.pp.bb, so for +//! yy-Year, mm-Major Release version, pp-Patch Release Version, bb- Build Number. +//! example, if the function returns 26000000, the driverlib version being used +//! is 26.00.00.00. +//! +//! \return Returns an integer value indicating the driverlib version. +// +//***************************************************************************** +extern uint32_t +Version_getLibVersion(void); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // VERSION_H diff --git a/gpio_driverlib_cpu1/device/driverlib/xbar.c b/gpio_driverlib_cpu1/device/driverlib/xbar.c new file mode 100644 index 0000000..008145a --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/xbar.c @@ -0,0 +1,255 @@ +//########################################################################### +// +// FILE: xbar.c +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#include "xbar.h" + +//***************************************************************************** +// +// XBAR_setOutputMuxConfig +// +//***************************************************************************** +void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)output << 1U) + 2U; + } + else + { + offset = (uint16_t)output << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR output. + // + EALLOW; + + HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) = + (HWREG(XBAR_OUTPUT_CFG_REG_BASE + offset) & + ~((uint32_t)0x3U << shift)) | + (((uint32_t)muxConfig & 0x3U) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setEPWMMuxConfig +// +//***************************************************************************** +void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)trip << 1U) + 2U; + } + else + { + offset = (uint16_t)trip << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR trip. + // + EALLOW; + + HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_EPWM_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_setCLBMuxConfig +// +//***************************************************************************** +void +XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, XBAR_CLBMuxConfig muxConfig) +{ + uint32_t shift; + uint16_t offset; + + // + // If the configuration is for MUX16-31, we'll need an odd value to index + // into the config registers. + // + if(((uint32_t)muxConfig & 0x2000U) != 0U) + { + offset = ((uint16_t)auxSignal << 1U) + 2U; + } + else + { + offset = (uint16_t)auxSignal << 1U; + } + + // + // Extract the shift from the input value. + // + shift = ((uint32_t)muxConfig >> 8U) & 0x1FU; + + // + // Write the requested muxing value for this XBAR auxSignal. + // + EALLOW; + + + HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) = + (HWREG(XBAR_CLB_CFG_REG_BASE + (uint32_t)offset) & ~(0x3UL << shift)) | + (((uint32_t)muxConfig & 0x3UL) << shift); + + EDIS; +} + +//***************************************************************************** +// +// XBAR_getInputFlagStatus +// +//***************************************************************************** +bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_FLG1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_FLG2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_FLG3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Get the status of the X-BAR input latch. + // + inputMask = (uint32_t)1U << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + + return((HWREG(XBAR_BASE + offset) & inputMask) != 0U); +} + +//***************************************************************************** +// +// XBAR_clearInputFlag +// +//***************************************************************************** +void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag) +{ + uint32_t offset; + uint32_t inputMask; + + // + // Determine flag clear register offset. + // + switch((uint16_t)inputFlag & XBAR_INPUT_FLG_REG_M) + { + case XBAR_INPUT_FLG_REG_1: + offset = XBAR_O_CLR1; + break; + + case XBAR_INPUT_FLG_REG_2: + offset = XBAR_O_CLR2; + break; + + case XBAR_INPUT_FLG_REG_3: + offset = XBAR_O_CLR3; + break; + + default: + // + // This should never happen if a valid inputFlag value is used. + // + offset = 0U; + break; + } + + // + // Set the bit that clears the X-BAR input latch. + // + inputMask = 1UL << ((uint32_t)inputFlag & XBAR_INPUT_FLG_INPUT_M); + HWREG(XBAR_BASE + offset) = inputMask; +} diff --git a/gpio_driverlib_cpu1/device/driverlib/xbar.h b/gpio_driverlib_cpu1/device/driverlib/xbar.h new file mode 100644 index 0000000..02e4e68 --- /dev/null +++ b/gpio_driverlib_cpu1/device/driverlib/xbar.h @@ -0,0 +1,1294 @@ +//########################################################################### +// +// FILE: xbar.h +// +// TITLE: C28x X-BAR driver. +// +//########################################################################### +// +// C2000Ware v26.00.00.00 +// +// Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com +// +// Redistribution and use in source and binary forms, with or without +// modification, are permitted provided that the following conditions +// are met: +// +// Redistributions of source code must retain the above copyright +// notice, this list of conditions and the following disclaimer. +// +// Redistributions in binary form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the +// distribution. +// +// Neither the name of Texas Instruments Incorporated nor the names of +// its contributors may be used to endorse or promote products derived +// from this software without specific prior written permission. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +// $ +//########################################################################### + +#ifndef XBAR_H +#define XBAR_H + +//***************************************************************************** +// +// If building with a C++ compiler, make all of the definitions in this header +// have a C binding. +// +//***************************************************************************** +#ifdef __cplusplus +extern "C" +{ +#endif + +//***************************************************************************** +// +//! \addtogroup xbar_api XBAR +//! @{ +// +//***************************************************************************** + +#include +#include +#include "inc/hw_clbxbar.h" +#include "inc/hw_epwmxbar.h" +#include "inc/hw_inputxbar.h" +#include "inc/hw_outputxbar.h" +#include "inc/hw_xbar.h" +#include "inc/hw_memmap.h" +#include "inc/hw_types.h" +#include "cpu.h" +#include "debug.h" + +//***************************************************************************** +// +// Useful defines used within the driver functions. +// Not intended for use by application code. +// +//***************************************************************************** +#define XBAR_OUTPUT_CFG_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUX0TO15CFG) +#define XBAR_OUTPUT_EN_REG_BASE (OUTPUTXBAR_BASE + XBAR_O_OUTPUT1MUXENABLE) +#define XBAR_EPWM_CFG_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUX0TO15CFG) +#define XBAR_EPWM_EN_REG_BASE (EPWMXBAR_BASE + XBAR_O_TRIP4MUXENABLE) +#define XBAR_CLB_CFG_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUX0TO15CFG) +#define XBAR_CLB_EN_REG_BASE (CLBXBAR_BASE + XBAR_O_AUXSIG0MUXENABLE) +#define XBAR_INPUT_BASE (INPUTXBAR_BASE + XBAR_O_INPUT1SELECT) + +#define XBAR_INPUT_FLG_INPUT_M 0x00FFU +#define XBAR_INPUT_FLG_REG_M 0xFF00U +#define XBAR_INPUT_FLG_REG_1 0x0000U +#define XBAR_INPUT_FLG_REG_2 0x0100U +#define XBAR_INPUT_FLG_REG_3 0x0200U + +#define XBAR_GPIO_MAX_CNT 168U + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +// The following values define the muxes parameter for XBAR_enableEPWMMux(), +// XBAR_enableOutputMux(), XBAR_disableEPWMMux(), and +// XBAR_disableOutputMux(). +// +//***************************************************************************** +#define XBAR_MUX00 0x00000001U //!< Mask for X-BAR mux 0 +#define XBAR_MUX01 0x00000002U //!< Mask for X-BAR mux 1 +#define XBAR_MUX02 0x00000004U //!< Mask for X-BAR mux 2 +#define XBAR_MUX03 0x00000008U //!< Mask for X-BAR mux 3 +#define XBAR_MUX04 0x00000010U //!< Mask for X-BAR mux 4 +#define XBAR_MUX05 0x00000020U //!< Mask for X-BAR mux 5 +#define XBAR_MUX06 0x00000040U //!< Mask for X-BAR mux 6 +#define XBAR_MUX07 0x00000080U //!< Mask for X-BAR mux 7 +#define XBAR_MUX08 0x00000100U //!< Mask for X-BAR mux 8 +#define XBAR_MUX09 0x00000200U //!< Mask for X-BAR mux 9 +#define XBAR_MUX10 0x00000400U //!< Mask for X-BAR mux 10 +#define XBAR_MUX11 0x00000800U //!< Mask for X-BAR mux 11 +#define XBAR_MUX12 0x00001000U //!< Mask for X-BAR mux 12 +#define XBAR_MUX13 0x00002000U //!< Mask for X-BAR mux 13 +#define XBAR_MUX14 0x00004000U //!< Mask for X-BAR mux 14 +#define XBAR_MUX15 0x00008000U //!< Mask for X-BAR mux 15 +#define XBAR_MUX16 0x00010000U //!< Mask for X-BAR mux 16 +#define XBAR_MUX17 0x00020000U //!< Mask for X-BAR mux 17 +#define XBAR_MUX18 0x00040000U //!< Mask for X-BAR mux 18 +#define XBAR_MUX19 0x00080000U //!< Mask for X-BAR mux 19 +#define XBAR_MUX20 0x00100000U //!< Mask for X-BAR mux 20 +#define XBAR_MUX21 0x00200000U //!< Mask for X-BAR mux 21 +#define XBAR_MUX22 0x00400000U //!< Mask for X-BAR mux 22 +#define XBAR_MUX23 0x00800000U //!< Mask for X-BAR mux 23 +#define XBAR_MUX24 0x01000000U //!< Mask for X-BAR mux 24 +#define XBAR_MUX25 0x02000000U //!< Mask for X-BAR mux 25 +#define XBAR_MUX26 0x04000000U //!< Mask for X-BAR mux 26 +#define XBAR_MUX27 0x08000000U //!< Mask for X-BAR mux 27 +#define XBAR_MUX28 0x10000000U //!< Mask for X-BAR mux 28 +#define XBAR_MUX29 0x20000000U //!< Mask for X-BAR mux 29 +#define XBAR_MUX30 0x40000000U //!< Mask for X-BAR mux 30 +#define XBAR_MUX31 0x80000000U //!< Mask for X-BAR mux 31 +#endif + +//***************************************************************************** +// +//! The following values define the \e output parameter for +//! XBAR_setOutputMuxConfig(), XBAR_enableOutputMux(), and +//! XBAR_disableOutputMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_OUTPUT1 = 0, //!< OUTPUT1 of the Output X-BAR + XBAR_OUTPUT2 = 2, //!< OUTPUT2 of the Output X-BAR + XBAR_OUTPUT3 = 4, //!< OUTPUT3 of the Output X-BAR + XBAR_OUTPUT4 = 6, //!< OUTPUT4 of the Output X-BAR + XBAR_OUTPUT5 = 8, //!< OUTPUT5 of the Output X-BAR + XBAR_OUTPUT6 = 10, //!< OUTPUT6 of the Output X-BAR + XBAR_OUTPUT7 = 12, //!< OUTPUT7 of the Output X-BAR + XBAR_OUTPUT8 = 14, //!< OUTPUT8 of the Output X-BAR +} XBAR_OutputNum; + +//***************************************************************************** +// +//! The following values define the \e trip parameter for +//! XBAR_setEPWMMuxConfig(), XBAR_invertEPWMSignal(), XBAR_enableEPWMMux(), +//! and XBAR_disableEPWMMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_TRIP4 = 0, //!< TRIP4 of the ePWM X-BAR + XBAR_TRIP5 = 2, //!< TRIP5 of the ePWM X-BAR + XBAR_TRIP7 = 4, //!< TRIP7 of the ePWM X-BAR + XBAR_TRIP8 = 6, //!< TRIP8 of the ePWM X-BAR + XBAR_TRIP9 = 8, //!< TRIP9 of the ePWM X-BAR + XBAR_TRIP10 = 10, //!< TRIP10 of the ePWM X-BAR + XBAR_TRIP11 = 12, //!< TRIP11 of the ePWM X-BAR + XBAR_TRIP12 = 14 //!< TRIP12 of the ePWM X-BAR +} XBAR_TripNum; + +//***************************************************************************** +// +// The following values define the trip parameter for XBAR_setCLBMuxConfig(), +// XBAR_enableCLBMux(), and XBAR_disableCLBMux(). +// +//***************************************************************************** +typedef enum +{ + XBAR_AUXSIG0 = 0, + XBAR_AUXSIG1 = 2, + XBAR_AUXSIG2 = 4, + XBAR_AUXSIG3 = 6, + XBAR_AUXSIG4 = 8, + XBAR_AUXSIG5 = 10, + XBAR_AUXSIG6 = 12, + XBAR_AUXSIG7 = 14 +} XBAR_AuxSigNum; + +//***************************************************************************** +// +//! The following values define the \e input parameter for XBAR_setInputPin(). +// +//***************************************************************************** +typedef enum +{ + XBAR_INPUT1, //!< ePWM[TZ1], ePWM[TRIP1], X-BARs + XBAR_INPUT2, //!< ePWM[TZ2], ePWM[TRIP2], X-BARs + XBAR_INPUT3, //!< ePWM[TZ3], ePWM[TRIP3], X-BARs + XBAR_INPUT4, //!< ADC wrappers, X-BARs, XINT1 + XBAR_INPUT5, //!< EXTSYNCIN1, X-BARs, XINT2 + XBAR_INPUT6, //!< EXTSYNCIN2, ePWM[TRIP6], X-BARs, XINT3 + XBAR_INPUT7, //!< eCAP1, X-BARs + XBAR_INPUT8, //!< eCAP2, X-BARs + XBAR_INPUT9, //!< eCAP3, X-BARs + XBAR_INPUT10, //!< eCAP4, X-BARs + XBAR_INPUT11, //!< eCAP5, X-BARs + XBAR_INPUT12, //!< eCAP6, X-BARs + XBAR_INPUT13, //!< XINT4, X-BARs + XBAR_INPUT14 //!< XINT5, X-BARs +} XBAR_InputNum; + +#ifndef DOXYGEN_PDF_IGNORE +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setOutputMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + // + //OUTPUTXBAR + // + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH = 0x0000, + XBAR_OUT_MUX00_CMPSS1_CTRIPOUTH_OR_L = 0x0001, + XBAR_OUT_MUX00_ADCAEVT1 = 0x0002, + XBAR_OUT_MUX00_ECAP1_OUT = 0x0003, + XBAR_OUT_MUX01_CMPSS1_CTRIPOUTL = 0x0200, + XBAR_OUT_MUX01_INPUTXBAR1 = 0x0201, + XBAR_OUT_MUX01_CLB1_OUT4 = 0x0202, + XBAR_OUT_MUX01_ADCCEVT1 = 0x0203, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH = 0x0400, + XBAR_OUT_MUX02_CMPSS2_CTRIPOUTH_OR_L = 0x0401, + XBAR_OUT_MUX02_ADCAEVT2 = 0x0402, + XBAR_OUT_MUX02_ECAP2_OUT = 0x0403, + XBAR_OUT_MUX03_CMPSS2_CTRIPOUTL = 0x0600, + XBAR_OUT_MUX03_INPUTXBAR2 = 0x0601, + XBAR_OUT_MUX03_CLB1_OUT5 = 0x0602, + XBAR_OUT_MUX03_ADCCEVT2 = 0x0603, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH = 0x0800, + XBAR_OUT_MUX04_CMPSS3_CTRIPOUTH_OR_L = 0x0801, + XBAR_OUT_MUX04_ADCAEVT3 = 0x0802, + XBAR_OUT_MUX04_ECAP3_OUT = 0x0803, + XBAR_OUT_MUX05_CMPSS3_CTRIPOUTL = 0x0A00, + XBAR_OUT_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_OUT_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_OUT_MUX05_ADCCEVT3 = 0x0A03, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH = 0x0C00, + XBAR_OUT_MUX06_CMPSS4_CTRIPOUTH_OR_L = 0x0C01, + XBAR_OUT_MUX06_ADCAEVT4 = 0x0C02, + XBAR_OUT_MUX06_ECAP4_OUT = 0x0C03, + XBAR_OUT_MUX07_CMPSS4_CTRIPOUTL = 0x0E00, + XBAR_OUT_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_OUT_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_OUT_MUX07_ADCCEVT4 = 0x0E03, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH = 0x1000, + XBAR_OUT_MUX08_CMPSS5_CTRIPOUTH_OR_L = 0x1001, + XBAR_OUT_MUX08_ADCBEVT1 = 0x1002, + XBAR_OUT_MUX08_ECAP5_OUT = 0x1003, + XBAR_OUT_MUX09_CMPSS5_CTRIPOUTL = 0x1200, + XBAR_OUT_MUX09_INPUTXBAR5 = 0x1201, + XBAR_OUT_MUX09_CLB3_OUT4 = 0x1202, + XBAR_OUT_MUX09_ADCDEVT1 = 0x1203, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH = 0x1400, + XBAR_OUT_MUX10_CMPSS6_CTRIPOUTH_OR_L = 0x1401, + XBAR_OUT_MUX10_ADCBEVT2 = 0x1402, + XBAR_OUT_MUX10_ECAP6_OUT = 0x1403, + XBAR_OUT_MUX11_CMPSS6_CTRIPOUTL = 0x1600, + XBAR_OUT_MUX11_INPUTXBAR6 = 0x1601, + XBAR_OUT_MUX11_CLB3_OUT5 = 0x1602, + XBAR_OUT_MUX11_ADCDEVT2 = 0x1603, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH = 0x1800, + XBAR_OUT_MUX12_CMPSS7_CTRIPOUTH_OR_L = 0x1801, + XBAR_OUT_MUX12_ADCBEVT3 = 0x1802, + XBAR_OUT_MUX13_CMPSS7_CTRIPOUTL = 0x1A00, + XBAR_OUT_MUX13_ADCSOCA = 0x1A01, + XBAR_OUT_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_OUT_MUX13_ADCDEVT3 = 0x1A03, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH = 0x1C00, + XBAR_OUT_MUX14_CMPSS8_CTRIPOUTH_OR_L = 0x1C01, + XBAR_OUT_MUX14_ADCBEVT4 = 0x1C02, + XBAR_OUT_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_OUT_MUX15_CMPSS8_CTRIPOUTL = 0x1E00, + XBAR_OUT_MUX15_ADCSOCB = 0x1E01, + XBAR_OUT_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_OUT_MUX15_ADCDEVT4 = 0x1E03, + XBAR_OUT_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_OUT_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_OUT_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_OUT_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_OUT_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_OUT_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_OUT_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_OUT_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_OUT_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_OUT_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_OUT_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_OUT_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_OUT_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_OUT_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_OUT_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_OUT_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_OUT_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_OUT_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_OUT_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_OUT_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_OUT_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_OUT_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_OUT_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_OUT_MUX31_SD2FLT4_COMPL = 0x3E00, + +} XBAR_OutputMuxConfig; + +//***************************************************************************** +// +//! The following values define the \e muxConfig parameter for +//! XBAR_setEPWMMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_EPWM_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_EPWM_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_EPWM_MUX00_ADCAEVT1 = 0x0002, + XBAR_EPWM_MUX00_ECAP1_OUT = 0x0003, + XBAR_EPWM_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_EPWM_MUX01_INPUTXBAR1 = 0x0201, + XBAR_EPWM_MUX01_CLB1_OUT4 = 0x0202, + XBAR_EPWM_MUX01_ADCCEVT1 = 0x0203, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_EPWM_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_EPWM_MUX02_ADCAEVT2 = 0x0402, + XBAR_EPWM_MUX02_ECAP2_OUT = 0x0403, + XBAR_EPWM_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_EPWM_MUX03_INPUTXBAR2 = 0x0601, + XBAR_EPWM_MUX03_CLB1_OUT5 = 0x0602, + XBAR_EPWM_MUX03_ADCCEVT2 = 0x0603, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_EPWM_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_EPWM_MUX04_ADCAEVT3 = 0x0802, + XBAR_EPWM_MUX04_ECAP3_OUT = 0x0803, + XBAR_EPWM_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_EPWM_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_EPWM_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_EPWM_MUX05_ADCCEVT3 = 0x0A03, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_EPWM_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_EPWM_MUX06_ADCAEVT4 = 0x0C02, + XBAR_EPWM_MUX06_ECAP4_OUT = 0x0C03, + XBAR_EPWM_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_EPWM_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_EPWM_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_EPWM_MUX07_ADCCEVT4 = 0x0E03, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_EPWM_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_EPWM_MUX08_ADCBEVT1 = 0x1002, + XBAR_EPWM_MUX08_ECAP5_OUT = 0x1003, + XBAR_EPWM_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_EPWM_MUX09_INPUTXBAR5 = 0x1201, + XBAR_EPWM_MUX09_CLB3_OUT4 = 0x1202, + XBAR_EPWM_MUX09_ADCDEVT1 = 0x1203, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_EPWM_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_EPWM_MUX10_ADCBEVT2 = 0x1402, + XBAR_EPWM_MUX10_ECAP6_OUT = 0x1403, + XBAR_EPWM_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_EPWM_MUX11_INPUTXBAR6 = 0x1601, + XBAR_EPWM_MUX11_CLB3_OUT5 = 0x1602, + XBAR_EPWM_MUX11_ADCDEVT2 = 0x1603, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_EPWM_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_EPWM_MUX12_ADCBEVT3 = 0x1802, + XBAR_EPWM_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_EPWM_MUX13_ADCSOCA = 0x1A01, + XBAR_EPWM_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_EPWM_MUX13_ADCDEVT3 = 0x1A03, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_EPWM_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_EPWM_MUX14_ADCBEVT4 = 0x1C02, + XBAR_EPWM_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_EPWM_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_EPWM_MUX15_ADCSOCB = 0x1E01, + XBAR_EPWM_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_EPWM_MUX15_ADCDEVT4 = 0x1E03, + XBAR_EPWM_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_EPWM_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_EPWM_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_EPWM_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_EPWM_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_EPWM_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_EPWM_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_EPWM_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_EPWM_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_EPWM_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_EPWM_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_EPWM_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_EPWM_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_EPWM_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_EPWM_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_EPWM_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_EPWM_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_EPWM_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_EPWM_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_EPWM_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_EPWM_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_EPWM_MUX31_SD2FLT4_COMPL = 0x3E00 +} XBAR_EPWMMuxConfig; + +//***************************************************************************** +// +// The following values define the muxConfig parameter for +// XBAR_setCLBMuxConfig(). +// +//***************************************************************************** +typedef enum +{ + XBAR_CLB_MUX00_CMPSS1_CTRIPH = 0x0000, + XBAR_CLB_MUX00_CMPSS1_CTRIPH_OR_L = 0x0001, + XBAR_CLB_MUX00_ADCAEVT1 = 0x0002, + XBAR_CLB_MUX00_ECAP1_OUT = 0x0003, + XBAR_CLB_MUX01_CMPSS1_CTRIPL = 0x0200, + XBAR_CLB_MUX01_INPUTXBAR1 = 0x0201, + XBAR_CLB_MUX01_CLB1_OUT4 = 0x0202, + XBAR_CLB_MUX01_ADCCEVT1 = 0x0203, + XBAR_CLB_MUX02_CMPSS2_CTRIPH = 0x0400, + XBAR_CLB_MUX02_CMPSS2_CTRIPH_OR_L = 0x0401, + XBAR_CLB_MUX02_ADCAEVT2 = 0x0402, + XBAR_CLB_MUX02_ECAP2_OUT = 0x0403, + XBAR_CLB_MUX03_CMPSS2_CTRIPL = 0x0600, + XBAR_CLB_MUX03_INPUTXBAR2 = 0x0601, + XBAR_CLB_MUX03_CLB1_OUT5 = 0x0602, + XBAR_CLB_MUX03_ADCCEVT2 = 0x0603, + XBAR_CLB_MUX04_CMPSS3_CTRIPH = 0x0800, + XBAR_CLB_MUX04_CMPSS3_CTRIPH_OR_L = 0x0801, + XBAR_CLB_MUX04_ADCAEVT3 = 0x0802, + XBAR_CLB_MUX04_ECAP3_OUT = 0x0803, + XBAR_CLB_MUX05_CMPSS3_CTRIPL = 0x0A00, + XBAR_CLB_MUX05_INPUTXBAR3 = 0x0A01, + XBAR_CLB_MUX05_CLB2_OUT4 = 0x0A02, + XBAR_CLB_MUX05_ADCCEVT3 = 0x0A03, + XBAR_CLB_MUX06_CMPSS4_CTRIPH = 0x0C00, + XBAR_CLB_MUX06_CMPSS4_CTRIPH_OR_L = 0x0C01, + XBAR_CLB_MUX06_ADCAEVT4 = 0x0C02, + XBAR_CLB_MUX06_ECAP4_OUT = 0x0C03, + XBAR_CLB_MUX07_CMPSS4_CTRIPL = 0x0E00, + XBAR_CLB_MUX07_INPUTXBAR4 = 0x0E01, + XBAR_CLB_MUX07_CLB2_OUT5 = 0x0E02, + XBAR_CLB_MUX07_ADCCEVT4 = 0x0E03, + XBAR_CLB_MUX08_CMPSS5_CTRIPH = 0x1000, + XBAR_CLB_MUX08_CMPSS5_CTRIPH_OR_L = 0x1001, + XBAR_CLB_MUX08_ADCBEVT1 = 0x1002, + XBAR_CLB_MUX08_ECAP5_OUT = 0x1003, + XBAR_CLB_MUX09_CMPSS5_CTRIPL = 0x1200, + XBAR_CLB_MUX09_INPUTXBAR5 = 0x1201, + XBAR_CLB_MUX09_CLB3_OUT4 = 0x1202, + XBAR_CLB_MUX09_ADCDEVT1 = 0x1203, + XBAR_CLB_MUX10_CMPSS6_CTRIPH = 0x1400, + XBAR_CLB_MUX10_CMPSS6_CTRIPH_OR_L = 0x1401, + XBAR_CLB_MUX10_ADCBEVT2 = 0x1402, + XBAR_CLB_MUX10_ECAP6_OUT = 0x1403, + XBAR_CLB_MUX11_CMPSS6_CTRIPL = 0x1600, + XBAR_CLB_MUX11_INPUTXBAR6 = 0x1601, + XBAR_CLB_MUX11_CLB3_OUT5 = 0x1602, + XBAR_CLB_MUX11_ADCDEVT2 = 0x1603, + XBAR_CLB_MUX12_CMPSS7_CTRIPH = 0x1800, + XBAR_CLB_MUX12_CMPSS7_CTRIPH_OR_L = 0x1801, + XBAR_CLB_MUX12_ADCBEVT3 = 0x1802, + XBAR_CLB_MUX13_CMPSS7_CTRIPL = 0x1A00, + XBAR_CLB_MUX13_ADCSOCA = 0x1A01, + XBAR_CLB_MUX13_CLB4_OUT4 = 0x1A02, + XBAR_CLB_MUX13_ADCDEVT3 = 0x1A03, + XBAR_CLB_MUX14_CMPSS8_CTRIPH = 0x1C00, + XBAR_CLB_MUX14_CMPSS8_CTRIPH_OR_L = 0x1C01, + XBAR_CLB_MUX14_ADCBEVT4 = 0x1C02, + XBAR_CLB_MUX14_EXTSYNCOUT = 0x1C03, + XBAR_CLB_MUX15_CMPSS8_CTRIPL = 0x1E00, + XBAR_CLB_MUX15_ADCSOCB = 0x1E01, + XBAR_CLB_MUX15_CLB4_OUT5 = 0x1E02, + XBAR_CLB_MUX15_ADCDEVT4 = 0x1E03, + XBAR_CLB_MUX16_SD1FLT1_COMPH = 0x2000, + XBAR_CLB_MUX16_SD1FLT1_COMPH_OR_COMPL = 0x2001, + XBAR_CLB_MUX17_SD1FLT1_COMPL = 0x2200, + XBAR_CLB_MUX18_SD1FLT2_COMPH = 0x2400, + XBAR_CLB_MUX18_SD1FLT2_COMPH_OR_COMPL = 0x2401, + XBAR_CLB_MUX19_SD1FLT2_COMPL = 0x2600, + XBAR_CLB_MUX20_SD1FLT3_COMPH = 0x2800, + XBAR_CLB_MUX20_SD1FLT3_COMPH_OR_COMPL = 0x2801, + XBAR_CLB_MUX21_SD1FLT3_COMPL = 0x2A00, + XBAR_CLB_MUX22_SD1FLT4_COMPH = 0x2C00, + XBAR_CLB_MUX22_SD1FLT4_COMPH_OR_COMPL = 0x2C01, + XBAR_CLB_MUX23_SD1FLT4_COMPL = 0x2E00, + XBAR_CLB_MUX24_SD2FLT1_COMPH = 0x3000, + XBAR_CLB_MUX24_SD2FLT1_COMPH_OR_COMPL = 0x3001, + XBAR_CLB_MUX25_SD2FLT1_COMPL = 0x3200, + XBAR_CLB_MUX26_SD2FLT2_COMPH = 0x3400, + XBAR_CLB_MUX26_SD2FLT2_COMPH_OR_COMPL = 0x3401, + XBAR_CLB_MUX27_SD2FLT2_COMPL = 0x3600, + XBAR_CLB_MUX28_SD2FLT3_COMPH = 0x3800, + XBAR_CLB_MUX28_SD2FLT3_COMPH_OR_COMPL = 0x3801, + XBAR_CLB_MUX29_SD2FLT3_COMPL = 0x3A00, + XBAR_CLB_MUX30_SD2FLT4_COMPH = 0x3C00, + XBAR_CLB_MUX30_SD2FLT4_COMPH_OR_COMPL = 0x3C01, + XBAR_CLB_MUX31_SD2FLT4_COMPL = 0x3E00, +} XBAR_CLBMuxConfig; + + +//***************************************************************************** +// +//! The following values define the \e inputFlag parameter for +//! XBAR_getInputFlagStatus() and XBAR_clearInputFlag(). +// +//***************************************************************************** +typedef enum +{ + // + // XBARFLG1 + // + XBAR_INPUT_FLG_CMPSS1_CTRIPL = 0x0000, + XBAR_INPUT_FLG_CMPSS1_CTRIPH = 0x0001, + XBAR_INPUT_FLG_CMPSS2_CTRIPL = 0x0002, + XBAR_INPUT_FLG_CMPSS2_CTRIPH = 0x0003, + XBAR_INPUT_FLG_CMPSS3_CTRIPL = 0x0004, + XBAR_INPUT_FLG_CMPSS3_CTRIPH = 0x0005, + XBAR_INPUT_FLG_CMPSS4_CTRIPL = 0x0006, + XBAR_INPUT_FLG_CMPSS4_CTRIPH = 0x0007, + XBAR_INPUT_FLG_CMPSS5_CTRIPL = 0x0008, + XBAR_INPUT_FLG_CMPSS5_CTRIPH = 0x0009, + XBAR_INPUT_FLG_CMPSS6_CTRIPL = 0x000A, + XBAR_INPUT_FLG_CMPSS6_CTRIPH = 0x000B, + XBAR_INPUT_FLG_CMPSS7_CTRIPL = 0x000C, + XBAR_INPUT_FLG_CMPSS7_CTRIPH = 0x000D, + XBAR_INPUT_FLG_CMPSS8_CTRIPL = 0x000E, + XBAR_INPUT_FLG_CMPSS8_CTRIPH = 0x000F, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTL = 0x0010, + XBAR_INPUT_FLG_CMPSS1_CTRIPOUTH = 0x0011, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTL = 0x0012, + XBAR_INPUT_FLG_CMPSS2_CTRIPOUTH = 0x0013, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTL = 0x0014, + XBAR_INPUT_FLG_CMPSS3_CTRIPOUTH = 0x0015, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTL = 0x0016, + XBAR_INPUT_FLG_CMPSS4_CTRIPOUTH = 0x0017, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTL = 0x0018, + XBAR_INPUT_FLG_CMPSS5_CTRIPOUTH = 0x0019, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTL = 0x001A, + XBAR_INPUT_FLG_CMPSS6_CTRIPOUTH = 0x001B, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTL = 0x001C, + XBAR_INPUT_FLG_CMPSS7_CTRIPOUTH = 0x001D, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTL = 0x001E, + XBAR_INPUT_FLG_CMPSS8_CTRIPOUTH = 0x001F, + // + // XBARFLG2 + // + XBAR_INPUT_FLG_INPUT1 = 0x0100, + XBAR_INPUT_FLG_INPUT2 = 0x0101, + XBAR_INPUT_FLG_INPUT3 = 0x0102, + XBAR_INPUT_FLG_INPUT4 = 0x0103, + XBAR_INPUT_FLG_INPUT5 = 0x0104, + XBAR_INPUT_FLG_INPUT6 = 0x0105, + XBAR_INPUT_FLG_ADCSOCA = 0x0106, + XBAR_INPUT_FLG_ADCSOCB = 0x0107, + XBAR_INPUT_FLG_CLB1_OUT4 = 0x0108, + XBAR_INPUT_FLG_CLB1_OUT5 = 0x0109, + XBAR_INPUT_FLG_CLB2_OUT4 = 0x010A, + XBAR_INPUT_FLG_CLB2_OUT5 = 0x010B, + XBAR_INPUT_FLG_CLB3_OUT4 = 0x010C, + XBAR_INPUT_FLG_CLB3_OUT5 = 0x010D, + XBAR_INPUT_FLG_CLB4_OUT4 = 0x010E, + XBAR_INPUT_FLG_CLB4_OUT5 = 0x010F, + XBAR_INPUT_FLG_ECAP1_OUT = 0x0110, + XBAR_INPUT_FLG_ECAP2_OUT = 0x0111, + XBAR_INPUT_FLG_ECAP3_OUT = 0x0112, + XBAR_INPUT_FLG_ECAP4_OUT = 0x0113, + XBAR_INPUT_FLG_ECAP5_OUT = 0x0114, + XBAR_INPUT_FLG_ECAP6_OUT = 0x0115, + XBAR_INPUT_FLG_EXTSYNCOUT = 0x0116, + XBAR_INPUT_FLG_ADCAEVT1 = 0x0117, + XBAR_INPUT_FLG_ADCAEVT2 = 0x0118, + XBAR_INPUT_FLG_ADCAEVT3 = 0x0119, + XBAR_INPUT_FLG_ADCAEVT4 = 0x011A, + XBAR_INPUT_FLG_ADCBEVT1 = 0x011B, + XBAR_INPUT_FLG_ADCBEVT2 = 0x011C, + XBAR_INPUT_FLG_ADCBEVT3 = 0x011D, + XBAR_INPUT_FLG_ADCBEVT4 = 0x011E, + XBAR_INPUT_FLG_ADCCEVT1 = 0x011F, + // + // XBARFLG3 + // + XBAR_INPUT_FLG_ADCCEVT2 = 0x0200, + XBAR_INPUT_FLG_ADCCEVT3 = 0x0201, + XBAR_INPUT_FLG_ADCCEVT4 = 0x0202, + XBAR_INPUT_FLG_ADCDEVT1 = 0x0203, + XBAR_INPUT_FLG_ADCDEVT2 = 0x0204, + XBAR_INPUT_FLG_ADCDEVT3 = 0x0205, + XBAR_INPUT_FLG_ADCDEVT4 = 0x0206, + XBAR_INPUT_FLG_SD1FLT1_COMPL = 0x0207, + XBAR_INPUT_FLG_SD1FLT1_COMPH = 0x0208, + XBAR_INPUT_FLG_SD1FLT2_COMPL = 0x0209, + XBAR_INPUT_FLG_SD1FLT2_COMPH = 0x020A, + XBAR_INPUT_FLG_SD1FLT3_COMPL = 0x020B, + XBAR_INPUT_FLG_SD1FLT3_COMPH = 0x020C, + XBAR_INPUT_FLG_SD1FLT4_COMPL = 0x020D, + XBAR_INPUT_FLG_SD1FLT4_COMPH = 0x020E, + XBAR_INPUT_FLG_SD2FLT1_COMPL = 0x020F, + XBAR_INPUT_FLG_SD2FLT1_COMPH = 0x0210, + XBAR_INPUT_FLG_SD2FLT2_COMPL = 0x0211, + XBAR_INPUT_FLG_SD2FLT2_COMPH = 0x0212, + XBAR_INPUT_FLG_SD2FLT3_COMPL = 0x0213, + XBAR_INPUT_FLG_SD2FLT3_COMPH = 0x0214, + XBAR_INPUT_FLG_SD2FLT4_COMPL = 0x0215, + XBAR_INPUT_FLG_SD2FLT4_COMPH = 0x0216 +} XBAR_InputFlag; +#endif + +//***************************************************************************** +// +// Prototypes for the APIs. +// +//***************************************************************************** +//***************************************************************************** +// +//! Enables the Output X-BAR mux values to be passed to the output signal. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to enable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would enable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) |= muxes; + + EDIS; + + +} + +//***************************************************************************** +// +//! Disables the Output X-BAR mux values from being passed to the output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values from being passed to the X-BAR output +//! signal. The \e output parameter is a value \b XBAR_OUTPUTy where y is +//! the output number between 1 and 8 inclusive. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be OR'd together to disable several +//! muxes on an output at the same time. For example, passing this function +//! ( \b XBAR_MUX04 | \b XBAR_MUX10 ) would disable muxes 4 and 10. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableOutputMux(XBAR_OutputNum output, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_OUTPUT_EN_REG_BASE + (uint16_t)output) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Enables or disables the output latch to drive the selected output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param enable is a flag that determines whether or not the latch is +//! selected to drive the X-BAR output. +//! +//! This function sets the Output X-BAR output signal latch mode. If the +//! \e enable parameter is \b true, the output specified by \e output will be +//! driven by the output latch. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setOutputLatchMode(XBAR_OutputNum output, bool enable) +{ + EALLOW; + + // + // Set or clear the latch setting bit based on the enable parameter. + // + if(enable) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHENABLE) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Returns the status of the output latch +//! +//! \param output is the X-BAR output being checked. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! \return Returns \b true if the output corresponding to \e output was +//! triggered. If not, it will return \b false. +// +//***************************************************************************** +static inline bool +XBAR_getOutputLatchStatus(XBAR_OutputNum output) +{ + // + // Get the status of the Output X-BAR output latch. + // + return((HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCH) & + (0x1U << ((uint16_t)output / 2U))) != 0U); +} + +//***************************************************************************** +// +//! Clears the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function clears the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_clearOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that clears the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHCLR) |= + 0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Forces the output latch for the specified output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! +//! This function forces the Output X-BAR output latch. The output to be +//! configured is specified by the \e output parameter. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_forceOutputLatch(XBAR_OutputNum output) +{ + // + // Set the bit that forces the corresponding OUTPUTLATCH bit. + // + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLATCHFRC) = + (uint16_t)0x1U << ((uint16_t)output / 2U); +} + +//***************************************************************************** +// +//! Configures the polarity of an Output X-BAR output. +//! +//! \param output is the X-BAR output being configured. +//! The valid inputs are XBAR_OUTPUTy where y is from 1 to 8. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the Output X-BAR signal if the \e invert parameter is +//! \b true. If \e invert is \b false, the signal will be passed as is. The +//! \e output parameter is a value \b XBAR_OUTPUTy where y is the output +//! number between 1 and 8 inclusive. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertOutputSignal(XBAR_OutputNum output, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) |= + 0x1U << ((uint16_t)output / 2U); + } + else + { + HWREGH(OUTPUTXBAR_BASE + XBAR_O_OUTPUTINV) &= + ~(0x1U << ((uint16_t)output / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Enables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) |= muxes; + EDIS; +} + +//***************************************************************************** +// +//! Disables the ePWM X-BAR mux values to be passed to an ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR trip +//! signal. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableEPWMMux(XBAR_TripNum trip, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_EPWM_EN_REG_BASE + (uint32_t)trip) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an ePWM X-BAR output. +//! +//! \param trip is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the ePWM X-BAR trip signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e trip parameter is a value \b XBAR_TRIPy where y is +//! the number of the trip signal on the ePWM X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertEPWMSignal(XBAR_TripNum trip, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) |= + 0x1U << ((uint16_t)trip / 2U); + } + else + { + HWREGH(EPWMXBAR_BASE + XBAR_O_TRIPOUTINV) &= + ~(0x1U << ((uint16_t)trip / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Sets the GPIO pin for an Input X-BAR input. +//! +//! \param input is the X-BAR input being configured. +//! \param pin is the identifying number of the pin. +//! +//! This function configures which GPIO is assigned to an Input X-BAR input. +//! The \e input parameter is a value in the form of a define \b XBAR_INPUTy +//! where y is a the input number for the Input X-BAR. +//! +//! The pin is specified by its numerical value. For example, GPIO34 is +//! specified by passing 34 as \e pin. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_setInputPin(XBAR_InputNum input, uint16_t pin) +{ + // + // Check the argument. + // + ASSERT(pin <= XBAR_GPIO_MAX_CNT); + + // + // Write the requested pin to the appropriate input select register. + // + EALLOW; + + HWREGH(XBAR_INPUT_BASE + (uint16_t)input) = pin; + + EDIS; +} + +//***************************************************************************** +// +//! Locks an input to the Input X-BAR. +//! +//! \param input is an input to the Input X-BAR. +//! +//! This function locks the specific input on the Input X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockInput(XBAR_InputNum input) +{ + // + // lock the input in the INPUTSELECTLOCK register. + // + EALLOW; + HWREG(INPUTXBAR_BASE + XBAR_O_INPUTSELECTLOCK) = + 1UL << (uint16_t)input; + EDIS; +} + +//***************************************************************************** +// +//! Locks the Output X-BAR. +//! +//! This function locks the Output X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockOutput(void) +{ + // + // Lock the Output X-BAR with the OUTPUTLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(OUTPUTXBAR_BASE + XBAR_O_OUTPUTLOCK) = + ((uint32_t)0x5A5A << XBAR_OUTPUTLOCK_KEY_S) | + (uint32_t)XBAR_OUTPUTLOCK_LOCK; + + EDIS; +} + +//***************************************************************************** +// +//! Locks the ePWM X-BAR. +//! +//! This function locks the ePWM X-BAR. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_lockEPWM(void) +{ + // + // Lock the ePWM X-BAR with the TRIPLOCK register. + // Write key 0x5A5A to the KEY bits and 1 to LOCK bit. + // + EALLOW; + + HWREG(EPWMXBAR_BASE + XBAR_O_TRIPLOCK) = + ((uint32_t)0x5A5A << XBAR_TRIPLOCK_KEY_S) | + (uint32_t)XBAR_TRIPLOCK_LOCK; + EDIS; +} + +//***************************************************************************** +// +//! Enables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be enabled. +//! +//! This function enables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being enabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! enable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_enableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Set the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) |= muxes; + + EDIS; +} + +//***************************************************************************** +// +//! Disables the CLB X-BAR mux values to be passed to an CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxes is a bit field of the muxes to be disabled. +//! +//! This function disables the mux values to be passed to the X-BAR auxSignal +//! signal. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB. +//! +//! The \e muxes parameter is a bit field of the muxes being disabled where bit +//! 0 represents mux 0, bit 1 represents mux 1 and so on. Defines are provided +//! in the form of \b XBAR_MUXnn that can be logically OR'd together to +//! disable several muxes on an output at the same time. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_disableCLBMux(XBAR_AuxSigNum auxSignal, uint32_t muxes) +{ + // + // Clear the enable bit. + // + EALLOW; + + HWREG(XBAR_CLB_EN_REG_BASE + (uint32_t)auxSignal) &= ~(muxes); + + EDIS; +} + +//***************************************************************************** +// +//! Configures the polarity of an CLB X-BAR output. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param invert is a flag that determines whether the output is active-high +//! or active-low. +//! +//! This function inverts the CLB X-BAR auxSignal signal if the \e invert +//! parameter is \b true. If \e invert is \b false, the signal will be passed +//! as is. The \e auxSignal parameter is a value \b XBAR_AUXSIGy where y is +//! the number of the signal on the CLB X-BAR that is being configured. +//! +//! \return None. +// +//***************************************************************************** +static inline void +XBAR_invertCLBSignal(XBAR_AuxSigNum auxSignal, bool invert) +{ + // + // Set or clear the polarity setting bit based on the invert parameter. + // + EALLOW; + + if(invert) + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) |= + 0x1U << ((uint16_t)auxSignal / 2U); + } + else + { + HWREGH(CLBXBAR_BASE + XBAR_O_AUXSIGOUTINV) &= + ~(0x1U << ((uint16_t)auxSignal / 2U)); + } + + EDIS; +} + +//***************************************************************************** +// +//! Configures the Output X-BAR mux that determines the signals passed to an +//! output. +//! +//! \param output is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an Output X-BAR mux. This determines which +//! signal(s) should be passed through the X-BAR to a GPIO. The \e output +//! parameter is a value \b XBAR_OUTPUTy where y is a the output number +//! between 1 and 8 inclusive. +//! +//! The \e muxConfig parameter for OUTPUT XBAR is the mux configuration +//! value that specifies which signal will be passed from the mux. The +//! values have the format of \b XBAR_OUT_MUXnn_xx where the 'xx' is +//! the signal and nn is the mux number. +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the output signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_OUT_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_OUT_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setOutputMuxConfig(XBAR_OutputNum output, XBAR_OutputMuxConfig muxConfig); + +//***************************************************************************** +// +//! Configures the ePWM X-BAR mux that determines the signals passed to an +//! ePWM module. +//! +//! \param trip is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an ePWM X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an ePWM module. The \e trip +//! parameter is a value \b XBAR_TRIPy where y is a the number of the trip +//! signal on the ePWM. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_EPWM_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the trip signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_EPWM_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_EPWM_MUX01_INPUTXBAR1, resulting in the values of MUX00 and MUX01 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_setEPWMMuxConfig(XBAR_TripNum trip, XBAR_EPWMMuxConfig muxConfig); + +//***************************************************************************** +// +//! Returns the status of the input latch. +//! +//! \param inputFlag is the X-BAR input latch being checked. Values are in the +//! format of /b XBAR_INPUT_FLG_XXXX where "XXXX" is name of the signal. +//! +//! \return Returns \b true if the X-BAR input corresponding to the +//! \e inputFlag has been triggered. If not, it will return \b false. +// +//***************************************************************************** +extern bool +XBAR_getInputFlagStatus(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Clears the input latch for the specified input latch. +//! +//! \param inputFlag is the X-BAR input latch being cleared. +//! +//! This function clears the Input X-BAR input latch. The input latch to be +//! cleared is specified by the \e inputFlag parameter. +//! +//! \return None. +// +//***************************************************************************** +extern void +XBAR_clearInputFlag(XBAR_InputFlag inputFlag); + +//***************************************************************************** +// +//! Configures the CLB X-BAR mux that determines the signals passed to a +//! CLB module. +//! +//! \param auxSignal is the X-BAR output being configured. +//! \param muxConfig is mux configuration that specifies the signal. +//! +//! This function configures an CLB X-BAR mux. This determines which signal(s) +//! should be passed through the X-BAR to an CLB module. The \e auxSignal +//! parameter is a value \b XBAR_AUXSIGy where y is a the number of the +//! signal on the CLB. +//! +//! The \e muxConfig parameter is the mux configuration value that specifies +//! which signal will be passed from the mux. The values have the format of +//! \b XBAR_CLB_MUXnn_xx where the 'xx' is the signal and nn is the mux +//! number (0 through 31). The possible values are found in xbar.h +//! +//! This function may be called for each mux of an output and their values will +//! be logically OR'd before being passed to the signal. This means that +//! this function may be called, for example, with the argument +//! \b XBAR_CLB_MUX00_ECAP1_OUT and then with the argument +//! \b XBAR_CLB_MUX03_INPUTXBAR2, resulting in the values of MUX00 and MUX03 +//! being logically OR'd if both are enabled. Calling the function twice for +//! the same mux on the output will result in the configuration in the second +//! call overwriting the first. +//! +//! \return None. +// +//***************************************************************************** +extern void XBAR_setCLBMuxConfig(XBAR_AuxSigNum auxSignal, + XBAR_CLBMuxConfig muxConfig); + +//***************************************************************************** +// +// Close the Doxygen group. +//! @} +// +//***************************************************************************** + +//***************************************************************************** +// +// Mark the end of the C bindings section for C++ compilers. +// +//***************************************************************************** +#ifdef __cplusplus +} +#endif + +#endif // XBAR_H diff --git a/gpio_driverlib_cpu1/gpio_driverlib_cpu1.c b/gpio_driverlib_cpu1/gpio_driverlib_cpu1.c new file mode 100644 index 0000000..e69de29 diff --git a/gpio_driverlib_cpu1/targetConfigs/TMS320F28377D.ccxml b/gpio_driverlib_cpu1/targetConfigs/TMS320F28377D.ccxml new file mode 100644 index 0000000..79dd5cc --- /dev/null +++ b/gpio_driverlib_cpu1/targetConfigs/TMS320F28377D.ccxml @@ -0,0 +1,22 @@ + + + + + + + + + + + + + + + + + + + + + + diff --git a/gpio_driverlib_cpu1/targetConfigs/readme.txt b/gpio_driverlib_cpu1/targetConfigs/readme.txt new file mode 100644 index 0000000..af97b62 --- /dev/null +++ b/gpio_driverlib_cpu1/targetConfigs/readme.txt @@ -0,0 +1,9 @@ +The 'targetConfigs' folder contains target-configuration (.ccxml) files, automatically generated based +on the device and connection settings specified in your project on the Properties > General page. + +Please note that in automatic target-configuration management, changes to the project's device and/or +connection settings will either modify an existing or generate a new target-configuration file. Thus, +if you manually edit these auto-generated files, you may need to re-apply your changes. Alternatively, +you may create your own target-configuration file for this project and manage it manually. You can +always switch back to automatic target-configuration management by checking the "Manage the project's +target-configuration automatically" checkbox on the project's Properties > General page. \ No newline at end of file