diff --git a/Readme.md b/Readme.md
index 20fa7a6..d1ea482 100644
--- a/Readme.md
+++ b/Readme.md
@@ -124,6 +124,7 @@ The following sections progressively fill in these steps. Register names are tho
 
 # 5 CPU1 code
 
+## initial steps
 - `CLK_CFG_REGS` Registers (section 3.17.11)-> PERCLKDIVSEL -> F2837xD_sysctrl.h
 - `DEV_CFG_REGS` (section 3.17.10), same file
 - `CPU_SYS_REGS` (section 3.17.12) -> PCLKCR2 register has the pwm bits -> F2837xD_sysctrl.h -> search for the struct `CPU_SYS_REGS ` 
@@ -227,6 +228,105 @@ void main(void)
 
 ```
 
+## Configuring actions
+
+```c
+#include "F28x_Project.h"
+#include "driverlib.h"
+#include "device.h"
+
+__interrupt void epwm1_isr(void) { /* TODO */ }
+__interrupt void epwm1_trip_isr(void) { /* TODO */ }
+__interrupt void epwm2_trip_isr(void) { /* TODO */ }
+
+void main(void)
+{
+    // 1. Initialize the system and interrupts.
+    InitSysCtrl();
+    EALLOW;
+    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; 
+    EDIS;
+    
+    // 2. Select ePWM clocks and assign CPU ownership.
+    EALLOW;
+    DevCfgRegs.CPUSEL0.bit.EPWM1 = 0; //cpu0
+    DevCfgRegs.CPUSEL0.bit.EPWM2 = 0;
+    DevCfgRegs.CPUSEL0.bit.EPWM4 = 1; //cpu1
+    DevCfgRegs.CPUSEL0.bit.EPWM5 = 1;
+    EDIS;
+    
+    // 3. Enable ePWM1 and ePWM2 clocks.
+    EALLOW;
+    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1;
+    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1;
+    EDIS;
+    
+    // 4. Stop time-base synchronization.
+    EALLOW;
+    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 1; //stop the timer
+    EDIS;
+    
+    // 5. Configure TB and CC.
+    // Configure the eWM modules 1 and 2
+		// Time base sub-module
+		// 100 MHz. TBCLK = 100 / (2 * 1) = 50 Mhz
+		EPwm1Regs.TBCTL.bit.FREE_SOFT = 2; // 2 or 3
+		EPwm1Regs.TBCTL.bit.CLKDIV = 0; I
+		EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1;
+		EPwm1Regs.TBCTL.bit.PRDLD = 0;
+		EPwm1Regs.TBCTL.bit.CTRMODE = 0;
+		
+		EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; // 2 or 3
+		EPwm2Regs.TBCTL.bit.CLKDIV = 0; I
+		EPwm2Regs.TBCTL.bit.HSPCLKDIV = 1;
+		EPwm2Regs.TBCTL.bit.PRDLD = 0;
+		EPwm2Regs.TBCTL.bit.CTRMODE = 2; // up-down count mode
+		
+		//Period registers
+		EPwm1Regs. TBPRD = 5000 - 1; // 10 kHz sawtooth
+		EPwm2Regs. TBPRD = 5000;      // 5 kHz triangular
+		
+		// Counter-compare sub-module
+		EPwm1Regs.CMPCTL.bit.SHDWAMODE = 0;
+		EPwm1Regs.CMPCTL.bit.LOADAMODE = 0;
+		
+		EPwm1Regs.CMPA.bit.CMPA = 1999;
+		
+		EPwm2Regs.CMPCTL.bit.SHDWAMODE = 0;
+		EPwm2Regs.CMPCTL.bit.LOADAMODE = 0;
+		
+		EPwm2Regs. CMPA.bit. CMPA = (uint16_t) ( ((-0.3+1)/2.0) * 5000 );
+	
+    // 6. Configure AQ and dead band.
+    
+    // Action qualifier sub-module
+		// ePWM1 - A output to be fed to the upper device of a leg
+		// B output to be fed to the lower device of a leg
+		// TBCTR = 0, A will be high, B will be low (ZRO - AQCTLA/B)
+		// TBCTR = CMPA. A will be low and B will be high (CAU - AQCTLA/B)
+		EPwm1Regs. AQCTLA.bit.ZRO = 2;
+		EPwm1Regs .AQCTLB.bit.ZRO = 1;
+		EPwm1Regs .AQCTLA.bit.CAU = 1;
+		EPwm1Regs.AQCTLB.bit.CAU = 2;
+		
+		// ePWM2 - A output to be fed to the upper device of a leg
+		// B output to be fed to the lower device of a leg
+		// TBCTR = CMPA first half, A will be high, B will be low (CAU - AQCTLA/B)
+		// TBCTR = CMPA second half. A will be low and B will be high (CAD - AQCTLA/B)
+		
+		EPwm2Regs. AQCTLA.bit.ZROI = 2;
+		EPwm2Regs .AQCTLB.bit.ZRO = 1;
+		EPwm2Regs. AQCTLA.bit.CAU = 1;
+		EPwm2Regs. AQCTLB.bit.CAU = 2;
+    // 7. Configure event triggers and trip zones.
+    // 8. Register and enable interrupts.
+    // 9. Configure PWM GPIOs, diagnostic pins, and X-BAR.
+    // 10. Confirm fault conditions and synchronize startup.
+    for (;;) {}
+}
+
+```
+
 ## 5. CPU1: system initialization and peripheral ownership
 
 The provided source initializes the system and interrupt tables:
diff --git a/ia-presentation/epwm.pdf b/ia-presentation/epwm.pdf
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