updating cpu1 main file for epwm 1 and 2

epwm_cpu1_bitfield/epwm_cpu1_bitfield_main.c

@@ -21,10 +21,72 @@ Objective:
 void main(void)
 {
     // 1. Initialize the system and interrupts
+    InitSysCtrl(); 
+    EALLOW;
+    ClkCfgRegs.PERCLKDIVSEL.bit.EPWMCLKDIV = 1; // 50MHz
+    EDIS;
+
     // 2. Select the ePWM clocks and assign CPU ownership
+    EALLOW;
+    DevCfgRegs.CPUSEL0.bit.EPWM1 = 0; //cpu1
+    DevCfgRegs.CPUSEL0.bit.EPWM2 = 0; //cpu1
+
+    DevCfgRegs.CPUSEL0.bit.EPWM4 = 1; //cpu2
+    DevCfgRegs.CPUSEL0.bit.EPWM5 = 1; //cpu2
+    EDIS;
+
     // 3. Enable ePWM1 and ePWM2 clocks
+    EALLOW;
+    CpuSysRegs.PCLKCR2.bit.EPWM1 = 1; //Module clock on
+    CpuSysRegs.PCLKCR2.bit.EPWM2 = 1; //Module clock on
+    EDIS;
+
     // 4. Stop time-base synchronization
+    EALLOW;
+    CpuSysRegs.PCLKCR0.bit.TBCLKSYNC = 0; // stop time base counter
+    EDIS;
+
     // 5. Configure TB and CC.
+    
+    // Configure epwm 1 and 2
+    
+    //Time base sub-module ePWM1
+    // 100MHz -> TBCLK = 100MHz/(HSPCLKDIV*CLKDIV) -> 50MHz
+    //                              2     * 1
+    EPwm1Regs.TBCTL.bit.FREE_SOFT = 2; // free run
+    EPwm1Regs.TBCTL.bit.CLKDIV = 0; // 1
+    EPwm1Regs.TBCTL.bit.HSPCLKDIV = 1; // 2
+    EPwm1Regs.TBCTL.bit.PRDLD = 0; //shadow mode
+    EPwm1Regs.TBCTL.bit.CTRMODE = 0; //up-count mode
+
+    //Time base sub-module ePWM2
+    // 100MHz -> TBCLK = 100MHz/(HSPCLKDIV*CLKDIV) -> 50MHz
+    //                              2     * 1
+    EPwm2Regs.TBCTL.bit.FREE_SOFT = 2; // free run
+    EPwm2Regs.TBCTL.bit.CLKDIV = 0; // 1
+    EPwm2Regs.TBCTL.bit.HSPCLKDIV = 1; // 2
+    EPwm2Regs.TBCTL.bit.PRDLD = 0; //shadow mode
+    EPwm2Regs.TBCTL.bit.CTRMODE = 2; //up-down count mode
+
+    // Period registers:
+    EPwm1Regs.TBPRD = 5000-1; // 10KHz sawtooth
+    EPwm2Regs.TBPRD = 5000; // 5KHz triangular
+
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     // 6. Configure AQ and dead band.
     // 7. Configure event trigger and trip-zones.
     // 8. Register and enable interrupts.