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# Enhanced Pulse Width Modulation
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---
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# 1. ePWM Module Overview
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TMS320F28379D Microcontroller
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---
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# What is ePWM?
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Enhanced Pulse Width Modulation
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Hardware-based PWM generation
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Configurable frequency and duty cycle
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Advanced control and protection features
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---
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# ePWM in the F28379D
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12 independent ePWM modules
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ePWM1 to ePWM12
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Controlled by CPU1 or CPU2
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Multiple configurable submodules
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---
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# ePWM Architecture
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/assets/epwm-architecture.jpg
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size: contain
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x: left
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Time-Base (TB)
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Counter-Compare (CC)
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Action Qualifier (AQ)
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Dead-Band (DB)
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Event Trigger (ET)
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Trip-Zone (TZ)
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---
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# Advanced ePWM Features
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Event Trigger (ET)
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Interrupts and ADC triggers
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Dead-Band (DB)
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Complementary switching delays
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Trip-Zone (TZ)
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Fault detection and protection
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---
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# Summary
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- The Time Base Sub-module generates the carrier waveform and also sets the PWM frequency.
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- The Event Trigger and Interrupt Sub-module generates interrupts and can also start converting measured analog signals to digital form.
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- The Counter Compare Sub-module performs a fine comparison between the carrier waveform and four possible values that can be modulation signals or duty ratios.
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- The Action Qualifier Sub-module can be used to decide what action (gating signals) to take based on comparison results.
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- The Dead Band Sub-module can be used to insert a dead band between complementary gating signals to prevent a shoot-through fault.
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- The Trip Zone Sub-module can turn off the gating signals based on fault feedback or user off signals.
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---
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# 2. Preparing the ePWM Module
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- Before configuring the ePWM module, a few preparations need to be made.
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- There is a maximum limit to the clock frequency that the ePWM module can accept as input. This differs from the processor's maximum clock (200 MHz).
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- Since the ePWM module is shared, we must decide which CPU controls it. By default, it is CPU1.
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- Once we decide which CPU controls the ePWM module, we must enable the clock signal to the ePWM module in the peripheral clock control register of that CPU.
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---
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# ePWM Clock Frequency
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/assets/clk 1.jpg
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size: contain
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The maximum ePWM clock frequency is 100 MHz.
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The maximum processor clock frequency is 200 MHz.
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---
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# ePWM Clock Divider
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## PERCLKDIVSEL Register
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/assets/epwm-reg-1.jpg
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size: contain
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EPWMCLKDIV determines the ePWM clock divider.
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EPWMCLKDIV = 0 → EPWMCLK = SYSCLK
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EPWMCLKDIV = 1 → EPWMCLK = SYSCLK / 2
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For SYSCLK = 200 MHz, use EPWMCLKDIV = 1.
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---
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# ePWM CPU Selection
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## CPUSEL0 Register
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/assets/epwm-reg-2.jpg
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size: contain
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The ePWM modules can be controlled by CPU1 or CPU2.
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By default, all ePWM modules are assigned to CPU1.
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Bit = 0 → CPU1
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Bit = 1 → CPU2
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---
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# ePWM Peripheral Clock
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## PCLKCR2 Register
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/assets/epwm-reg-3.jpg
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size: contain
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Each ePWM module has an individual clock enable bit.
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The controlling CPU must enable the corresponding peripheral clock.
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Bit = 0 → Clock disabled
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Bit = 1 → Clock enabled
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---
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# ePWM Clock Synchronization
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## PCLKCR0 Register
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/assets/epwm-reg-4.jpg
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size: contain
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TBCLKSYNC → Time-Base clock synchronization
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GTBCLKSYNC → Global Time-Base clock synchronization
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TBCLKSYNC = 1 → Start the ePWM Time-Base clocks.
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GTBCLKSYNC = 1 → Start ePWM Time-Base clocks globally in synchronization.
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GTBCLKSYNC overrides TBCLKSYNC.
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---
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# 3. Time Base Sub-module
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The Time Base Sub-module sets up the carrier waveform through a counter similar to the timers in the previous section.
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The timers in the Time Base Sub-module can count in different directions: up (sawtooth), down (reverse sawtooth), and up-down (triangular).
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The Time Base Sub-module can synchronize with either an external pin or other ePWM modules.
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The Time Base Sub-module cannot generate interrupts like the timers in the previous section.
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The simplest example will use the Time Base Sub-module in combination with the Counter Compare Sub-module and the Action Qualifier Sub-module.
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---
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# Time Base Sub-module
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## TBPRD Register
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/assets/time-base-1.jpg
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16-bit period register.
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This period register is mirrored by default.
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This means another register acts as a clone.
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Any reads or writes to TBPRD are actually from or to the mirror register.
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The mirror register's value is loaded into TBPRD at a scheduled time, so writing to TBPRD does not change the switching-cycle interval mid-cycle.
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---
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# Time Base Sub-module
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## TBCTL Register
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/assets/time-base-2.jpg
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Bits 14–15 (FREE_SOFT) are similar to the timer. FREE = 1 implies a free-running timer.
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Bits 10–12 (CLKDIV) provide the option of dividing EPWMCLK when generating slower switching-frequency gating signals.
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Bits 7–9 (HSPCLKDIV) also provide the option of dividing EPWMCLK when generating slower switching-frequency gating signals.
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Bit 2 (PHSEN), bits 4–5 (SYNCOSEL), bit 6 (SWFSYNC), and bit 13 (PHSDIR) are related to the synchronization feature.
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---
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# Time Base Sub-module
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## Counter Modes — CTRMODE
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/assets/time-base-3.jpg
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size: contain
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Bits 0–1 (CTRMODE) determine how the counter will count.
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CTRMODE = 0 (00): The counter counts upwards from 0 to the value in the period register, then returns to 0 and starts again.
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CTRMODE = 1 (01): The counter counts downwards from the value in the period register to 0, then returns to the period value and starts again.
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CTRMODE = 2 (10): The counter counts upwards from 0 to the value in the period register, then counts down to 0 and starts again.
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CTRMODE = 3 (11): The counter is stopped (default).
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---
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# Time Base Sub-module
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## Period Load — PRDLD
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Bit 3 (PRDLD) is the Period Load Bit.
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This determines when to load the period mirror register value into the period register TBPRD.
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By default, when we write to the PRD register, we write to the mirror register PRDM. This is shadow mode.
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This feature prevents disturbances if a write to the period register occurs during a PWM cycle.
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The change is reflected only when the counter becomes 0. This occurs at the end of a cycle (down mode) or at the beginning of a cycle (up and up-down modes).
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Setting PRDLD to 1 enables immediate load mode, where any write to the period register takes effect immediately, even in the middle of a cycle.
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---
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# Time Base Sub-module
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## TBSTS Register
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/assets/time-base-4.jpg
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The TBSTS register indicates the timer's status.
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CTRDIR is a read-only bit. It is 0 if the counter is counting down and 1 if it is counting up.
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The processor sets CTRMAX when the counter reaches the maximum value: 0xFFFF. |